Artificial intelligence chip architecture system

Abstract

According to the artificial intelligence chip architecture system provided by the invention, in the process of processing the camera data, the chip architecture utilizes the main processor and the neural network processor to realize effective processing of the camera data through linkage of the transmission channel; the whole chip framework orderly promotes the whole data flow process of importing, analyzing, reasoning and exporting camera data through ingenious internal arrangement and external arrangement, and in the whole framework, the external arrangement adopts a transmission channel as a main line to connect a main processor and a neural network processor in series. According to the internal arrangement, a pre-processing circuit block, an inference circuit block, a data post-processing circuit block and the like are connected in series in the neural network processor, and the whole data flow is orderly driven from input to output, so that the whole chip architecture can operate efficiently.

Description

Technical Field

[0001] The present invention relates to an artificial intelligence chip architecture system. Background Art

[0002] As we all know, in the process of big data processing, the chip architecture plays an extremely important role in the smoothness and speed of data processing.

[0003] This is especially critical for camera data processing. Just one captured image contains a vast amount of pixel data. Therefore, if the chip architecture is not reasonable, the processing of this massive amount of pixel data will be extremely time-consuming and labor-intensive.

[0004] Therefore, building a reasonable chip architecture to process massive amounts of camera data will be an issue that needs to be focused on and overcome in this field. Summary of the Invention

[0005] The present invention provides an artificial intelligence chip architecture system that effectively solves the above-mentioned problems existing in the prior art.

[0006] Specifically, the present invention provides an artificial intelligence chip architecture system, which includes: a camera for shooting a target object and forming camera data; a camera interface for extracting camera data from the camera; a transmission channel, to which the camera interface is connected; a main processor, the transmission channel is bidirectionally connected to the main processor, and the main processor is communicatively connected to the camera; and a neural network processor, which is connected to the transmission channel, and the neural network processor includes a data pre-processing circuit block, an inference circuit block, a data post-processing circuit block, a computing core engine circuit block, and a process storage circuit block, wherein the main processor transmits the artificial intelligence function weight file firmware along the transmission channel. The data is loaded into the neural network processor, and the main processor turns on the camera through the communication connection. The camera generates video data, which is transported to the neural network processor along the transmission channel. The pre-processing circuit block in the neural network processor pre-processes the video data to form pre-processed data. The pre-processed data is input to the inference circuit block. The inference circuit block is provided with multiple neural network inference layers. The pre-processed data passes through the multiple neural network inference layers in sequence for layer-by-layer inference. The processed data of each layer is used as the input of the next layer. The final inference data is output from the last layer of the multiple neural network inference layers. The final inference data is restored to recognizable data through the data post-processing circuit block for recognition by the main processor.

[0007] Preferably, the inference circuit block further includes a denoising sub-block for performing noise reduction processing on the camera data; and an enhancement sub-block for performing enhancement processing on the camera data.

[0008] Preferably, the transmission channel is formed by a circuit bus.

[0009] Preferably, the system further includes a timer communicatively connected to the neural network processor for timing the inference in the neural network processor.

[0010] Preferably, the system further includes a dynamic memory, and the transmission channel is bidirectionally connected to the dynamic memory, and the captured data is stored in the dynamic memory via the transmission channel.

[0011] Preferably, the dynamic memory is a dynamic random access memory.

[0012] Generally speaking, the present invention provides an artificial intelligence chip architecture system. In the process of processing the captured data, the chip architecture utilizes the linkage of the main processor and the neural network processor via the transmission channel to achieve effective processing of the captured data. The entire chip framework orderly promotes the entire data flow process of importing, analyzing, inferring, and exporting the camera data through ingenious internal and external arrangements. In the overall architecture, the external arrangement uses the transmission channel as the main line to connect the main processor and the neural network processor in series, and the internal arrangement connects the pre-processing circuit block, inference circuit block, data post-processing circuit block, etc. in series in the neural network processor. The entire data flow is driven orderly from input to output, enabling the overall chip architecture to operate efficiently. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will discuss the drawings required for the description of the embodiments or the prior art. Obviously, the technical solutions described in conjunction with the drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments and their drawings can be obtained based on these embodiments shown in the drawings.

[0014] Figure 1 Shows a schematic diagram of the overall architecture of the artificial intelligence chip architecture system according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] The following will clearly and completely describe the technical solutions of the embodiments of the present invention in conjunction with the drawings. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments described in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0016] The present invention provides an artificial intelligence chip architecture system. In this system, a camera interface 101 connected to a camera is connected to a transmission channel 100. A camera is set to capture a target object and form captured data, and the camera interface 101 is responsible for extracting the captured data from the camera. The transmission channel 100 is responsible for the back-and-forth transmission of various types of data in the system. In short, it becomes the main traffic artery in this system. Preferably, the transmission channel 100 is composed of a circuit bus.

[0017] Preferably, the transmission channel 100 is bidirectionally connected to a dynamic memory 102, and the captured data extracted by the camera interface 101 is stored in the dynamic memory 102 via the transmission channel 100. The dynamic memory 102 is, for example, a dynamic random access memory.

[0018] The transmission channel 100 is also bidirectionally connected to a main processor 103, and the main processor 103 is also communicatively connected to the camera. The main processor 103 is responsible for extracting data and regulating data for other hardware devices in the system via the transmission channel 100.

[0019] The transmission channel 100 is also bidirectionally connected to a neural network processor 104. The main processor 103 can call the captured data stored in the dynamic memory 102 to the neural network processor 104 via the transmission channel.

[0020] The neural network processor 104 mainly includes three parts, namely, a data preprocessing circuit block 104a, an inference circuit block 104b, and a data postprocessing circuit block 104c.

[0021] During operation, the main processor 103 loads the artificial intelligence function weight file firmware along the transmission channel 100 to the neural network processor 104 to complete the initialization of the neural network processor 104, so that the neural network processor 104 can be in a standby state for subsequent operation.

[0022] Subsequently, the main processor 103 turns on the camera through the communication connection relationship already formed with the camera, so as to start the camera to transport the captured data along the transmission channel 100 to the neural network processor 104. Thus, the data preprocessing circuit block 104a preprocesses the captured data to form preprocessed data. The preprocessed data is intended to meet the requirements of the neural network processor 104 for the data format, so as to facilitate the operation of subsequent circuit blocks.

[0023] For example, different from the traditional line-by-line processing mode, the data preprocessing circuit block 104a can perform frame-level processing on the captured data transported from the transmission channel 100 to improve the image quality, and the data preprocessing circuit block 104a adopts a full-frame data processing mechanism.

[0024] The camera interface 101 transmits a complete frame of image data as camera data to the data pre - processing circuit block 104a along the transmission channel 100 at one time, and performs dynamic range expansion and multi - scale denoising based on the spatial correlation of the full - frame data in the camera data. For example, through global histogram analysis and adaptive filtering algorithms, the details of the highlight and shadow areas of each frame of image data can be synchronously optimized within a single frame of the full - frame data, and accurate noise reduction can also be achieved by utilizing the intra - frame pixel correlation of the image data. Compared with traditional line - by - line processing, the dynamic range is increased by 20%, and the denoising effect is increased by 15%.

[0025] The pre - processed data is then input to the inference circuit block 104b. The inference circuit block is provided with multiple neural network inference layers, and these neural network inference layers are arranged in a stacked relationship. Thus, the pre - processed data sequentially passes through these neural network inference layers for layer - by - layer inference. During the inference process, the data output after each layer of processing is used as the input data for the next stacked layer. Thus, as the layer - by - layer inference progresses, the last layer in the multiple neural network inference layers outputs the final inference data.

[0026] The final inference data is then input to the post - processing circuit block 104c and restored to recognizable data for the main processor 103 to recognize. Preferably, during the data evolution from the data pre - processing circuit block 104a to the data post - processing circuit block 104c, all calculation data is in the FP8 data format. The data pre - processing circuit block 104a quantizes the original camera data from a high bit - width (such as 12 - bit RAW format) to the FP8 format. All multiply - add operations in the inference circuit block 104b are performed based on FP8 precision. The data post - processing circuit block 104c restores the high - bit output through inverse quantization.

[0027] The FP8 format significantly reduces the data storage bandwidth and the power consumption of the computing unit while ensuring the inference accuracy. After actual measurement, the overall power consumption of the system is reduced by 40% compared with the traditional FP16 architecture, and at the same time, the chip area is reduced by 25%.

[0028] Preferably, the inference circuit block 104b adopts a compute - in - memory design. The computing core engine circuit block and the process storage circuit block are integrated through a 3D stacking process, and the weight data is directly stored in the SRAM adjacent to the computing unit. During the inference process, the multiply - add operation is directly completed inside the storage unit, avoiding the frequent data transfer in the traditional von Neumann architecture, reducing the single - inference latency by 30%, and is especially suitable for scenarios with high real - time requirements (such as target recognition in autonomous driving).

[0029] During this process, the ingenious circuit layout constructed by the overall data flow from input to output ensures the efficient operation of the processing process.

[0030] Preferably, the inference circuit block 104b itself may include a denoising sub-block and an enhancement sub-block. The denoising sub-block is responsible for performing noise reduction processing on the camera data, while the enhancement sub-block is responsible for performing enhancement processing on the camera data. The noise reduction processing and the enhancement processing together constitute morphological processing.

[0031] The system provided by the present invention may further include a timer 105, which is communicatively connected to the neural network processor and is used to time the inference in the neural network processor.

[0032] Figure 1 A specific structural diagram of the artificial intelligence chip architecture system according to the present invention is shown.

[0033] This completes the description of the basic structure of the present invention. In summary, the present invention provides an artificial intelligence chip architecture system. During camera data processing, this chip architecture utilizes the linkage of a main processor and a neural network processor via a transmission channel to achieve efficient camera data processing. The entire chip framework, through ingenious internal and external arrangements, systematically facilitates the entire data flow process of camera data import, analysis, reasoning, and export. Within the overall architecture, the external arrangement connects the main processor and the neural network processor in series using the transmission channel as the main line, while the internal arrangement connects the pre-processing circuit block, reasoning circuit block, data post-processing circuit block, and so on within the neural network processor. This drives the entire data flow from input to output in an orderly manner, enabling the efficient operation of the overall chip architecture.

[0034] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An artificial intelligence chip architecture system, characterized in that, The system includes: a camera for capturing a target object and forming captured data; a camera interface for extracting the captured data from the camera; a transmission channel to which the camera interface is connected; a main processor, the transmission channel being bidirectionally connected to the main processor, and the main processor being communicatively connected to the camera; and a neural network processor connected to the transmission channel, the neural network processor including a data pre-processing circuit block, an inference circuit block, and a data post-processing circuit block, wherein the main processor loads an artificial intelligence function weight file firmware along the transmission channel to the neural network processor to complete the initialization of the neural network processor, the main processor turns on the camera through the communicative connection, the camera forms captured data, the captured data is transported along the transmission channel to the neural network processor, the pre-processing circuit block in the neural network processor pre-processes the captured data to form pre-processed data, the pre-processed data is input to the inference circuit block, the inference circuit block is provided with a plurality of neural network inference layers, the pre-processed data sequentially passes through the plurality of neural network inference layers for layer-by-layer inference, the data processed by each layer is used as the input of the next layer, and final inference data is output from the last layer of the plurality of neural network inference layers, and the final inference data is restored into recognizable data by the data post-processing circuit block for the main processor to recognize.

2. The system according to claim 1, wherein The inference circuit block further includes: a denoising sub-block for denoising the captured data; and an enhancement sub-block for enhancing the captured data.

3. The system according to claim 1, wherein The transmission channel is constituted by a circuit bus.

4. The system according to claim 1, wherein The system further includes a timer communicatively connected to the neural network processor for timing the inference in the neural network processor.

5. The system according to claim 1, characterized in that The system further includes a dynamic memory, the transmission channel being bidirectionally connected to the dynamic memory, and the captured data being stored in the dynamic memory via the transmission channel.

6. The system according to claim 5, wherein The dynamic memory is a dynamic random access memory.

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