Chopped wave amplifier based on automatic zero calibration assistance
By introducing an automatic zero-calibration circuit into the chopper stable amplifier, the problems of offset voltage and low-frequency noise in traditional chopper amplifiers are solved, and high-precision and stable amplifier design are achieved, reducing chip area and cost.
Patent Information
- Application Number
- CN202510307251.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-16
- Publication Date
- 2025-08-01
AI Technical Summary
When traditional chopper amplifiers deal with offset voltages, there are problems such as bandwidth limitation, offset voltage and low-frequency noise generation, and the offset voltage suppression effect of high-frequency paths is limited, resulting in insufficient system accuracy and stability.
An automatic zero calibration circuit is introduced in the traditional chopper stable amplifier. Through the IDAC, comparator and logic section, the input offset voltage and mismatch are automatically eliminated to achieve offset calibration of high-frequency and low-frequency paths.
Improves the accuracy and stability of the amplifier, reduces the residual offset voltage, simplifies design complexity, reduces the matching requirement for the amplifier stage, and reduces chip area and cost.
Smart Images
Figure CN120415337A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic circuits, and particularly to a precision chopper instrumentation amplifier assisted by automatic zero calibration, which is used to eliminate the input offset voltage and improve the accuracy of the amplifier. Background Art
[0002] Traditional chopper instrumentation amplifiers effectively reduce low-frequency noise and offset voltage through modulation and demodulation techniques. However, traditional chopper amplifiers limit the bandwidth of the amplifier, and at the same time, the offset voltage and low-frequency noise modulated to the chopping frequency and its multiples generate ripples at the output.
[0003] The proposed chopper-stabilized amplifier preferably solves the above two problems. By introducing a high-frequency path, the processing ability for higher-frequency signals is achieved. At the same time, a low-frequency path with high gain is introduced, and under the action of the feedback loop, the low-frequency noise and offset voltage of the high-frequency path are effectively suppressed. The offset voltage and low-frequency noise of the low-frequency path are eliminated by chopping, and at the same time, due to the lower bandwidth of the low-frequency path, the modulated offset voltage and low-frequency noise will be suppressed.
[0004] However, since the suppression of the offset voltage of the high-frequency path is achieved through the low-frequency path, the attenuation multiple is related to the gain of the first-stage amplifier of the low-frequency path at the chopping frequency, and usually cannot be made very large. And the maximum offset voltage that the system can handle is also related to the ratio of the transconductance of the first stage of the high-frequency path to that of the second stage of the low-frequency path. Therefore, too large an initial offset voltage may saturate the low-frequency path. Moreover, the offset voltage of the second stage of the low-frequency path also contributes a part of the residual offset voltage.
[0005] Therefore, there is an urgent need for a precision chopper instrumentation amplifier capable of automatic zero calibration to automatically eliminate mismatches before the amplifier works, so as to improve the accuracy and stability of the system.
[0006] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention
[0007] The object of the present invention is to provide a precision chopper instrumentation amplifier assisted by automatic zero calibration. By introducing an automatic zero calibration circuit on the basis of a traditional chopper-stabilized amplifier, it can automatically eliminate the input offset voltage and mismatch before the amplifier works, thereby improving the accuracy of the amplifier and achieving a lower residual offset voltage.
[0008] The technical solution of the present invention is as follows: First is the chopper-stabilized amplifier part, which follows the traditional chopper-stabilized amplifier structure. At the same time, it achieves a relatively high bandwidth and low low-frequency noise and offset voltage. At the same time, some modules for reducing ripple can be added according to requirements, such as a Notch Filter or a dedicated Ripple reduction loop, etc.
[0009] Another part is the auto-zeroing module, which includes an IDAC, a comparator, and a logic part. During auto-zeroing, the inputs of the first-stage amplifier 203 of the high-frequency path and the second-stage amplifier 208 of the low-frequency path are shorted and connected to the common-mode voltage. The comparator compares the amplifier output with the common-mode voltage, and the comparison result is input to the logic part and finally controls the IDAC. The IDAC can be a binary, thermometer code, or even a combination of the two schemes. The IDAC can automatically calibrate the offset voltages of both paths by controlling the current at the junction of the low-frequency and high-frequency paths. The number of bits of the IDAC can be designed according to the designed input pair transistor area and the target residual offset voltage. After all bit comparisons are completed, the auto-zeroing process ends. The switch that is shorted at the start of auto-zeroing is disconnected and remains so until the end of operation. After that, the amplifier can enter the normal working stage.
[0010] The above auto-zeroing assisted scheme can be carried out when the chip leaves the factory to achieve the offset caused by production. It can also be carried out every time the power is turned on to address the offset caused by production and the drift of the offset due to aging, etc. Description of the Drawings
[0011] Figure 1 It shows a schematic structural diagram of a chopper-stabilized amplifier.
[0012] Figure 2 It shows a schematic structural diagram of the chopper-stabilized amplifier assisted by auto-zeroing of the present invention.
[0013] Figure 3 It shows the auto-zeroing module used in the present invention. Detailed Embodiments
[0014] The present invention includes an auto-zeroing module and a chopper-stabilized amplifier module.
[0015] Figure 1Fig. 0 shows a traditional chopper-stabilized circuit, which includes a high-frequency path 11 and a low-frequency path (composed of an amplifier 13, a transconductance amplifier 14, and an operational amplifier 15). When the chopper-stabilized circuit works, the whole circuit works in a closed-loop system. Taking resistor feedback as an example, the Clk signal controls the chopper switch. When the Clk signal is high, the circuit input Vip is shorted to the positive input terminal of the first-stage amplifier 13 of the low-frequency path, and Vin is shorted to the negative input terminal. This part of the operation is realized by the chopper switch 16. At the same time, the output Vop1 of the amplifier 13 is shorted to the positive input terminal of the second-stage amplifier 14 of the low-frequency path, and Von1 is shorted to the negative input of the amplifier 14. This part of the function is realized by the chopper switch 17. When the Clk signal is low, the chopper switches 16 and 17 are switched. The circuit input Vip is shorted to the negative input terminal of the first-stage amplifier 13 of the low-frequency path, and Vin is shorted to the positive input terminal of the amplifier 14. At the same time, the output Vop1 of the amplifier 13 of the low-frequency path is shorted to the input of the amplifier 14 of the low-frequency path, and Von1 is shorted to the positive input. If there is an offset due to the manufacturing process, it will be modulated by the periodically changing chopper switch. Ideally, it can be equivalent to a periodically changing rectangular wave modulation, and the low-frequency noise and offset voltage will be shifted to the chopper frequency and its harmonics. This part of the ripple is attenuated by the low-frequency path on the one hand and can be attenuated by means such as subsequent series low-pass filtering, introducing a ripple suppression loop, and series notch filtering on the other hand. In summary, a precision operational amplifier with high bandwidth and low offset is realized.
[0016] For Figure 1 the chopper-stabilized amplifier circuit in where A2 is the gain of the amplifier 13 at the chopper frequency. And since the demodulation switch of the chopper is before the transconductance amplifier 14, its offset will not be modulated, and its equivalent input offset voltage is: To reduce the ripple generated after chopping the offset voltage and meet the requirements of system stability, the chopper frequency is usually greater than the crossover frequency between the low-frequency path and the high-frequency path. This crossover frequency is the frequency at which the gains of the low-frequency path and the high-frequency path are the same. The expression of this frequency is: Among them, GBW is the gain-bandwidth product of the operational amplifier. On the one hand, the chopping frequency should be greater than the crossover frequency. However, in order to ensure a low input current, the chopping frequency should be as low as possible. Therefore, the crossover frequency should be made as low as possible, that is, gm3 should be much smaller than gm0. However, it can be seen that this is contradictory to low input offset.
[0017] This design proposes a feasible solution. By introducing an auxiliary auto-zero module before the chopper-stabilized operational amplifier works, the input offsets of amplifiers 12 and 13 are cancelled. Thus, the design difficulty is effectively reduced. At the same time, since the offset of amplifier 13 is also calibrated, it can be implemented with a smaller area than without using the auto-zero circuit. Thus, the chip area and cost are effectively reduced.
[0018] Figure 2 It shows the chopper-stabilized amplifier circuit with an auto-zero module introduced. Among them, 201 is the auto-zero module part. It usually consists of an N-bit IDAC, a SAR logic part, and a comparator. In this invention, a single-ended binary IDAC (301) is taken as an example. The IDAC is short-circuited with the output of the first-stage amplifier 203 of the high-frequency path and the output of the second-stage amplifier 208 of the low-frequency path, so that the offset voltages from the high-frequency and low-frequency paths can be eliminated simultaneously during auto-calibration. One end of the input of comparator 31 is connected to the output of the chopper-stabilized amplifier, and the other end is connected to the common-mode voltage. This common-mode voltage can be used as the reference voltage for controlling the CMFB of the low-frequency path to reduce the bias requirement. The output of the comparator is used as the input signal of the SAR logic part 32. In this example, a single-ended IDAC is adopted. Therefore, the first cycle of the SAR logic is used for polarity judgment, that is, to determine which end the IDAC should be connected to. This process is realized by the switch 303. After that, it is the same as the traditional SAR logic: in each cycle, first flip the corresponding bit of the IDAC, wait for a setup time, and then the comparator works. If the comparator result is 1, it means that the IDAC current introduced is too large, so this bit of the IDAC cancels the flip; on the contrary, if the comparison result is 0, it means that the IDAC current introduced is not enough, so this bit of the IDAC remains in the flipped state. After passing through the N-bit SAR logic, we can ensure that the offsets of the high-frequency and low-frequency paths are calibrated. Then the amplifier enters the normal working stage, and the IDAC maintains this offset compensation current. This part of the offset compensation current will cancel the mismatch current caused by the input offset voltage, thus achieving a very low residual offset voltage. The number of bits of the IDAC can be designed according to the target offset voltage to be achieved.
[0019] Figure 3An implementation scheme of an automatic zero calibration module is presented, which consists of a comparator 31, a logic part 32, and an IDAC 33. One end of the comparator is connected to VCM, and the same voltage as that used in the CMFB of the fully differential amplifier 206 can be applied. The other end of the comparator is connected to the output of operational amplifier 2. Ideally, when the inputs of operational amplifiers 203 and 208 are shorted, if there is no mismatch, the output should be VCM. However, due to the existence of random and systematic mismatches, as well as a large DC gain, the output of amplifier 2 is not VCM. By comparing the output voltage with VCM using comparator 31, the polarity of the mismatch voltage can be determined. Therefore, the connection mode of the output switch 34 of the IDAC will be controlled for the first time. For example, when the output of amplifier 2 is greater than VCM, the IDAC current sink will be connected to vop_az, thereby reducing the output of amplifier 2 and ensuring it is close to VCM.
[0020] After the first comparison is completed, the subsequent automatic zero calibration process is the same as that of the traditional SAR logic. First, the IDAC starts from the reset stage, and the IDAC current is 0 during the reset stage. After the Az_en signal is pulled high, the IDAC is enabled, its MSB is set to 1, and the IDAC will draw current from the output of the transconductance amplifier 203, which is also the output of 208. When the rising edge of the Clk signal arrives, the logic part 32 outputs a comparator enable signal comp_ctr. After enabling comparator 31, the comparator operates and outputs the result, which is input to the logic part 32. The logic part determines whether to retain the MSB based on the comparator result. If the comparator result is 1, it means that after compensating with the MSB current, the polarity of the mismatch has not changed, that is, the compensated current is not enough, so the MSB will be retained. On the contrary, if the comparator result is 0, it means that the current compensated by the IDAC is too large, and the current of the MSB will be turned off. While this part of the logic is completed, the MSB - 1 bit will be set to 1 to prepare for the next comparison. The subsequent logic repeats the above operations.
[0021] In summary, the present invention provides a chopper precision amplifier circuit, including: a chopper amplifier composed of a high - frequency path and a low - frequency path, and an automatic zero calibration module including a switch, a comparator, a logic part, and an IDAC. The present invention uses the automatic zero calibration technology to alleviate the design complexity of the traditional chopper - stabilized amplifier, and at the same time reduces the matching requirements, that is, the area requirements, for some amplification stages. Therefore, the present invention effectively overcomes some of the shortcomings in the prior art and has value.
[0022] The above - mentioned embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above - mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A chopper-stabilized amplifier circuit with automatic zero calibration assistance, characterized in that, The automatic zero calibration part at least includes: a short - circuit switch 209 existing at the input end of the input stage 203 of the high - frequency path and a short - circuit switch 210 existing at the input end of the second - stage amplifier 208 of the low - frequency path, and an automatic zero calibration module. The input of the automatic zero calibration module is connected to the output of the chopper - stabilized amplifier, and the output of the automatic zero calibration module is connected to the intersection part of the low - frequency path and the high - frequency path. Because short - circuit switches exist in both the low - frequency path and the high - frequency path, the offset voltages of both parts can be attenuated by the automatic zero calibration module.
2. The automatic zero calibration circuit according to claim 1, wherein: It simultaneously includes a comparator, an IDAC for calibration, and a logic part. One end of the comparator is connected to a fixed voltage (usually the common - mode voltage), and the other end is connected to the output of the chopper - stabilized circuit. The output of the comparator is connected to the input of the logic part. The logic part outputs to control the IDAC. The output of the IDAC is the output of the automatic zero calibration module, which is connected to the intersection part of the low - frequency path and the high - frequency path and is used to eliminate the partial offset existing in the low - frequency path and the high - frequency path.