A parallel decoding method, decoder, device and storage medium

Abstract

The application provides a parallel decoding method, a decoder, a device and a storage medium, and relates to the technical field of decoding. The method comprises the following steps: obtaining a check matrix to be decoded, and dividing the check matrix into a plurality of matrix subblocks according to a set matrix division mode; calculating the subblock lengths of the plurality of matrix subblocks in each layer of the divided check matrix; according to the matrix subblock synchronization principle and the subblock lengths of the plurality of matrix subblocks in each layer of the divided check matrix, performing layer sequence adjustment and layer insertion on the plurality of matrix subblocks, wherein the layer insertion comprises layer insertion and interlayer insertion; and according to the arrangement sequence of each layer after the layer sequence adjustment, performing parallel two-stage calculation on the plurality of matrix subblocks in each layer after the insertion until the calculation result meets a check rule, and generating a decoding result. In this way, the check matrix is divided into a plurality of matrix subblocks to perform parallel calculation, parallel decoding is realized without significantly increasing resource consumption, decoding delay is reduced, and decoding efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of decoding, in particular to a parallel decoding method, a decoder, a device and a storage medium. BACKGROUND

[0002] With the growth of data storage demand, bit errors caused by threshold voltage drift in flash media need to be corrected by LDPC (Low Density Parity Check) code. The traditional LDPC decoder adopts a hardware implementation scheme of layered minimum sum algorithm, which requires serial calculation of each layer according to the check matrix (H matrix), and each layer is processed in column order. For large H matrix (thousands of subblocks), serial calculation results in significant decoding delay. The existing scheme for reducing delay is to use multiple decoders for parallel decoding, but there are problems of hardware resource waste and low efficiency of single decoder. Therefore, how to provide a scheme to improve the LDPC decoding efficiency and reduce the decoding delay, while avoiding hardware resource waste, has become a technical problem to be solved at present. SUMMARY

[0003] The present application provides a parallel decoding method, a decoder, a device and a storage medium to at least solve the above technical problems in the prior art.

[0004] According to a first aspect of the present application, a parallel decoding method is provided, the method comprising:

[0005] obtaining a check matrix to be decoded, and dividing the check matrix into a plurality of matrix subblocks according to a set matrix division manner;

[0006] calculating the subblock length of each layer of the plurality of matrix subblocks of the check matrix after division, and adjusting the layer order and inserting a gap in each layer of the plurality of matrix subblocks according to the matrix subblock synchronization principle and the subblock length of each layer of the plurality of matrix subblocks of the check matrix after division, wherein the gap insertion includes intra-layer gap insertion and inter-layer gap insertion;

[0007] performing parallel two-stage calculation on the plurality of matrix subblocks in each layer after gap insertion according to the arrangement order of each layer after layer order adjustment, until the calculation result meets the check rule, to generate a decoding result.

[0008] In an implementation manner, the set matrix division manner includes a parity column division manner or a front and rear column division manner; accordingly,

[0009] dividing the check matrix into a plurality of matrix subblocks according to the set matrix division manner includes one of the following operations:

[0010] In the case that the set matrix split mode is the odd-even column split mode, the parity check matrix is divided into a matrix sub-block of odd columns and a matrix sub-block of even columns;

[0011] In the case that the set matrix split mode is the front-back column split mode, the parity check matrix is divided into a matrix sub-block of front half columns and a matrix sub-block of back half columns from the middle of columns.

[0012] In an implementation, according to the matrix sub-block synchronization principle and the sub-block length of each matrix sub-block in each layer after the split, the layer sequence adjustment and layer insertion of the matrix sub-blocks are performed, including:

[0013] For each matrix sub-block in each layer, the matrix sub-blocks in the current layer are inserted according to the number of matrix blocks of the matrix sub-block with the maximum sub-block length in the current layer;

[0014] The layer length of each layer after the insertion is calculated, and the layer sequence adjustment of the matrix sub-blocks after the insertion is performed according to the layer length of each layer;

[0015] The inter-layer insertion of all matrix sub-blocks in each layer is performed according to the layer length of all layers after the layer sequence adjustment.

[0016] In an implementation, the sub-block length is the number of matrix blocks contained in the matrix sub-block, and the layer length is the sum of the number of matrix blocks of all matrix sub-blocks in the corresponding layer.

[0017] In an implementation, the layer sequence adjustment of the matrix sub-blocks after the insertion is performed according to the layer length of each layer, including one of the following operations:

[0018] The layers are sorted in descending order of the layer length;

[0019] The layers are sorted in ascending order of the layer length.

[0020] In an implementation, the parallel two-stage calculation of the matrix sub-blocks in each layer after the insertion is performed until the calculation result meets the check rule, and the decoding result is generated, including:

[0021] The parallel two-stage calculation of the matrix sub-blocks in each layer after the insertion is iteratively performed;

[0022] After each round of iterative calculation, it is checked whether the calculation result meets the check rule;

[0023] If the calculation result meets the check rule, the calculation result of the current all matrix sub-blocks is integrated to generate the decoding result.

[0024] In an implementation, the parallel two-stage calculation includes:

[0025] In the variable preparation stage, information transmitted from the variable node to the check node is calculated, and the calculation result is integrated;

[0026] In the variable operation stage, information transmitted from the check node to the variable node and the new value of the variable node after decoding are calculated according to the integrated calculation result.

[0027] In an implementation manner, the method further comprises:

[0028] If the calculation result does not conform to the check rule and the preset maximum iteration number is not reached, iteration calculation is continued;

[0029] If the calculation result does not conform to the check rule and the preset maximum iteration number is reached, decoding failure information is output.

[0030] According to a second aspect of the present application, a decoder is provided, which comprises:

[0031] An acquisition module is configured to acquire a check matrix to be decoded, and split the check matrix into a plurality of matrix subblocks according to a set matrix splitting manner;

[0032] A parallel decoding module is configured to calculate the subblock length of the plurality of matrix subblocks in each layer of the split check matrix, and perform layer sequence adjustment and layer insertion according to the matrix subblock synchronization principle and the subblock length of the plurality of matrix subblocks in each layer of the split check matrix, wherein the layer insertion comprises intra-layer insertion and inter-layer insertion; and perform parallel two-stage calculation on the plurality of matrix subblocks in each layer after the layer sequence adjustment according to the arrangement sequence of each layer, until the calculation result conforms to the check rule, to generate a decoding result.

[0033] In an implementation manner, the set matrix splitting manner comprises a parity column splitting manner or a front and rear column splitting manner; correspondingly, the acquisition module comprises one of the following:

[0034] A first splitting sub-module is configured to, in the case that the set matrix splitting manner is the parity column splitting manner, divide the check matrix into matrix subblocks of odd columns and matrix subblocks of even columns;

[0035] A second splitting sub-module is configured to, in the case that the set matrix splitting manner is the front and rear column splitting manner, divide the check matrix into matrix subblocks of front half columns and matrix subblocks of rear half columns from the middle position of columns.

[0036] In an implementation manner, the parallel decoding module comprises:

[0037] The layer control sub-module is configured to, for each matrix sub-block in each layer, perform intra-layer padding on other matrix sub-blocks in the current layer according to a matrix block number of a matrix sub-block with the largest sub-block length among the matrix sub-blocks in the current layer, calculate a layer length of each layer after intra-layer padding, and perform layer sequence adjustment on the plurality of matrix sub-blocks after intra-layer padding according to the layer length of each layer; and perform inter-layer padding on all matrix sub-blocks in each layer according to the layer length of all layers after layer sequence adjustment.

[0038] In an implementation, the layer control sub-module comprises one of the following units:

[0039] The first sorting unit is configured to sort the layers according to the layer length from large to small.

[0040] The second sorting unit is configured to sort the layers according to the layer length from small to large.

[0041] In an implementation, the parallel decoding module further comprises:

[0042] The plurality of matrix block operation sub-modules are configured to perform parallel two-stage calculation on the plurality of matrix sub-blocks in each layer after padding iteratively.

[0043] The check sub-module is configured to check whether the calculation result meets a check rule after each round of iterative calculation.

[0044] The plurality of matrix block operation sub-modules are further configured to, if the calculation result meets the check rule, integrate the calculation results of all current matrix sub-blocks to generate a decoding result.

[0045] In an implementation, the matrix block operation sub-module comprises:

[0046] The variable preparation unit is configured to, in a variable preparation stage, calculate information transmitted from a variable node to a check node, and integrate the calculation result.

[0047] The variable operation unit is configured to, in a variable operation stage, calculate information transmitted from the check node to the variable node and a new value of the variable node after decoding according to the integrated calculation result.

[0048] In an implementation, the decoder further comprises:

[0049] The first judgment module is configured to, if the calculation result does not meet the check rule and a preset maximum number of iterations is not reached, continue iterative calculation.

[0050] The second judgment module is configured to, if the calculation result does not meet the check rule and the preset maximum number of iterations is reached, output a decoding failure message.

[0051] According to a third aspect of the present application, an electronic device is provided, comprising:

[0052] at least one processor; and

[0053] a memory in communication with the at least one processor; wherein

[0054] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present application.

[0055] According to a fourth aspect of the present application, a non-transitory computer readable storage medium storing computer instructions is provided, the computer instructions being used to enable the computer to perform the method described in the present application.

[0056] The parallel decoding method, decoder, device and storage medium provided by the present application obtain a check matrix to be decoded, split the check matrix into a plurality of matrix subblocks according to a set matrix splitting manner; calculate the subblock length of the plurality of matrix subblocks in each layer of the split check matrix, and perform layer sequence adjustment and layer insertion according to the matrix subblock synchronization principle and the subblock length of the plurality of matrix subblocks in each layer of the split check matrix, the layer insertion includes intra-layer insertion and inter-layer insertion; perform parallel two-stage calculation on the plurality of matrix subblocks in each layer after the layer sequence adjustment according to the arrangement sequence of each layer, until the calculation result meets the check rule, and generate a decoding result. By splitting the check matrix into a plurality of matrix subblocks to perform parallel calculation, parallel decoding is realized without significantly increasing resource consumption, and the calculation speed is improved. In addition, by the layer insertion scheme, the alignment problem of each layer calculation is solved, the calculation timing is ensured to be consistent, the decoding delay is effectively reduced, and the decoding efficiency is improved.

[0057] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0058] The above and other objects, features and advantages of the example embodiments of the present application will be more apparent from the following detailed description read in conjunction with the accompanying drawings, in which:

[0059] In the drawings, identical or corresponding reference numerals indicate identical or corresponding parts.

[0060] Figure 1 An implementation flowchart of the parallel decoding method provided by the embodiments of the present application is shown;

[0061] Figure 2 An example diagram of the check matrix of the parallel decoding method provided by the embodiments of the present application is shown.

[0062] Figure 3 An example of the matrix splitting operation of the parallel decoding method provided by the embodiment of the present application is shown Figure 1 ;

[0063] Figure 4 An example of the matrix splitting operation of the parallel decoding method provided by the embodiment of the present application is shown Figure 2 ;

[0064] Figure 5 An implementation flowchart of the layer order adjustment and layer insertion operation of the parallel decoding method provided by the embodiment of the present application is shown

[0065] Figure 6 An example of the layer insertion principle of the parallel decoding method provided by the embodiment of the present application is shown

[0066] Figure 7 An implementation flowchart of the iteration calculation operation of the parallel decoding method provided by the embodiment of the present application is shown

[0067] Figure 8 A composition structure diagram of the decoder provided by the embodiment of the present application is shown

[0068] Figure 9 A composition structure diagram of the matrix block operation sub-module of the decoder provided by the embodiment of the present application is shown

[0069] Figure 10 A composition structure diagram of an electronic device provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0070] In order to make the objectives, characteristics and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0071] First, the application scenario of the present application is described. Nowadays, a large amount of data is generated every day. The data is stored in a hard disk. The hard disk is a non-volatile memory, and the data can still be retained after the power is cut off. Flash memory is a widely used storage medium, which has the characteristics of fast read-write speed, low power consumption and large capacity. The storage medium has a specific threshold voltage, which is a key parameter for reading and writing data. However, as the number of read-write times of the storage medium increases, the threshold voltage will change, resulting in errors in individual bits of the read data.

[0072] The read data can be corrected using an error correction code. For flash memory media, a common error correction code is a low-density parity-check code (LDPC). LDPC codes have the advantages of strong error correction capability, low complexity, and suitability for hardware implementation. At present, the LDPC decoder suitable for flash memory media generally adopts a hardware implementation scheme of a layered minimum sum algorithm. When decoding, the layered minimum sum algorithm requires that the layers of the check matrix (H matrix) be taken as the calculation unit, and the calculation is performed layer by layer. After each layer is calculated, the calculation of the next layer can be started. At the same time, the calculation is performed column by column in each layer, and each time a sub-block of one layer in the H matrix is calculated.

[0073] Since the minimum calculation unit of the LDPC decoder is a sub-block of the H matrix, and for a large H matrix, there can be thousands of sub-blocks, resulting in an increase in decoding delay. The existing method for reducing decoding delay is to use multiple decoders for parallel decoding, but this scheme has the problems of resource waste and low efficiency of a single decoder. Therefore, to solve the above problems, the present application provides a parallel decoding method, a decoder, a device and a storage medium.

[0074] Figure 1 An implementation flowchart of the parallel decoding method provided by the embodiments of the present application is shown.

[0075] Reference Figure 1 The embodiments of the present application provide a parallel decoding method applied to an LDPC decoder, which comprises: operation 101, obtaining a check matrix to be decoded, and dividing the check matrix into a plurality of matrix sub-blocks according to a set matrix division mode; operation 102, calculating the sub-block length of the plurality of matrix sub-blocks in each layer of the divided check matrix, and adjusting the layer order and inserting a gap in each layer of the plurality of matrix sub-blocks according to the matrix sub-block synchronization principle and the sub-block length of the plurality of matrix sub-blocks in each layer of the divided check matrix, wherein the gap insertion in each layer includes gap insertion in the layer and gap insertion between layers; operation 103, performing parallel two-stage calculation on the plurality of matrix sub-blocks in each layer after the gap insertion according to the arrangement order of each layer after the layer order adjustment, until the calculation result meets the check rule, and generating a decoding result.

[0076] In operation 101, a check matrix to be decoded is obtained, and the check matrix is divided into a plurality of matrix sub-blocks according to a set matrix division mode.

[0077] When decoding is needed, a check matrix to be decoded is first obtained. The check matrix is a core component of an LDPC code and is a two-dimensional matrix, the elements of which are usually 0 and 1, and is used to represent the check relationship between each bit in the code word. In the check matrix, each row corresponds to a check equation and a check node, and each column corresponds to a bit in the code word and a variable node.

[0078] After the check matrix is acquired, in order to be able to perform parallel processing on different parts of the check matrix, thereby improving decoding efficiency, the check matrix is also divided into multiple matrix sub-blocks according to a set matrix division mode.

[0079] The check matrix can be divided into multiple parts according to columns, in order to facilitate the description of the scheme of the embodiments of the present application, the scheme of the present application is described by taking the case of being divided into two parts as an example.

[0080] In an embodiment of the present application, the set matrix division mode includes a parity column division mode or a front and rear column division mode; accordingly, the check matrix is divided into multiple matrix sub-blocks according to the set matrix division mode, including one of the following operations: in the case where the set matrix division mode is the parity column division mode, the check matrix is divided into a matrix sub-block of odd columns and a matrix sub-block of even columns; in the case where the set matrix division mode is the front and rear column division mode, the check matrix is divided into a matrix sub-block of the front half columns and a matrix sub-block of the rear half columns from the middle of the columns.

[0081] The set matrix division mode can be a parity column division mode, and the principle of the parity column division mode is to extract the odd columns and the even columns of the check matrix to form a matrix sub-block. For example, referring to Figure 2 and Figure 3 , Figure 2 an example diagram of the check matrix of the parallel decoding method provided by the embodiments of the present application is shown, Figure 3 an example of the matrix division operation of the parallel decoding method provided by the embodiments of the present application is shown Figure 1 The odd columns (1st column, 3rd column, 5th column, 7th column) and the even columns (2nd column, 4th column, 6th column, 8th column) of the check matrix shown in Figure 2 are extracted respectively to form Figure 3 a matrix sub-block corresponding to the odd columns on the left and Figure 3 a matrix sub-block corresponding to the even columns on the right.

[0082] Further, in addition to the parity column division mode, the set matrix division mode can also be a front and rear column division mode, and the principle of the front and rear column division mode is to divide the check matrix into a matrix sub-block of the front half columns and a matrix sub-block of the rear half columns from the middle of the columns. For example, referring to Figure 4 , Figure 4 an example of the matrix division operation of the parallel decoding method provided by the embodiments of the present application is shown Figure 2 The check matrix in Figure 2 is divided into Figure 4 a matrix sub-block corresponding to the front half columns on the left (the first 4 columns) and Figure 4 a matrix sub-block corresponding to the rear half columns on the right (the last 4 columns) from the middle of the columns.

[0083] The specific matrix splitting manner can be selected according to actual requirements. If the check matrix needs to be split into two uniform parts, the check matrix can be split into two parts from the middle of the check matrix. However, generally, for the convenience of coding, the check matrix can be divided into an information bit part and a check bit part with reference to the codeword. However, this splitting will result in that the entire check matrix is not uniform when being constructed. In order to make the splitting result more uniform, the matrix is preferably split into two parts according to odd columns and even columns.

[0084] In operation 102, the subblock lengths of the matrix subblocks in each layer of the split check matrix are calculated, and the matrix subblocks are adjusted in layer sequence and inserted with a layer gap according to the matrix subblock synchronization principle and the subblock lengths of the matrix subblocks in each layer of the split check matrix. The layer gap includes an intra-layer gap and an inter-layer gap.

[0085] Since decoding is calculated layer by layer, after the check matrix is split, the calculation amount of the parallel calculation processes of a layer is determined. In order to ensure that the parallel calculation of a layer is completed synchronously and avoid the problems of delay and asynchronous operation caused by the inconsistent completion time of the calculation processes, the alignment of the start and end of each layer needs to be solved. The layer generally refers to one or more rows of the check matrix. For the convenience of understanding the technical solution of the present application, the present application will take one row of the check matrix as the layer for illustration, for example, the first row (1, 2, 3, 4, 5) in the check matrix in FIG. 1 is a layer. Figure 2

[0086] Therefore, in order to solve the alignment problem of the start and end of each layer, the present application embodiment designs a layer gap insertion scheme. Through layer sequence adjustment and layer gap insertion operations, the calculation sequence of each layer is optimized, and the calculation processes of each layer are aligned in time by inserting a blank matrix block.

[0087] The calculation time depends on the subblock length in the matrix subblock. Therefore, the layer sequence adjustment and layer gap insertion operations are based on the subblock length of each matrix subblock in each layer. The matrix subblock in each layer can be regarded as a matrix block of each row in the matrix subblock. For example, for the matrix subblock of the odd columns on the left side in the check matrix in FIG. 1, the matrix blocks 1, 2, 3, and 5 of the first row, the matrix blocks 6 and 8 of the second row, the matrix block 13 of the third row, and the matrix blocks 16 and 18 of the fourth row are the matrix subblocks in each layer. Figure 3

[0088] ​​In an embodiment of the present application, in addition to ensuring that each layer of parallel computation is completed synchronously, it is also necessary to reduce the waiting delay between layers, to ensure that the difference between the matrix blocks of each layer is as close to zero as possible or less than a set threshold, which can be configured according to actual requirements. Correspondingly, the matrix sub-block synchronization principle can be understood as a strategy aimed at achieving synchronous completion of parallel computation within a layer, minimizing the waiting time between layers, and ensuring efficient decoding process, for example, ensuring that the calculation of all matrix sub-blocks within the same layer can start and end synchronously, and the calculation of matrix sub-blocks between different layers can be coordinated. This principle adjusts the layer order and performs layer insertion operation to make the calculation of each layer proceed in coordination, thereby optimizing the time efficiency and resource utilization of the entire decoding process.

[0089] Further, corresponding to the matrix sub-block synchronization principle, layer insertion includes intra-layer insertion and inter-layer insertion. Intra-layer insertion refers to inserting a blank matrix block into a shorter matrix sub-block within the same layer to make its length consistent with the longest matrix sub-block in the layer. Inter-layer insertion refers to inserting a blank matrix block to make the total length of adjacent layers consistent according to the length of the layers.

[0090] In operation 103, according to the arrangement order of each layer after the layer order adjustment, parallel two-stage calculation is performed on the multiple matrix sub-blocks within each layer after insertion, until the calculation result meets the check rule, to generate the decoding result.

[0091] According to the adjusted arrangement order of each layer, the multiple matrix sub-blocks within each layer after insertion are calculated in parallel in two stages. The two-stage calculation usually includes variable node update and check node update, which are alternately performed in the decoding process to gradually approach the correct codeword.

[0092] After each round of iterative calculation, it is checked whether the calculation result meets the check rule, such as whether the parity check condition of the check node is met. If the calculation result meets the check rule, the decoding is successful, and the final decoding result is generated.

[0093] The check rule is a standard for judging whether the decoding is successful, which is usually the check equation of the LDPC code. Specifically, the check equation of the LDPC code is defined by the check matrix (H matrix), and each check equation corresponds to a row in the check matrix. In the check process, it is judged whether the decoding is successful by calculating whether the parity check condition of the check node is met. The parity check condition usually refers to whether the parity of the input information of the check node is consistent with the expectation. If the parity check condition of all check nodes is met, it is considered that the decoding is successful.

[0094] In an embodiment of the present application, if the calculation result does not conform to the check rule and the preset maximum iteration number is not reached, the iteration calculation is continued; if the calculation result does not conform to the check rule and the preset maximum iteration number is reached, the decoding failure information is output.

[0095] If the calculation result does not conform to the check rule and the preset maximum iteration number is not reached, the decoding process continues the iteration calculation. Specifically, the parallel two-stage calculation is repeatedly performed on the matrix sub-blocks after the insertion, including the variable preparation stage and the variable operation stage, to update the information of the variable nodes and the check nodes, further optimize the decoding result, until the calculation result conforms to the check rule or the maximum iteration number is reached.

[0096] If the calculation result still does not conform to the check rule and the preset maximum iteration number is reached, the decoding failure information is output. Specifically, after the iteration for the set number of times, if the data satisfying the check rule is still not successfully restored, at this time, other measures may need to be taken, for example, adjusting the decoding parameters, checking the quality of the received signal or using other decoding algorithms, etc., to solve the decoding failure problem. In this way, by outputting the decoding failure information, it is ensured that the decoding process is completed within a limited time and resources, avoiding the unlimited attempt of the decoding which cannot be successfully completed, and improving the decoding efficiency and reliability.

[0097] It should be noted that the present application only improves the operation form in the decoding process, and the data used in the decoding process, the specific calculation content, and the format and content of the final output decoding result can all refer to the decoding process of the conventional LDPC code, which will not be described here.

[0098] In this way, the embodiment of the present application realizes parallel decoding without significantly increasing resource consumption by dividing the check matrix into multiple matrix sub-blocks to perform parallel calculation, thereby effectively improving the calculation speed. At the same time, by accurately calculating the sub-block length of each matrix sub-block and performing layer order adjustment and layer insertion operation (including intra-layer insertion and inter-layer insertion) according to the matrix sub-block synchronization principle, the problem of inconsistent calculation timing and waiting delay caused by the misalignment of each layer calculation is successfully solved, ensuring the uniformity of the calculation timing, thereby effectively reducing the decoding delay and significantly improving the LDPC decoding efficiency.

[0099] Figure 5 The implementation flowchart of the layer order adjustment and layer insertion operation of the parallel decoding method provided by the embodiment of the present application is shown.

[0100] Reference Figure 5In one embodiment of this application, the above-mentioned operation 101, based on the matrix sub-block synchronization principle and the sub-block lengths of multiple matrix sub-blocks in each layer of the split verification matrix, adjusts the layer order and inserts layers into multiple matrix sub-blocks, including: operation 201, for each matrix sub-block in each layer, inserts other matrix sub-blocks in the current layer into layers according to the number of matrix sub-blocks with the largest sub-block length in the current layer; operation 202, calculates the layer length of each layer after layer insertion, and adjusts the layer order of multiple matrix sub-blocks after layer insertion according to the layer length of each layer; operation 203, inserts layers into all matrix sub-blocks in each layer according to the layer lengths of all layers after layer order adjustment.

[0101] In one embodiment of this application, the sub-block length is the number of matrix blocks contained in the matrix sub-block, and the layer length is the sum of the number of matrix blocks in all matrix sub-blocks in the corresponding layer.

[0102] In operation 201, for each matrix sub-block within a layer, interpolation is performed on the other matrix sub-blocks within the current layer according to the number of matrix sub-blocks with the largest sub-block length among the matrix sub-blocks in the current layer.

[0103] For each matrix sub-block within a layer, first determine the sub-block length of all matrix sub-blocks within the current layer, and find the matrix sub-block with the largest sub-block length. Then, using the number of matrix sub-blocks as a benchmark, perform in-layer interpolation on the other matrix sub-blocks within the current layer. Specifically, insert blank matrix blocks into these shorter matrix sub-blocks, so that the length of all matrix sub-blocks within the layer is consistent with the length of the longest matrix sub-block. This ensures that during parallel computation, the matrix sub-blocks within the same layer can complete the computation synchronously, avoiding the problem of asynchronous operation caused by different lengths.

[0104] For example, see reference. Figure 6 , Figure 6 This diagram illustrates an example of the layer interpolation principle of the parallel decoding method provided in this application. Figure 6 The left and right sides of the image show two matrix sub-blocks respectively. Each row represents a layer. Taking the first row (layer) as an example, the process of inserting blanks in the layer can be regarded as obtaining the number of matrix blocks in the first layer of the matrix sub-blocks on the left and right sides. The left matrix blocks are 1, 2, 3, and 5, with a total of 4 matrix blocks. The right matrix blocks are 4, with a total of 1 matrix block. Based on the longest matrix sub-block in the layer, that is, the length of the left matrix sub-block is 4, insert 3 blank matrix blocks X into the right matrix sub-block in the same layer.

[0105] In operation 202, the layer length of each layer after interpolation is calculated, and the layer order of multiple matrix sub-blocks after interpolation is adjusted according to the layer length of each layer.

[0106] In an embodiment of the present application, the plurality of matrix sub-blocks after the intra-layer insertion of the blank is adjusted in layer sequence according to the layer length of each layer, including one of the following operations: sorting the layers according to the layer length from large to small; sorting the layers according to the layer length from small to large.

[0107] Each matrix sub-block of each layer is calculated twice, that is, parallel double-stage calculation. In actual calculation, if the calculation of a layer enters the parallel second-stage calculation, the parallel first-stage calculation of the next layer can be started. However, due to the inconsistency of the layer length of each layer, there may be a case that the parallel first-stage calculation of the next layer is completed, but the parallel second-stage calculation of the previous layer is not completed, at which time it is necessary to wait until the parallel second-stage calculation of the previous layer is completed before proceeding, resulting in a large amount of delay in the decoding process. In order to avoid the inter-layer waiting, an embodiment of the present application designs an inter-layer insertion method, that is, if the overall length of the next layer is shorter than that of the previous layer, all parts of the next layer are inserted with a blank until the lengths of the two layers are consistent.

[0108] According to the unique properties of the check matrix, exchanging any two rows of the check matrix will not change the check result, nor will it change the error correction capability of the check matrix. That is, since the layered decoding scheme is layered by rows, adjusting the calculation sequence of all layers will not change the decoding result. An embodiment of the present application also designs a layer sequence adjustment method to reduce the number of inter-layer insertion of the blank.

[0109] Specifically, after the intra-layer insertion of the blank is completed, the layer length of each layer is calculated. The layer length refers to the sum of the number of matrix blocks of all matrix sub-blocks in the layer. According to the layer length of each layer, the plurality of matrix sub-blocks after the intra-layer insertion of the blank is adjusted in layer sequence. Specifically, each layer can be reordered in the order of the layer length from large to small or from small to large, thereby determining the calculation sequence of each layer, optimizing the overall operation process, enabling more efficient use of computing resources in subsequent parallel calculation, reducing unnecessary waiting time, and further improving decoding efficiency. The layer sequence adjustment can be understood as adjusting the sequence of each row of the matrix sub-block.

[0110] Under normal circumstances, since the overall operation is in the form of multiple rounds of iteration, it can be considered that the last layer and the first layer are connected, and the insertion amount is consistent when arranged in the order of small to large and large to small. Therefore, both the arrangement from small to large and the arrangement from large to small can be selected, but in order to better solve the column conflict problem, the arrangement that can make the column insertion amount of each layer uniform after sorting is preferred.

[0111] In operation 203, all matrix sub-blocks in each layer are inserted with a blank between layers according to the layer length of all layers after the layer sequence adjustment.

[0112] According to the layer length of each layer determined after the layer sequence adjustment, interlayer insertion gaps are formed in each layer. The interlayer insertion gap is formed by inserting a blank matrix block between different layers so that the total length of adjacent layers is consistent. Specifically, for two adjacent layers, according to the number of matrix blocks of the layer with a larger layer length, a corresponding number of blank matrix blocks are inserted in the shorter layer until the layer length of the two adjacent layers is consistent. For example, if the layer length of each layer arranged in sequence after adjustment is 12, 10, respectively, when the interlayer insertion gap is formed, 2 blank matrix blocks need to be inserted in the second layer so that the length of the second layer becomes 12.

[0113] In the formula, the insertion gap is the insertion of a blank matrix block, which does not participate in actual calculation in the calculation process and only plays a role in occupying space and alignment.

[0114] In this way, the embodiment of the present application ensures that the lengths of the matrix subblocks in the same layer are consistent through the intra-layer insertion gap, realizes the synchronous completion of parallel calculation, reduces the waiting time through the layer sequence adjustment and layer length sorting, and avoids the operation delay through the interlayer insertion gap to make the total length of each layer consistent. Thus, the decoding efficiency is significantly improved, the decoding delay is reduced, the waste of hardware resources is avoided, and the decoding process is ensured to be efficient and orderly.

[0115] Figure 7 An implementation flowchart of the iterative calculation operation of the parallel decoding method provided by the embodiment of the present application is shown.

[0116] Reference Figure 7 In an embodiment of the present application, the operation 103 is to perform parallel two-stage calculation on the plurality of matrix subblocks in each layer after the insertion gap until the calculation result meets the check rule to generate the decoding result, including: operation 301, iteratively performing parallel two-stage calculation on the plurality of matrix subblocks in each layer after the insertion gap; operation 302, after each round of iterative calculation, checking whether the calculation result meets the check rule; and operation 303, if the calculation result meets the check rule, integrating the calculation results of all the matrix subblocks to generate the decoding result.

[0117] In operation 301, the plurality of matrix subblocks in each layer after the insertion gap are iteratively calculated in parallel.

[0118] In an embodiment of the present application, the parallel two-stage calculation includes: in the variable preparation stage, calculating the information transmitted from the variable node to the check node and integrating the calculation result; and in the variable operation stage, according to the integrated calculation result, calculating the information transmitted from the check node to the variable node and the new value of the variable node after decoding.

[0119] Specifically, the parallel two-stage calculation is divided into two main stages, a variable preparation stage and a variable operation stage. In the variable preparation stage, the main task is to calculate the information passed from the variable node to the check node. This process is based on the received signal and a priori information to make a probability calculation to obtain the information passed from the variable node to the check node. After the calculation is completed, these messages are integrated for use in subsequent check node calculations. The integration is usually a summary and processing of the information of each variable node to form a comprehensive input for the check node.

[0120] In the variable operation stage, according to the integrated calculation results of the variable preparation stage, the information sent from the check node to the variable node and the new value of the variable node after decoding are calculated.

[0121] In operation 302, after each round of iterative calculation, it is checked whether the calculation result meets the check rule.

[0122] After each round of iterative calculation, the calculation result needs to be strictly checked to determine whether it meets the preset check rule. The check rule is mainly based on the check equations of the LDPC code, which are defined by the check matrix. Specifically, each check equation corresponds to a row in the check matrix, which is used to verify whether the corresponding parity check condition is met. In the check process, the parity check condition of each check node is checked one by one, and after ensuring that all conditions are met, it is determined that the calculation result meets the check rule.

[0123] In operation 303, if the calculation result meets the check rule, the calculation results of all the matrix subblocks are integrated to generate a decoding result.

[0124] If the calculation result meets the check rule, the calculation results of all the matrix subblocks are integrated to generate a decoding result. Among them, the integration process can be regarded as combining the estimated values or probability information of the variable nodes of each matrix subblock according to the original structure of the check matrix to form a complete codeword estimate value or its corresponding binary bit sequence, and obtaining the final decoding result.

[0125] Figure 8 A composition structure schematic diagram of a decoder provided by an embodiment of the application is shown.

[0126] Reference Figure 8 Based on the above parallel decoding method, an embodiment of the application further provides a decoder, also known as an LDPC decoder, which comprises:

[0127] An acquisition module is configured to acquire a check matrix to be decoded, and split the check matrix into a plurality of matrix subblocks according to a set matrix splitting manner.

[0128] The parallel decoding module is configured to calculate sub-block lengths of the plurality of matrix sub-blocks in each layer of the split check matrix, and perform layer sequence adjustment and layer insertion according to the matrix sub-block synchronization principle and the sub-block lengths of the plurality of matrix sub-blocks in each layer of the split check matrix, wherein the layer insertion includes intra-layer insertion and inter-layer insertion; and perform parallel two-stage calculation on the plurality of matrix sub-blocks in each layer after the layer sequence adjustment, until the calculation result meets the check rule, to generate a decoding result.

[0129] In an embodiment of the present application, the set matrix splitting mode includes a parity column splitting mode or a front and rear column splitting mode; correspondingly, the obtaining module includes one of the following:

[0130] The first splitting submodule is configured to, in a case where the set matrix splitting mode is the parity column splitting mode, split the check matrix into matrix sub-blocks of odd columns and matrix sub-blocks of even columns.

[0131] The second splitting submodule is configured to, in a case where the set matrix splitting mode is the front and rear column splitting mode, split the check matrix from a middle position of columns into matrix sub-blocks of front half columns and matrix sub-blocks of rear half columns.

[0132] In an embodiment of the present application, the parallel decoding module includes a layer control submodule, which is configured to, for the matrix sub-blocks in each layer, perform intra-layer insertion on other matrix sub-blocks in the current layer according to the matrix block quantity of the matrix sub-block with the maximum sub-block length among the matrix sub-blocks in the current layer; calculate the layer length of each layer after the intra-layer insertion, and perform layer sequence adjustment on the plurality of matrix sub-blocks after the intra-layer insertion according to the layer length of each layer; and perform inter-layer insertion on all the matrix sub-blocks in each layer according to the layer length of all the layers after the layer sequence adjustment.

[0133] In an embodiment of the present application, the layer control submodule includes one of the following units:

[0134] The first sorting unit is configured to sort the layers from large to small according to the layer length.

[0135] The second sorting unit is configured to sort the layers from small to large according to the layer length.

[0136] In an embodiment of the present application, the parallel decoding module includes a plurality of matrix block operation submodules and a check submodule, the plurality of matrix block operation submodules are configured to perform parallel two-stage calculation on the plurality of matrix sub-blocks in each layer after the insertion; the check submodule is configured to check whether the calculation result meets the check rule after each round of iterative calculation; and the plurality of matrix block operation submodules are further configured to, if the calculation result meets the check rule, integrate the calculation results of all the matrix sub-blocks to generate a decoding result.

[0137] In an implementation, the decoder further comprises:

[0138] The first judging module is configured to continue the iterative calculation if the calculation result does not conform to the check rule and the preset maximum iteration number is not reached.

[0139] The second judging module is configured to output a decoding failure information if the calculation result does not conform to the check rule and the preset maximum iteration number is reached.

[0140] Specifically, the parallel decoding module is divided into a layer control submodule, a plurality of matrix operation submodules, a layer operation submodule and a check submodule. The layer control submodule is configured to calculate the subblock length of the plurality of matrix subblocks in each layer of the split check matrix, and to adjust the layer sequence and insert a blank in each layer according to the matrix subblock synchronization principle and the subblock length of the plurality of matrix subblocks in each layer of the split check matrix, and to control the plurality of matrix operation submodules to operate. The plurality of matrix operation submodules are configured to perform parallel two-stage calculation on the plurality of matrix subblocks in each layer after the blank insertion based on the control of the layer control submodule according to the arrangement sequence of each layer after the layer sequence adjustment, and to send the calculation result to the check submodule and the layer operation submodule. The check submodule is configured to judge whether the calculation result conforms to the check rule. The layer operation submodule is configured to integrate the calculation result of the plurality of matrix subblocks in each layer into a calculation result of one layer and send the calculation result to each matrix operation submodule as input data for the next iteration operation.

[0141] The working process of the LDPC decoder can be considered as that, when data is input, the acquisition module sends the split matrix subblocks to the plurality of matrix block operation submodules according to the check matrix splitting scheme (matrix splitting mode is set), the matrix operation submodules operate according to the signals sent by the layer control submodule, the calculation result is sent to the layer operation submodule for operation of one layer after the operation of one layer is completed. The calculation result of the layer operation submodule will become the input data for the next iteration of the matrix block operation submodule. Meanwhile, the current calculation result is continuously sent to the check submodule while the matrix block operation submodule operates, and the check submodule checks whether the check is passed. If the check is passed, it means that the decoding is completed, the data of the matrix block operation submodule is re-integrated into a complete data to form a decoding result, and the decoding result is output. If the calculation result does not conform to the check rule and the preset maximum iteration number is not reached, the iterative calculation is continued; if the calculation result does not conform to the check rule and the preset maximum iteration number is reached, a decoding failure information is output.

[0142] Figure 9 A component structure diagram of the matrix block operation submodule of the decoder provided by the embodiment of the application is shown.

[0143] In an embodiment of the present application, the matrix block operation sub-module comprises a variable preparation unit and a variable operation unit, the variable preparation unit is configured to calculate the information transmitted from the variable node to the check node and integrate the calculation result in the variable preparation stage; and the variable operation unit is configured to calculate the information transmitted from the check node to the variable node and the new value of the variable node after decoding according to the integrated calculation result in the variable operation stage.

[0144] Specifically, the matrix operation sub-module is divided into a variable preparation unit and a variable operation unit, the variable preparation unit is connected with the layer control sub-module and the layer operation sub-module, and the variable operation unit is connected with the layer operation sub-module and the check sub-module. In the matrix block operation sub-module, each matrix sub-block is calculated twice, the first time is in the variable preparation unit, the information transmitted from the variable node to the check node is calculated, and after the calculation is completed, the calculation result is sent to the layer operation sub-module for integration. Then, the layer operation sub-module sends the integrated result to the variable operation unit, and the information transmitted from the check node to the variable node and the new value of the variable node after decoding are calculated.

[0145] It should be noted that the description of the decoder of the embodiment of the present application is similar to the description of the method embodiment, has similar beneficial effects as the method embodiment, and thus will not be described herein. For the technical details not described in the decoder provided by the embodiment of the present application, they can be understood according to the description of any one of the accompanying drawings. Figure 1 to Figure 7

[0146] According to the embodiments of the present application, the present application further provides an electronic device and a readable storage medium.

[0147] Figure 10 A schematic block diagram of an example electronic device 400 that can be used to implement embodiments of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application described and / or claimed in this document.

[0148] As Figure 10 ​As shown, the device 400 includes a computing unit 401 that can perform various appropriate actions and processes in accordance with a computer program stored in a read-only memory (ROM) 402 or a computer program loaded from a storage unit 408 into a random access memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the device 400 can also be stored. The computing unit 401, the ROM 402, and the RAM 403 are connected to each other through a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0149] A plurality of components in the device 400 are connected to the I / O interface 405, including: an input unit 406, such as a keyboard, a mouse, etc.; an output unit 407, such as various types of displays, speakers, etc.; a storage unit 408, such as a magnetic disk, an optical disk, etc.; and a communication unit 409, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 409 allows the device 400 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0150] The computing unit 401 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 401 performs various methods and processes described above, such as the parallel decoding method. For example, in some embodiments, the parallel decoding method can be implemented as a computer software program that is tangibly embodied in a machine-readable medium, such as the storage unit 408. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 400 via the ROM 402 and / or the communication unit 409. When the computer program is loaded into the RAM 403 and executed by the computing unit 401, one or more steps of the parallel decoding method described above can be performed. Alternatively, in other embodiments, the computing unit 401 can be configured to perform the parallel decoding method by any other appropriate means, such as by means of firmware.

[0151] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, specially designed application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0152] Program code for carrying out methods of the present application can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces a means for implementing the functions / acts specified in the flowcharts and / or block diagrams. The program code can be executed entirely on a machine, partially on a machine, fully on a machine and partially on a remote machine or entirely on a remote machine or server.

[0153] In the context of the present application, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0154] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0155] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0156] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server is generally established by computer programs running on the respective computers and having a client-server relationship to each other. The servers can be cloud servers, servers of a distributed system, or servers combined with a blockchain.

[0157] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present application can be executed in parallel, in series, or in a different order, without departing from the desired results of the technology disclosed in the present application, and are not limited herein.

[0158] In addition, the terms "first", "second", etc., are used herein only to describe different instances, and do not imply or suggest relative importance or imply the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0159] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A parallel decoding method, characterized by, The method comprises: acquiring a check matrix to be decoded, and dividing the check matrix into a plurality of matrix sub-blocks according to a set matrix division mode; calculating the sub-block length of the plurality of matrix sub-blocks in each layer of the divided check matrix, and adjusting the layer order and inserting a gap in each layer of the plurality of matrix sub-blocks according to the matrix sub-block synchronization principle and the sub-block length of the plurality of matrix sub-blocks in each layer of the divided check matrix, wherein the gap insertion in each layer comprises intra-layer gap insertion and inter-layer gap insertion; performing parallel two-stage calculation on the plurality of matrix sub-blocks in each layer after the layer order adjustment according to the arrangement order of each layer, until the calculation result meets the check rule, to generate a decoding result; wherein the set matrix division mode comprises a parity column division mode or a front and rear column division mode; correspondingly, dividing the check matrix into a plurality of matrix sub-blocks according to the set matrix division mode comprises one of the following operations: in the case that the set matrix division mode is the parity column division mode, dividing the check matrix into matrix sub-blocks of odd columns and matrix sub-blocks of even columns; in the case that the set matrix division mode is the front and rear column division mode, dividing the check matrix into matrix sub-blocks of front half columns and matrix sub-blocks of rear half columns from the middle of the columns; adjusting the layer order and inserting a gap in the plurality of matrix sub-blocks according to the matrix sub-block synchronization principle and the sub-block length of the plurality of matrix sub-blocks in each layer of the divided check matrix, comprising: for the matrix sub-blocks in each layer, inserting a gap in other matrix sub-blocks in the current layer according to the number of matrix blocks of the matrix sub-block with the maximum sub-block length among the matrix sub-blocks in the current layer; calculating the layer length of each layer after the intra-layer gap insertion, and adjusting the layer order of the plurality of matrix sub-blocks after the intra-layer gap insertion according to the layer length of each layer; inserting a gap among the layers according to the layer length of all layers after the layer order adjustment.

2. The method of claim 1, wherein, The sub-block length is the number of matrix blocks contained in the matrix sub-block, and the layer length is the sum of the number of matrix blocks of all matrix sub-blocks in the corresponding layer.

3. The method of claim 1, wherein, Adjusting the layer order of the plurality of matrix sub-blocks after the intra-layer gap insertion according to the layer length of each layer comprises one of the following operations: sorting the layers from large to small according to the layer length; sorting the layers from small to large according to the layer length.

4. The method of claim 1, wherein, Performing parallel two-stage calculation on the plurality of matrix sub-blocks in each layer after the gap insertion, until the calculation result meets the check rule, to generate a decoding result, comprising: iteratively performing parallel two-stage calculation on the plurality of matrix sub-blocks in each layer after the gap insertion; after each round of iterative calculation, checking whether the calculation result meets the check rule; if the calculation result meets the check rule, integrating the calculation result of the current all matrix sub-blocks to generate a decoding result.

5. The method of claim 4, wherein, The parallel two-stage calculation comprises: in the variable preparation stage, calculating the information transmitted from the variable node to the check node, and integrating the calculation result; in the variable operation stage, calculating the information transmitted from the check node to the variable node and the new value of the variable node after decoding according to the integrated calculation result.

6. The method of claim 1, wherein, The method further comprises: if the calculation result does not meet the check rule and the preset maximum number of iterations has not been reached, continuing the iterative calculation; if the calculation result does not meet the check rule and the preset maximum number of iterations has been reached, outputting a decoding failure information.

7. A decoder, characterized in that The decoder comprises: an acquisition module, configured to acquire a check matrix to be decoded, and split the check matrix into a plurality of matrix subblocks according to a set matrix splitting mode; a parallel decoding module, configured to calculate the subblock length of the plurality of matrix subblocks in each layer of the check matrix after splitting, and perform layer sequence adjustment and layer insertion on the plurality of matrix subblocks according to the matrix subblock synchronization principle and the subblock length of the plurality of matrix subblocks in each layer of the check matrix after splitting, wherein the layer insertion comprises intra-layer insertion and inter-layer insertion; and perform parallel two-stage calculation on the plurality of matrix subblocks in each layer after the layer sequence adjustment according to the arrangement sequence of each layer, until the calculation result meets a check rule, to generate a decoding result; wherein the set matrix splitting mode comprises a parity column splitting mode or a front and rear column splitting mode; correspondingly, the acquisition module comprises one of the following: a first splitting submodule, configured to, in the case that the set matrix splitting mode is the parity column splitting mode, divide the check matrix into matrix subblocks of odd columns and matrix subblocks of even columns; a second splitting submodule, configured to, in the case that the set matrix splitting mode is the front and rear column splitting mode, divide the check matrix into matrix subblocks of front half columns and matrix subblocks of rear half columns from the middle of columns; the parallel decoding module comprises: a layer control submodule, configured to, for the matrix subblocks in each layer, perform intra-layer insertion on other matrix subblocks in the current layer according to the matrix block quantity of the matrix subblock with the maximum subblock length among the matrix subblocks in the current layer; calculate the layer length of each layer after the intra-layer insertion, and perform layer sequence adjustment on the plurality of matrix subblocks after the intra-layer insertion according to the layer length of each layer; and perform inter-layer insertion on all the matrix subblocks in each layer according to the layer length of all the layers after the layer sequence adjustment.

8. The decoder of claim 7, wherein, The layer control submodule comprises one of the following units: a first sorting unit, configured to sort the layers from large to small according to the layer length; a second sorting unit, configured to sort the layers from small to large according to the layer length.

9. The decoder of claim 7, wherein, The parallel decoding module further comprises: a plurality of matrix block operation submodules, configured to perform parallel two-stage calculation on the plurality of matrix subblocks in each layer after the insertion in iteration; a check submodule, configured to check whether the calculation result meets the check rule after each round of iteration calculation; The plurality of matrix block operation submodules are further configured to, if the calculation result meets the check rule, integrate the calculation result of all the matrix subblocks to generate a decoding result.

10. The decoder of claim 9, wherein, The matrix block operation submodule comprises: a variable preparation unit, configured to calculate the information passed from a variable node to a check node in a variable preparation stage, and integrate the calculation result; a variable operation unit, configured to calculate the information sent from the check node to the variable node and the new value of the variable node after decoding according to the integrated calculation result in a variable operation stage.

11. The decoder of claim 7, wherein, The decoder further comprises: a first judgment module, configured to, if the calculation result does not meet the check rule and the preset maximum iteration number has not been reached, continue iteration calculation; a second judgment module, configured to, if the calculation result does not meet the check rule and the preset maximum iteration number has been reached, output a decoding failure information.

12. An electronic device, comprising: comprise: at least one processor; and a memory connected in communication with the at least one processor; wherein, The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

13. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, The computer instructions are for causing a computer to perform the method of any one of claims 1-6.

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