Data processing method, storage medium and electronic equipment

Abstract

The invention discloses a data processing method, a storage medium and an electronic device, and relates to the technical field of network communication, the data processing method comprises the following steps: receiving an FSK modulation signal sent by a target device, the FSK modulation signal comprising a synchronization head and target data; the synchronization head comprises a first frequency time period, and the synchronization head is identified according to the number of first frequency carriers received in the first frequency time period; and in the process of counting the number of the first frequency carriers, the time interval between the two adjacent first frequency carriers does not exceed the first timeout duration, so that the interference of abnormal signals in the communication process is reduced.

Description

Technical Field

[0001] The present invention relates to the field of network communication technologies, and in particular, to a data processing method, a storage medium, and an electronic device. Background Art

[0002] In the oil logging industry, when downhole instruments communicate and exchange data, there are problems of long communication distance and strong electromagnetic interference. During the communication process, abnormal signals are likely to be generated due to glitches or error messages, thereby interfering with the reception of normal data. Summary of the Invention

[0003] The present invention aims to at least solve one of the technical problems in the related art to some extent. To this end, an object of the present invention is to provide a data processing method, a storage medium, and an electronic device to reduce the interference of abnormal signals during the communication process. <(

[0004] According to a first aspect of an embodiment of the present invention, there is provided a data processing method, including:

[0005] Receiving an FSK modulation signal sent by a target device, where the FSK modulation signal includes a synchronization header and target data;

[0006] The synchronization header includes a first frequency time period, and the synchronization header is identified according to the number of first frequency carriers received in the first frequency time period;

[0007] During the process of counting the number of the first frequency carriers, the time interval between two adjacent first frequency carriers does not exceed a first timeout duration.

[0008] According to a second aspect of an embodiment of the present invention, there is provided a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the above data processing method is implemented.

[0009] According to a third aspect of an embodiment of the present invention, there is provided an electronic device, including: a memory and a processor; a computer program is stored on the memory, and when the computer program is executed by the processor, the above data processing method is implemented.

[0010] In the solution provided by the embodiment of the present invention, the synchronization header and the target data are sent in the form of an FSK modulation signal, so that before receiving the data, the synchronization header can be detected first. Thus, by determining whether there are a sufficient number of first frequency carriers in the first frequency time period, if so, it indicates that the synchronization header is correct and there is target data to be received, and then the target data is received and decoded. By buffering the synchronization header, the incorrect decoding of the valid data is avoided, thereby improving the correct rate of data processing and reducing the interference of abnormal signals.

[0011] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Description of the Drawings

[0012] Figure 1 is a schematic flowchart of a first data processing method provided by an embodiment of the present invention;

[0013] Figure 2 is a schematic flowchart of a second data processing method provided by an embodiment of the present invention;

[0014] Figure 3 is a schematic flowchart of a third data processing method provided by an embodiment of the present invention;

[0015] Figure 4 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed Embodiments

[0016] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0017] The data processing method, storage medium, and electronic device according to embodiments of the present invention will be described below with reference to the drawings.

[0018] In one embodiment of the present invention, referring to Figure 1 , a data processing method is provided, including the following steps S101-S102.

[0019] S101: Receive an FSK modulation signal sent by a target device. The FSK modulation signal includes a synchronization header and target data;

[0020] S102: The synchronization header includes a first frequency time period. Identify the synchronization header according to the number of first frequency carriers received in the first frequency time period. During the process of counting the number of first frequency carriers, the time interval between two adjacent first frequency carriers does not exceed a first timeout duration.

[0021] In the above steps, when the target device sends an FSK (Frequency Shift Keying) modulation signal, the synchronization header is added to the front of the target data.

[0022] In the case of receiving an FSK modulated signal, the sync header is converted into a square wave signal by a comparator, and the frequency of the square wave signal is judged by a single-chip microcomputer. Specifically, a voltage comparator is used to compare the amplitudes of the first-frequency carrier wave and the second-frequency carrier wave in the FSK modulated signal, and a threshold level is set. When the amplitude is higher than the threshold, a high level is output, for example, 3.3V is output; when it is lower than the threshold, a low level is output, for example, 0V is output. In this way, the FSK modulated signal is converted into a square wave signal, and the shortening of the battery life caused by the continuous high-frequency signal emission can be avoided.

[0023] The method for detecting the FSK modulated signal can be to collect the rising edge or falling edge of the earliest-occurring square wave signal as the valid edge. For example, taking the rising edge as the valid edge, record the acquisition timing of each rising edge. When collecting the current rising edge, compare the acquisition timing of this rising edge with the acquisition timing of the previous rising edge, so as to know the time interval between the current rising edge and the previous rising edge, and judge the period of the current square wave signal from this, so as to know the frequency of the square wave signal.

[0024] The square wave signal can have two frequencies, the first frequency and the second frequency. Specifically, multiple consecutive square wave signals with the first frequency can be used to represent binary 1. In the embodiment of the present invention, taking the first frequency representing binary 1 as an example, correspondingly, the frequency representing binary 0 is called the second frequency.

[0025] For example, the first frequency is set to 1 kHz, and the second frequency is set to 0.6 kHz. The specific numerical values of the set frequencies can be adjusted manually.

[0026] In some other embodiments, the first frequency can also represent binary 0, and correspondingly, the second frequency represents binary 1.

[0027] For the first frequency, if the time interval exceeds the first timeout duration, it is considered that there is an abnormality. For example, the previously received FSK modulated signal may be caused by noise.

[0028] According to the above steps, each received square wave signal can be counted, and the final count value is used as the number of first-frequency carrier waves. During the counting process, if the time interval between two square wave signals exceeds the first timeout duration, such as the time interval between the Xth square wave signal and the (X + 1)th square wave signal exceeds the first timeout duration, and the time intervals between adjacent two square wave signals among the previous X square wave signals do not exceed the first timeout duration, then the final count value is X.

[0029] In this case, it is judged whether X reaches the preset quantity threshold. If it reaches, the sync header is recognized. And the counter is reset to zero for re-counting when receiving the sync header next time.

[0030] When a sync header is recognized, the target data is received and processed, such as decoding or storing the target data, etc.

[0031] When the target device sends an FSK modulated signal and determines the frequency and duty cycle, a sine wave output can be achieved by the PWM module and the timer without the participation of the CPU. Therefore, the data modulation process will not cause a heavy load on the CPU.

[0032] The target device can be any type of electronic device, such as a server, a personal computer, etc., and the embodiments of the present invention do not limit this.

[0033] When recognizing the sync header, a single frequency time period can be used, that is, the first frequency time period is adopted, and the sequence of the sync header is specified as: a sequence composed of 0xFF and 0x00. Specifically, 0xFF can be set first as needed, or 0x00 can be set first, or a sequence formed by other numbers of 0s and 1s can also be set.

[0034] For example, if the first frequency time period is 8 ms and the first frequency represents binary 1, the number of first frequency carriers exceeds 1000, that is, at least 1000 first frequency carriers are received in 8 ms, that is, the sine wave with the first frequency in the FSK modulated signal, it is determined that the sync header is recognized.

[0035] In an embodiment of the present invention, two frequency time periods can be set to respectively count the numbers of binary 1 and binary 0 included in the FSK modulated signal, so as to determine whether a sync header with a preset binary sequence is received. Referring to the subsequent embodiments, the first frequency time period and the second frequency time period can be set simultaneously, which can achieve the determination under the condition of receiving a partial sync header, thereby improving the efficiency.

[0036] After adding the sync header to the target data, the target device can place it in a data packet and send it as a whole.

[0037] The decoding method of the target data corresponds to the encoding method of the target data, such as Base64 encoding and decoding, etc., and the embodiments of the present invention do not limit this.

[0038] In the solution provided by the embodiments of the present invention, the sync header and the target data are sent as an FSK modulated signal, so that before receiving the data, the sync header can be detected first. Thus, by judging whether there are enough numbers of first frequency carriers in the first frequency time period, if so, it means that the sync header is correct and there is target data to be received, and then the target data is received and decoded. By buffering the sync header, the incorrect decoding of the valid data can be avoided, thereby improving the correct rate of data processing and reducing the interference of abnormal signals.

[0039] In one embodiment, the synchronization header includes a second frequency time period, and the synchronization header is identified according to the number of second frequency carriers received in the second frequency time period and the number of first frequency carriers.

[0040] During the process of counting the number of second frequency carriers, the time interval between two adjacent second frequency carriers does not exceed the second timeout duration.

[0041] The counting method of the number of second frequency carriers and the timeout determination method of the second timeout duration are completely similar to the counting method of the number of first frequency carriers and the timeout determination method of the first timeout duration in the foregoing embodiment, and the difference is only the replacement of the name concept.

[0042] For example, when the binary sequence in the synchronization header is 0xFF first and 0x00 second, first determine whether the number of first frequency carriers reaches the preset first quantity within the first frequency time period of 8 ms, and then determine whether the number of second frequency carriers reaches the preset second quantity within the next second frequency time period of 8 ms. If both are reached, the synchronization header is identified.

[0043] The first quantity and the second quantity may be the same or different, and the durations of the first and second frequency time periods may be the same or different. The embodiments of the present invention do not limit this.

[0044] In this way, it is possible to directly determine that there is no synchronization header and interrupt the detection in case of timeout, instead of always waiting until the duration threshold timing is completed to determine that there is no synchronization, which can further save time and improve the decoding efficiency.

[0045] As Figure 2 shown, when 0xFF is first and 0x00 is second in the synchronization header, the process of identifying the synchronization header can be implemented based on a state machine. Among them, the decoding idle state is the initial state where decoding has not started and the synchronization header has not been detected yet. When a valid edge is received, the state switches from the decoding idle state to the synchronization state 1.

[0046] If the synchronization state 1 times out, that is, during the process of counting the number of first frequency carriers, when the time interval between two adjacent first frequency carriers exceeds the first timeout duration and the number of first frequency carriers does not exceed the first quantity, it returns to the decoding idle state;

[0047] If the synchronization state 1 does not time out and the number of 1 kHz square waves received is greater than F0_BYTE_CNT_TH, where 1 kHz is the first frequency corresponding to binary 1 and F0_BYTE_CNT_TH is the first quantity, in this case, the state machine switches to the synchronization state 2.

[0048] If the synchronization state 2 times out, that is, during the process of counting the number of second-frequency carriers, when the time interval between two adjacent second-frequency carriers exceeds the second timeout duration, and the number of second-frequency carriers does not exceed the second quantity, then it resumes to the decoding idle state; similar to the synchronization state 1, resuming to the decoding idle state is equivalent to determining that the synchronization header has not been received.

[0049] If the synchronization state 2 does not time out and the number of received 0.6 kHz square waves is greater than F0_BYTE_CNT_TH, where 0.6 kHz is the second frequency, corresponding to binary 0, and F0_BYTE_CNT_TH is the second quantity, in this case, the state machine switches to the data decoding state, that is, it is determined that the synchronization header has been received. In this embodiment, the first quantity and the second quantity are the same. In some other embodiments, the first quantity and the second quantity can also be set to different values.

[0050] In the data decoding state, after decoding a specified number of target data, it switches back to the decoding idle state and waits for the next synchronization header.

[0051] In the above embodiments, the synchronization header is judged by first detecting the binary 1 sequence and then detecting the binary 0 sequence. In some other embodiments, if the binary 0 sequence of the synchronization header is in the front, it can also first detect the binary 0 sequence and then detect the binary 1 sequence. Similar to the above method, the difference is only the replacement of the step order.

[0052] According to the above method, as long as a partial synchronization header is received and the number of carriers reaches the preset quantity condition, the determination can be completed and decoding can be performed, thereby improving the efficiency. Moreover, the binary sequence in the synchronization header may also be interfered by abnormal signals. However, by setting the judgment conditions of the first quantity and the second quantity, it can be realized that the determination can still be completed and the target data can be received even when the synchronization header is not severely missing.

[0053] In one embodiment, in one embodiment, the FSK modulation signal includes a first original frequency and a second original frequency. Based on a preset local oscillator frequency, the first original frequency and the second original frequency are down-converted to obtain a first-frequency carrier and a second-frequency carrier.

[0054] The specific implementation of down-conversion processing is as follows: The received FSK modulated signal contains sine wave signals of two frequencies, F1 hz and F2 hz. F1 hz is the first original frequency, and F2 hz is the second original frequency, mixed with a sine wave of the local oscillator frequency F3 hz. That is, the sine waves of F1 hz and F2 hz are respectively ±F3 hz, so as to obtain sine waves of (F1 - F3) hz, (F2 - F3) hz and (F1 + F3) hz, (F2 + F3) hz. Among them, (F1 - F3) hz and (F2 - F3) hz are low-frequency components. If it is preset that F1 hz corresponds to binary 1, then the sine wave of (F1 - F3) hz is the first frequency carrier, and if F2 hz corresponds to binary 0, then the sine wave of (F2 - F3) hz is the second frequency carrier, which is retained by means of low-pass filtering, and the square waves of (F1 + F3) hz and (F2 + F3) hz are filtered out as high-frequency components.

[0055] In this way, if there are abnormal signals in the FSK modulated signal, such as some low-frequency noises, after mixing, they will become high-frequency noises and be filtered out. For example, in the underground environment, there is a noise of 0.5 khz. In the FSK modulated signal, the 8.5 khz square wave represents binary 1, and the 8 khz square wave represents binary 0. Mixing is carried out with 7 khz. The 0.5 khz noise generates a 6.5 khz component as a high-frequency component after mixing, while the 8.5 khz square wave and the 8 khz square wave will generate low-frequency components of 8.5 - 7 = 1.5 khz and 8 - 7 = 1 khz, which can be filtered out by low-pass filtering. For example, it can be set that frequencies higher than 2 khz are all filtered, so that the noise can be filtered out, thereby optimizing for the underground high-temperature, high-pressure, and strong electromagnetic interference environment and improving signal stability.

[0056] In some other embodiments, if the noise in the environment has little influence, the mixing process can also be omitted, and the signal frequencies in the FSK modulated signal can be directly measured, and the sine wave with a frequency of F1 is obtained as the first frequency carrier, and the sine wave with a frequency of F2 is obtained as the second frequency carrier.

[0057] In one embodiment of the present invention, the first timeout duration is determined based on the abnormal probability of the first frequency and the first frequency carrier.

[0058] The abnormal probability refers to the probability of the occurrence of abnormal signals. The normal signals refer to the sine wave signals of the first frequency and the second frequency received; on the contrary, the abnormal signals refer to the sine wave signals representing noises, glitches, and error messages received.

[0059] According to the abnormal probability and the first frequency, the expected waiting period can be determined, and thus the first timeout duration is set according to the expected waiting period.

[0060] The above-mentioned expected waiting period refers to a set period during which normal signals are continuously received with a probability not less than the preset expectation. For example, when the expected waiting period is 4, for the first timeout duration, it means that normal signals can be continuously received for 4 periods.

[0061] Specifically, the calculation method of the first timeout duration is as follows:

[0062]

[0063] Among them, x represents the expected waiting period of the first frequency carrier in the first timeout duration, which is the ceiling value of the expected waiting period; f1 represents the first original frequency; f represents the local oscillator frequency.

[0064] Among them, the expected waiting period is obtained in the following way:

[0065] Obtain the occurrence frequencies of abnormal signals corresponding to multiple historical synchronization headers; among them, for each historical synchronization header, calculate the occurrence frequency k1 in the following way:

[0066]

[0067] Among them, f1 represents the first original frequency; f represents the local oscillator frequency; n1 represents the actual number of square wave receptions corresponding to the first frequency when receiving the historical synchronization header; n represents the number of binary 1 encodings in the historical synchronization header; t represents the encoding time of each bit of data;

[0068] The historical synchronization header is a synchronization header of the same type received previously. The same type means having the same preset binary sequence in step S102. Correspondingly, for the occurrence frequency of the abnormal signal, when determining whether the historical synchronization header has the preset binary sequence, it is the number of occurrences of the abnormal signal received per unit time.

[0069] The encoding time is a fixed value. For example, set the encoding time to 0.5s. Then every 0.5 seconds is used as a time period to transmit a binary 0 or 1.

[0070] Within this 0.5 seconds, the FSK modulation signals that the target device can send can include several sine wave signals representing binary 1 or sine wave signals representing binary 0. At the receiving end, that is, on the device applying the data processing method provided in the embodiment of the present invention, then every 0.5 seconds, extract one or more sine wave frequencies from the square wave signals converted from the received sine wave signals, and determine whether 0 or 1 is transmitted in the current encoding time period based on the mode of the extracted frequencies (the extracted frequencies may have noise and are not completely frequencies representing 1 or 0).

[0071] If the variance of each obtained occurrence frequency is less than a preset variance threshold, the expected waiting period is calculated as follows:

[0072]

[0073] Where f1 represents the first original frequency; f represents the local oscillator frequency; represents the average value of each occurrence frequency; x represents the expected waiting period; N is the expected value of setting the filtered abnormal signal.

[0074] The value of N can be set manually or obtained by measurement. For example, the number of cycles of the actually filtered abnormal signal when receiving the historical synchronization header before measurement is used as the value of N.

[0075] When the variance of the occurrence frequency is less than the variance threshold, it can be considered that the discreteness of the occurrence frequency is low. In this case, using the average value for calculation is more representative statistically. Otherwise, the maximum value is used as in the following embodiments.

[0076] If the variance of each obtained occurrence frequency is not less than the variance threshold, the expected waiting period is calculated as follows:

[0077]

[0078] Where f1 represents the first original frequency; f represents the local oscillator frequency; max(B1) represents the maximum value of each occurrence frequency; x represents the expected waiting period; N is the expected value of setting the filtered abnormal signal.

[0079] The expected waiting period x is calculated according to the above two inequalities. The expression in the parentheses on the left side of the inequality represents the reciprocal of the abnormal signal occurrence probability. That is, the higher the abnormal signal occurrence probability, the smaller the expected waiting period is set accordingly, so as to adapt to environments with different degrees of noise interference.

[0080] The determination method of the second timeout duration is similar to the acquisition method of the foregoing first timeout duration, and is determined based on the local oscillator frequency, the second frequency of the second signal, and the abnormal probability of the second frequency carrier.

[0081] In the following embodiments, the second expected waiting period is similar to the foregoing expected waiting period x, and the only difference lies in the specific parameters used in the calculation. As follows, it can be calculated based on the following formula:

[0082]

[0083] Where y represents the second expected waiting period, f0 represents the second original frequency, and f represents the local oscillator frequency.

[0084] The calculation method of y is similar to that of x in the foregoing embodiments. For example, let n1 represent the actual number of square wave receptions corresponding to the first frequency when receiving historical synchronization headers, and n0 represent the actual number of square wave receptions corresponding to the second frequency.

[0085] Statistically analyze the previous n0 and n1 values to form a set A1 of n1 values = {n 11 , n 12 , n 13 …n 1m}, and a set A0 of n0 values = {n 01 , n 02 , n 03 , …n 0m}.

[0086] Among them, obtain the occurrence frequencies k1 according to A1, and obtain the corresponding occurrence frequency k0 of A0 in a similar manner.

[0087]

[0088] Among them, f, n, and t are the same as the formula for calculating k1, and f0 represents the second original frequency.

[0089] Similarly, the variance of the occurrence frequency k0 can be calculated. When the calculated variance is less than the variance threshold, calculate the second expected waiting period based on the average value of k0. If it is greater than the variance threshold, calculate the second expected waiting period based on the maximum value of k0, which is exactly similar to the formula for the expected waiting period x, except for the replacement of the name concept.

[0090] Based on the above method, if the timeout duration is set too long, the ability of the synchronization header to filter out glitches and error information is weak, because these abnormal information may be misidentified as the same group of synchronization headers as the subsequent correct synchronization headers, which is likely to cause the synchronization time to move forward; conversely, if the timeout duration is set too short, the synchronization time may move backward. For example, if some sine wave signals arrive later than the timeout duration due to network transmission delay, the reception of the synchronization header will be detected as a timeout and not recognized when the number of carrier waves at the first frequency or the second frequency is insufficient, and the target data may be discarded, resulting in incorrect square wave counting at the target frequency. By using the statistical value of the abnormal information in the historical synchronization header, a more appropriate timeout duration can be determined, and a more reasonable expected waiting period can be ensured with a higher probability, thereby improving the accuracy of receiving the synchronization header and subsequent target data.

[0091] In the above embodiments, the historical synchronization header can be obtained during the decoding process of the ground system monitoring single-chip microcomputer, and the above first and second timeout durations can be automatically determined.

[0092] In some other embodiments, the first and second timeout durations can also be set according to human experience or adjusted dynamically to improve the accuracy of sync header recognition and sync time judgment.

[0093] In one embodiment of the present invention, a check bit is set in the target data so that after receiving the target data, the checksum of the target data is calculated, and it is determined whether the target data is successfully received based on the comparison result between the checksum and the check bit.

[0094] When calculating the checksum, the bytes of the data can be added together to obtain a sum value, which is compared with the value of the check bit. If they are the same, it is determined that the target data is successfully received; otherwise, the received data is not successful.

[0095] The overall process of the above data processing method is described below through Figure 3 the embodiments shown.

[0096] First, wait for a valid edge to be detected; in the case of capturing a valid edge, perform sync header judgment and start timeout judgment, that is, identify the sync header based on the number of first-frequency carriers received in the first frequency time period and the number of second-frequency carriers received in the second frequency time period.

[0097] If a timeout or sync header error occurs, that is, the received sequence is not the binary sequence of the preset sync header, such as a binary sequence consisting of 1 first and then 0, then return to the waiting state; if the sync header is correct and there is no timeout, that is, during the counting of the number of first-frequency carriers, the time interval between adjacent first-frequency carriers does not exceed the first timeout duration, and during the counting of the number of second-frequency carriers, the time interval between adjacent second-frequency carriers does not exceed the second timeout duration, then decode the target data.

[0098] In one embodiment of the present invention, a computer-readable storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, the data processing method described in any of the above embodiments is implemented.

[0099] In one embodiment of the present invention, an electronic device is further provided, including: a memory, a processor; a computer program is stored on the memory, and when the computer program is executed by the processor, the data processing method described in any of the above embodiments is implemented.

[0100] Figure 4 is the structural block diagram of the electronic device according to the embodiment of the present invention.

[0101] As Figure 4As shown, the electronic device 400 includes: a processor 401 and a memory 403. Among them, the processor 401 and the memory 403 are connected, such as through a bus 402. Optionally, the electronic device 400 may further include a transceiver 404. It should be noted that in practical applications, the transceiver 404 is not limited to one, and the structure of the electronic device 400 does not constitute a limitation to the embodiments of the present invention.

[0102] The processor 401 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logical blocks, modules, and circuits described in connection with the disclosure of the present invention. The processor 401 may also be a combination that realizes computing functions, such as a combination including one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0103] The bus 402 may include a path for transmitting information between the above components. The bus 402 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus 402 may be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, Figure 4 only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus.

[0104] The memory 403 is used to store a computer program corresponding to the data processing method of the above embodiments of the present invention, and this computer program is controlled and executed by the processor 401. The processor 401 is used to execute the computer program stored in the memory 403 to implement the content shown in the foregoing method embodiments.

[0105] Among them, the electronic device 400 includes but is not limited to: mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 4The illustrated electronic device 400 is merely an example and should not impose any limitations on the functions and usage scope of the embodiments of the present invention.

[0106] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in combination with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in combination with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion (electronic device) having one or more wirings, a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other suitable processing as necessary, and then storing it in a computer memory.

[0107] It should be understood that various parts of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0108] In the description of this specification, the descriptions with reference to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0109] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0110] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0111] In the present invention, unless otherwise clearly specified and defined, terms such as "mounted", "connected", "connected to", "fixed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0112] In the present invention, unless otherwise expressly specified or limited, a first feature being "on" or "under" a second feature may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intermediate medium. Further, a first feature being "above", "over" and "on top of" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature has a higher level of height than the second feature. A first feature being "under", "below" and "beneath" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature has a lower level of height than the second feature.

[0113] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art may make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A data processing method, characterized in that, Including: Receiving an FSK modulated signal sent by a target device, where the FSK modulated signal includes a synchronization header and target data; The synchronization header includes a first frequency time period, and the synchronization header is identified according to the number of first frequency carriers received in the first frequency time period; During the process of counting the number of the first frequency carriers, the time interval between two adjacent first frequency carriers does not exceed a first timeout duration.

2. The method according to claim 1, characterized in that, The synchronization header includes a second frequency time period, and the synchronization header is identified according to the number of second frequency carriers received in the second frequency time period and the number of first frequency carriers; During the process of counting the number of the second frequency carriers, the time interval between two adjacent second frequency carriers does not exceed a second timeout duration.

3. The method according to claim 2, wherein The synchronization header is converted into a square wave signal through a comparator, and the frequency of the square wave signal is judged by a single-chip microcomputer.

4. The method according to claim 3, characterized in that, The FSK modulated signal includes a first original frequency and a second original frequency; Based on a preset local oscillator frequency, down-conversion processing is performed on the first original frequency and the second original frequency to obtain the first frequency carrier and the second frequency carrier.

5. The method according to claim 4, wherein The first timeout duration is determined based on the abnormal probability of the first frequency and the first frequency carrier.

6. The method according to claim 5, wherein The first timeout duration is calculated in the following manner: Where x represents the expected waiting period of the first frequency carrier in the first timeout duration; f1 represents the first original frequency; f represents the local oscillator frequency.

7. The method according to claim 6, characterized in that, The expected waiting period is obtained in the following manner: Obtaining the occurrence frequency of abnormal signals corresponding to multiple historical synchronization headers; where, for each historical synchronization header, the occurrence frequency k1 is calculated in the following manner: Where f1 represents the first original frequency; f represents the local oscillator frequency; n1 represents the actual number of square wave receptions of the first frequency corresponding to receiving the historical synchronization header; n represents the number of binary 1 encodings in the historical synchronization header; t represents the encoding time of each bit of data; If the variance of the obtained occurrence frequencies is less than a preset variance threshold, the expected waiting period is calculated in the following manner: Among them, f1 represents the first original frequency; f represents the local oscillator frequency; represents the average value of each occurrence frequency; x represents the expected waiting period; N is the expected value set for filtering abnormal signals; If the variance of the obtained occurrence frequencies is not less than the variance threshold, the expected waiting period is calculated in the following manner: Where f1 represents the first original frequency; f represents the local oscillator frequency; max(B1) represents the maximum value of the occurrence frequencies; x represents the expected waiting period; N is the expected value set for filtering abnormal signals.

8. The method according to claim 1, wherein A check bit is set in the target data, so that after receiving the target data, the checksum of the target data is calculated, and based on the comparison result between the checksum and the check bit, it is determined whether the target data is received successfully.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the data processing method described in any one of claims 1-8.

10. An electronic device, characterized in that, Including: A memory and a processor; A computer program is stored on the memory, and when the computer program is executed by the processor, it implements the data processing method described in any one of claims 1-8.

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