GMP-based signal STM-1 to OTN mapping method and system

Abstract

The present invention discloses a GMP-based STM-1 signal to OTN mapping method and system. The GMP-based STM-1 to OTN signal mapping method includes: multiplexing 2×7 channels of STM-1 frame data into 2 channels of STM1_MUX signals; mapping the 2 channels of STM1_MUX signals into 2 channels of ODU0 frames using GMP; mapping the 2 channels of ODU0 frames into 1 channel of OPU1 frames using AMP; encapsulating the OPU1 frames into ODU1 frames, and finally generating OTU1 frames. The GMP-based STM-1 to OTN signal mapping system includes: a management CPU, a transmitting-end FPGA1, a receiving-end FPGA2, a first OTN optical module, and a second OTN optical module. This method significantly saves bandwidth and reduces resource waste.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a method and system for mapping a signal STM-1 to OTN based on GMP. Background Art

[0002] With technological advancements, OTN (Optical Transport Network) has gradually replaced SDH (Synchronous Digital Hierarchy) as the mainstream transmission network technology. However, a large number of SDH devices are still in use in currently deployed transmission networks, necessitating a technology to transmit SDH signals over OTN networks to achieve compatibility between SDH and OTN networks. STM-N is a rate system within SDH, a universally accepted interface standard with the following rates: STM-1: 155M, STM-4: 622M, STM-16: 2488M, and STM-64: 10G. The current mainstream solution is to map an STM-1 or STM-4 signal to ODU0 using GMP (Generic Mapping Procedure), map an STM-16 signal to ODU1 using AMP, and map an STM-64 signal to ODU2 using AMP. ODU0 and ODU1 are terms in optical communications, representing different optical channel data units (OCDs).

[0003] However, the nominal rate of the low-speed SDH signal STM-1 is 155.52 Mbit / s, while the nominal rate of ODU0 is 1.244 Gbit / s. Currently, when using GMP mapping to map low-speed SDH signals STM-1 into ODU0 frames, the existing solution is to map one STM-1 channel into one ODU0 frame. Due to the significant rate difference between STM-1 and ODU0, the mapping process requires inserting a large amount of fixed stuff (FS) into the ODU0 payload area. This fixed stuff does not transmit data, resulting in significant bandwidth waste. Therefore, how to avoid this waste of bandwidth resources is an urgent issue. Summary of the Invention

[0004] To address the above problems, the present invention proposes a method and system for mapping STM-1 signals to OTN based on GMP.

[0005] To achieve the purpose of the present invention, a method for mapping a signal STM-1 to OTN based on GMP is provided, comprising the following steps:

[0006] s1: Based on the pre-enabled STM-1 interface numbers, the transmitting FPGA1 receives 2×7 channels of STM-1 frame data from the corresponding enabled interfaces. Simultaneously, the transmitting FPGA1 generates empty STM-1 frame data to replace the disabled STM-1 interfaces. The empty STM-1 data frame contains only the frame header overhead, with the rest of the data set being all zeros. This facilitates the receiving end in locating the frame header of the STM1_MUX signal.

[0007] s2: The transmitting end FPGA1 synchronizes the 2×7-channel STM-1 frame data to the system clock, performs framing, frame synchronization, and descrambling processing on the 2×7-channel STM-1 frame data, and numbers the processed 2×7-channel STM-1 frame data from 0 to 13 to obtain STM-1 frame data numbered 0 to 13 respectively;

[0008] s3: The transmitting end FPGA1 uses byte interleaving to time-division multiplex the STM-1 frame data numbered 0 to 6 into one STM1_MUX signal, and time-division multiplex the STM-1 frame data numbered 7 to 13 into another STM1_MUX signal;

[0009] s4: Map the two STM1_MUX signals into two ODU0 frames respectively through GMP mapping;

[0010] s5: The transmitting end FPGA1 maps the two ODU0 frames into OPU1 frames through AMP;

[0011] s6: The transmitting end FPGA1 adds the ODU1 overhead, OTU1 overhead, and frame header overhead to the OPU1 frame in sequence to form an OTU1 frame, then scrambles the OTU1 frame and sends the scrambled OTU1 frame to the OTN network through the OTN optical module.

[0012] s7: The receiving end FPGA2 receives the scrambled OTU1 frame from the OTN network, descrambles it, and obtains the OTU1 frame; obtains the two ODU0 frames from the OTU1 frame through AMP demapping;

[0013] s8: The receiving end FPGA2 extracts and obtains the two STM1_MUX signals from the two ODU0 frames through GMP demapping;

[0014] s9: The receiving end FPGA2 demultiplexes the two STM1_MUX signals respectively, obtains the 2×7 STM-1 frame data, and completes framing and frame synchronization;

[0015] s10: The receiving end FPGA2 confirms and obtains the STM-1 interface corresponding to the 2×7-channel STM-1 frame data based on the 2nd row and 6th column overhead of the 2×7-channel STM-1 frame data, sets the overhead to 0, scrambles the 2×7-channel STM-1 frame data, synchronizes the scrambled 2×7-channel STM-1 frame data to the SDH clock, and then sends it out from the corresponding STM-1 interface.

[0016] Furthermore, in the step s1, the process of pre-enabling the STM-1 interface number includes: configuring the interface number of the STM-1 interface by using a management CPU.

[0017] Furthermore, in step s2, numbers 0 to 13 of the 2×7-channel STM-1 frame data are stored in an empty overhead byte in row 2 and column 6 of the 2×7-channel STM-1 frame data.

[0018] Furthermore, in step s2, when descrambling the 2×7-channel STM-1 frame data, the SDH scrambling code polynomial is .

[0019] Furthermore, in step s5, the specific process of the transmitting end FPGA1 mapping the two ODU0 frames into the OPU1 frame through the AMP includes the following:

[0020] The transmitting end FPGA1 stores the two ODU0 frames in an asynchronous FIFO; the transmitting end FPGA1 takes the two ODU0 frames from the asynchronous FIFO and maps them into two 8×1904 ODTU01s respectively, while adjusting the byte overhead according to the data transmission status;

[0021] The adjusted two 8×1904 ODTU01s are inserted into the OPU1 payload in a byte-interleaved manner. Every two multiframes correspond to the overhead of two ODTU01s. That is, when the eighth bit of the MFAS is 0, the OPU overhead corresponds to the overhead of the first ODTU01. When the eighth bit of the MFAS is 1, the OPU overhead corresponds to the overhead of the second ODTU01.

[0022] Furthermore, the specific process of adjusting the byte overhead according to the data transmission status includes the following:

[0023] The transmitting end FPGA1 checks the remaining capacity of the asynchronous FIFO. If the remaining capacity of the asynchronous FIFO is less than a preset threshold A, a negative adjustment overhead is inserted into the JC overhead of the two 8×1904 ODTU01s. If the remaining capacity of the asynchronous FIFO is greater than a preset threshold B, a positive adjustment overhead is inserted into the JC overhead of the two 8×1904 ODTU01s.

[0024] Furthermore, in step s6, the scrambling polynomial for scrambling the OTU1 frame is: .

[0025] The present invention also provides a GMP-based signal STM-1 to OTN mapping system, comprising: a management CPU, a transmitting end FPGA1, a receiving end FPGA2, a first OTN optical module, and a second OTN optical module;

[0026] The transmitting end FPGA1 includes: a first STM-1 interface module, a first STM-1 processing module, an SDH to OTN module, a first CPU interface module and a first SERDES interface; the first STM-1 processing module includes: a first asynchronous FIFO, a first STM-1 preprocessing module and an STM-1 multiplexing module; the SDH to OTN module includes: a GMP mapping module, an AMP mapping module and an OTU1 framing module;

[0027] The receiving end FPGA2 includes: a second STM-1 interface module, a second STM-1 processing module, an OTN to SDH module, a second CPU interface module and a second SERRES interface; the second STM-1 processing module includes: a second asynchronous FIFO, a second STM-1 preprocessing module and an STM-1 demultiplexing module; the OTN to SDH module includes: a GMP demapping module, an AMP demapping module and an OPU1 extraction module;

[0028] The management CPU is used to: configure the enabling of the first STM-1 interface module through the LOCAL BUS bus; read the frame synchronization status of the 2×7-channel STM-1 frame data of the receiving end FPGA2 collected by the second CPU interface module through the LOCAL BUS bus;

[0029] The first STM-1 interface module is configured to: receive 2×7 STM-1 frame data corresponding to enabled interfaces according to the enable of the first STM-1 interface module configured by the management CPU; then generate empty STM-1 data frames for unenabled interfaces in the received 2×7 STM-1 frame data; and finally store the 2×7 STM-1 frame data into the first asynchronous FIFO;

[0030] The first asynchronous FIFO is used to synchronize the 2×7-channel STM-1 frame data to the system clock;

[0031] The first STM-1 preprocessing module is used to: implement framing and frame synchronization for the 2×7-channel STM-1 frame data, and descramble the frame data, and then insert numbers 0 to 13 into the 2nd row and 6th column of the 2×7-channel STM-1 frame data;

[0032] The STM-1 multiplexing module is used to: time-division multiplex the 2×7-channel STM-1 frame data into 2-channel STM1_MUX signals by byte interleaving;

[0033] The GMP mapping module is used to: map the two STM1_MUX signals into two ODU0 frames through GMP respectively;

[0034] The AMP mapping module is used to: map the two ODU0 frames into OPU1 frames through AMP;

[0035] The OTU1 framing module is used to: add the ODU1 overhead, OTU1 overhead and frame header overhead to the OPU1 frame in sequence to form an OTU1 frame, and then perform a scrambling operation on the OTU1 frame;

[0036] The first SERDES interface is used to: send the scrambled OTU1 frame into the OTN network through the first OTN optical module;

[0037] The first CPU interface module is used to: configure the enabling of 2×7 STM-1 interfaces of the transmitting end FPGA1;

[0038] The second SERRES port is used to: receive the scrambled OTU1 frame from the OTN network;

[0039] The OPU1 extraction module is used to: first descramble the scrambled OTU1 frame and extract the OPU1 frame;

[0040] The AMP demapping module is used to: demap the OPU1 frame into two ODU0 frames through AMP;

[0041] The GMP demapping module is used to demap the two ODU0 frames into two STM1_MUX signals through GMP;

[0042] The STM-1 demultiplexing module is used to demultiplex 2-way STM1_MUX signals into 2×7-way STM-1 frame data;

[0043] The second STM-1 preprocessing module is configured to: implement framing and frame synchronization for the 2×7-channel STM-1 frame data, and send the frame synchronization status to the management CPU through the second CPU interface module; parse the overhead in the second row and sixth column of the 2×7-channel STM-1 frame data to obtain a corresponding interface number, restore the overhead to 0, scramble the 2×7-channel STM-1 frame data, and then store the scrambled 2×7-channel STM-1 frame data in the second asynchronous FIFO corresponding to the interface number;

[0044] The second asynchronous FIFO is used to synchronize the scrambled 2×7-channel STM-1 frame data to the SDH clock;

[0045] The second STM-1 interface module is used to send out the scrambled 2×7-channel STM-1 frame data in the second asynchronous FIFO.

[0046] Compared with the prior art, the present invention has the following beneficial technical effects:

[0047] In the present invention, during the process of mapping the SDH signal STM-1 to the OTN, 2-channel ODU0 carries a maximum of 14-channel STM-1 signals, and the fixed filler FS inserted into the ODU0 payload area is reduced, thereby greatly reducing bandwidth waste and increasing the data transmission efficiency of the SDH signal in the OTN network. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 1 is a flow chart of a method for mapping a GMP-based signal STM-1 to OTN according to an embodiment;

[0049] Figure 2 is a schematic diagram of a module of a GMP-based signal STM-1 to OTN mapping system according to an embodiment;

[0050] Figure 3 is a schematic diagram of an STM-1 interface module according to an embodiment;

[0051] Figure 4 A schematic diagram of the STM1_MUX signal multiplexing structure according to an embodiment;

[0052] Figure 5 Schematic diagram of GMP mapping from STM1_MUX to OPU0 payload in one embodiment;

[0053] Figure 6 This is a flowchart of the service processing of the transmitting end FPGA1 according to an embodiment;

[0054] Figure 7 This is a flowchart of the service processing of FPGA2 at the receiving end according to an embodiment. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0056] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0057] refer to Figure 1 As shown, Figure 1 The flowchart of a method for mapping an STM-1 signal to an OTN based on GMP according to an embodiment is shown. The method for mapping an STM-1 signal to an OTN based on GMP comprises the following steps:

[0058] s1: The transmitting end FPGA1 receives 2×7 channels of STM-1 frame data corresponding to the enabled interface based on the pre-enabled STM-1 interface number; at the same time, the transmitting end FPGA1 generates empty STM-1 frame data instead of the disabled STM-1 interface; Figure 3 FIG. 1 is a schematic diagram of an STM-1 interface module according to an embodiment of the present invention.

[0059] s2: The transmitting end FPGA1 synchronizes the 2×7-channel STM-1 frame data to the system clock, performs framing, frame synchronization, and descrambling processing on the 2×7-channel STM-1 frame data, and numbers the processed 2×7-channel STM-1 frame data from 0 to 13 to obtain STM-1 frame data numbered 0 to 13 respectively;

[0060] s3: The transmitting end FPGA1 uses byte interleaving to time-division multiplex the STM-1 frame data numbered 0 to 6 into one STM1_MUX signal, and time-division multiplex the STM-1 frame data numbered 7 to 13 into another STM1_MUX signal; Figure 4 FIG. 1 is a schematic diagram of an STM1_MUX signal multiplexing structure according to an embodiment of the present invention.

[0061] s4: Map the two STM1_MUX signals into two ODU0 frames respectively through GMP mapping; Figure 5 FIG. 1 is a schematic diagram of GMP mapping from STM1_MUX to OPU0 payload in one embodiment;

[0062] s5: The transmitting end FPGA1 maps the two ODU0 frames into OPU1 frames through AMP;

[0063] s6: The transmitting end FPGA1 adds the ODU1 overhead, OTU1 overhead, and frame header overhead to the OPU1 frame in sequence to form an OTU1 frame, then scrambles the OTU1 frame and sends the scrambled OTU1 frame to the OTN network through the OTN optical module.

[0064] s7: The receiving end FPGA2 receives the scrambled OTU1 frame from the OTN network, descrambles it, and obtains the OTU1 frame; obtains the two ODU0 frames from the OTU1 frame through AMP demapping;

[0065] s8: The receiving end FPGA2 extracts and obtains the two STM1_MUX signals from the two ODU0 frames through GMP demapping;

[0066] s9: The receiving end FPGA2 demultiplexes the two STM1_MUX signals respectively, obtains the 2×7 STM-1 frame data, and completes framing and frame synchronization;

[0067] s10: The receiving end FPGA2 confirms and obtains the STM-1 interface corresponding to the 2×7-channel STM-1 frame data based on the 2nd row and 6th column overhead of the 2×7-channel STM-1 frame data, sets the overhead to 0, scrambles the 2×7-channel STM-1 frame data, synchronizes the scrambled 2×7-channel STM-1 frame data to the SDH clock, and then sends it out from the corresponding STM-1 interface.

[0068] In one embodiment, in step s1, the process of pre-enabling the STM-1 interface number includes: configuring the interface number of the STM-1 interface using a management CPU.

[0069] In one embodiment, in step s2, numbers 0 to 13 of the 2×7-channel STM-1 frame data are stored in an empty overhead byte in row 2 and column 6 of the 2×7-channel STM-1 frame data.

[0070] In one embodiment, in step s2, when descrambling the 2×7-channel STM-1 frame data, the SDH scrambling code polynomial is: .

[0071] In one embodiment, in step s5, the specific process of the transmitting end FPGA1 mapping the two ODU0 frames into the OPU1 frame through the AMP includes the following:

[0072] The transmitting end FPGA1 stores the two ODU0 frames in an asynchronous FIFO; the transmitting end FPGA1 takes the two ODU0 frames from the asynchronous FIFO and maps them into two 8×1904 ODTU01s respectively, while adjusting the byte overhead according to the data transmission status;

[0073] The adjusted two 8×1904 ODTU01s are inserted into the OPU1 payload in a byte-interleaved manner. Every two multiframes correspond to the overhead of two ODTU01s. That is, when the eighth bit of the MFAS is 0, the OPU overhead corresponds to the overhead of the first ODTU01. When the eighth bit of the MFAS is 1, the OPU overhead corresponds to the overhead of the second ODTU01.

[0074] In one embodiment, the specific process of adjusting the byte overhead according to the transmission status of the data includes the following:

[0075] The transmitting end FPGA1 checks the remaining capacity of the asynchronous FIFO. If the remaining capacity of the asynchronous FIFO is less than a preset threshold A, a negative adjustment overhead is inserted into the JC overhead of the two 8×1904 ODTU01s. If the remaining capacity of the asynchronous FIFO is greater than a preset threshold B, a positive adjustment overhead is inserted into the JC overhead of the two 8×1904 ODTU01s.

[0076] In one embodiment, in step s6, the scrambling polynomial for scrambling the OTU1 frame is: .

[0077] Figure 2 The module diagram of a GMP-based STM-1 to OTN signal mapping system according to an embodiment is shown. The GMP-based STM-1 to OTN signal mapping system includes: a management CPU, a transmitting end FPGA 1, a receiving end FPGA 2, a first OTN optical module, and a second OTN optical module;

[0078] The transmitting end FPGA1 includes: a first STM-1 interface module, a first STM-1 processing module, an SDH to OTN module, a first CPU interface module and a first SERDES interface; the first STM-1 processing module includes: a first asynchronous FIFO, a first STM-1 preprocessing module and an STM-1 multiplexing module; the SDH to OTN module includes: a GMP mapping module, an AMP mapping module and an OTU1 framing module;

[0079] The receiving end FPGA2 includes: a second STM-1 interface module, a second STM-1 processing module, an OTN to SDH module, a second CPU interface module and a second SERRES interface; the second STM-1 processing module includes: a second asynchronous FIFO, a second STM-1 preprocessing module and an STM-1 demultiplexing module; the OTN to SDH module includes: a GMP demapping module, an AMP demapping module and an OPU1 extraction module;

[0080] The management CPU is used to: configure the enabling of the first STM-1 interface module through the LOCAL BUS bus; read the frame synchronization status of the 2×7-channel STM-1 frame data of the receiving end FPGA2 collected by the second CPU interface module through the LOCAL BUS bus;

[0081] The first STM-1 interface module is configured to: accept 2×7-channel STM-1 frame data corresponding to an enabled interface according to the enabling of the first STM-1 interface module configured by the management CPU, generate an empty STM-1 data frame for an unenabled interface, and finally store the 2×7-channel STM-1 frame data and the empty STM-1 data frame into the first asynchronous FIFO;

[0082] The first asynchronous FIFO is used to synchronize the 2×7-channel STM-1 frame data to the system clock;

[0083] The first STM-1 preprocessing module is used to: implement framing and frame synchronization for the 2×7-channel STM-1 frame data, and descramble the frame data, and then insert numbers 0 to 13 into the 2nd row and 6th column of the 2×7-channel STM-1 frame data;

[0084] The STM-1 multiplexing module is used to: time-division multiplex the 2×7-channel STM-1 frame data into 2-channel STM1_MUX signals by byte interleaving;

[0085] The GMP mapping module is used to: map the two STM1_MUX signals into two ODU0 frames through GMP respectively;

[0086] The AMP mapping module is used to: map the two ODU0 frames into OPU1 frames through AMP;

[0087] The OTU1 framing module is used to: add the ODU1 overhead, OTU1 overhead and frame header overhead to the OPU1 frame in sequence to form an OTU1 frame, and then perform a scrambling operation on the OTU1 frame;

[0088] The first SERDES interface is used to: send the scrambled OTU1 frame into the OTN network through the first OTN optical module;

[0089] The first CPU interface module is used to: configure the enabling of 2×7 STM-1 interfaces of the transmitting end FPGA1;

[0090] The second SERRES interface is used to: receive the scrambled OTU1 frame from the OTN network;

[0091] The OPU1 extraction module is used to: first descramble the scrambled OTU1 frame and extract the OPU1 frame;

[0092] The AMP demapping module is used to: demap the OPU1 frame into two ODU0 frames through AMP;

[0093] The GMP demapping module is used to demap the two ODU0 frames into two STM1_MUX signals through GMP;

[0094] The STM-1 demultiplexing module is used to demultiplex 2-way STM1_MUX signals into 2×7-way STM-1 frame data;

[0095] The second STM-1 preprocessing module is configured to: implement framing and frame synchronization for the 2×7-channel STM-1 frame data, and send the frame synchronization status to the management CPU through the second CPU interface module; parse the overhead in the second row and sixth column of the 2×7-channel STM-1 frame data to obtain a corresponding interface number, restore the overhead to 0, scramble the 2×7-channel STM-1 frame data, and then store the scrambled 2×7-channel STM-1 frame data in the second asynchronous FIFO corresponding to the interface number;

[0096] The second asynchronous FIFO is used to synchronize the scrambled 2×7-channel STM-1 frame data to the SDH clock;

[0097] The second STM-1 interface module is used to send out the scrambled 2×7-channel STM-1 frame data in the second asynchronous FIFO.

[0098] In one embodiment, Figure 6 As shown, the management CPU first configures the enable signals for the 2×7 STM-1 interfaces. The transmitting FPGA1 receives STM-1 frame signals corresponding to the enabled interfaces based on the STM-1 interface numbers configured by the management CPU. For disabled interfaces, FPGA1 generates empty STM-1 frames instead. These 2×7 STM-1 signals are buffered in the first asynchronous FIFO and synchronized to the system clock.

[0099] The transmitting end FPGA1 performs framing and frame synchronization operations on these 2×7 STM-1 signals.

[0100] FPGA1 on the transmitting end descrambles the frame-synchronized STM-1 signal and inserts numbers 0 to 13 into the overhead of row 2, column 6 of the STM-1 frame structure. This number is used by FPGA2 on the receiving end to identify the STM-1 interface number.

[0101] The transmitting end FPGA1 performs time division multiplexing on the STM-1 signals numbered 0 to 6 and 7 to 13 in the form of byte interleaving to form two STM1_MUX signals;

[0102] The transmitting end FPGA1 maps the two STM1_MUX signals to OPU0 through GMP, and adds ODU0 overhead to form ODU0 frames;

[0103] The transmitting end FPGA1 maps two ODU0 frames into one OPU1 frame through AMP, adds OPU1 overhead, ODU1 overhead, OTU1 overhead, and frame header overhead to form an OTU1 frame, and scrambles it.

[0104] The transmitting end FPGA1 transmits OTU1 to the first OTN optical module through the first SERDES interface and enters the OTN network.

[0105] In one embodiment, Figure 7 As shown, the receiving end FPGA2 receives the OTU1 frame transmitted from the OTN network from the second OTN optical module through the second SERDES interface and descrambles it;

[0106] FPGA2 at the receiving end extracts the OPU1 payload from the OTU1 frame and demaps it into two ODU0 frames through AMP.

[0107] FPGA2 on the receiving end demaps two STM1_MUX channels from two ODU0 frames using GMP.

[0108] FPGA2 at the receiving end demultiplexes 2×7 channels of STM-1 frame data from the 2-channel STM1_MUX signal;

[0109] FPGA2 on the receiving end completes framing and frame synchronization for the 2×7 channels of STM-1 data and sends the frame synchronization status to the management CPU.

[0110] FPGA2 on the receiving end obtains the interface number of the corresponding STM-1 frame based on the overhead in row 2, column 6 of the STM-1 frame, restores the overhead to 0, and scrambles the STM-1 frame.

[0111] The receiving end FPGA2 buffers the 2×7-channel STM-1 frame data into the second asynchronous FIFO, synchronizes the 2×7-channel STM-1 frame data to the SDH clock, and sends the data out from the corresponding interface.

[0112] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] It should be noted that the terms "first, second, and third" used in the embodiments of the present application are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understood that the terms "first, second, and third" may interchangeably represent a specific order or precedence, where permitted. It should be understood that the terms "first, second, and third" may interchangeably represent objects, where appropriate, such that the embodiments of the present application described herein may be implemented in an order other than that illustrated or described herein.

[0114] The terms "including," "having," and any variations thereof in the embodiments of the present application are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product, or device comprising a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to the process, method, product, or device.

[0115] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A GMP-based signal STM-1 to OTN mapping method, characterized in that: The steps include: s1: The transmitting end FPGA1 receives 2×7 channels of STM-1 frame data from the enabled STM-1 interface based on the pre-enabled STM-1 interface number. At the same time, the transmitting end FPGA1 generates empty STM-1 frame data to replace the disabled STM-1 interface. s2: The transmitting end FPGA1 synchronizes the 2×7-channel STM-1 frame data to the system clock, performs framing, frame synchronization, and descrambling processing on the 2×7-channel STM-1 frame data, and numbers the processed 2×7-channel STM-1 frame data from 0 to 13 to obtain STM-1 frame data numbered 0 to 13 respectively; s3: The transmitting end FPGA1 uses byte interleaving to time-division multiplex the STM-1 frame data numbered 0 to 6 into one STM1_MUX signal, and time-division multiplex the STM-1 frame data numbered 7 to 13 into another STM1_MUX signal; s4: Maps two STM1_MUX signals into two ODU0 frames respectively through GMP mapping; s5: The transmitting end FPGA1 maps the two ODU0 frames into OPU1 frames through AMP; s6: The transmitting end FPGA1 adds the ODU1 overhead, OTU1 overhead, and frame header overhead to the OPU1 frame in sequence to form an OTU1 frame, then scrambles the OTU1 frame and sends the scrambled OTU1 frame to the OTN network through the OTN optical module. s7: The receiving end FPGA2 receives the scrambled OTU1 frame from the OTN network, descrambles it, and obtains the OTU1 frame; obtains the two ODU0 frames from the OTU1 frame through AMP demapping; s8: The receiving end FPGA2 extracts and obtains the two STM1_MUX signals from the two ODU0 frames through GMP demapping; s9: The receiving end FPGA2 demultiplexes the two STM1_MUX signals respectively, obtains the 2×7 STM-1 frame data, and completes framing and frame synchronization; s10: The receiving end FPGA2 confirms and obtains the STM-1 interface corresponding to the 2×7-channel STM-1 frame data based on the 2nd row and 6th column overhead of the 2×7-channel STM-1 frame data, sets the overhead to 0, scrambles the 2×7-channel STM-1 frame data, synchronizes the scrambled 2×7-channel STM-1 frame data to the SDH clock, and then sends it out from the corresponding STM-1 interface.

2. The method for mapping a signal STM-1 to OTN based on GMP according to claim 1, characterized in that: In the step s1, the process of pre-enabling the STM-1 interface number includes: configuring the interface number of the STM-1 interface using a management CPU.

3. The method for mapping a signal STM-1 to OTN based on GMP according to claim 2, characterized in that: In step s2, numbers 0 to 13 of the 2×7-channel STM-1 frame data are stored in the empty overhead bytes of the 2nd row and 6th column of the 2×7-channel STM-1 frame data.

4. The method for mapping a signal STM-1 to OTN based on GMP according to claim 3, characterized in that: In step s2, when descrambling the 2×7-channel STM-1 frame data, the SDH scrambling code polynomial is: .

5. The method for mapping a signal STM-1 to OTN based on GMP according to claim 4, characterized in that: In step s5, the specific process of the transmitting end FPGA1 mapping the two ODU0 frames into the OPU1 frame through the AMP includes the following: The transmitting end FPGA1 stores the two ODU0 frames in an asynchronous FIFO; the transmitting end FPGA1 takes the two ODU0 frames from the asynchronous FIFO and maps them into two 8×1904 ODTU01s respectively, while adjusting the byte overhead according to the data transmission status; The adjusted two 8×1904 ODTU01s are inserted into the OPU1 payload in a byte-interleaved manner. Every two multiframes correspond to the overhead of two ODTU01s. That is, when the eighth bit of the MFAS is 0, the OPU overhead corresponds to the overhead of the first ODTU01. When the eighth bit of the MFAS is 1, the OPU overhead corresponds to the overhead of the second ODTU01.

6. The method for mapping a signal STM-1 to OTN based on GMP according to claim 5, characterized in that: The specific process of adjusting the byte overhead according to the data transmission status is as follows: The transmitting end FPGA1 checks the remaining capacity of the asynchronous FIFO. If the remaining capacity of the asynchronous FIFO is less than a preset threshold A, a negative adjustment overhead is inserted into the JC overhead of the two 8×1904 ODTU01s. If the remaining capacity of the asynchronous FIFO is greater than a preset threshold B, a positive adjustment overhead is inserted into the JC overhead of the two 8×1904 ODTU01s.

7. The method for mapping a signal STM-1 to OTN based on GMP according to claim 6, characterized in that: In step s6, the scrambling polynomial for scrambling the OTU1 frame is: .

8. The GMP-based signal STM-1 to OTN mapping system is characterized by: include: Management CPU, transmitting end FPGA1, receiving end FPGA2, first OTN optical module and second OTN optical module; The transmitting end FPGA1 includes: a first STM-1 interface module, a first STM-1 processing module, an SDH to OTN module, a first CPU interface module and a first SERDES interface; the first STM-1 processing module includes: a first asynchronous FIFO, a first STM-1 preprocessing module and an STM-1 multiplexing module; the SDH to OTN module includes: a GMP mapping module, an AMP mapping module and an OTU1 framing module; The receiving end FPGA2 includes: a second STM-1 interface module, a second STM-1 processing module, an OTN to SDH module, a second CPU interface module and a second SERRES interface; the second STM-1 processing module includes: a second asynchronous FIFO, a second STM-1 preprocessing module and an STM-1 demultiplexing module; the OTN to SDH module includes: a GMP demapping module, an AMP demapping module and an OPU1 extraction module; The management CPU is used to: configure the enabling of the first STM-1 interface module through the LOCAL BUS bus; read the frame synchronization status of the 2×7-channel STM-1 frame data of the receiving end FPGA2 collected by the second CPU interface module through the LOCAL BUS bus; The first STM-1 interface module is configured to: receive 2×7 STM-1 frame data corresponding to enabled interfaces according to the enable of the first STM-1 interface module configured by the management CPU; then generate empty STM-1 data frames for unenabled interfaces in the received 2×7 STM-1 frame data; and finally store the 2×7 STM-1 frame data into the first asynchronous FIFO; The first asynchronous FIFO is used to synchronize the 2×7-channel STM-1 frame data to the system clock; The first STM-1 preprocessing module is used to: implement framing and frame synchronization for the 2×7-channel STM-1 frame data, and descramble the frame data, and then insert numbers 0 to 13 into the 2nd row and 6th column of the 2×7-channel STM-1 frame data; The STM-1 multiplexing module is used to: time-division multiplex the 2×7-channel STM-1 frame data into 2-channel STM1_MUX signals by byte interleaving; The GMP mapping module is used to: map the two STM1_MUX signals into two ODU0 frames through GMP respectively; The AMP mapping module is used to: map the two ODU0 frames into OPU1 frames through AMP; The OTU1 framing module is used to: add the ODU1 overhead, OTU1 overhead and frame header overhead to the OPU1 frame in sequence to form an OTU1 frame, and then perform a scrambling operation on the OTU1 frame; The first SERDES interface is used to: send the scrambled OTU1 frame into the OTN network through the first OTN optical module; The first CPU interface module is used to: configure the enabling of 2×7 STM-1 interfaces of the transmitting end FPGA1; The second SERRES port is used to: receive the scrambled OTU1 frame from the OTN network; The OPU1 extraction module is used to: first descramble the scrambled OTU1 frame and extract the OPU1 frame; The AMP demapping module is used to: demap the OPU1 frame into two ODU0 frames through AMP; The GMP demapping module is used to demap the two ODU0 frames into two STM1_MUX signals through GMP; The STM-1 demultiplexing module is used to demultiplex 2-way STM1_MUX signals into 2×7-way STM-1 frame data; The second STM-1 preprocessing module is configured to: implement framing and frame synchronization for the 2×7-channel STM-1 frame data, and send the frame synchronization status to the management CPU through the second CPU interface module; parse the overhead in the second row and sixth column of the 2×7-channel STM-1 frame data to obtain a corresponding interface number, restore the overhead to 0, scramble the 2×7-channel STM-1 frame data, and then store the scrambled 2×7-channel STM-1 frame data in the second asynchronous FIFO corresponding to the interface number; The second asynchronous FIFO is used to synchronize the scrambled 2×7-channel STM-1 frame data to the SDH clock; The second STM-1 interface module is used to send out the scrambled 2×7-channel STM-1 frame data in the second asynchronous FIFO.

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