Back contact battery and preparation method thereof

Abstract

The invention discloses a back contact battery and a preparation method thereof. The preparation method comprises the following steps: polishing a silicon wafer; preparing a tunneling silicon oxide layer, an intrinsic polycrystalline silicon layer and a mask layer; patterning and windowing to form an N-region pattern and a P-region pattern; cleaning and texturing; depositing a passivation layer, an intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer, an antireflection layer and a transparent conductive oxide layer; and windowing and printing a metal electrode to finish the preparation of the back contact battery. The preparation method of the back contact cell has the advantages of simple process flow, low manufacturing cost, convenience in mass production and the like, the isolation layer is arranged between the N region and the P region, the conduction risk can be remarkably reduced, the cell can be ensured to have very high conversion efficiency, the mass production efficiency of the back contact cell is improved by 0.38%, and the production efficiency of the back contact cell is greatly improved. And the method has important significance for promoting the industrial application of the back contact battery.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cell preparation, and relates to a back contact battery and a preparation method thereof. Background Art

[0002] The back contact battery (Back Contact, abbreviated as BC battery) is a high-efficiency photovoltaic battery technology. Its core feature is that all the positive and negative electrodes of the battery are arranged on the back of the battery, thus significantly improving the photoelectric conversion efficiency and aesthetics. For example, the interdigitated back contact (IBC) battery, due to no light shading on the front and the ability to stack tunneling passivation contact structures, can greatly improve its efficiency. The theoretical efficiency can reach more than 27%, and it has good application prospects. However, the existing back contact batteries and their preparation processes still have the following disadvantages: (a) For non-passivated contact back contact batteries, their efficiency is relatively low, only about 24-24.5%, and they have no advantage in terms of efficiency; (b) For P-type back contact batteries, the efficiency can reach 25-25.5%, but it is difficult to further improve the efficiency. Moreover, the P region is directly in contact with aluminum metal, and the recombination is much larger than that of the passivation contact structure; (c) For back contact batteries with tunneling silicon oxide + doped polysilicon passivation contact structures in both the N region and the P region, although the mass production efficiency is above 26%, the passivation of the tunneling silicon oxide + P-type doped polysilicon structure is somewhat lacking, and the efficiency still needs to be further improved. In addition, the high-temperature process has relatively high energy consumption; (d) For back contact batteries with intrinsic amorphous silicon and doped amorphous silicon structures in both the N region and the P region, their preparation process flow is complex, the equipment investment cost is high, and it is difficult to achieve mass production; (e) For back contact batteries with tunneling silicon oxide + doped polysilicon passivation contact structures in both the N region and the P region, their preparation route has not been fully determined and they have not been mass-produced yet. Moreover, for the isolation between the back N region and the P region, some technologies use laser windowing to directly separate the N region and the P region or prepare an intrinsic layer between the N region and the P region. These two methods either have a greater impact on the efficiency and are difficult to improve the efficiency of the battery, or the process is complex, increasing the difficulty of mass production and making it difficult to achieve industrial production. In particular, there is still a problem of conduction leakage in the isolation layer prepared between the back N region and the P region. Therefore, how to efficiently prepare the isolation layer between the N region and the P region without damaging the silicon wafer is of great significance for improving the efficiency and mass producibility of back contact batteries and for promoting the industrial application of back contact batteries. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a preparation method of a back contact battery and a back contact battery with a simple process flow, easy mass production and high efficiency.

[0004] To solve the above technical problems, the present invention adopts the following technical solutions:

[0005] A method for preparing a back-contact battery, comprising the following steps:

[0006] S1. Polish the silicon wafer.

[0007] S2. Sequentially prepare a tunneling silicon oxide layer, an intrinsic polysilicon layer, and a mask layer on the back surface of the silicon wafer.

[0008] S3. Pattern and open windows on the back surface of the silicon wafer until the intrinsic polysilicon layer is exposed, and form an N-region pattern on the back surface of the silicon wafer.

[0009] S4. Perform phosphorus diffusion on the back surface of the silicon wafer to form an N-type doped polysilicon layer.

[0010] S5. Pattern and open windows on the unopened area of the back surface of the silicon wafer, and keep an unopened width of at least 30 μm or more from the boundary with the opened area until the intrinsic polysilicon layer is exposed, and form a P-region pattern.

[0011] S6. Clean and texture the front surface of the silicon wafer.

[0012] S7. Sequentially deposit a passivation layer on the front surface of the silicon wafer, deposit an intrinsic amorphous silicon layer on the back surface of the silicon wafer, and deposit a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer on the intrinsic amorphous silicon layer on the back surface of the silicon wafer.

[0013] S8. Deposit an antireflection layer on the front surface of the silicon wafer.

[0014] S9. Deposit a transparent conductive oxide layer on the back surface of the silicon wafer.

[0015] S10. Open windows on the area above the N-type doped polysilicon layer on the back surface of the silicon wafer until the intrinsic N-type doped polysilicon layer is exposed, and open windows on the area above the intrinsic polysilicon layer on the back surface of the silicon wafer until the intrinsic polysilicon layer is exposed.

[0016] S11. Print metal electrodes on the N-type doped polysilicon layer and the deposited transparent conductive oxide layer, and anneal to form an ohmic contact, thus completing the preparation of the back-contact battery.

[0017] In the above preparation method, further improved, in step S5, keep an unopened width of 30 μm to 100 μm from the boundary with the opened area.

[0018] In the above preparation method, further improved, in step S5, use green nanosecond laser, green picosecond laser, or ultraviolet picosecond laser to pattern and open windows on the unopened area of the back surface of the silicon wafer.

[0019] In the above preparation method, further improved, in step S1, use an alkaline solution to polish the silicon wafer to remove the damaged layer on the surface of the silicon wafer and form a polished surface on the surface of the silicon wafer; the silicon wafer is an N-type silicon wafer; the resistivity of the silicon wafer is 0.3 Ω·cm to 21 Ω·cm.

[0020] In the above preparation method, for further improvement, in step S2, a tunneling oxide layer, an intrinsic polysilicon layer, and a mask layer are sequentially formed on the back surface of the silicon wafer by LPCVD or PECVD; when the tunneling oxide layer is formed by LPCVD, it is carried out in an oxygen atmosphere, and the thermal oxidation temperature is 550°C to 630°C; when the intrinsic polysilicon layer is formed by LPCVD, silane is used as the reaction gas, and the reaction temperature is 550°C to 630°C; when the mask layer is formed by LPCVD, tetraethyl orthosilicate is used as the oxygen source, and the reaction temperature is 550°C to 630°C; when the tunneling oxide layer is formed by PECVD, one of the combinations of nitrous oxide, nitrous oxide and argon, and nitrous oxide and hydrogen is used as the oxygen source, and the reaction temperature is 400°C to 500°C; when the intrinsic polysilicon layer is formed by PECVD, silane is used as the reaction gas, and hydrogen, argon or nitrogen is used as the dilution gas, and the reaction temperature is 400°C to 500°C; when the mask layer is formed by PECVD, silane and nitrous oxide are used as the reaction gases, and the reaction temperature is 400°C to 500°C; the thickness of the tunneling oxide layer is 0.5 nm to 3 nm; the thickness of the intrinsic polysilicon layer is 40 nm to 400 nm; the mask layer is a silicon oxide thin film; the thickness of the mask layer is 10 nm to 150 nm.

[0021] In the above preparation method, for further improvement, in step S3, ultraviolet picosecond laser is used to pattern and open windows on the back surface of the silicon wafer.

[0022] In the above preparation method, for further improvement, in step S4, the temperature during the phosphorus diffusion process is 860°C to 960°C; the phosphorus source used during the phosphorus diffusion process is phosphorus oxychloride; the thickness of the N-type doped polysilicon layer is 40 nm to 400 nm; the doping concentration of the N-type doped polysilicon layer is 1E20 cm -3 ~3E21 cm -3 .

[0023] In the above preparation method, for further improvement, in step S6, hydrofluoric acid is used to clean the front surface of the silicon wafer in a single-sided chain manner to remove the silicon oxide or PSG on the front surface.

[0024] In the above preparation method, further improved, in step S7, the passivation layer is deposited on the front side of the silicon wafer by PECVD method in sequence, and the intrinsic amorphous silicon layer is prepared on the back side of the silicon wafer; the thickness of the passivation layer is 1 nm to 20 nm; the passivation layer is an intrinsic amorphous silicon thin film or a composite film of an intrinsic amorphous silicon thin film and a doped amorphous silicon thin film; the thickness of the intrinsic amorphous silicon layer is 1 nm to 20 nm; a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer is deposited on the intrinsic amorphous silicon layer on the back side of the silicon wafer by PECVD method; the thickness of the P-type doped amorphous silicon layer is 3 nm to 40 nm, and the doping concentration is 1E18 cm -3 ~1E20cm -3 ; the thickness of the P-type doped microcrystalline silicon layer is 3 nm to 40 nm, and the doping concentration is 1E18 cm -3 ~1E20 cm -3 .

[0025] In the above preparation method, further improved, in step S8, the antireflection layer is one of a silicon nitride thin film, a silicon oxynitride thin film, a silicon oxide thin film, and a transparent conductive oxide thin film or a composite film stacked by them; when the antireflection layer is a silicon nitride thin film, a silicon oxynitride thin film, or a silicon oxide thin film, the antireflection layer is deposited on the front side of the silicon wafer by PECVD method; when the antireflection layer is a transparent conductive oxide thin film, it is deposited by PVD method; the thickness of the antireflection layer is 60 nm to 100 nm.

[0026] In the above preparation method, further improved, in step S9, a transparent conductive oxide layer is deposited on the back side of the silicon wafer by PVD method; the material of the transparent conductive oxide layer is at least one of ITO, AZO, and IWO; the thickness of the transparent conductive oxide layer is 20 nm to 300 nm.

[0027] In the above preparation method, further improved, in step S10, laser is used to open a window in the area above the intrinsic polysilicon layer and the N-type doped polysilicon layer on the back side of the silicon wafer.

[0028] In the above preparation method, further improved, in step S11, the material of the metal electrode includes at least one of silver, copper, and nickel.

[0029] In the above preparation method, further improved, in step S1, the resistivity of the silicon wafer is 1 Ω·cm to 7 Ω·cm.

[0030] In the above preparation method, further improved, in step S2, the thickness of the tunneling silicon oxide layer is 1.2 nm to 2.0 nm; the thickness of the mask layer is 40 nm to 100 nm.

[0031] In the above preparation method, further improved, in step S4, the thickness of the N-type doped polysilicon layer is 70 nm to 200 nm; the doping concentration of the N-type doped polysilicon layer is 5E20 cm -3 ~2E21 cm -3 .

[0032] In the above preparation method, further improved, in step S7, the thickness of the passivation layer is 3 nm to 15 nm; the thickness of the intrinsic amorphous silicon layer is 3 nm to 15 nm; the thickness of the P-type doped amorphous silicon layer is 5 nm to 20 nm; the thickness of the P-type doped microcrystalline silicon layer is 5 nm to 20 nm.

[0033] As a general technical concept, the present invention also provides a back contact battery, which is prepared by the above preparation method.

[0034] In the above back contact battery, further improved, the back contact battery includes a silicon substrate, and an N-type tunneling passivation contact structure and a P-type tunneling passivation contact structure are alternately arranged on the back of the silicon substrate, and an isolation layer is arranged between the N-type tunneling passivation contact structure and the P-type tunneling passivation contact structure; the width of the isolation layer is 30 μm to 100 μm.

[0035] In the above back contact battery, further improved, the isolation layer is sequentially a tunneling silicon oxide layer and an intrinsic polysilicon layer from inside to outside.

[0036] In the above back contact battery, further improved, the N-type tunneling passivation contact structure is sequentially a tunneling silicon oxide layer, an N-type doped polysilicon layer, an intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer, a transparent conductive oxide layer and a first metal electrode from inside to outside; the first metal electrode sequentially passes through the transparent conductive oxide layer, the P-type doped amorphous silicon layer or the P-type doped microcrystalline silicon layer, and the intrinsic amorphous silicon layer and then is connected to the N-type doped polysilicon layer to form an ohmic contact.

[0037] In the above back contact battery, further improved, the P-type tunneling passivation contact structure is sequentially an intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer, a transparent conductive oxide layer and a second metal electrode from inside to outside; the second metal electrode is connected to the transparent conductive oxide layer to form an ohmic contact.

[0038] In the above back contact battery, further improved, the isolation layer is located between the N-type doped polysilicon layer and the intrinsic amorphous silicon layer.

[0039] In the above back contact battery, further improved, the front of the silicon substrate is sequentially a passivation layer and an antireflection layer from inside to outside.

[0040] Compared with the prior art, the advantages of the present invention are:

[0041] (1) In view of the shortcomings of the existing back contact battery preparation method, such as the isolation layer being easy to conduct and difficult to balance the output and efficiency, the present invention creatively proposes a back contact battery preparation method. By sequentially depositing a tunneling silicon oxide layer, an intrinsic polysilicon layer, and a mask layer on the back of a silicon wafer, and by optimizing the width of the non-windowing area during the patterned windowing process, an isolation layer with good isolation effect can be prepared without damaging the silicon wafer substrate. On the one hand, by precisely controlling the graphic size accuracy of the patterned windowing, the process complexity can be greatly reduced and the introduction of other pollution sources can be avoided, which can significantly reduce the manufacturing cost, be conducive to improving mass production, and significantly improve production efficiency. On the other hand, while ensuring a good passivation effect, the isolation layer can be used to achieve effective isolation of P / N, significantly reducing the risk of leakage, and thus significantly improving the conversion efficiency of the battery. The preparation method of the back contact battery of the present invention has the advantages of simple process flow, low manufacturing cost, and easy mass production, and can ensure that the battery has a very high conversion efficiency. The improvement in the mass production efficiency of the back contact battery is as high as 0.38%, which is of great significance for promoting the industrial application of back contact batteries.

[0042] (2) In the preparation method of the present invention, when patterning and opening windows in the areas where the N and P regions are located, a width of 30 μm to 100 μm from the boundary of the windowed area is retained without opening windows, which is conducive to forming an isolation layer with good leakage prevention effect between the N and P regions. Generally speaking, the width of the isolation area has a more significant impact on the electrical performance of the battery. When the width of the unopened window is small, the isolation area is thin. In this case, it is easy to be partially etched along the edge during the subsequent wet etching process, which may cause subsequent P / N conduction and large leakage. Secondly, due to the limitations of laser accuracy and the size of the light spot, when the isolation area is relatively narrow, when the ITO is opened by the laser in the subsequent process, it may cause damage to the P region or the laser opening in the N region may cause incomplete removal of the ITO in the isolation area, and the isolation effect is not achieved. In addition, when the width of the isolation area is too wide, the mass production process window is large, but since the isolation area is not doped, on the one hand, the passivation effect is not as good as the P / N area, which will affect the efficiency. Secondly, the carriers at this position cannot be extracted, and the carriers generated in the substrate corresponding to this position need to be extracted from the P / N area on both sides. The carrier path becomes longer, affecting the collection efficiency and thus affecting the efficiency of the battery.

[0043] (3) The back contact cell of the present invention comprises a silicon substrate, and an N-type tunnel passivation contact structure and a P-type tunnel passivation contact structure are alternately provided on the back of the silicon substrate, and an isolation layer is provided between the N-type tunnel passivation contact structure and the P-type tunnel passivation contact structure, wherein the width of the isolation layer is 30 μm to 100 μm, which can ensure that an insulating layer with excellent insulation effect is formed between the N-type tunnel passivation contact structure and the P-type tunnel passivation contact structure, can significantly reduce leakage current, and can reduce the leakage current of the isolation region to below 0.1A, and can significantly improve the opening voltage and FF, thereby helping to improve the efficiency of the cell, and can also obtain a larger process window under the premise of ensuring high cell efficiency. Generally speaking, when the width is less than 30 μm, due to the accuracy of the laser of ±10 μm, the ITO removal effect in a local position may be unsatisfactory due to the window opening accuracy, resulting in conduction phenomenon or the laser offset to the amorphous silicon region, destroying the passivation of the P region and affecting efficiency. When the width is greater than 100 μm, the process window is large and the insulation effect can be guaranteed, but too wide will lead to a decrease in efficiency. It can be seen that when the width of the isolation layer is in the range of 30 to 100 μm, both the process window and the cell efficiency are taken into account, which can ensure that good isolation is achieved without causing excessive efficiency loss due to the intrinsic polysilicon isolation area being too wide. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0045] Figure 1 Schematic diagram of the structure of the back contact battery in Example 1 of the present invention.

[0046] Legend:

[0047] 1. Silicon substrate; 2. Tunneling silicon oxide layer; 3. N-type doped polysilicon layer; 4. Intrinsic polysilicon layer; 5. Intrinsic amorphous silicon layer; 6. P-type doped amorphous silicon layer; 7. Transparent conductive oxide layer; 8. First metal electrode; 9. Second metal electrode; 10. Passivation layer; 11. Anti-reflection layer. DETAILED DESCRIPTION

[0048] The present invention will be further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the scope of protection of the present invention is not limited thereby.

[0049] In the following examples of the present invention, unless otherwise specified, the materials and instruments used are commercially available, the equipment used is conventional equipment, and the data obtained are the average values of more than three repeated experiments.

[0050] Example 1

[0051] A method for preparing a back-contact battery, comprising the following steps:

[0052] (1) Double-sided polishing: For an N-type silicon wafer with a resistivity of 2.5 Ω·cm, use a KOH solution to remove the damaged layers on the front and back surfaces, polish the surface, and then clean it with a hydrochloric acid + hydrofluoric acid solution.

[0053] (2) Preparation of back tunneling silicon oxide + intrinsic polysilicon: Using the technical solution of tube PECVD, with nitrous oxide as the oxygen source and a deposition temperature of 450 °C, grow a tunneling silicon oxide layer with a thickness of 1.5 nm on the back surface of the silicon wafer; then use silane as the reaction gas and hydrogen as the dilution gas, with a deposition temperature of 450 °C, and deposit an intrinsic polysilicon layer with a thickness of 150 nm above the tunneling silicon oxide layer; finally, use silane and nitrous oxide as the reaction gases, with a deposition temperature of 450 °C, and deposit a mask layer with a thickness of 60 nm above the intrinsic polysilicon layer, specifically a silicon oxide thin film.

[0054] (3) Laser window opening: Use ultraviolet picosecond laser to perform laser patterning window opening on the back surface of the silicon wafer to remove the mask layer (silicon oxide thin film) above the intrinsic polysilicon.

[0055] (4) Phosphorus diffusion: Use phosphorus oxychloride as the phosphorus source for phosphorus diffusion, where the deposition temperature is 860 °C and the pushing temperature is 910 °C. In the laser window opening area, due to the lack of protection of the silicon oxide mask, the intrinsic polysilicon layer becomes an N-type doped polysilicon layer after phosphorus diffusion, with a thickness of 150 nm and a doping concentration of 5E20 cm -3 , in addition, a layer of phosphosilicate glass layer (PSG) is also formed above the N-type doped polysilicon layer; in the area without laser window opening, due to a thicker silicon oxide mask layer above, the bottom remains an undoped intrinsic polysilicon layer.

[0056] (5) Laser window opening: Use green nanosecond laser to perform laser window opening on the area without window opening (the area with a silicon oxide mask) in the window opening in step 3, leaving a width of 50 μm from the intersection position with the previous window opening without window opening, and exposing the intrinsic polysilicon layer at other positions.

[0057] (6) Wet etching: First, use hydrofluoric acid to clean and remove the silicon oxide and PSG on the front surface in a single-sided chain manner, and then perform alkali texturing in a tank-type device. While texturing the front surface, remove the polysilicon and tunneling oxide layer in the window opening area on the back surface in step 5, and then clean it with hydrochloric acid and hydrofluoric acid.

[0058] (7) Intrinsic amorphous silicon and doped amorphous silicon deposition: Using a plate-type PECVD device, first deposit an 8-nm-thick intrinsic amorphous silicon thin film on the front side as a passivation layer; then deposit a 5-nm-thick intrinsic amorphous silicon layer on the back side; and then deposit a 10-nm-thick boron-doped amorphous silicon layer (P-type doped amorphous silicon layer) above the back-side intrinsic amorphous silicon layer.

[0059] (8) Front-side antireflection layer deposition: Use PVD to deposit an 80-nm-thick ITO on the front side as an antireflection layer.

[0060] (9) Back-side transparent conductive oxide thin film deposition: Use PVD to deposit an ITO on the back side with a thickness of 70 nm.

[0061] (10) Laser window opening: Use a laser to perform patterned laser window opening in the area where the N-type doped polysilicon layer is located and above the intrinsic polysilicon layer. The width of the window opening spot is 30 μm, removing the intrinsic amorphous silicon, P-type doped amorphous silicon, and transparent conductive oxide thin film above the N-type doped amorphous silicon layer and the intrinsic polysilicon layer without damaging the underlying tunneling silicon oxide layer.

[0062] (11) Screen printing: Use screen printing to print silver electrodes on the back side of the battery. Specifically, print silver electrodes on the N-type doped polysilicon layer and the deposited transparent conductive oxide layer, which are the first metal electrode and the second metal electrode in sequence, and then perform drying and curing to form a metal ohmic contact, completing the preparation of the back-contact battery.

[0063] As Figure 1 shown, the back-contact battery prepared by the present invention includes a silicon substrate 1, and an N-type tunneling passivation contact structure and a P-type tunneling passivation contact structure are alternately provided on the back side of the silicon substrate 1, and an isolation layer is provided between the N-type tunneling passivation contact structure and the P-type tunneling passivation contact structure, and the width of the isolation layer is 50 μm.

[0064] In this embodiment, the isolation layer is sequentially composed of a tunneling silicon oxide layer 2 and an intrinsic polysilicon layer 4 from the inside to the outside.

[0065] In this embodiment, the N-type tunneling passivation contact structure is sequentially composed of a tunneling silicon oxide layer 2, an N-type doped polysilicon layer 3, an intrinsic amorphous silicon layer 5, a P-type doped amorphous silicon layer 6, a transparent conductive oxide layer 7, and a first metal electrode 8 from the inside to the outside. The first metal electrode sequentially passes through the transparent conductive oxide layer 7, the P-type doped amorphous silicon layer 6, and the intrinsic amorphous silicon layer 5 and then connects to the N-type doped polysilicon layer 3 to form an ohmic contact.

[0066] In this embodiment, the P-type tunneling passivation contact structure is sequentially composed of an intrinsic amorphous silicon layer 5, a P-type doped amorphous silicon layer 6, a transparent conductive oxide layer 7, and a second metal electrode 9 from the inside to the outside. The second metal electrode 9 connects to the transparent conductive oxide layer 7 to form an ohmic contact;

[0067] In this embodiment, the isolation layer is located between the N-type doped polysilicon layer 3 of the N-type tunneling passivation contact structure and the intrinsic amorphous silicon layer of the P-type tunneling passivation contact structure.

[0068] In this embodiment, the front side of the silicon substrate is successively a passivation layer 10 and an antireflection layer 11 from the inside out, where the passivation layer 10 is an intrinsic amorphous silicon thin film.

[0069] Embodiment 2

[0070] A method for preparing a back-contact battery includes the following steps:

[0071] (1) Double-sided polishing: For an N-type silicon wafer with a resistivity of 3 Ω·cm, the damage layers on the front and back are removed using KOH, and the surface is polished. Then, it is cleaned using a hydrochloric acid + hydrofluoric acid solution.

[0072] (2) Preparation of back tunneling silicon oxide + intrinsic polysilicon: In a tube-type LPCVD device, first, a tunneling silicon oxide layer with a thickness of 1.6 nm is grown on the silicon wafer surface under an oxygen atmosphere at 600 °C. Then, silane is introduced as a reaction gas and decomposed at 600 °C to grow an intrinsic polysilicon layer with a thickness of 200 nm above the oxide layer. Finally, tetraethyl orthosilicate is used as an oxygen source and decomposed at 600 °C to deposit a silicon oxide thin film with a thickness of 40 nm above the intrinsic polysilicon layer as a mask layer.

[0073] (3) Laser window opening: Ultraviolet picosecond laser is used for laser patterning window opening on the back of the silicon wafer to remove the silicon oxide mask layer above the intrinsic polysilicon layer.

[0074] (4) Diffusion: Using phosphorus oxychloride as a phosphorus source, phosphorus diffusion is carried out under the conditions of a deposition temperature of 860 °C and a driving temperature of 920 °C. In the laser window opening area, since there is no silicon oxide mask protection, the intrinsic polysilicon layer becomes an N-type doped polysilicon layer after phosphorus diffusion, with a doping concentration of 4E20 cm -3 , and in addition, there is a layer of phosphosilicate glass (PSG) above the N-type doped polysilicon layer; in the area where laser window opening is not performed, since there is a relatively thick silicon oxide mask layer above, the underlying layer remains an undoped intrinsic polysilicon layer.

[0075] (5) Laser window opening: Green nanosecond laser is used to perform laser window opening on the area where window opening was not performed in the third step (the area with a silicon oxide mask), leaving a width of 50 μm that is not windowed at the position where it intersects with the previous window opening to expose the intrinsic polysilicon layer at other positions.

[0076] (6) Wet etching: First, use hydrofluoric acid to clean and remove the silicon oxide and PSG on the front side in a single-sided chain manner, and then perform alkali texturing in a tank-type device. While texturing the front side, remove the polysilicon and tunneling oxide layer in the window area of the fifth step on the back side, and then clean with hydrochloric acid and hydrofluoric acid.

[0077] (7) Intrinsic amorphous silicon and doped amorphous silicon deposition: Use a plate-type PECVD device to first deposit an intrinsic amorphous silicon thin film with a thickness of 5 nm on the front side as a passivation layer; then deposit an intrinsic amorphous silicon layer with a thickness of 5 nm on the back side; and then deposit a boron-doped amorphous silicon layer (P-type doped amorphous silicon layer) with a thickness of 10 nm above the intrinsic amorphous silicon layer on the back side.

[0078] (8) Front anti-reflection layer deposition: Use plate-type PECVD to deposit a silicon nitride and silicon oxide stacked film on the front side as an anti-reflection layer, and the total thickness of the anti-reflection layer is 80 nm.

[0079] (9) Back transparent conductive oxide thin film deposition: Use PVD to deposit an ITO on the back side with a thickness of 70 nm.

[0080] (10) Laser window opening: Use a laser to perform patterned laser window opening in the N-type doped polysilicon region and above the intrinsic polysilicon layer. The width of the window opening spot size is 30 μm, and remove the intrinsic amorphous silicon thin film, P-type doped amorphous silicon, and transparent conductive oxide thin film above the N-type doped amorphous silicon and intrinsic polysilicon without damaging the underlying tunneling silicon oxide layer.

[0081] (11) Screen printing: Use screen printing to print silver electrodes on the back side of the battery. Specifically, print silver electrodes on the N-type doped polysilicon layer and the deposited transparent conductive oxide layer, which are the first metal electrode and the second metal electrode in sequence, and then perform drying and curing to form a metal ohmic contact, completing the preparation of the back-contact battery.

[0082] The back-contact battery prepared by the present invention includes a silicon substrate 1, and an N-type tunneling passivation contact structure and a P-type tunneling passivation contact structure are alternately arranged on the back side of the silicon substrate 1, and an isolation layer is provided between the N-type tunneling passivation contact structure and the P-type tunneling passivation contact structure, and the width of the isolation layer is 50 μm.

[0083] In this embodiment, the isolation layer is sequentially composed of a tunneling silicon oxide layer 2 and an intrinsic polysilicon layer 4 from the inside to the outside.

[0084] In this embodiment, the N-type tunneling passivation contact structure, from the inside out, is successively a tunneling silicon oxide layer 2, an N-type doped polysilicon layer 3, an intrinsic amorphous silicon layer 5, a P-type doped amorphous silicon layer 6, a transparent conductive oxide layer 7, and a first metal electrode 8. The first metal electrode passes through the transparent conductive oxide layer 7, the P-type doped amorphous silicon layer 6, and the intrinsic amorphous silicon layer 5 in sequence and then connects with the N-type doped polysilicon layer 3 to form an ohmic contact.

[0085] In this embodiment, the P-type tunneling passivation contact structure, from the inside out, is successively an intrinsic amorphous silicon layer 5, a P-type doped amorphous silicon layer 6, a transparent conductive oxide layer 7, and a second metal electrode 9. The second metal electrode 9 connects with the transparent conductive oxide layer 7 to form an ohmic contact.

[0086] In this embodiment, the isolation layer is located between the N-type doped polysilicon layer 3 of the N-type tunneling passivation contact structure and the intrinsic amorphous silicon layer of the P-type tunneling passivation contact structure.

[0087] In this embodiment, the front side of the silicon substrate, from the inside out, is successively a passivation layer 10 and an antireflection layer 11, where the passivation layer 10 is an intrinsic amorphous silicon thin film.

[0088] The back contact cells prepared in Example 1 and Example 2 were tested, and the results are shown in Table 1.

[0089] Table 1 Improvement amplitude data of various electrical properties of different back contact cells

[0090]

[0091] In Table 1, in the conventional IBC cell, the N region and the P region are alternately arranged on the silicon substrate, and both the N region and the P region adopt a tunneling silicon oxide layer + doped polysilicon passivation contact structure. A groove is provided between the N region and the P region as an isolation region, with a width of 50 micrometers.

[0092] As can be seen from Table 1, compared with the conventional IBC cell, the conversion efficiency of the back contact cells (which are actually IBC cells) prepared in Example 1 and Example 2 of the present invention is significantly improved, with an improvement amplitude of up to 0.16% - 0.38%. Thus, in the present invention, by optimizing the width of the non-window opening region, an isolation layer with good isolation effect can be prepared without damaging the silicon wafer substrate. On the one hand, by precisely controlling the pattern size accuracy of the patterned window opening, the process complexity can be greatly reduced and other pollution sources can be avoided from being introduced, the manufacturing cost can be significantly reduced, which is beneficial to improving the mass production ability, and the production efficiency is significantly improved. On the other hand, while ensuring a good passivation effect, the isolation layer can be used to effectively isolate P / N, significantly reducing the leakage risk, and thus the conversion efficiency of the battery can be significantly improved. It has the advantages of simple process flow, low manufacturing cost, easy mass production, etc., and can ensure that the battery has a very high conversion efficiency, which is of great significance for promoting the industrial application of back contact cells.

[0093] In addition, the present invention also investigates the effect of different isolation layer widths on back contact cells, as shown in Table 2.

[0094] Table 2 Effect of different isolation layer widths on various electrical performance data of back contact batteries

[0095]

[0096]

[0097] As can be seen from Table 2, in the present invention, by optimizing the width of the isolation layer to 30μm to 100μm, it is possible to ensure that an insulating layer with excellent insulation effect is formed between the N-type tunnel passivation contact structure and the P-type tunnel passivation contact structure, which can significantly reduce leakage current and reduce the leakage current of the isolation region to below 0.1A. At the same time, it can significantly improve the opening voltage and FF, thereby improving the efficiency of the battery. While ensuring high battery efficiency, a larger process window can also be obtained. Generally speaking, when the width is less than 30μm, due to the laser accuracy of ±10μm, the ITO removal effect in local locations may be unsatisfactory due to the window opening accuracy, resulting in conduction or the laser shifting to the amorphous silicon area, destroying the P region passivation and affecting efficiency. When the width is greater than 100μm, the process window is large and the insulation effect can be guaranteed, but excessive width will lead to reduced efficiency. It can be seen that when the width of the isolation layer is in the range of 30 to 100 μm, both the process window and the cell efficiency are taken into account, which can ensure that good isolation is achieved without causing excessive efficiency loss due to the intrinsic polysilicon isolation area being too wide.

[0098] It can be seen from the above results that compared with conventional back-contact batteries (such as IBC batteries), the preparation method of the back-contact battery of the present invention has the advantages of simple process flow, low manufacturing cost, and easy mass production, and can ensure that the battery has a very high conversion efficiency. The improvement in the mass production efficiency of the back-contact battery is as high as 0.38%, which is of great significance for promoting the industrial application of back-contact batteries.

[0099] The above embodiments are merely preferred embodiments of the present invention, and the scope of protection of the present invention is not limited to the above embodiments. All technical solutions that fall within the scope of protection of the present invention are within the scope of protection of the present invention. It should be noted that improvements and modifications that can be made by a person skilled in the art without departing from the principles of the present invention are also considered to be within the scope of protection of the present invention.

Claims

1. A preparation method of a back-contact battery, characterized in that, It includes the following steps: S1. Polish the silicon wafer; S2. Sequentially prepare a tunneling oxide layer, an intrinsic polysilicon layer, and a mask layer on the back of the silicon wafer; S3. Pattern and open windows on the back of the silicon wafer until the intrinsic polysilicon layer is exposed, and form an N-region pattern on the back of the silicon wafer; S4. Perform phosphorus diffusion on the back of the silicon wafer to form an N-type doped polysilicon layer; S5. Pattern and open windows on the unopened area on the back of the silicon wafer, and keep the width of at least 30 μm or more from the boundary with the opened area unopened until the intrinsic polysilicon layer is exposed, and form a P-region pattern; S6. Clean and texture the front of the silicon wafer; S7. Sequentially deposit a passivation layer on the front of the silicon wafer, deposit an intrinsic amorphous silicon layer on the back of the silicon wafer, and deposit a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer on the intrinsic amorphous silicon layer on the back of the silicon wafer; S8. Deposit an antireflection layer on the front of the silicon wafer; S9. Deposit a transparent conductive oxide layer on the back of the silicon wafer; S10. Open a window on the area above the N-type doped polysilicon layer on the back of the silicon wafer until the intrinsic N-type doped polysilicon layer is exposed, and open a window on the area above the intrinsic polysilicon layer on the back of the silicon wafer until the intrinsic polysilicon layer is exposed; S11. Print a metal electrode on the N-type doped polysilicon layer and the deposited transparent conductive oxide layer, and anneal to form an ohmic contact, completing the preparation of the back-contact battery.

2. The preparation method according to claim 1, wherein In step S5, keep the width of 30 μm to 100 μm from the boundary with the opened area unopened.

3. The preparation method according to claim 2, characterized in that, In step S5, use green nanosecond laser, green picosecond laser, or ultraviolet picosecond laser to pattern and open windows on the unopened area on the back of the silicon wafer.

4. The preparation method according to any one of claims 1 to 3, characterized in that, In step S1, use an alkaline solution to polish the silicon wafer to remove the damaged layer on the surface of the silicon wafer and form a polished surface on the surface of the silicon wafer; the silicon wafer is an N-type silicon wafer; the resistivity of the silicon wafer is 0.3 Ω·cm to 21 Ω·cm; In step S2, use the LPCVD method or the PECVD method to sequentially prepare a tunneling oxide layer, an intrinsic polysilicon layer, and a mask layer on the back of the silicon wafer; when using the LPCVD method to prepare the tunneling oxide layer, it is carried out in an oxygen atmosphere, and the thermal oxidation temperature is 550 °C to 630 °C; when using the LPCVD method to prepare the intrinsic polysilicon layer, use silane as the reaction gas, and the reaction temperature is 550 °C to 630 °C; when using the LPCVD method to prepare the mask layer, use tetraethyl orthosilicate as the oxygen source, and the reaction temperature is 550 °C to 630 °C; when using the PECVD method to prepare the tunneling oxide layer, use one of the combinations of nitrous oxide, nitrous oxide and argon, or nitrous oxide and hydrogen as the oxygen source, and the reaction temperature is 400 °C to 500 °C; when using the PECVD method to prepare the intrinsic polysilicon layer, use silane as the reaction gas, and hydrogen, argon or nitrogen as the dilution gas, and the reaction temperature is 400 °C to 500 °C; when using the PECVD method to prepare the mask layer, use silane and nitrous oxide as the reaction gas, and the reaction temperature is 400 °C to 500 °C; the thickness of the tunneling oxide layer is 0.5 nm to 3 nm; the thickness of the intrinsic polysilicon layer is 40 nm to 400 nm; the mask layer is a silicon oxide thin film; the thickness of the mask layer is 10 nm to 150 nm; In step S3, ultraviolet picosecond laser is used to pattern and open windows on the back side of the silicon wafer; In step S4, the temperature during the phosphorus diffusion process is 860°C to 960°C; the phosphorus source used during the phosphorus diffusion process is phosphorus oxychloride; the thickness of the N-type doped polysilicon layer is 40 nm to 400 nm; the doping concentration of the N-type doped polysilicon layer is 1E20 cm -3 ~3E21 cm -3 ; In step S6, hydrofluoric acid is used to clean the front side of the silicon wafer in a single-sided chain manner to remove silicon oxide or PSG on the front side; In step S7, a passivation layer is sequentially deposited on the front surface of the silicon wafer by PECVD method, and an intrinsic amorphous silicon layer is prepared on the back surface of the silicon wafer; the thickness of the passivation layer is 1 nm to 20 nm; the passivation layer is an intrinsic amorphous silicon thin film or a composite film of an intrinsic amorphous silicon thin film and a doped amorphous silicon thin film; the thickness of the intrinsic amorphous silicon layer is 1 nm to 20 nm; a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer is deposited on the intrinsic amorphous silicon layer on the back surface of the silicon wafer by PECVD method; the thickness of the P-type doped amorphous silicon layer is 3 nm to 40 nm, and the doping concentration is 1E18 cm -3 ~1E20 cm -3 ; the thickness of the P-type doped microcrystalline silicon layer is 3 nm to 40 nm, and the doping concentration is 1E18 cm -3 ~1E20 cm -3 ; In step S8, the antireflection layer is one of silicon nitride thin film, silicon oxynitride thin film, silicon oxide thin film, and transparent conductive oxide thin film, or a composite film stacked by them; when the antireflection layer is silicon nitride thin film, silicon oxynitride thin film, or silicon oxide thin film, the antireflection layer is deposited on the front side of the silicon wafer by PECVD method; when the antireflection layer is transparent conductive oxide thin film, PVD method is used for deposition; the thickness of the antireflection layer is 60nm - 100nm; In step S9, a transparent conductive oxide layer is deposited on the back side of the silicon wafer by PVD method; the material of the transparent conductive oxide layer is at least one of ITO, AZO, and IWO; the thickness of the transparent conductive oxide layer is 20nm - 300nm; In step S10, laser is used to open windows on the regions above the intrinsic polysilicon layer and N-type doped polysilicon layer on the back side of the silicon wafer; In step S11, the material of the metal electrode includes at least one of silver, copper, and nickel.

5. The preparation method according to claim 4, characterized in that, In step S1, the resistivity of the silicon wafer is 1Ω·cm - 7Ω·cm; In step S2, the thickness of the tunneling silicon oxide layer is 1.2nm - 2.0nm; the thickness of the mask layer is 40nm - 100nm; In step S4, the thickness of the N-type doped polysilicon layer is 70 nm to 200 nm; the doping concentration of the N-type doped polysilicon layer is 5E20 cm -3 ~2E21 cm -3 ; In step S7, the thickness of the passivation layer is 3nm - 15nm; the thickness of the intrinsic amorphous silicon layer is 3nm - 15nm; the thickness of the P-type doped amorphous silicon layer is 5nm - 20nm; the thickness of the P-type doped microcrystalline silicon layer is 5nm - 20nm.

6. A back-contact battery, characterized in that, The back contact battery is prepared by the preparation method described in any one of claims 1 - 5.

7. The back-contact battery according to claim 6, characterized in that, The back contact battery includes a silicon substrate, on the back side of which N-type tunneling passivation contact structures and P-type tunneling passivation contact structures are alternately provided, and an isolation layer is provided between the N-type tunneling passivation contact structures and the P-type tunneling passivation contact structures; the width of the isolation layer is 30μm - 100μm.

8. The back contact battery according to claim 7, characterized in that, The isolation layer is sequentially composed of a tunneling silicon oxide layer and an intrinsic polysilicon layer from inside to outside.

9. The back contact battery according to claim 7 or 8, characterized in that, The N-type tunneling passivation contact structure is sequentially composed of a tunneling silicon oxide layer, an N-type doped polysilicon layer, an intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer, a transparent conductive oxide layer, and a first metal electrode from inside to outside; the first metal electrode passes through the transparent conductive oxide layer, the P-type doped amorphous silicon layer or the P-type doped microcrystalline silicon layer, and the intrinsic amorphous silicon layer in sequence and is connected to the N-type doped polysilicon layer to form an ohmic contact; The P-type tunneling passivation contact structure is sequentially composed of an intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer, a transparent conductive oxide layer, and a second metal electrode from inside to outside; the second metal electrode is connected to the transparent conductive oxide layer to form an ohmic contact; The isolation layer is located between the N-type doped polysilicon layer and the intrinsic amorphous silicon layer.

10. The back-contact battery according to claim 9, wherein, On the front side of the silicon substrate, there are a passivation layer and an antireflection layer from inside to outside in sequence.

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