Perovskite crystalline silicon laminated bottom cell structure, laminated cell and preparation method

Abstract

The invention provides a perovskite crystalline silicon laminated bottom cell structure, a laminated cell and a preparation method, the bottom cell structure comprises a semiconductor substrate layer, the first surface of the semiconductor substrate layer is sequentially provided with a boron doped layer, a suede, a passive film layer and a first metal electrode from inside to outside, the second surface of the semiconductor substrate layer is sequentially provided with a small suede, a tunneling oxide layer and an N-type polycrystalline silicon layer from inside to outside, the N-type polycrystalline silicon layer comprises at least two kinds of polycrystalline silicon layers which are alternately arranged in the horizontal direction and are different in thickness, and the height of the small suede is smaller than that of the suede. According to the invention, the N-type polycrystalline silicon layer is arranged into polycrystalline silicon layers with different thicknesses which are alternately arranged, so that the parasitic absorption of photons is reduced, and the current output of the bottom cell is improved. After photon parasitic absorption is reduced, the deposition thickness of the first polycrystalline silicon layer is increased, and under the condition that the second surface is a textured surface, npoly can uniformly cover the textured surface, so that the passivation level is ensured, and the conditions of exposure defects, increase of carrier recombination and reduction of cell performance are avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of perovskite solar cells, and in particular relates to a perovskite crystalline silicon stacked bottom cell structure and a stacked cell and a preparation method thereof. Background Art

[0002] With the continuous growth of global energy demand and increasing environmental awareness, the development and utilization of solar energy as a clean and renewable energy source is gaining increasing attention. In the field of solar cell technology, tandem solar cells have become a research hotspot due to their ability to more efficiently utilize the solar spectrum and improve photoelectric conversion efficiency. Perovskite-crystalline silicon tandem cells, in particular, demonstrate enormous application potential due to their combined advantages of perovskite materials and crystalline silicon.

[0003] Related research shows that for every 10nm increase in the thickness of the front polysilicon, the current loss will increase by 0.5mA / cm 2 This severely restricts the development of high-performance bifacial TOPCon cells. As the bottom cell of perovskite-silicon tandem cells, it also limits the development of tandem cells. Therefore, controlling the thickness of the polysilicon layer in perovskite-silicon tandem cells remains a key technical challenge.

[0004] In the prior art, polysilicon layers typically have a uniform thickness. For example, CN110867516A discloses a perovskite and crystalline silicon back-passivated tandem solar cell and its manufacturing method. The cell comprises a bottom cell and a top cell, with an upper electrode fixedly connected to the top cell. An intermediate layer is provided between the bottom and top cells. The bottom cell is a crystalline silicon back-passivated cell, the intermediate layer is a transparent conductive layer, and the top cell is a perovskite cell. The bottom cell is defined as a uniform back-doped polysilicon layer with a thickness of 40 to 450 nm.

[0005] This technical solution faces a dilemma: On the one hand, excessively thick polysilicon layers will produce excessive parasitic absorption, reducing the number of photons reaching the bottom cell and thus reducing the current output of the bottom cell; on the other hand, too thin a polysilicon layer will affect the passivation effect of the bottom cell, leading to increased carrier recombination and reduced cell performance. In addition, the existing planar polysilicon layer structure limits the contact area with the transparent conductive layer, increasing the interface contact resistance and lateral transmission resistance, which is not conducive to current collection and transmission. Summary of the Invention

[0006] The purpose of the present invention is to provide a perovskite crystalline silicon stacked bottom cell structure to solve the above-mentioned technical problems existing in the prior art.

[0007] Another object of the present invention is to provide a method for preparing a perovskite crystalline silicon stacked bottom cell structure, in which a polycrystalline silicon layer is arranged into a first crystalline silicon layer and a second crystalline silicon layer of different thicknesses arranged alternately by a wet method.

[0008] Another object of the present invention is to provide a perovskite crystalline silicon stacked cell, which increases the contact area between the polysilicon layer and the transparent conductive layer, can reduce the interface contact resistance and lateral transmission resistance, is beneficial to the collection and transmission of current between the bottom cell and the top cell, improves cell filling, and enhances cell efficiency.

[0009] Another object of the present invention is to provide a method for preparing a perovskite crystalline silicon stacked cell.

[0010] To this end, the technical solutions provided by the present invention are as follows:

[0011] A perovskite crystalline silicon stacked bottom cell structure includes a semiconductor substrate layer, wherein the first surface of the semiconductor substrate layer is provided with a boron-doped layer, a passivation film layer and a first metal electrode in sequence from the inside to the outside of the velvet structure, and the second surface of the semiconductor substrate layer is provided with a small velvet, a tunneling oxide layer and an N-type polysilicon layer in sequence from the inside to the outside of the velvet structure, wherein the N-type polysilicon layer includes at least two polysilicon layers alternately arranged in the horizontal direction and having different thicknesses, and the height of the small velvet is less than the height of the velvet structure.

[0012] The N-type polysilicon layer includes a first polysilicon layer and a second polysilicon layer, the thickness of the first polysilicon layer is 10nm-400nm, the thickness of the second polysilicon layer is 20%-90% of the thickness of the first polysilicon layer, and the second polysilicon layer occupies 2%-45% of the area of ​​the N-type polysilicon layer.

[0013] The height of the small suede surface is 0.5 μm-1.2 μm.

[0014] A method for preparing a perovskite crystalline silicon stacked bottom cell structure comprises the following steps:

[0015] Step 1) Texturing: using alkaline solution etching to form a pyramid texture structure of uniform size on both sides of the semiconductor substrate layer;

[0016] Step 2) Boron diffusion: Using BCl3 as the diffusion source, the diffusion temperature is 500℃-900℃, and the diffusion resistance is controlled at 200-500Ω / Sq;

[0017] Step 3) removing the second surface of the semiconductor substrate layer from the coating and polishing;

[0018] Step 4) Secondary texturing to prepare a small textured surface: using an alkaline solution to etch, a small textured surface with a small pyramid structure of uniform size is formed on the second surface of the semiconductor substrate layer;

[0019] Step 5) depositing a tunnel oxide layer and an intrinsic polysilicon layer;

[0020] Step 6) Phosphorus diffusion: Using POCl3 as a diffusion source, phosphorus is diffused in the intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer and a PSG layer;

[0021] Step 7) Forming an alkali-washed second polysilicon layer window: Using laser to process the PSG layer, ablating SiOx to form an alkali-washed second polysilicon layer window, with the ablation area being 1%-40%;

[0022] Step 8) Plating the first surface;

[0023] Step 9) forming a second polysilicon layer on the second surface: alkali-washing the second polysilicon layer window and then etching with alkaline solution to form the second polysilicon layer, thereby obtaining an N-type polysilicon layer in which the first polysilicon layer and the second polysilicon layer are alternately arranged in a horizontal direction; after etching, the semiconductor substrate layer is cleaned with a cleaning solution and then dried;

[0024] Step 10) Deposition of passivation film and H + Passivation: Deposit a passivation layer on the first surface of the semiconductor substrate layer; perform hydrogen passivation on the second surface of the semiconductor substrate layer, using the passivation film and H in an NH3 atmosphere. + sedimentation;

[0025] Step 11) Printing and sintering: Printing AgAl paste on the first surface of the semiconductor substrate layer and sintering to form a front first metal electrode.

[0026] In step 5), the tunnel oxide layer and the intrinsic polysilicon layer are deposited using LPCVD technology. The thickness of the deposited tunnel oxide layer is 1 nm to 5 nm, and the thickness of the deposited intrinsic polysilicon film is 40 nm to 500 nm.

[0027] Step 6) Phosphorus diffusion temperature is 700℃-900℃, doping concentration is 1~5E20cm -3 , wherein the thickness of the PSG layer is 10nm-100nm.

[0028] In step 7), the output power of the laser is 10W~70W, the pulse repetition frequency is 5kHz~20kHz, the diameter of the laser spot is 5Pm~15Pm, and the laser beam speed is 30mm / s~60mm / s.

[0029] In step 9), the alkaline solution is one of NaOH and KOH or a mixture thereof, the concentration of the alkaline solution is 0.5wt%-10wt%, and the etching time is 10s-150s.

[0030] A perovskite / TOPCon stacked cell, comprising a perovskite cell, a transparent conductive oxide layer, and a perovskite crystalline silicon layer bottom cell structure arranged sequentially from top to bottom, wherein the transparent conductive oxide layer and the second surface of the perovskite crystalline silicon layer bottom cell structure are in contact;

[0031] The perovskite battery comprises a hole transport layer, a perovskite thin film layer, an electron transport layer, a carrier recombination layer, an anti-reflection film layer and a second metal electrode, which are arranged in sequence from the inside to the outside.

[0032] A method for preparing a perovskite / TOPCon stacked cell comprises the following steps:

[0033] S1, preparation of the bottom cell structure of the perovskite crystalline silicon layer: the semiconductor substrate layer is sequentially textured and boron diffused, the second surface is polished after de-plating, the second surface is textured again to form a small velvet surface, an oxide tunneling oxide layer and an intrinsic polysilicon layer are deposited, followed by phosphorus diffusion, the second polysilicon layer PSG is laser treated, the positive de-plating is performed and alkaline washing is performed to form the second polysilicon layer, a passivation film layer and H+ passivation are deposited, the first metal electrode is printed and sintered to obtain the bottom cell;

[0034] S2, preparation of transparent conductive oxide layer: under a pressure of ≤1Pa and an argon-oxygen ratio of 1:0.02-0.1, the power density is 1-3W / cm 2 , preparing a transparent conductive oxide layer on the second surface of the bottom cell by PVD magnetron sputtering;

[0035] S3, preparation of hole transport layer: preparation of dense TiO2 layer with thickness of 30nm-100nm at high temperature of 400℃-550℃ by spray pyrolysis method;

[0036] S4, preparing a perovskite thin film layer: the band gap width of the perovskite layer is 1.3eV-1.8eV, the perovskite material structure is ABX3, wherein A is any one of methylamine, formamidine, and Cs or a mixture of several cations, B is Pb or Sn, and X is any one of Cl, Br, and I or a mixture of three anions, and the thickness is 800nm-1200nm;

[0037] S5, preparing an electron transport layer: preparing an electron transport layer made of SnO2 on the perovskite film layer, with a thickness of 15nm-40nm;

[0038] S6, preparing a carrier recombination layer: preparing a carrier recombination layer on the electron transport layer, the material of which is ITO with a thickness of 30 nm to 100 nm;

[0039] S7, depositing an anti-reflection film layer;

[0040] S8, printing AgAl paste on the front side of the stack, forming the second metal electrode on the front side after sintering to obtain a perovskite crystalline silicon stacked battery.

[0041] The beneficial effects of the present invention are:

[0042] The perovskite crystalline silicon stacked bottom cell structure provided by the present invention features an N-type polysilicon layer configured as a first and second crystalline silicon layer of varying thicknesses, alternating between them. This reduces parasitic absorption of photons by the polysilicon layer, thereby improving the current output of the bottom cell. While ensuring reduced parasitic absorption, the first polysilicon layer can be deposited with a suitable thickness. This allows the N-type polysilicon layer to evenly cover the velvet surface on the second surface, ensuring passivation and preventing defects from being exposed, increasing carrier recombination, and degrading cell performance.

[0043] The perovskite crystalline silicon stacked cell provided by the present invention increases the contact area between the polysilicon layer and the transparent conductive layer, can reduce the interface contact resistance and lateral transmission resistance, is beneficial to the collection and transmission of current between the bottom cell and the top cell, improves cell filling, and enhances cell efficiency.

[0044] The method of the present invention deposits a polysilicon layer and a PSG layer of uniform thickness on the second surface of the bottom cell. According to different designs of polysilicon thickness difference patterns, the PSG on the second polysilicon layer is first processed by laser, and then a part of the polysilicon layer in the second polysilicon region of the bottom cell is removed by alkaline solution. Finally, the remaining PSG on the first polysilicon layer is cleaned and removed by acid solution, thereby achieving alternating arrangement of two or more polysilicon layers according to the design, and solving technical problems such as excessive parasitic absorption caused by uniform thickness of the polysilicon layer, and influence of the passivation effect of the bottom cell caused by excessive thinness, as well as limiting the contact between the polysilicon layer and the transparent conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a schematic structural diagram of an embodiment of the perovskite crystalline silicon stacked bottom cell structure of the present invention;

[0046] Figure 2 This is a schematic structural diagram of an embodiment of the perovskite / TOPCon tandem battery of the present invention;

[0047] Figure 3 This is a flow chart for preparing the perovskite crystalline silicon stacked bottom cell structure of the present invention.

[0048] Explanation of the accompanying symbols: 1. N-type polysilicon layer; 2. Semiconductor substrate layer; 3. Passivation film layer; 4. First polysilicon layer; 5. Tunneling oxide layer; 6. Boron-doped layer; 7. First metal electrode; 8. Second polysilicon layer; 9. Anti-reflection film layer; 10. Carrier recombination layer; 11. Electron transport layer; 12. Perovskite thin film layer; 13. Hole transport layer; 14. Transparent conductive oxide layer; 15. Second metal electrode; 16. Bottom cell; 17. Small velvet; 18. Velvet structure. DETAILED DESCRIPTION

[0049] The following describes the embodiments of the invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the invention from the contents disclosed in this specification.

[0050] Exemplary embodiments of the present invention will now be described with reference to the accompanying drawings. However, the invention may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so as to provide a thorough and complete disclosure of the invention and fully convey the scope of the invention to those skilled in the art. The terms used in the exemplary embodiments shown in the accompanying drawings are not intended to limit the invention. In the accompanying drawings, identical units / elements are denoted by the same reference numerals.

[0051] Unless otherwise specified, the terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have meanings consistent with the context of their relevant fields and should not be interpreted as idealized or overly formal.

[0052] Example 1

[0053] The present invention provides a perovskite crystalline silicon stacked bottom cell structure, comprising a semiconductor substrate layer 2, wherein the first surface of the semiconductor substrate layer 2 is provided with a boron-doped layer 6, a passivation film layer 3 and a first metal electrode 7 with a velvet structure 18 from the inside to the outside, and the second surface of the semiconductor substrate layer 2 is provided with a small velvet 17, a tunneling oxide layer 5 and an N-type polysilicon layer 1 from the inside to the outside, wherein the N-type polysilicon layer 1 includes at least two polysilicon layers alternately arranged in the horizontal direction and having different thicknesses, and the height of the small velvet 17 is less than the height of the velvet structure 18.

[0054] In the perovskite crystalline silicon stacked bottom cell structure provided by the present invention, the N-type polysilicon layer 1 is configured as polysilicon layers of varying thicknesses, reducing parasitic absorption of photons by the polysilicon layer, thereby improving the current output of the bottom cell 16. After ensuring reduced parasitic absorption of photons, the first polysilicon layer 4 can be deposited with an appropriately increased thickness. This allows the N-type polysilicon layer to evenly cover the textured surface when the second surface is textured, ensuring a high level of passivation and preventing defects from being exposed, increasing carrier recombination, and degrading cell performance.

[0055] Example 2

[0056] Based on Example 1, this embodiment provides a perovskite crystalline silicon stacked bottom cell structure, such as Figure 1As shown, the N-type polysilicon layer 1 includes a first polysilicon layer 4 and a second polysilicon layer 8. The thickness of the first polysilicon layer 4 is 10nm-400nm, the second polysilicon layer 8 is 20%-90% of the thickness of the first polysilicon layer 4, and the second polysilicon layer 8 occupies 2%-45% of the area of ​​the N-type polysilicon layer 1.

[0057] The height of the small suede surface 17 is 0.5 μm-1.2 μm.

[0058] The preparation process is as follows:

[0059] The single crystal silicon wafer (semiconductor substrate layer 2) is sequentially textured, boron diffused, and the second surface is removed for plating and polished. The small velvet surface 17 of the second surface is textured a second time. The tunneling oxide layer 5 is oxidized by LPCVD and an intrinsic polysilicon layer is deposited. Phosphorus is diffused, the second polysilicon layer 8PSG is laser treated, the first surface is removed for plating and the second polysilicon layer 8 is alkaline washed, a passivation film layer 3 and H+ passivation are deposited, a metal electrode is printed and sintered to obtain a bottom battery 16.

[0060] Example 3

[0061] This embodiment provides a method for preparing a perovskite crystalline silicon stacked bottom cell structure. Figure 3 As shown, the following steps are included:

[0062] Step 1) Texturing: using an alkaline solution to etch, a pyramid texture structure 18 of uniform size is formed on both sides of the semiconductor substrate layer 2;

[0063] Step 2) Boron diffusion: Using BCl3 as the diffusion source, the diffusion temperature is 500℃-900℃, and the diffusion resistance is controlled at 200-500Ω / Sq;

[0064] Step 3) removing the wrap-around plating on the second surface of the semiconductor substrate layer 2 and polishing; removing the wrap-around plating on the back side using high-concentration HF, wherein the HF concentration is controlled between 5 wt% and 20 wt%;

[0065] Step 4) Secondary texturing to prepare small textured surfaces 17: using alkaline solution etching to form small textured surfaces 17 of uniform pyramidal structure on the second surface of the semiconductor substrate layer 2; the height of the small textured surfaces 17 is controlled to be between 0.5-1.2 μm;

[0066] Step 5) depositing a tunnel oxide layer 5 and an intrinsic polysilicon layer; using LPCVD technology, depositing the tunnel oxide layer 5 to a thickness of 1-5 nm; and continuing to deposit an intrinsic polysilicon film to a thickness of 40-500 nm;

[0067] Step 6) Phosphorus diffusion: Using POCl3 as a diffusion source, phosphorus is diffused in the intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer and a PSG layer; the thickness of the phosphorus-doped first polysilicon layer 4 is 10-400nm, the thickness of the PSG is 10-100nm, the diffusion temperature is 700-900℃, and the doping concentration is 1~5E20cm -3 ;

[0068] Step 7) Forming a window in the alkaline-washed second polysilicon layer 8: Using a laser to process the PSG layer, ablating SiOx to form a window in the alkaline-washed second polysilicon layer 8, with the ablation area ranging from 1% to 40%. The laser parameters are: output power of 10W to 70W, pulse repetition frequency of 5 to 20kHz, laser spot diameter of 5 μm to 15 μm, and laser beam speed of 30 mm / s to 60 mm / s.

[0069] Step 8) Remove the first surface wrap-around plating; use HF to remove the back surface wrap-around plating;

[0070] Step 9) forming a second polysilicon layer 8 on the second surface: alkali-washing the window of the second polysilicon layer 8 and etching with alkaline solution to form the second polysilicon layer 8, thereby obtaining an N-type polysilicon layer 1 in which the first polysilicon layers 4 and the second polysilicon layers 8 are alternately arranged in a horizontal direction; after etching, the semiconductor substrate layer 2 is cleaned with a cleaning solution and then dried;

[0071] The etching depth of the second polysilicon layer 8 is 10%-80% of the first polysilicon layer 4 (i.e., the second polysilicon layer 8 is 20%-90% of the thickness of the first polysilicon layer 4). After alkali washing, the area of ​​the second polysilicon layer 8 accounts for 2%-45%; the alkali solution used is one of NaOH or KOH or a mixture, the concentration of the alkali solution is 0.5-10wt%, and the etching time is 10s-150s; after etching, the silicon wafer is cleaned with HF / H2O2 and NH3 / H2O2 cleaning solutions, and then dried.

[0072] Step 10) Deposition of passivation film layers 3 and H + Passivation: Deposit a passivation layer on the first surface of the semiconductor substrate layer 2; Perform hydrogen passivation on the second surface of the semiconductor substrate layer 2, using the passivation film layer 3 and H in an NH3 atmosphere. + Deposition: using PECVD to deposit one or more SiOx or SiNx film layers to form passivation; hydrogen passivation uses PECVD, and the NH3 flow rate is controlled at 6000ml-20000ml;

[0073] Step 11) Printing and sintering: Printing AgAl paste on the first surface of the semiconductor substrate layer 2 and sintering to form the front first metal electrode 7.

[0074] The method of the present invention deposits a polysilicon layer and a PSG layer of uniform thickness on the second surface of the bottom cell 16. According to different designs of polysilicon thickness difference patterns, the PSG on the second polysilicon layer 8 is first processed by laser, and then a part of the polysilicon layer in the second polysilicon region of the bottom cell 16 is removed by alkaline solution. Finally, the mask of the first polysilicon layer 4 is cleaned and removed by acid solution, thereby achieving an alternating arrangement of two or more polysilicon layers according to the design, and solving technical problems such as excessive parasitic absorption caused by uniform thickness of the polysilicon layer, and the effect of excessive thinness on the passivation effect of the bottom cell 16, as well as limiting the contact between the polysilicon layer and the transparent conductive layer.

[0075] Example 4

[0076] This embodiment provides a perovskite / TOPCon stacked cell, such as Figure 2 As shown, it includes a perovskite cell, a transparent conductive oxide layer 14 and a perovskite crystalline silicon layer bottom cell structure arranged in sequence from top to bottom, and the transparent conductive oxide layer is in contact with the second surface of the perovskite crystalline silicon layer bottom cell structure;

[0077] The perovskite cell includes a hole transport layer 13, a perovskite thin film layer 12, an electron transport layer 11, a carrier recombination layer 10, an anti-reflection film layer 9 and a second metal electrode 15, which are arranged in sequence from the inside to the outside.

[0078] The bottom cell 16 of the stacked battery of the present invention utilizes a wet method to remove part of the polysilicon to form an N-type polysilicon layer 1 having alternating first and second polysilicon layers 4 and 8 and different thicknesses. This reduces the parasitic absorption of photons by the polysilicon layer, thereby improving the current output of the bottom cell 16. The alternating structure of polysilicon of different thicknesses increases the contact area between the polysilicon layer and the transparent conductive layer, which can reduce the interface contact resistance and lateral transmission resistance, thereby facilitating the collection and transmission of current between the bottom cell 16 and the top cell, improving cell filling, and improving cell efficiency.

[0079] Example 5

[0080] This embodiment provides a method for preparing a perovskite / TOPCon tandem cell, comprising the following steps:

[0081] S1, preparing a perovskite crystalline silicon bottom cell structure: the semiconductor substrate layer 2 is sequentially textured and boron diffused, the second surface is removed for winding plating and then polished, a second textured surface 17 of the second surface is formed, an oxide tunneling oxide layer 5 and an intrinsic polysilicon layer are deposited, phosphorus is diffused, the second polysilicon layer 8PSG is laser treated, the positive winding plating is removed and alkaline washing is performed to form a second polysilicon layer 8, a passivation film layer 3 and H+ passivation are deposited, a first metal electrode 7 is printed and sintered to obtain a bottom cell 16;

[0082] S2, preparing a transparent conductive oxide layer 14: in an atmosphere with a pressure of ≤1 Pa and an argon-oxygen ratio of 1:0.02-0.1, the power density is 1-3 W / cm 2 , preparing a transparent conductive oxide layer 14 on the second surface of the bottom cell 16 by PVD magnetron sputtering;

[0083] S3, preparing the hole transport layer 13: preparing a dense TiO2 layer with a thickness of 30nm-100nm at a high temperature of 400℃-550℃ by spray pyrolysis method;

[0084] S4, preparing a perovskite thin film layer 12: the band gap width of the perovskite layer is 1.3eV-1.8eV, the perovskite material structure is ABX3, wherein A is any one of methylamine, formamidine, and Cs or a mixture of several cations, B is Pb or Sn, and X is any one of Cl, Br, and I or a mixture of three anions, and the thickness is 800nm-1200nm;

[0085] S5, preparing an electron transport layer 11: preparing an electron transport layer 11 on the perovskite thin film layer 12. The material of the electron transport layer 11 is SnO2, and the thickness thereof is 15nm-40nm;

[0086] S6, preparing a carrier recombination layer 10: preparing a carrier recombination layer 10 on the electron transport layer 11, the material of which is ITO, with a thickness of 30nm-100nm;

[0087] S7, depositing an anti-reflection film layer 9;

[0088] S8, printing AgAl paste on the front side of the stack, and forming the second metal electrode 15 on the front side after sintering to obtain a perovskite crystalline silicon stacked cell.

[0089] The perovskite crystalline silicon stacked cell provided by the present invention increases the contact area between the polysilicon layer and the transparent conductive layer, can reduce the interface contact resistance and the lateral transmission resistance, is beneficial to the collection and transmission of current between the bottom cell 16 and the top cell, improves cell filling, and enhances cell efficiency.

[0090] Example 6

[0091] Based on Example 5, this example provides a method for preparing a perovskite / TOPCon tandem cell, comprising the following steps:

[0092] S1, texturing: Using a low-concentration alkaline solution to etch, a pyramid structure of uniform size is formed on both sides of the semiconductor substrate layer 2 silicon wafer (N-type single-crystal silicon wafer, resistivity range 1.0-7.0 / (Ω×m), thickness 100-200 μm, size 182×183.75 mm). The low-concentration alkaline solution is controlled at 1-3wt%, the texturing time is controlled at 500 s, the texturing temperature is controlled at 65℃-75℃, and the height is 1.2μm.

[0093] S2, Boron Diffusion: Use BCl3 as a diffusion source to diffuse on the first surface of the silicon wafer to lightly dope the emitter; the diffusion temperature is 500℃, and the diffusion resistance is controlled at 200Ω / Sq;

[0094] S3, removing the second surface wrap and polishing: using high concentration HF to remove the second surface wrap; wherein the HF concentration is controlled at 6wt%;

[0095] S4, secondary texturing to prepare small textured surface 17 on the second surface: using low-concentration alkaline solution to etch, small pyramid structures of uniform size are formed on the second surface of the silicon wafer, with the texture height controlled at 0.7 μm; the low-concentration alkaline solution is controlled at 2wt%, the texturing time is controlled at 100 s, and the texturing temperature is controlled at 60°C;

[0096] S5, tunnel oxide layer 5 and intrinsic polysilicon layer: using LPCVD technology, deposit a tunnel oxide layer 5 with a thickness of 1.5 nm on the second surface; and then continue to deposit an intrinsic polysilicon film with a thickness of 90 nm on the tunnel oxide layer 5 to form an intrinsic polysilicon layer;

[0097] S6, Phosphorus Diffusion: Using POCl3 as a diffusion source, phosphorus is diffused in the intrinsic polysilicon layer to form a phosphorus-doped layer and a PSG layer. The thickness of the phosphorus-doped first polysilicon layer 4 is 50nm, and the thickness of the PSG is 40nm; the diffusion temperature is 700℃, and the doping concentration is 1E20cm -3 ;

[0098] S7, laser treatment of the second polysilicon layer 8 PSG: using laser treatment of the PSG layer, ablating SiOx to form a window for alkali-washing the second polysilicon layer 8, with an ablation area of ​​25%; the laser parameters are: output power 50W, pulse repetition frequency 10kHz, laser spot diameter 10μm, and laser beam speed 55mm / s;

[0099] S8, removing the second polysilicon layer 8 from the first surface by wrapping and alkali washing: using high-concentration HF to remove the wrapping on the back side; using alkaline solution to form the second polysilicon layer 8, the etching depth is 60% of the first polysilicon layer 4, the thickness is 20nm, and the area of ​​the second polysilicon layer 8 after alkali washing accounts for 27%; the alkaline solution used is NaOH, the alkaline solution concentration is 3wt%, and the etching time is 100s; after etching, the silicon wafer is cleaned with HF / H2O2 and NH3 / H2O2 cleaning solutions, and then dried;

[0100] S9, Deposition of Passivation Film Layer 3 and H+ Passivation: Deposit a passivation layer on the first surface of the silicon wafer using PECVD to deposit a SiNx film with a thickness of 30 nm; Perform hydrogen passivation on the second surface of the silicon wafer using an NH3 atmosphere to passivate the silicon wafer and provide H+. The instrument used is a PECVD device with an NH3 flow rate controlled at 10,000 ml.

[0101] S10, printing: printing AgAl paste on the first surface of the silicon wafer, forming the first metal electrode 7 after sintering. The bottom cell structure is as follows: Figure 2 As shown;

[0102] S11, using 8 wt% HF to remove the SiNx film on the second surface of the bottom cell 16; then using PVD magnetron sputtering equipment, forming an 80 nm thick ITO material as a transparent conductive oxide layer 14 on the second surface of the TOPCon bottom cell 16;

[0103] S12, using a spray pyrolysis method to prepare a 50 nm thick TiO2 material as a hole transport layer 13 on the transparent conductive oxide layer 14;

[0104] S13, preparing a perovskite thin film layer 121000 nm on the hole transport layer 13 by spin coating;

[0105] S14, using a spin coating method to prepare a 30 nm thick SnO2 material layer as an electron transport layer 11 on the perovskite thin film layer 12;

[0106] S15, using PVD magnetron sputtering, forming an 80 nm thick ITO material as a carrier recombination layer 10 on the electron transport layer 11;

[0107] S16, using PECVD to deposit a 70nm thick SiNx film layer (reflective layer) on the front, printing AgAl paste on the front of the stack, and forming the second metal electrode 15 on the front after sintering to obtain a perovskite crystalline silicon stacked battery. The structure of the perovskite crystalline silicon stacked battery is as follows: Figure 3 shown.

[0108] In order to further illustrate the effects of the present invention, the electrical performance of the perovskite / TOPCon stacked cell prepared in Example 6 was compared with that of Comparative Examples 1 to 6.

[0109] Comparative Example 1

[0110] Compared with Example 6, the difference in the preparation method of Comparative Example 1 is that the thickness of the first polysilicon layer 4 is too thick.

[0111] In the preparation method of the bottom cell 16, S5 tunnels the oxide layer 5 and the intrinsic polysilicon layer: using LPCVD technology, a tunnel oxide layer 5 with a thickness of 1.5 nm is deposited on the second surface; and an intrinsic polysilicon film with a thickness of 600 nm is continuously deposited on the tunnel oxide layer 5 to form an intrinsic polysilicon layer.

[0112] S6 Phosphorus Diffusion: Using POCl3 as a diffusion source, phosphorus is diffused in the intrinsic polysilicon layer to form a phosphorus-doped layer and a PSG layer. The thickness of the phosphorus-doped first polysilicon layer 4 is 550nm, and the thickness of the PSG is 50nm; the diffusion temperature is 700℃, and the doping concentration is 1E20cm -3 ;

[0113] S7 Laser Treatment of Second Polysilicon Layer 8PSG: Laser treatment of the PSG layer to ablate SiOx to form a window for alkali-washing the second polysilicon layer 8, with an ablation area of ​​25%. The laser parameters are: output power 50W, pulse repetition frequency 10kHz, laser spot diameter 10pm, and laser beam speed 55mm / s.

[0114] S8: Remove the second polysilicon layer 8 after wraparound plating on the first surface and then alkali-wash it: Use high-concentration HF to remove the wraparound plating on the back side; use alkali solution to form the second polysilicon layer 8, the etching depth is 60% of the first polysilicon layer 4, the thickness is 330nm, and the area of ​​the second polysilicon layer 8 after alkali washing accounts for 27%; the alkali solution used is NaOH, the alkali solution concentration is 3wt%, and the etching time is 100s; after etching, the silicon wafer is cleaned with HF / H2O2 and NH3 / H2O2 cleaning solutions, and then dried;

[0115] The remaining steps are the same as those in Example 6.

[0116] Comparative Example 2

[0117] Compared with Example 6, the difference in the preparation method of Comparative Example 2 is that the thickness of the first polysilicon layer 4 is too thin.

[0118] In the preparation method of the bottom cell 16, S5 tunneling oxide layer 5 and intrinsic polysilicon layer: using LPCVD technology, a tunneling oxide layer 5 with a thickness of 1.5 nm is deposited on the second surface; and an intrinsic polysilicon film with a thickness of 20 nm is continuously deposited on the tunneling oxide layer 5 to form an intrinsic polysilicon layer.

[0119] S6 Phosphorus Diffusion: Using POCl3 as a diffusion source, phosphorus is diffused in the intrinsic polysilicon layer to form a phosphorus-doped layer and a PSG layer. The thickness of the phosphorus-doped first polysilicon layer 4 is 10nm, and the thickness of the PSG is 10nm; the diffusion temperature is 700℃, and the doping concentration is 1E20cm -3 ;

[0120] S7 Laser treatment of the second polysilicon layer 8 PSG: Laser treatment of the PSG layer to ablate SiOx to form a window for alkali-washing the second polysilicon layer 8, with an ablation area of ​​25%. The laser parameters are: output power 30 W, pulse repetition frequency 7 kHz, laser spot diameter 10 μm, and laser beam speed 55 mm / s.

[0121] S8: Remove the second polysilicon layer 8 on the first surface by wrapping around and alkali washing: Use high concentration HF to remove the wrapping around the back side; use alkali solution to form the second polysilicon layer 8, the etching depth is 60% of the first polysilicon layer 4, the thickness is 6nm, and the area of ​​the second polysilicon layer 8 after alkali washing accounts for 27%; the alkali solution used is NaOH, the concentration of the alkali solution is 1wt%, and the etching time is 10s; after etching, use HF / H2O2 and NH3 / H2O2 cleaning solutions to clean the silicon wafer; and then dry it.

[0122] The remaining steps are the same as those in Example 6.

[0123] Comparative Example 3

[0124] Compared with Example 6, the difference in the preparation method of Comparative Example 3 is that the etching depth of the second polysilicon layer 8 is too deep.

[0125] In the preparation method of the bottom cell 16, S5 tunneling oxide layer 5 and intrinsic polysilicon layer: using LPCVD technology, a tunneling oxide layer 5 with a thickness of 1.5 nm is deposited on the second surface; and an intrinsic polysilicon film with a thickness of 90 nm is continuously deposited on the tunneling oxide layer 5 to form an intrinsic polysilicon layer.

[0126] S6 Phosphorus Diffusion: Using POCl3 as a diffusion source, phosphorus is diffused in the intrinsic polysilicon layer to form a phosphorus-doped layer and a PSG layer. The thickness of the phosphorus-doped first polysilicon layer 4 is 50 nm, and the thickness of the PSG is 40 nm. The diffusion temperature is 700 ° C, and the doping concentration is 1E20 cm -3 ;

[0127] S7 Laser Treatment of Second Polysilicon Layer 8PSG: Laser treatment of the PSG layer to ablate SiOx to form a window for alkali-washing the second polysilicon layer 8, with an ablation area of ​​25%. The laser parameters are: output power 50W, pulse repetition frequency 10kHz, laser spot diameter 10pm, and laser beam speed 55mm / s.

[0128] S8: Remove the second polysilicon layer 8 on the first surface by wrap-around plating and add alkali washing: Use high concentration HF to remove the wrap-around plating on the back side; use alkali solution to form the second polysilicon layer 8, the etching depth is 90% of the first polysilicon layer 4, the thickness is 5 nm, and the area of ​​the second polysilicon layer 8 after alkali washing accounts for 27%; the alkali solution used is NaOH, the concentration of the alkali solution is 5wt%, and the etching time is 400s; after etching, use HF / H2O2 and NH3 / H2O2 cleaning solutions to clean the silicon wafer; and then dry it.

[0129] The remaining steps are the same as those in Example 6.

[0130] Comparative Example 4

[0131] Compared with Example 6, the difference in the preparation method of Comparative Example 4 is that the etching depth of the second polysilicon layer 8 is too shallow.

[0132] In the preparation method of the bottom cell 16, S5 tunneling oxide layer 5 and intrinsic polysilicon layer: using LPCVD technology, a tunneling oxide layer 5 with a thickness of 1.5 nm is deposited on the second surface; and an intrinsic polysilicon film with a thickness of 90 nm is continuously deposited on the tunneling oxide layer 5 to form an intrinsic polysilicon layer.

[0133] S6 Phosphorus Diffusion: Using POCl3 as a diffusion source, phosphorus is diffused in the intrinsic polysilicon layer to form a phosphorus-doped layer and a PSG layer. The thickness of the phosphorus-doped first polysilicon layer 4 is 50 nm, and the thickness of the PSG is 40 nm. The diffusion temperature is 700 ° C, and the doping concentration is 1E20 cm -3 ;

[0134] S7 Laser Treatment of Second Polysilicon Layer 8PSG: Laser treatment of the PSG layer to ablate SiOx to form a window for alkali-washing the second polysilicon layer 8, with the ablation area being 90%. The laser parameters are: output power 50W, pulse repetition frequency 10kHz, laser spot diameter 10pm, and laser beam speed 55mm / s.

[0135] S8: Remove the second polysilicon layer 8 on the first surface by wrapping around and alkali washing: Use high concentration HF to remove the wrapping around the back side; use alkali solution to form the second polysilicon layer 8, the etching depth is 6% of the first polysilicon layer 4, the thickness is 47 nm, and the area of ​​the second polysilicon layer 8 after alkali washing accounts for 27%; the alkali solution used is NaOH, the concentration of the alkali solution is 1wt%, and the etching time is 10s; after etching, use HF / H2O2 and NH3 / H2O2 cleaning solutions to clean the silicon wafer; and then dry it.

[0136] The remaining steps are the same as those in Example 6.

[0137] Comparative Example 5

[0138] Compared with Example 6, the difference in the preparation method of Comparative Example 5 is that the second polysilicon layer 8 occupies too large an area.

[0139] In the preparation method of the bottom cell 16, S5 tunneling oxide layer 5 and intrinsic polysilicon layer: using LPCVD technology, a tunneling oxide layer 5 with a thickness of 1.5 nm is deposited on the second surface; and an intrinsic polysilicon film with a thickness of 90 nm is continuously deposited on the tunneling oxide layer 5 to form an intrinsic polysilicon layer.

[0140] S6 Phosphorus Diffusion: Using POCl3 as a diffusion source, phosphorus is diffused in the intrinsic polysilicon layer to form a phosphorus-doped layer and a PSG layer. The thickness of the phosphorus-doped first polysilicon layer 4 is 50 nm, and the thickness of the PSG is 40 nm. The diffusion temperature is 700 ° C, and the doping concentration is 1E20 cm -3 ;

[0141] S7 Laser Treatment of Second Polysilicon Layer 8PSG: Laser treatment of the PSG layer to ablate SiOx to form a window for alkali-washing the second polysilicon layer 8, with an ablation area of ​​70%. The laser parameters are: output power 50W, pulse repetition frequency 10kHz, laser spot diameter 10pm, and laser beam speed 55mm / s.

[0142] S8: Remove the second polysilicon layer 8 on the first surface by wrapping around and alkali washing: Use high concentration HF to remove the wrapping around the back side; use alkali solution to form the second polysilicon layer 8, the etching depth is 60% of the first polysilicon layer 4, the thickness is 20nm, and the area of ​​the second polysilicon layer 8 after alkali washing accounts for 75%; the alkali solution used is NaOH, the concentration of the alkali solution is 3wt%, and the etching time is 100s; after etching, use HF / H2O2 and NH3 / H2O2 cleaning solutions to clean the silicon wafer; and then dry it.

[0143] The remaining steps are the same as those in Example 6.

[0144] Comparative Example 6

[0145] Compared with Example 6, Comparative Example 6 differs in that the second polysilicon layer 8 is not provided in the structure, that is, the second polysilicon layer 8 accounts for 0% of the area.

[0146] In the preparation method of the bottom cell 16, S5 tunneling oxide layer 5 and intrinsic polysilicon layer: using LPCVD technology, a tunneling oxide layer 5 with a thickness of 1.5 nm is deposited on the second surface; and an intrinsic polysilicon film with a thickness of 90 nm is continuously deposited on the tunneling oxide layer 5 to form an intrinsic polysilicon layer.

[0147] S6 Phosphorus Diffusion: Using POCl3 as a diffusion source, phosphorus is diffused in the intrinsic polysilicon layer to form a phosphorus-doped layer and a PSG layer. The thickness of the phosphorus-doped first polysilicon layer 4 is 50 nm, and the thickness of the PSG is 40 nm. The diffusion temperature is 700 ° C, and the doping concentration is 1E20 cm -3 ;

[0148] S7 does not laser treat the PSG layer;

[0149] S8: Remove the first surface wrap-around plating and clean: Use high-concentration HF to remove the back-side wrap-around plating; then use HF / H2O2 and NH3 / H2O2 cleaning solutions to clean the silicon wafer; and then dry it.

[0150] The remaining steps are the same as those in Example 6.

[0151] The electrical performance of the perovskite / TOPCon tandem cells prepared in Example 6 and Comparative Examples 1-6 was tested using a steady-state light source IV sorting test system jointly developed by Shanghai Wilson and Yamashita Denso of Japan. This was achieved by measuring the current-voltage (IV) characteristic curves of the solar cells or modules. This system, based on the photoelectric effect and circuit measurement technology, combines a steady-state light source to simulate standard lighting conditions to rapidly evaluate the device's static electrical performance, including static parameters such as open-circuit voltage (Uoc), short-circuit current (Isc), and conversion efficiency (Eta). Specific standards refer to international photovoltaic module testing specifications such as IEC 61215 and IEC 61730. The results are shown in Table 1.

[0152] Table 1 Test results of battery performance of Example 6 and Comparative Examples 1 to 6

[0153]

[0154] As shown in Table 1, the conversion efficiency of the perovskite / crystalline silicon tandem cells prepared by the preparation method provided in Example 6 is higher than that of Comparative Examples 1 to 6. It can be seen that the method provided in Example 6 of the present invention can produce perovskite / crystalline silicon tandem cells with higher conversion efficiency.

[0155] As shown in Table 1, compared with Example 6, the first polysilicon layer 4 defined in Comparative Example 1 is too thick, and the current and filling parameters of the resulting perovskite / crystalline silicon tandem cell are both lower than those of Example 6. It can be seen that the excessive thickness of the first polysilicon layer 4 has a significant impact on the current, resulting in a decrease in the conversion efficiency of the resulting perovskite / crystalline silicon tandem cell.

[0156] Compared with Example 6, the first polysilicon layer 4 defined in Comparative Example 2 is too thin. It can be seen that an overly thin first polysilicon layer 4 will result in poor passivation of the bottom cell 16, leading to reduced opening voltage, current, and fill of the perovskite tandem cell, with the opening voltage being the main concern, resulting in a lower conversion efficiency of the resulting perovskite / crystalline silicon tandem cell.

[0157] Compared with Example 6, the etching depth of the second polysilicon layer 8 in Comparative Examples 3 and 4 is different. In Comparative Example 3, the etching depth of the second polysilicon layer 8 is too deep, resulting in poor passivation of the bottom cell 16, causing a significant decrease in the voltage of the perovskite tandem cell, resulting in a decrease in the conversion efficiency of the prepared perovskite / crystalline silicon tandem cell; in Comparative Example 4, the etching depth of the second polysilicon layer 8 is too shallow, resulting in a large parasitic absorption of the second polysilicon layer 8, causing a significant decrease in the current of the perovskite tandem, resulting in a decrease in the conversion efficiency of the prepared perovskite / crystalline silicon tandem cell.

[0158] Compared with Example 6, the area occupied by the second polysilicon layer 8 in Comparative Examples 5 and 6 is different. It can be seen that when the area occupied by the second polysilicon layer 8 is too large, it will affect the passivation effect of its bottom cell 16, resulting in reduced opening voltage, current, and fill. When the second polysilicon layer 8 is not provided, the polysilicon layer has strong parasitic absorption of photons, resulting in a significant reduction in its current, resulting in a decrease in the conversion efficiency of the resulting perovskite / crystalline silicon tandem cell.

[0159] The above examples are merely illustrative of the invention and do not constitute a limitation on the scope of protection of the invention. Any design that is identical or similar to the invention falls within the scope of protection of the invention.

Claims

1. A perovskite crystalline silicon stacked bottom cell structure, characterized by: The invention comprises a semiconductor substrate layer, wherein the first surface of the semiconductor substrate layer is provided with a boron-doped layer, a passivation film layer and a first metal electrode with a velvet structure in sequence from the inside to the outside, and the second surface of the semiconductor substrate layer is provided with a small velvet, a tunneling oxide layer and an N-type polysilicon layer in sequence from the inside to the outside, wherein the N-type polysilicon layer comprises at least two polysilicon layers alternately arranged in a horizontal direction and having different thicknesses, and the height of the small velvet is smaller than the height of the velvet structure.

2. The perovskite crystalline silicon stacked bottom cell structure according to claim 1, characterized in that: The N-type polysilicon layer includes a first polysilicon layer and a second polysilicon layer, the thickness of the first polysilicon layer is 10nm-400nm, the thickness of the second polysilicon layer is 20%-90% of the thickness of the first polysilicon layer, and the second polysilicon layer occupies 2%-45% of the area of ​​the N-type polysilicon layer.

3. The perovskite crystalline silicon stacked bottom cell structure according to claim 1, characterized in that: The height of the small suede surface is 0.5 μm-1.2 μm.

4. A method for preparing a perovskite crystalline silicon stacked bottom cell structure according to claim 2, characterized in that: The following steps are involved: Step 1) Texturing: using alkaline solution etching to form a pyramid texture structure of uniform size on both sides of the semiconductor substrate layer; Step 2) Boron diffusion: Using BCl3 as the diffusion source, the diffusion temperature is 500℃-900℃, and the diffusion resistance is controlled at 200-500Ω / Sq; Step 3) removing the second surface of the semiconductor substrate layer from the coating and polishing; Step 4) Secondary texturing to prepare a small textured surface: using an alkaline solution to etch, a small textured surface with a small pyramid structure of uniform size is formed on the second surface of the semiconductor substrate layer; Step 5) depositing a tunnel oxide layer and an intrinsic polysilicon layer; Step 6) Phosphorus diffusion: Using POCl3 as a diffusion source, phosphorus is diffused in the intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer and a PSG layer; Step 7) Forming an alkali-washed second polysilicon layer window: Using laser to process the PSG layer, ablating SiOx to form an alkali-washed second polysilicon layer window, with the ablation area being 1%-40%; Step 8) Plating the first surface; Step 9) forming a second polysilicon layer on the second surface: alkali-washing the windows of the second polysilicon layer and then etching with alkaline solution to form the second polysilicon layer, thereby obtaining an N-type polysilicon layer in which the first polysilicon layer and the second polysilicon layer are alternately arranged in a horizontal direction; After etching, the semiconductor substrate layer is cleaned with a cleaning solution and then dried; Step 10) Deposition of passivation film and H + Passivation: depositing a passivation layer on the first surface of the semiconductor substrate layer; The second surface of the semiconductor substrate layer is hydrogen passivated by using a passivation film layer and H + sedimentation; Step 11) Printing and sintering: Printing AgAl paste on the first surface of the semiconductor substrate layer and sintering to form a front first metal electrode.

5. The method for preparing a perovskite crystalline silicon stacked bottom cell structure according to claim 4, characterized in that: In step 5), the tunnel oxide layer and the intrinsic polysilicon layer are deposited using LPCVD technology. The thickness of the deposited tunnel oxide layer is 1 nm to 5 nm, and the thickness of the deposited intrinsic polysilicon film is 40 nm to 500 nm.

6. The method for preparing a perovskite crystalline silicon stacked bottom cell structure according to claim 4, characterized in that: Step 6) Phosphorus diffusion temperature is 700℃-900℃, doping concentration is 1~5E20cm -3 , wherein the thickness of the PSG layer is 10nm-100nm.

7. The method for preparing a perovskite crystalline silicon stacked bottom cell structure according to claim 4, characterized in that: In step 7), the output power of the laser is 10W~70W, the pulse repetition frequency is 5kHz~20kHz, the diameter of the laser spot is 5Pm~15Pm, and the laser beam speed is 30mm / s~60mm / s.

8. The method for preparing a perovskite crystalline silicon bottom cell structure according to claim 4, characterized in that: In step 9), the alkaline solution is one of NaOH and KOH or a mixture thereof, the concentration of the alkaline solution is 0.5wt%-10wt%, and the etching time is 10s-150s.

9. A perovskite / TOPCon tandem cell, characterized in that: The invention comprises a perovskite cell, a transparent conductive oxide layer, and the perovskite crystalline silicon layer bottom cell structure according to any one of claims 1 to 3, which are arranged in sequence from top to bottom, wherein the transparent conductive oxide layer is in contact with the second surface of the perovskite crystalline silicon layer bottom cell structure; The perovskite battery comprises a hole transport layer, a perovskite thin film layer, an electron transport layer, a carrier recombination layer, an anti-reflection film layer and a second metal electrode, which are arranged in sequence from the inside to the outside.

10. A method for preparing a perovskite / TOPCon tandem cell according to claim 9, characterized in that: The following steps are involved: S1, preparation of the bottom cell structure of the perovskite crystalline silicon layer: the semiconductor substrate layer is sequentially textured and boron diffused, the second surface is polished after de-plating, the second surface is textured again to form a small velvet surface, an oxide tunneling oxide layer and an intrinsic polysilicon layer are deposited, followed by phosphorus diffusion, the second polysilicon layer PSG is laser treated, the positive de-plating is performed and alkaline washing is performed to form the second polysilicon layer, a passivation film layer and H+ passivation are deposited, the first metal electrode is printed and sintered to obtain the bottom cell; S2, preparation of transparent conductive oxide layer: under a pressure of ≤1Pa and an argon-oxygen ratio of 1:0.02-0.1, the power density is 1-3W / cm 2 , preparing a transparent conductive oxide layer on the second surface of the bottom cell by PVD magnetron sputtering; S3, preparation of hole transport layer: preparation of dense TiO2 layer with thickness of 30nm-100nm at high temperature of 400℃-550℃ by spray pyrolysis method; S4, preparing a perovskite thin film layer: the band gap width of the perovskite layer is 1.3eV-1.8eV, the perovskite material structure is ABX3, wherein A is any one of methylamine, formamidine, and Cs or a mixture of several cations, B is Pb or Sn, and X is any one of Cl, Br, and I or a mixture of three anions, and the thickness is 800nm-1200nm; S5, preparing an electron transport layer: preparing an electron transport layer made of SnO2 on the perovskite film layer, with a thickness of 15nm-40nm; S6, preparing a carrier recombination layer: preparing a carrier recombination layer on the electron transport layer, the material of which is ITO with a thickness of 30 nm to 100 nm; S7, depositing an anti-reflection film layer; S8, printing AgAl paste on the front side of the stack, forming the second metal electrode on the front side after sintering to obtain a perovskite crystalline silicon stacked battery.

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