Semiconductor device test program building method and device, storage medium and terminal
By automatically filling in variable parameters and parameter assignment methods, the problem of low efficiency and error-prone construction of semiconductor device test programs in the prior art is solved, efficient and accurate testing program generation is achieved, and labor costs and programming difficulties are reduced.
Patent Information
- Application Number
- CN202410115120.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-26
- Publication Date
- 2025-08-05
AI Technical Summary
The existing semiconductor device testing program construction method requires manual writing of all test-related data into a table, which is extremely inefficient and error-prone, and the code needs to be re-written when the algorithm is updated, which is complicated.
By obtaining the test information file set by the user, using the algorithm library and algorithm classification in the interactive interface or application, automatically fill in variable parameters and default values, and assign parameters based on the test structure and device information files to generate a test program.
It greatly reduces labor costs, improves the accuracy of filling out forms, reduces programming time, and does not require modification of computer programs to update algorithms, simplifying the program construction process.
Smart Images
Figure CN120428066A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor testing technology, and in particular to a method and device for building a semiconductor device test program, a storage medium, and a terminal. Background Art
[0002] WAT (Wafer Acceptance Test) is a wafer acceptance test. Its purpose is to monitor process anomalies by electrically evaluating the test device. To promptly detect anomalies, WAT testing must include parameters such as resistance, capacitance, device threshold voltage, turn-on current, diode conduction and cut-off characteristics, leakage current, and insulation properties for both the front-end and back-end processes. For new products, in particular, it is important to collect as many test structures as possible to comprehensively test all aspects. Consequently, the number of test items can reach thousands. Traditional manual programming methods are time-consuming and labor-intensive, and manual programming carries the risk of errors.
[0003] A WAT test program includes the test structure name, test device name, test algorithm name, test conditions, the terminal pins connected to the test structure, and the output parameter numbers. Writing a test program typically requires manually entering all fields in an Excel document, including the names of each algorithm variable and terminal, and then assigning values to each parameter. All of this requires manual character input. Furthermore, because variable parameter names, terminal names, and output numbers vary across algorithms, Excel's shortcut tools cannot synchronize different algorithms. Using a fixed-code conversion program requires writing algorithm variables in the code. Any algorithm change requires revising the code, making the entire process cumbersome. Furthermore, the file specifying parameter numbers, device names, and parameter control lines (the limit file) is also manually written in Excel. The parameter IDs and names in the limit file must correspond exactly to those in the program, making the workload enormous with thousands of parameters. Summary of the Invention
[0004] The purpose of this application is to provide a method and device for building a semiconductor device test program, a storage medium and a terminal, which are used to solve the problem that the existing method of building a semiconductor device test program requires manual writing of all test-related data into a table, which requires a lot of manpower, is extremely inefficient and prone to errors; and if code conversion is performed through fixed code, if the algorithm is updated, the code needs to be rewritten, and the process is too complicated.
[0005] In a first aspect, the present application provides a method for building a semiconductor device test program, comprising:
[0006] Acquire a test information file set by a user based on a device under test group, wherein the test information file includes at least one piece of test algorithm information, and the test algorithm information includes an algorithm library name, an algorithm name, a test structure name, and a device under test name;
[0007] Based on the algorithm library name of each test algorithm information, link to the corresponding algorithm library, based on the algorithm name of each test algorithm information, obtain the parameter definition file of the corresponding algorithm from the corresponding algorithm library, obtain all variable parameters and the default values corresponding to the variable parameters from the parameter definition file and add them to the corresponding test algorithm information;
[0008] Based on the test structure name, the device under test name, and each variable parameter in the test algorithm information, obtaining parameter assignments of each variable parameter from the device under test information file corresponding to the device under test name, and replacing the default values of the corresponding variable parameters in the test algorithm information with the obtained parameter assignments;
[0009] The test information file with all parameter assignments replaced is input into a test development environment to generate a test program for the device group under test.
[0010] In one embodiment of the present application, the algorithm library name and the algorithm name in the test algorithm information are set by the user based on the DUT information file obtained from the DUT information file library corresponding to the test structure name and the DUT name.
[0011] In one embodiment of the present application, the user sets the test information file based on the device under test group through an interactive interface or an application.
[0012] In one embodiment of the present application, the interactive interface or application includes all algorithm library names, each algorithm library name includes multiple algorithm classification groups, and each algorithm classification group includes multiple algorithm names.
[0013] In one embodiment of the present application, each algorithm library name in the interactive interface or application is linked to the corresponding algorithm library, and each algorithm name is linked to the corresponding parameter definition file and algorithm body.
[0014] In one embodiment of the present application, the steps of inputting the test information file with all parameter assignments replaced into a test development environment to generate a test program for the device under test group include:
[0015] The output parameters of all the test algorithm information in the test information file after all parameter assignments and replacements are sorted, and the sorted test information file is input into a test development environment to generate a test program for the device under test group.
[0016] In one embodiment of the present application, the test development environment is a Test Development Environment.
[0017] In a second aspect, the present application further provides a semiconductor device test program construction device, characterized in that it includes an initial setting module, a parameter acquisition module, a parameter assignment module and a program generation module;
[0018] The initial setting module is used to obtain a test information file set by a user based on a device under test group, wherein the test information file includes at least one test algorithm information, and the test algorithm information includes an algorithm library name, an algorithm name, a test structure name, and a device under test name;
[0019] The parameter acquisition module is used to link to the corresponding algorithm library based on the algorithm library name of each test algorithm information, obtain the parameter definition file of the corresponding algorithm from the corresponding algorithm library based on the algorithm name of each test algorithm information, obtain all variable parameters and the default values corresponding to the variable parameters from the parameter definition file and add them to the corresponding test algorithm information;
[0020] The parameter assignment module is configured to obtain parameter assignments of the variable parameters from the DUT information file corresponding to the DUT name based on the test structure name, the DUT name, and the variable parameters in the test algorithm information, and replace the default values of the corresponding variable parameters in the test algorithm information with the obtained parameter assignments;
[0021] The program generation module is used to input the test information file with all parameter assignments replaced into the test development environment to generate a test program for the device under test group;
[0022] Wherein, the device under test group includes at least one device under test.
[0023] In a third aspect, the present application also provides a storage medium on which a computer program is stored, which implements the semiconductor device test program construction method when executed by a processor.
[0024] In a fourth aspect, the present application further provides a terminal, comprising: a processor and a memory, wherein the memory is communicatively connected to the processor;
[0025] The memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the terminal executes the semiconductor device test program construction method as described above.
[0026] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:
[0027] By applying the semiconductor device test program building method provided by the embodiment of the present invention, the user sets the algorithm of the device to be tested based on the algorithm library stored in the interactive interface or application and the classified algorithms in the algorithm library, which greatly reduces the algorithm input time and reduces the algorithm input difficulty, thereby improving the user experience; further based on the algorithm library name and algorithm name in the test algorithm information, the variable parameters and default values are obtained from the corresponding parameter definition file and added to the corresponding test algorithm information, thereby realizing automatic filling of the algorithm parameters and default values; based on the test structure name, the device to be tested name and each variable parameter in the test algorithm information, the corresponding parameter assignment is obtained from the corresponding device to be tested information file, and the default values of the corresponding variable parameters are replaced, thereby realizing automatic assignment of variable parameters, and the default values of parameters that do not need to be assigned are also retained, without the need for manual filling, which also greatly reduces the data input time. The present invention realizes automatic filling of algorithm variable parameters and variable parameter assignments, greatly reducing labor costs and improving the accuracy of filling in forms; and the method of the present invention only links the algorithm in the program, and does not integrate the algorithm content into the computer program that executes the semiconductor device test program construction method of the present invention. Therefore, even if the algorithm is changed, there is no need to change the computer program that executes the semiconductor device test program construction method of the present invention, thereby reducing the difficulty of using the computer program of the semiconductor device test program construction method. Using the method of the present invention, there is no need to write each test item word by word, especially for testing multiple items of the same device, or a series of devices that only differ in size, which can significantly save programming time.
[0028] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:
[0030] Figure 1 Shown is a flow chart of a method for building a semiconductor device test program according to an embodiment of the present application.
[0031] Figure 2 Shown is a process rendering of the semiconductor device test program construction method described in an embodiment of the present application.
[0032] Figure 3 Shown are examples of test structure names and test devices in the embodiments of the present application.
[0033] Figure 4 Shown are example diagrams of the algorithm default values in the embodiment of this application and a display effect diagram in the test information file.
[0034] Figure 5 Shown is an example diagram of customized algorithm grouping in the interactive interface or application of an embodiment of the present application.
[0035] Figure 6 Shown is a structural schematic diagram of a semiconductor device test program building device according to an embodiment of the present application.
[0036] Figure 7 Shown is a schematic diagram of the structure of the terminal described in an embodiment of the present application. DETAILED DESCRIPTION
[0037] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.
[0038] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. Therefore, the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.
[0039] WAT testing is a means of monitoring the health of chip manufacturing processes. It involves numerous test items and frequent program updates. New products can require thousands of test items to comprehensively cover various categories. Traditionally, this involved manually entering all the characters in Excel documents, then pasting the Excel contents into the machine software to generate a file that met the machine's format requirements. This was a significant workload.
[0040] The following embodiments of the present application provide a method and apparatus for building a semiconductor device test program, a storage medium, and a terminal. The principles and implementation methods of a method and apparatus for building a semiconductor device test program, a storage medium, and a terminal according to the present embodiment will be described in detail below in conjunction with the accompanying drawings, so that those skilled in the art can understand the method and apparatus for building a semiconductor device test program, a storage medium, and a terminal according to the present embodiment without requiring creative effort.
[0041] like Figure 1 As shown, this embodiment provides a method for building a semiconductor device test program, including the following steps.
[0042] Step S101: obtaining a test information file set by a user based on a device under test group.
[0043] Since the method of this embodiment can generate test programs for multiple projects of the same device, and can also generate test programs for a series of devices of different sizes, the device group to be tested in the method of this embodiment can include only one device to be tested, or can include multiple devices to be tested. Each device to be tested has its corresponding device to be tested information file, and the device to be tested information file contains the name of the device to be tested (device name) and the test structure (Testkey) information to which the device to be tested belongs, the device size and other related information names and specific data. The name of the device to be tested (devicename) and the test structure (Testkey) information to which the device to be tested belongs can be used to determine which items need to be tested for the device to be tested and the test algorithm to be adopted. Multiple devices to be tested can be set in the test structure, and the relationship between the test structure and the device to be tested is as follows: Figure 3 As shown, for example Figure 3 There is a device under test between pin 1 (terminal) and pin 2 (terminal), and there is another device under test between pin 4 (terminal) and pin 5 (terminal). In this embodiment, the user mainly uses an interactive interface or application to set the algorithm used for the device under test. In order to facilitate user settings, the interactive interface or application used in this embodiment classifies the existing algorithms. Since the same device under test can test one test item or multiple test items; and each test item can have multiple test methods (for example, a test resistor can apply voltage to measure current, or apply current to measure voltage, and then calculate according to Ohm's law), each test method corresponds to an algorithm. Therefore, based on the measurement purpose, type, etc., the algorithms can be divided into multiple algorithm classification groups. For example, the algorithms for all test resistors (for example, the test item is a test resistor) can be set to one algorithm classification group (such as Figure 5As shown in the figure), multiple algorithms for testing multiple test items of the same device under test (such as a MOS device) can also be set into one algorithm classification group (not shown in the figure). It can be seen that each algorithm classification group includes multiple algorithms. For example, applying voltage to measure current is an algorithm for measuring resistance, and applying current to measure voltage is another algorithm for measuring resistance. Figure 5 As shown in the table, if the test item is resistance, then fill in RS under "Module Selection" (that is, the algorithm classification group of RS is selected), and ForceV under "algo" on the right side of the table represents an algorithm (ForceV is the name of the algorithm), which measures the current by applying voltage and thus obtains the test resistance. Similarly, ForceI represents another algorithm, which measures the voltage by applying current and thus obtains the test resistance. Similarly, fill in MOS under "Module Selection" (that is, the algorithm classification group of MOS is selected), which means that the test item is to test MOS devices. In summary, if Figure 5 As shown, by integrating and classifying the algorithms in this way, after selecting a certain algorithm classification group, the corresponding algorithm will be brought out, making the algorithm selection process simpler, clearer, and less prone to errors.
[0044] The specific process is as follows Figure 2 As shown, first set the algorithm, that is, when the user selects the algorithm for the device under test, the user needs to determine the algorithm library name and algorithm name to be used based on the name of the device under test and the test structure name corresponding to the device under test (a specific device under test corresponds to a specific test structure name), according to the test needs and the relevant information of the device under test in the device under test information file, and then select the algorithm library corresponding to the device under test (e.g., Algo library, etc.) by manually entering the algorithm library name based on the interactive interface or application. Figure 2 Enter the contents of library1 in the Algo library column of a), and then select "Algorithm Classification Group" (that is, Figure 2 b) below the list corresponding to the "Template Selection", such as MOS, etc.) and then display the group (that is, after the content in the table under "Template Selection" is determined, such as Figure 2 After selecting MOS in b), all algorithms are selected, and then the corresponding algorithm name (algo, for example Figure 2 c) under the algo column (e.g., algorithm MOS1, algorithm MOS2), the selected algorithm name will be displayed in Figure 2 In the list under table b "algo", finally fill in the test structure name and the device name of the device under test into the corresponding table, that is, generate the corresponding initial test algorithm information.
[0045] The above user setting process is as follows Figure 2The ac display process is shown in the figure. At this time, the test algorithm information includes the algorithm library name (Algo library, for example Figure 2 a) under Algo library, the algorithm name (algo, for example Figure 2 c), the test structure name, and the device under test name. A user generates multiple pieces of test algorithm information based on the device under test information files for all devices under test in the device under test group to form a corresponding test information file. It should be noted that the test information file can be presented in a tabular format. In some embodiments, for example, each row can represent a piece of test algorithm information for executing that algorithm.
[0046] The above algorithm classification groups (e.g. Figure 2 b) in the MOS) algorithm (e.g. Figure 2 c MOS corresponding to MOS1, MOS2, MOS3, etc.) supports single selection, multiple selection and full selection, which serves as a prompt for writing programs (i.e., improving test algorithm information), and is convenient for directly selecting the corresponding content under the "algo" column as needed. In the case of testing multiple parameters of the device under test, the corresponding algorithm classification group can be selected, which can save a lot of algorithm selection time. The interactive interface or application can include multiple algorithm libraries for different products (i.e., devices under test). The algorithm library is a collection of all the corresponding algorithms. Each algorithm library name in the interactive interface or application is linked to the corresponding algorithm library, that is, based on the corresponding link, the content in the corresponding algorithm library can be obtained from the specified path; each algorithm name in the interactive interface or application is also linked to the corresponding algorithm, that is, based on the corresponding link, the parameter definition file and algorithm body in the corresponding algorithm file can be obtained from the specified path.
[0047] Step S102: link to the corresponding algorithm library based on the algorithm library name of each test algorithm information, obtain the parameter definition file of the corresponding algorithm from the corresponding algorithm library based on the algorithm name of each test algorithm information, obtain all variable parameters and the default values corresponding to the variable parameters from the parameter definition file and add them to the corresponding test algorithm information.
[0048] Specifically, according to each test algorithm information, the parameter definition file of the corresponding algorithm is obtained, and then all the variable parameters and corresponding default values in the parameter definition file are added to the corresponding test algorithm information to realize the variable parameter setting and improvement process in each test algorithm information. The specific process is explained by taking a single test algorithm information as an example. The algorithm library name based on the test algorithm information is linked to the corresponding algorithm library. Based on the algorithm name in the test algorithm information, the algorithm is linked from the linked algorithm library to the parameter definition file in the algorithm file corresponding to the algorithm. The parameter definition file contains the definition of the input variable name and the default value, the definition of the output variable name and the definition of the pin name (i.e., terminal) connected to the device under test. All variable parameters and the corresponding default values of the variable parameters in the parameter definition file are read, wherein the variable parameters include the input variable name, the output variable name and the pin name connected to the device under test. The output variable and the pin name connected to the device under test have no default values and can be omitted. Finally, the read variable parameters and the corresponding default values are stored in the corresponding test algorithm information to realize the setting of the variable parameters in the test algorithm information. After the setting of the variable parameters is completed, the table is as follows Figure 2 d, where the default values of the variable parameters exist but are not displayed (i.e., the input variable names from left to right are Type, W, L, N, Norm to VB, the pin name is Terminal, and the output variable name is output). In other embodiments, they can also be displayed, and the size of the default value can be the industry test standard value.
[0049] Each piece of test algorithm information in the test information file can realize the setting of variable parameters in all test algorithm information through the above process, and at this time the test algorithm information with all variable parameters set can be obtained.
[0050] The input variable names and default values in the parameter definition file are as follows Figure 4 As shown, it should be noted that during the above variable parameter setting process, the default values of the input variables may not be fully displayed, and can also be set to be fully displayed as needed.
[0051] It's important to note that the algorithm file to which the algorithm is linked also includes the algorithm body, which primarily includes the specific algorithm code and instructions, as well as how it connects to the tester board. The algorithm code and instructions enable specific algorithm processes. For example, by executing the instructions, a voltage is applied to the device under test and the current is measured. The algorithm code then calculates the resistance value based on the voltage and current values and outputs it. The algorithm body in the algorithm file is then called within the generated test program. Specifically, within the test program, the algorithm name links to the corresponding algorithm body, enabling the call.
[0052] Step S103, based on the test structure name, the name of the device under test and each variable parameter in the test algorithm information, obtain the parameter assignment of each variable parameter from the device under test information file corresponding to the device under test name, and replace the default value of the corresponding variable parameter in the test algorithm information with the obtained parameter assignment (that is, change the default value of the variable parameter by assignment).
[0053] Specifically, this step is also required for each test algorithm information to realize the re-assignment of some variable parameters of each test algorithm information according to the actual test or device situation. The process of re-assigning variable parameters for a single test algorithm information is as follows: based on the test structure name and the device under test name in the test algorithm information, the corresponding device under test information file is searched from the device under test information file database, and then each variable parameter in the test algorithm information is compared with each parameter in the obtained device under test information file. If a variable parameter matches a parameter in the device under test information file (matching means variable parameters with exactly the same concept), when the variable parameter that successfully matches in the device under test information file has a specific value, the assignment of the parameter is obtained as the parameter assignment of the corresponding variable parameter, and the default value of the corresponding variable parameter in the test algorithm information is replaced with the parameter assignment (for no specific value, the original default value is not changed), thereby realizing the re-assignment of the variable parameter. If the variable parameter does not match all the parameters in the DUT information file, it will not be reassigned. In this case, the default value of the variable parameter in the test algorithm information will be retained unchanged (for example, the default value of the variable parameter in the non-display state will be unchanged, such as Figure 2 (Leave blank under type, N, and Norm in e).
[0054] All the variable parameters that need to be re-assigned in the test algorithm information are re-assigned, that is, the test algorithm information with all parameter assignments replaced is obtained. The test algorithm information with all parameter assignments replaced is as follows: Figure 2 e. The test algorithm information after all parameter assignments are replaced forms a test information file after all parameter assignments are replaced.
[0055] Step S104 : inputting the test information file with all parameter assignments replaced into a test development environment to generate a test program for the device under test group.
[0056] Before completing the test program generation in the test environment, the output parameters of all test algorithm information in the test information file with all parameter assignments replaced are numbered based on the order in the table, and then the test information file with the output parameter numbering completed is input into the TDE (Test Development Environment) to generate the test program for the device group under test (the test program contains all the information that needs to be tested, including the input parameters required during the test process (such as the values under the input "input" and the pin "terminal"). As you can see, Figure 2 Many blank spaces in the table in e are default values. Figure 2 f, have been displayed, for example, Type = 1, W = 10, etc.), as well as the output parameters that are finally obtained (i.e., the parameters under "output"), and the output parameters are numbered. The purpose of numbering the output parameters is to put the output parameters obtained from the test under the corresponding number, such as Figure 2 As shown in Figure 5, TDE stands for test development environment.
[0057] The semiconductor device test program building method provided by the embodiment of the present invention enables the user to set the algorithm of the device to be tested based on the algorithm library stored in the interactive interface or application and the classified algorithms in the algorithm library, which greatly reduces the algorithm input time and reduces the difficulty of algorithm input, thereby improving the user experience; further based on the algorithm library name and algorithm name in the test algorithm information, variable parameters and default values are obtained from the corresponding parameter definition file and added to the corresponding test algorithm information, thereby realizing automatic filling of algorithm parameters and default values; based on the test structure name, device to be tested name and various variable parameters in the test algorithm information, corresponding parameter assignments are obtained from the corresponding device to be tested information file, and the default values of the corresponding variable parameters are replaced, thereby realizing automatic assignment of variable parameters, and retaining the default values for parameters that do not require assignment, without the need for manual filling, thereby greatly reducing data input time. The present invention realizes automatic filling of algorithm variable parameters and variable parameter assignments, greatly reducing labor costs and improving the accuracy of filling in forms; and the method of the present invention only links the algorithm in the program, and does not integrate the algorithm content into the computer program that executes the semiconductor device test program construction method of the present invention. Therefore, even if the algorithm is changed, there is no need to change the computer program that executes the semiconductor device test program construction method of the present invention, reducing the difficulty of using the computer program that executes the semiconductor device test program construction method of the present invention. Using the method of the present invention, there is no need to write each test item word by word, especially for testing multiple items of the same device, or a series of devices that only differ in size, which can significantly save programming time.
[0058] like Figure 6As shown, this embodiment provides a semiconductor device test program construction device, including an initial setting module, a parameter acquisition module, a parameter assignment module and a program generation module.
[0059] The initial setting module is used to obtain a test information file set by the user based on the device under test group. The test information file includes at least one test algorithm information, and the test algorithm information includes the algorithm library name, algorithm name, test structure name and device under test name.
[0060] The parameter acquisition module is used to link to the corresponding algorithm library based on the algorithm library name of each test algorithm information, obtain the parameter definition file of the corresponding algorithm from the corresponding algorithm library based on the algorithm name of each test algorithm information, obtain all variable parameters and the corresponding default values of the variable parameters from the parameter definition file and add them to the corresponding test algorithm information.
[0061] The parameter assignment module is used to obtain the parameter assignment of each variable parameter from the device under test information file corresponding to the device under test name based on the device under test name, test structure name and each variable parameter in the test algorithm information, and replace the default value of the corresponding variable parameter in the test algorithm information with the obtained parameter assignment.
[0062] The program generation module is used to input the test information file with all parameter assignments replaced into the test development environment to generate a test program for the device group under test.
[0063] The device under test group includes at least one device under test.
[0064] The semiconductor device test program building device provided by the embodiment of the present invention enables the user to set the algorithm of the device to be tested based on the algorithm library stored in the interactive interface or application and the classified algorithms in the algorithm library, which greatly reduces the algorithm input time and at the same time reduces the algorithm input difficulty, thereby improving the user experience; further based on the algorithm library name and algorithm name in the test algorithm information, variable parameters and default values are obtained from the corresponding parameter definition file and added to the corresponding test algorithm information, thereby realizing automatic filling of algorithm parameters and default values; based on the test structure name, device to be tested name and various variable parameters in the test algorithm information, corresponding parameter assignments are obtained from the corresponding device to be tested information file, and the default values of the corresponding variable parameters are replaced, thereby realizing re-assignment of variable parameters, and retaining the default values for parameters that do not require assignment, without the need for manual filling, thereby greatly reducing data input time. The present invention realizes automatic filling of algorithm variable parameters and variable parameter assignments, greatly reducing labor costs and improving the accuracy of filling in forms; and the device of the present invention only links the algorithm in the program, and does not integrate the algorithm content into the computer program that executes the semiconductor device test program construction method of the present invention. Therefore, even if the algorithm is changed, there is no need to change the computer program that executes the semiconductor device test program construction method of the present invention, reducing the difficulty of using the computer program that executes the semiconductor device test program construction method of the present invention. Using the device of the present invention, there is no need to write each test item word by word, especially for testing multiple items of the same device, or a series of devices that only differ in size, which can significantly save programming time.
[0065] The embodiment of the present application also provides a computer-readable storage medium. Those skilled in the art will understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the processor through a program, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state drive, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above-mentioned storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid-state drive (SSD)), etc.
[0066] like Figure 7 As shown, an embodiment of the present application provides a terminal.
[0067] The terminal of this embodiment includes a processor and a memory connected to each other; the memory is used to store computer programs, and the processor is used to execute the computer programs stored in the memory, so that all or part of the steps in the above embodiment method can be implemented when the terminal executes them.
[0068] The beneficial effects of all or part of the steps of the method in the above embodiment are the same as the beneficial effects obtained by applying the terminal provided by the embodiment of the present invention, and will not be described in detail here.
[0069] It should be noted that the memory may include random access memory (RAM) and may also include non-volatile memory (non-volatile memory), such as at least one disk storage. Similarly, the processor may also be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0070] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of protection of the present invention shall remain subject to the scope defined by the appended claims.
Claims
1. A method for building a semiconductor device test program, comprising: Acquire a test information file set by a user based on a device under test group, wherein the test information file includes at least one piece of test algorithm information, and the test algorithm information includes an algorithm library name, an algorithm name, a test structure name, and a device under test name; Based on the algorithm library name of each piece of the test algorithm information, link to the corresponding algorithm library; based on the algorithm name of each piece of the test algorithm information, obtain the parameter definition file of the corresponding algorithm from the linked algorithm library; obtain all variable parameters from the parameter definition file and the default values corresponding to the variable parameters and add them to the corresponding test algorithm information; Based on the test structure name, the device under test name, and each variable parameter in the test algorithm information, obtaining parameter assignments of each variable parameter from the device under test information file corresponding to the device under test name, and replacing the default values of the corresponding variable parameters in the test algorithm information with the obtained parameter assignments; The test information file with all parameter assignments replaced is input into a test development environment to generate a test program for the device group under test.
2. The construction method according to claim 1, wherein: The algorithm library name and the algorithm name in the test algorithm information are set by the user based on the DUT information file obtained from the DUT information file library corresponding to the test structure name and the DUT name.
3. The construction method according to claim 1, wherein: The user sets the test information file based on the device under test group through an interactive interface or an application.
4. The construction method according to claim 3, characterized in that: The interactive interface or application includes all algorithm library names, each algorithm library name includes multiple algorithm classification groups, and each algorithm classification group includes multiple algorithm names.
5. The construction method according to claim 4, characterized in that: Each algorithm library name in the interactive interface or application is linked to the corresponding algorithm library, and each algorithm name is linked to the corresponding parameter definition file and algorithm body.
6. The construction method according to claim 1, characterized in that: The steps of inputting the test information file after all parameter assignments are replaced into a test development environment to generate a test program for the device under test group include: The output parameters of all the test algorithm information in the test information file after all parameter assignments and replacements are completed are numbered, and the numbered test information file is input into a test development environment to generate a test program for the device under test group.
7. The construction method according to claim 1 or 6, characterized in that: The test development environment is TestDevelopment Environment.
8. A semiconductor device test program construction device, characterized in that: It includes initial setting module, parameter acquisition module, parameter assignment module and program generation module; The initial setting module is used to obtain a test information file set by a user based on a device under test group, wherein the test information file includes at least one test algorithm information, and the test algorithm information includes an algorithm library name, an algorithm name, a test structure, and a device under test name; The parameter acquisition module is used to link to the corresponding algorithm library based on the algorithm library name of each test algorithm information, obtain the parameter definition file of the corresponding algorithm from the corresponding algorithm library based on the algorithm name of each test algorithm information, obtain all variable parameters and the default values corresponding to the variable parameters from the parameter definition file and add them to the corresponding test algorithm information; The parameter assignment module is configured to obtain parameter assignments of the variable parameters from the DUT information file corresponding to the DUT name based on the test structure name, the DUT name, and the variable parameters in the test algorithm information, and replace the default values of the corresponding variable parameters in the test algorithm information with the obtained parameter assignments; The program generation module is used to input the test information file with all parameter assignments replaced into the test development environment to generate a test program for the device under test group; Wherein, the device under test group includes at least one device under test.
9. A storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the semiconductor device test program building method described in claims 1 to 7 is implemented.
10. A terminal, characterized in that: include: a processor and a memory, wherein the memory is communicatively connected to the processor; The memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the terminal executes the semiconductor device test program construction method as described in claims 1 to 7.