plc instruction system

Abstract

The disclosure provides a PLC instruction system, and relates to the technical field of programmable logic controller, which comprises an instruction executor, a register and a memory mechanism; the instruction executor is used for executing instructions stored in a program block, accessing the register and the memory mechanism according to the instructions, and interacting inside the PLC instruction system through the instructions stored in the program block; the register is used for storing bit logic results of current operation; and the memory mechanism is used for storing data and accessed by a program. The instruction executor in the disclosure accesses the register and the memory mechanism through the instructions stored in the program block, unifies the format inside the PLC instruction system, has the role of unified format, and solves the problem that the PLC instruction system is not unified in the related art.

Description

Technical Field

[0001] This disclosure relates to the field of programmable logic controller (PLC) technology, and more specifically to a PLC instruction system. Background Technology

[0002] Currently, there are many Programmable Logic Controller (PLC) products on the market. Although the programming languages ​​of various PLC products are basically the same, each manufacturer designs its own PLC instruction system, resulting in a lack of uniformity in the internal instruction system.

[0003] There is currently no effective technical solution to the problem of inconsistent PLC instruction systems in related technologies. Summary of the Invention

[0004] The main purpose of this disclosure is to provide a PLC instruction system to solve the problem of inconsistent PLC instruction systems in related technologies.

[0005] To achieve the above objectives, a first aspect of this disclosure provides a PLC instruction system, including an instruction executor, registers, and a memory mechanism;

[0006] The instruction executor is used to execute the instructions stored in the program block, access registers and memory mechanisms according to the instructions, and interact within the PLC instruction system through the instructions stored in the program block.

[0007] The register is used to store the bit logic result of the current operation;

[0008] The memory mechanism is used to store data and is accessed by the program.

[0009] Optionally, the memory structure includes global memory and local memory;

[0010] The global memory operates globally and is accessible to all programs.

[0011] The local memory refers to the memory area used internally by the program, including temporary variable memory, anonymous variable memory, parameter block memory, and pointer memory.

[0012] Optionally, the instruction includes an opcode and multiple operands;

[0013] The opcode is used to represent a function or a class of functions, and the format of the opcode determines the number of operands.

[0014] Furthermore, the operands include multiple prefix modifiers and actual data;

[0015] Each prefix modifier is 8 bits. The high 3 bits of the prefix modifier are used to identify the category of the operand, and the low 5 bits of the prefix modifier are determined by the operand.

[0016] The value and number of bytes of the actual data are determined by the prefix value in the operand.

[0017] Furthermore, the instructions also include operation subcodes and modifiers;

[0018] The opcode is used to represent a specific function within a class of functions represented by the current opcode.

[0019] Optionally, the program block includes a system organization block, system functions, system function blocks, user functions, user function blocks, and user organization blocks;

[0020] The system functions, system function blocks, user functions, and user function blocks are used by users to prepare local block memory for the function through function preparation instructions, pass input parameters, enter the function after preparation is complete and the input parameters have been passed, execute the operation corresponding to the function, obtain output parameters, and release the local block memory prepared for the function.

[0021] Furthermore, the instruction executor includes an instruction set for execution;

[0022] The execution instruction set is used to represent the instructions contained in the instruction executor.

[0023] Furthermore, the execution instruction set includes system instructions, system functions, system function blocks, user functions, and user function blocks;

[0024] The system instructions, system functions, and system function blocks are defined internally by the PLC instruction system, while the user functions and user function blocks are defined by the user.

[0025] Furthermore, the system instructions, system functions, and system function blocks are designed from statements or instructions in the PLC programming language;

[0026] The system function block is used to represent statements in the PLC programming language that require a local block.

[0027] Optionally, the system function is also used to design jump instructions suitable for the ENO mechanism, and to determine whether the current instruction block should be executed based on the value of RLO. If RLO is 0, the jump is made directly to the label and other instructions are executed. If RLO is 1, the jump does not occur and the next instruction is executed directly to perform the program block access operation.

[0028] The PLC instruction system provided in this embodiment includes an instruction executor, registers, and a memory mechanism. The instruction executor executes instructions stored in a program block, accesses registers and the memory mechanism according to the instructions, and interacts within the PLC instruction system through the instructions stored in the program block. The registers store the bit logic results of the current execution; the memory mechanism stores data and is accessed by the program. The instruction executor accesses registers and the memory mechanism through instructions stored in the program block, unifying the internal format of the PLC instruction system and solving the problem of inconsistent PLC instruction systems in related technologies. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is an architecture diagram of the PLC instruction system provided in the embodiments of this disclosure. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0035] Currently, there are many Programmable Logic Controller (PLC) products available on the market. PLC instructions are machine instructions used by PLCs. Although the programming languages ​​of various PLC products are basically the same, each manufacturer designs its own PLC instruction system, resulting in a lack of uniformity in the internal instruction system.

[0036] To address the aforementioned problems, this disclosure provides a PLC instruction system, such as... Figure 1 As shown, the PLC instruction system includes an instruction executor, registers, and memory.

[0037] The instruction executor is used to execute the instructions stored in the program block, access registers and memory mechanisms according to the instructions, and interact within the PLC instruction system through the instructions stored in the program block; the instructions stored in the program block are read and executed by the instruction executor.

[0038] A register is used to store the bit logic result of the current operation. PLC programming languages ​​include ladder diagram language, instruction list language, function block diagram language, structured text language, etc. This disclosure uses ladder diagram language as an example to explain the technical solution. Based on the characteristics of ladder diagram language, a 1-bit Result of Logic Operation (RLO) register is designed to store the bit logic result of the current operation. In addition, additional registers can be added as needed, and corresponding instructions can be added to the program block to access the register.

[0039] Memory is a mechanism used to store data and is accessed by programs.

[0040] In this embodiment of the disclosure, the instruction executor accesses registers and memory mechanisms through instructions stored in the program block, which unifies the internal format of the PLC instruction system and has the function of unifying the format, thus solving the problem of inconsistent PLC instruction systems in related technologies.

[0041] In one optional embodiment of this disclosure, the memory structure includes global memory and local memory;

[0042] Global memory operates globally and is accessible to all programs; all programs can access global memory, such as input I, output Q, bit memory M, data block DB, etc.

[0043] Local memory operates on memory regions used internally by a program, including temporary variable memory, anonymous variable memory, parameter block memory, and pointer memory. Local memory specifically refers to the memory regions used internally by the program itself, namely temporary variable memory (L), anonymous variable memory (A), parameter block memory (ARG), and pointer memory (PTR). Temporary variable memory (L) is a user-defined area for temporary variables, which the user can monitor and enforce. Anonymous variable memory (A) is a variable area generated on demand during compilation, invisible to the user and unmonitorable. Parameter block memory (ARG) is the area for user-defined input and output parameters. Pointer memory (PTR) is the area where non-user-declared pointers are stored. For example, if a large variable is defined as an input parameter, and the compiler interprets it as a pointer pass, then that variable resides in the pointer memory area.

[0044] In one optional embodiment of this disclosure, the instruction includes an opcode and multiple operands; the operands have various categories and can be constants, variables, expressions, or function return values; the opcode is 8 bits, and the operands are 8N bits, where N is a natural number;

[0045] An opcode is used to represent a function or a class of functions, and the format of the opcode determines the number of operands. For example, if the opcode is addition, it requires three operands: addend, sum, and sum.

[0046] In one optional embodiment of this disclosure, the instruction further includes an operation subcode and a modifier; the operation subcode is 8 bits, and the modifier is 8N bits.

[0047] The opcode is used to represent a specific function within a class of functions represented by the current opcode.

[0048] For example, an instruction may include an opcode, an opcode, a modifier, and m operands (m>1), as shown in Table 1 below:

[0049] Table 1

[0050]

[0051] This disclosure provides specific instruction formats, which can standardize instruction formats.

[0052] In one optional embodiment of this disclosure, the operands include multiple prefix modifiers and actual data;

[0053] Each prefix modifier is 8 bits long. The high 3 bits of the prefix modifier are used to identify the type of operand, and the low 5 bits of the prefix modifier are determined by the operand. A total of 8 types of operands can be defined by the prefix modifier.

[0054] The actual data value and number of bytes are determined by the prefix value in the operand. The actual data is 8N bits.

[0055] For example, operands can include n prefix modifiers (n>1) and actual data, as shown in Table 2 below:

[0056] Table 2

[0057]

[0058] Taking constant operands as an example, assuming the category code of constant operands is 0x0, the format definition of the lower 5 bits of the prefix modification is shown in Table 3 below:

[0059] Table 3

[0060]

[0061] Among them, values ​​starting with 0x are hexadecimal integer constants; the above constant operands are flexible and variable, which can reduce the number of bytes of generated bytecode. Furthermore, the embodiments of this disclosure provide specific formats for operands and prefix modifiers, which can unify the operand format and prefix modifier format.

[0062] In one optional embodiment of this disclosure, the program block includes a system organization block, system functions, system function blocks, user functions, user function blocks, and user organization blocks; the program block (POU) of the PLC instruction system can be divided into system organization blocks (SOB), system functions (SFC), system function blocks (SFB), user functions (UFC), user function blocks (UFB), and user organization blocks (UOB).

[0063] System functions, system function blocks, user functions, and user function blocks are used by users to prepare local memory blocks for the function through function preparation instructions, pass input parameters, enter the function after preparation is complete and the input parameters have been passed, execute the corresponding operation of the function, obtain output parameters, and release the local memory blocks prepared for the function.

[0064] Except for System Organization Blocks (SOBs) and User Organization Blocks (UOBs), all other blocks can be invoked by users, and the invocation process is as follows:

[0065] Function preparation instructions, such as sfc, sfb, ufc, ufb, etc., create block frames to prepare for passing parameters;

[0066] Parameter passing commands: such as push, pushb, pushw, pushd, pushq, etc.;

[0067] Execution instructions: Once ready and parameters have been passed, execute the program block, call, etc.

[0068] Obtain output parameters such as pop, popb, popw, popd, popq, etc.

[0069] Release the local block of memory prepared for the program: end.

[0070] When called, the local block memory is first prepared for the program to be called by function preparation instructions such as sfc, sfb, ufc, and ufb. Then, the parameters are passed, the called program is executed, the parameters that need to be output are obtained, and finally the local block memory prepared for the program is released. For the calling process of different blocks in the program block, the operations performed are the same, but the input parameters, output parameters or offsets are different, and the calling method has high scalability.

[0071] For example, suppose a system function (SFC) declared as (Input bool in, Inout bool inout, Output int out) is called, with the number 0. The pseudocode description of the call is as follows:

[0072] sfc 0 / / Prepare local block memory such as parameter block for function number 0

[0073] push true, 0 / / Push true to the input parameter in, 0 represents the offset of parameter in.

[0074] push bvar,1 / / Push bvar to the input parameter inout, where 1 represents the offset of inout.

[0075] enter / / Enter the function and perform the corresponding operation.

[0076] pop 1, bvar / / Retrieves the parameter value and stores it in parameter bvar, where 1 represents the offset of inout.

[0077] pop 2,tvar / / Get the parameter value and store it in the variable tvar, where 2 represents the offset of out.

[0078] end / / Release the local block of memory prepared for the function

[0079] In one optional embodiment of this disclosure, the instruction executor includes an instruction set for execution;

[0080] The instruction set is used to represent the instructions contained in the instruction executor.

[0081] In one optional embodiment of this disclosure, the execution instruction set includes system instructions, system functions, system function blocks, user functions, and user function blocks; the execution instruction set can be divided into system instructions (INS), system functions (SFC), system function blocks (SFB), user functions (UFC), and user function blocks (UFB).

[0082] System instructions, system functions, and system function blocks are defined internally by the PLC instruction set, while user functions and user function blocks are defined by the user. The data types supported by the PLC instruction set include basic types, arrays, pointers, System Types (SDTs), and User Types (UDTs). The execution instruction set provided in this disclosure can provide a reliable reference for designing specific instruction sets and has high scalability.

[0083] In one optional embodiment of this disclosure, system instructions, system functions, and system function blocks are designed from statements or instructions in a PLC programming language;

[0084] System function blocks are used to represent statements in PLC programming languages ​​that require local blocks.

[0085] In PLC programming languages, statements or instructions can be designed into different data types depending on the operation. If an operation requires a local block to store information for user access, it can be designed as a system function block; if the operation requires many parameters, it can be designed as a system function; if the operation requires few parameters, it can be designed as a system instruction. Taking ladder diagram language as an example, normally open contacts can be designed as system instructions, counters can be designed as system function blocks, and timers can be designed as corresponding instructions to operate the DB instance defined by the timer.

[0086] In one optional implementation of this disclosure, the system function is also used to design jump instructions suitable for the ENO mechanism. It determines whether the current instruction block should perform a jump based on the value of RLO. If RLO is 0, it jumps directly to the label and runs other instructions. If RLO is 1, no jump occurs and the next instruction is executed directly to perform the program block access operation.

[0087] The ENO (Enable Output) mechanism in Siemens PLCs determines whether the current instruction block should be executed based on the RLO value. Therefore, a jump instruction specifically for ENO mechanism jumps is designed, such as the instruction `jen offset`, with the pseudocode shown below:

[0088] jen L100 / / Performs an EN condition check to determine whether to jump to the last line of tags.

[0089] sfc 1, / / Prepare local block memory such as parameter block for function number 1

[0090] push true,0 / / Push true to in, 0 represents the offset of in.

[0091] push bvar,1 / / Push bvar to inout, 1 represents the offset of inout.

[0092] enter / / Enter the function and perform the corresponding operation.

[0093] pop 1, bvar / / Get the inout value into bvar, where 1 represents the offset of inout.

[0094] pop 2,tvar / / Get the value of out and store it in tvar, where 2 represents the offset of out.

[0095] end / / Release the local block of memory prepared for the function

[0096] L100: / / tag

[0097] When the instruction executor reaches jen, if RLO is 0, it jumps directly to label L100 to execute other instructions; if RLO is 1, no jump occurs, and the next instruction is executed directly to perform program block access operations.

[0098] For some instructions, there are versions that support and versions that do not support the EN / ENO (enable input / enable output) mechanism.

[0099] By combining the functions of the PLC programming language, specific instructions can be designed. For example, for normally open contacts, there are three corresponding instructions, namely the three instructions LD, A, and O in the STL language. Among them, LD is Load, used for normally open contacts; A is And and normally open, used for normally open contacts in series; and O is Or or normally open, used for normally open contacts in parallel.

[0100] The embodiments disclosed herein can provide a reliable reference for designing specific instruction sets, and can be combined with the functions of PLC programming languages ​​to design specific instructions, thus exhibiting high scalability.

[0101] As can be seen from the above description, this disclosure achieves the following technical effects:

[0102] In this disclosure, the instruction executor accesses registers and memory mechanisms through instructions stored in program blocks, unifying the internal format of the PLC instruction system and solving the problem of inconsistent PLC instruction systems in related technologies.

[0103] Compared with related technologies, this disclosure can unify the instruction format, operand format, and prefix modification format;

[0104] This disclosure provides a reliable reference for designing specific instruction sets and is highly scalable.

[0105] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0106] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A PLC instruction system, characterized in that, This includes the instruction executor, registers, and memory mechanisms; The instruction executor is used to execute the instructions stored in the program block, access registers and memory mechanisms according to the instructions, and interact within the PLC instruction system through the instructions stored in the program block; the instructions stored in the program block are read and executed by the instruction executor. The register is used to store the bit logic result of the current operation; The memory mechanism is used to store data and is accessed by the program; The instruction includes an opcode and multiple operands, wherein the opcode is 8 bits. The opcode is used to represent a function or a class of functions, and the format of the opcode determines the number of operands; The operands include multiple prefix modifiers and actual data; Each prefix modifier is 8 bits. The high 3 bits of the prefix modifier are used to identify the category of the operand, and the low 5 bits of the prefix modifier are determined by the operand. The value and number of bytes of the actual data are determined by the value of the prefix modifier in the operand; The instruction also includes an operation subcode and a modifier, wherein the operation subcode is 8 bits; The operation subcode is used to represent a specific function within a class of functions represented by the current operation code; The memory structure includes global memory and local memory; The global memory operates globally and is accessible to all programs. The local memory refers to the memory area used inside the program, including temporary variable memory, anonymous variable memory, parameter block memory, and pointer memory; among them, temporary variable memory is a user-defined temporary variable area, anonymous variable memory is a variable area generated on demand at compile time, parameter block memory is an area for user-defined input and output parameters, and pointer memory is an area for storing pointers not declared by the user. The program block includes a system organization block, a system function, a system function block, a user function, a user function block, and a user organization block; The system functions, system function blocks, user functions, and user function blocks are used by users to prepare local block memory for the function through function preparation instructions, pass input parameters, enter the function after preparation is complete and the input parameters have been passed, execute the operation corresponding to the function, obtain output parameters, and release the local block memory prepared for the function; wherein, for the calling process of different blocks in the program block, the operation performed is the same, but the input parameters or output parameters are different.

2. The PLC instruction system according to claim 1, characterized in that, The instruction executor includes an instruction set to be executed; The execution instruction set is used to represent the instructions contained in the instruction executor.

3. The PLC instruction system according to claim 2, characterized in that, The execution instruction set includes system instructions, system functions, system function blocks, user functions, and user function blocks; The system instructions, system functions, and system function blocks are defined internally by the PLC instruction system, while the user functions and user function blocks are defined by the user.

4. The PLC instruction system according to claim 3, characterized in that, The system instructions, system functions, and system function blocks are designed using statements or instructions in the PLC programming language; The system function block is used to represent statements in the PLC programming language that require a local block.

5. The PLC instruction system according to claim 1, characterized in that, The system function is also used to design jump instructions suitable for the ENO mechanism. It determines whether to execute a jump based on the value of RLO. If RLO is 0, it jumps directly to the label and runs other instructions. If RLO is 1, no jump occurs and the next instruction is executed directly to perform the program block access operation.

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