Chip testing method, device, system, readable storage medium and program product

Abstract

The present application relates to the field of semiconductor testing, and provides a chip testing method, device, system, readable storage medium, and program product. The method comprises: obtaining a digital signal to be tested, wherein the digital signal to be tested is obtained by processing a preset analog signal by the chip to be tested; when the digital signal to be tested is a non-integer period sampling signal, calling a target window function to smooth the digital signal to be tested, and obtaining spectrum data to be tested; based on the spectrum data to be tested and a preset chip performance qualification index, determining the performance test result of the chip to be tested, wherein the preset chip performance qualification index is determined based on the performance parameters of the chip to be tested. The present application can process discrete digital signals even when the clock signal synchronization is not performed on various parts of the chip testing system, and can effectively smooth the digital signal to be tested, thereby minimizing the occurrence of problems such as spectrum leakage and error accumulation, and thereby improving the accuracy of the chip test results.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing, and in particular to a chip testing method, device, system, readable storage medium, and program product. Background Art

[0002] The chip production process (such as semiconductor chips) typically includes chip design, chip production, chip packaging, and chip testing. During the chip testing phase, the chip under test needs to be tested to ensure that its performance meets the relevant specifications.

[0003] Traditional chip testing methods typically require strict clock synchronization across all components of the chip test system to ensure full-cycle sampling and avoid issues like spectral leakage after Fourier transforms. However, in practice, strict clock synchronization across all components of the chip test system is often difficult to achieve, making full-cycle sampling difficult. This can lead to spectral leakage and error accumulation after Fourier transforms, ultimately resulting in inaccurate chip test results. Summary of the Invention

[0004] In view of this, the embodiments of the present application provide a chip testing method, device, system, readable storage medium and program product to solve the problems in the prior art that it is difficult to achieve strict clock synchronization of various parts of the chip testing system, and that spectrum leakage and error accumulation are prone to occur after Fourier transform, which ultimately leads to inaccurate chip test results.

[0005] According to a first aspect of an embodiment of the present application, a chip testing method is provided, which is used in a chip testing device, including:

[0006] Acquire a digital signal to be tested, wherein the digital signal to be tested is obtained by processing a preset analog signal by the chip to be tested;

[0007] When the digital signal to be measured is a non-integer period sampling signal, the target window function is called to smooth the digital signal to be measured to obtain the spectrum data to be measured; wherein, the expression of the target window function is as follows:

[0008] ;

[0009] in, represents the target window function, 、 、 、 are the first coefficient, second coefficient, third coefficient and fourth coefficient of the target window function respectively, Indicates the sampling value corresponding to the current sampling point, Indicates the total number of sampling points of the sampled time domain signal;

[0010] Based on the spectrum data to be tested and the preset chip performance qualification index, a performance test result of the chip to be tested is determined, wherein the preset chip performance qualification index is determined based on the performance parameters of the chip to be tested.

[0011] A second aspect of an embodiment of the present application provides a chip testing system, comprising: a signal source transmitting device, a digital-to-analog conversion device, a chip to be tested, and a chip testing device;

[0012] The signal source transmitting device is connected to the digital-to-analog conversion device, the digital-to-analog conversion device is connected to the chip to be tested, and the chip to be tested is connected to the chip testing device;

[0013] The chip testing device is used to perform the method of the first aspect.

[0014] According to a third aspect of an embodiment of the present application, a chip testing device is provided, comprising: a memory and a processor, wherein the memory is used to store a computer program; and the processor is used to execute the method of the first aspect when calling the computer program.

[0015] According to a fourth aspect of an embodiment of the present application, a readable storage medium is provided, on which a program is stored, and when the program is executed by a processor, the method of the first aspect is implemented.

[0016] According to a fifth aspect of the embodiments of the present application, a program product is provided. When the program product is run on a chip testing device, the chip testing device executes the method of the first aspect.

[0017] Compared with the prior art, the embodiments of the present application have at least the following beneficial effects: even when the various parts of the chip test system are not synchronized with the clock signal, discrete digital signals can still be processed and correct signal parameter calculation results can be obtained, thereby reducing the requirements for the synchronization of the chip test system and reducing the difficulty and cost of designing and implementing the chip test system. Secondly, the embodiments of the present application design a new window function (i.e., a target window function). When the digital signal to be tested is a non-integer period sampling signal, the target window function can be used to effectively smooth the digital signal to be tested, thereby minimizing the occurrence of problems such as spectrum leakage and error accumulation, thereby improving the accuracy of the chip test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1This is a schematic diagram of the chip test system structure according to an embodiment of the present application;

[0020] Figure 2 This is a flow chart of a chip testing method provided in an embodiment of the present application;

[0021] Figure 3 It is a structural schematic diagram of a chip testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0023] A chip testing method, device, and system according to an embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0024] In the field of semiconductor testing, chips are typically tested before they ship to ensure their performance meets specifications. Traditional chip testing methods require strict clock synchronization across all test components, which poses significant difficulties and limitations to the design and implementation of chip test systems. Furthermore, traditional chip testing methods are unable to effectively smooth sampled data, which can easily lead to problems such as spectrum leakage and error accumulation, ultimately resulting in inaccurate chip test results.

[0025] In view of this, an embodiment of the present application provides a chip testing method that can process discrete digital signals and obtain correct signal parameter calculation results even when the various parts of the chip testing system are not synchronized with the clock signal, thereby reducing the requirements for the synchronization of the chip testing system and reducing the difficulty and cost of designing and implementing the chip testing system. Secondly, an embodiment of the present application designs a new window function (i.e., a target window function). When the digital signal to be tested is a non-integer period sampling signal, the target window function can be used to effectively smooth the digital signal to be tested, thereby minimizing the occurrence of problems such as spectrum leakage and error accumulation, thereby improving the accuracy of the chip test results.

[0026] The chip testing method, device, and system provided in the embodiments of the present application are applicable to the fields of semiconductor testing, digital signal processing, and embedded systems.

[0027] Figure 1 1 is a schematic diagram of the system structure of a chip testing system provided in one embodiment of the present application.

[0028] See also Figure 1 The chip testing system of the embodiment of the present application includes: a signal source transmitting device 101, a digital-to-analog converter 102, a chip under test 103, and a chip testing device 104. The signal source transmitting device 101 is connected to the digital-to-analog converter 102, the digital-to-analog converter 102 is connected to the chip under test 103, and the chip under test 103 is connected to the chip testing device 104.

[0029] The signal source transmitting device 101 may be an excitation signal source transmitting device, which is used to generate and transmit a specific signal (such as an excitation signal with a specific frequency, amplitude, and waveform (such as a sine wave, square wave, pulse wave, etc.)) and output it to the digital-to-analog conversion device 102.

[0030] The digital-to-analog conversion device 102 is used to convert the excitation signal (which is a digital signal) output by the signal source transmitting device 101 into an analog signal, and output it to the chip under test 103 .

[0031] The chip under test 103 is used to convert the analog signal output by the digital-to-analog conversion device 102 into a digital signal under test, and output the digital signal to the chip testing device 104 .

[0032] The chip testing device 104 is used to detect the digital signal to be tested output by the chip to be tested 103 to determine the performance test result of the chip to be tested 103 .

[0033] As an example, the signal source transmitting device 101 generates a preset excitation signal and sends the preset excitation signal to the digital-to-analog conversion device 102. The digital-to-analog conversion device 102 performs digital-to-analog conversion on the received preset excitation signal to obtain a preset analog signal, and sends the preset analog signal to the chip under test 103. The chip under test 103 performs signal processing on the received preset analog signal to obtain a digital signal under test, and sends the digital signal under test to the chip testing device 104. If the digital signal under test is a non-integer period sampling signal, the chip testing device 104 calls a target window function to smooth the digital signal under test to obtain spectrum data under test; and determines the performance test result of the chip under test based on the spectrum data under test and the preset chip performance qualification index.

[0034] Figure 2 It is a flowchart of a chip testing method provided in one embodiment of the present application. Figure 2 The chip testing method can be Figure 1 The chip testing device 104 in the chip testing system is executed.

[0035] See also Figure 2 The chip testing method of the embodiment of the present application may include the following steps:

[0036] Step S201 : obtaining a digital signal to be tested, wherein the digital signal to be tested is obtained by processing a preset analog signal by the chip to be tested.

[0037] The chip under test is a chip that collects analog signals, for example, it can be a power management chip (PMIC), a data conversion chip (ADC / DAC), etc.

[0038] Step S202 : When the digital signal to be measured is a non-integer period sampling signal, a target window function is called to perform smoothing processing on the digital signal to be measured to obtain spectrum data to be measured.

[0039] Non-integer-cycle sampling refers to the situation where, when sampling a periodic signal (such as a digital signal output by a chip under test), the sampling duration (or number of sampling points) fails to include an integer number of complete cycles of the signal, resulting in the signal being truncated in the time domain at a point that is not an integer multiple of the signal period.

[0040] The non-integer period sampling signal refers to the signal collected by the above-mentioned non-integer period sampling.

[0041] When a periodic signal is truncated by a non-integer period, the periodicity of the signal will be destroyed, which will lead to problems such as spectrum leakage.

[0042] In order to solve the problem of spectrum leakage caused by the truncation of periodic signals by non-integer periods, the embodiment of the present application designs a new window function (i.e., a target window function), and uses the target window function to smooth the non-integer period sampling signal. It can effectively balance and adjust the sidelobe amplitude and mainlobe width (resolution) of the sampled time domain signal so that the signal energy is concentrated on the mainlobe as much as possible and the signal energy appearing on the sidelobe is minimized, thereby minimizing the problems of spectrum leakage and error accumulation, thereby improving the accuracy of the chip test results.

[0043] The target window function in this embodiment is derived using cosine polynomial fitting. Using this target window function to smooth the sampled time-domain signal enables a flexible trade-off between the signal's mainlobe width (resolution) and sidelobe suppression to suit different application requirements. It also minimizes spectral leakage and error accumulation, thereby improving the accuracy of chip test results.

[0044] Step S203 : determining a performance test result of the chip to be tested based on the spectrum data to be tested and a preset chip performance qualification index, wherein the preset chip performance qualification index is determined based on performance parameters of the chip to be tested.

[0045] The preset chip performance qualification index is determined based on at least one of the following performance parameters: a performance parameter of a preset excitation signal, a performance parameter of a digital-to-analog conversion, and a performance parameter of the chip to be tested.

[0046] The performance parameters of the preset excitation signal can be determined based on the system characteristic analysis objective. For example, if the analysis objective is system transient response, the performance parameters of the preset excitation signal can be selected from amplitude, rise time, pulse width, etc. For another example, if the analysis objective is multi-system coordinated control, the performance parameters of the preset excitation signal can be selected from synchronization parameters such as phase difference and timing delay.

[0047] The performance parameters of digital-to-analog conversion include but are not limited to: signal-to-noise ratio (SNR), total harmonic distortion (THD), etc.

[0048] The performance parameters of the chip under test can be determined based on the type of chip under test. For example, if the chip under test is an analog-to-digital converter (ADC), its performance parameters include signal-to-noise ratio (SNR), sampling rate, resolution, and spurious-free dynamic range (SFDR).

[0049] The technical solutions provided by the embodiments of the present application do not require strict clock synchronization across all components of the chip test system, significantly reducing the design and implementation difficulty and cost of the chip test system (no additional circuit design is required). The embodiments of the present application utilize a specific target window function to effectively smooth sampled data over a limited time period, minimizing the risk of spectral leakage caused by data abrupt changes during infinite Fourier transform expansion. This reduces the risk of spectral leakage and error accumulation after the Fourier transform, thereby improving the accuracy of chip test results.

[0050] In some embodiments, when the digital signal to be measured is a non-integer period sampling signal, calling the target window function to smooth the digital signal to be measured to obtain the spectrum data to be measured includes:

[0051] Sampling the digital signal to be measured to obtain a sampling time domain signal of finite length;

[0052] If the sampling time domain signal is a non-integer period sampling signal, the target window function is called to smooth the sampling time domain signal to obtain the time domain signal to be measured;

[0053] The time domain signal to be measured is converted into the frequency domain signal to be measured, and the frequency domain signal to be measured is logarithmized and normalized to obtain the spectrum data to be measured.

[0054] Finite length refers to a finite sampling length. In practical applications, the sampling length can be determined based on the characteristics of the digital signal output by the chip under test. For example, the sampling length can be 1 second, 2 seconds, etc.

[0055] As an example, see Figure 1In the chip testing scenario, first, a specific excitation signal (digital signal) is generated and transmitted by the signal source transmitting device 101, and output to the digital-to-analog conversion device 102. The digital-to-analog conversion device 102 converts the specific excitation signal (digital signal) into an analog signal and outputs it to the chip under test 103. The chip under test 103 processes the analog signal and outputs the digital signal under test to the chip testing device 104. The chip testing device 104 intercepts and samples the digital signal under test to obtain a sampling time domain signal of a finite length.

[0056] Normally, the digital signal to be tested output by the chip to be tested 103 is a periodic signal of infinite length. In order to facilitate signal analysis, reduce the amount of calculation and improve the efficiency of signal analysis, the digital signal to be tested is generally intercepted and sampled to obtain a sampling time domain signal of finite length, and then the sampling time domain signal is subsequently analyzed.

[0057] In the process of signal transmission and processing, there will inevitably be certain errors and noise. The embodiment of the present application can effectively reduce the errors and noise generated in the process of signal transmission and processing by logarithmizing and normalizing the frequency domain signal to be measured, thereby further improving the accuracy of the chip test results.

[0058] The technical solution of the embodiment of the present application can effectively reduce the errors and noise generated during signal transmission and processing by performing logarithmic and normalized processing on the frequency domain signal to be measured, thereby further improving the accuracy of the chip test results.

[0059] In some embodiments, calling a target window function to smooth the sampled time domain signal to obtain a time domain signal to be measured includes:

[0060] Based on the target window function, determining the sampling weight coefficient corresponding to each sampling point of the sampled time domain signal;

[0061] The sampling weight coefficient corresponding to each sampling point is used to smooth the sampled time domain signal to obtain the time domain signal to be measured.

[0062] In some embodiments, determining a sampling weighting coefficient corresponding to each sampling point of the sampled time domain signal based on the target window function includes:

[0063] Determine the sampling value corresponding to each sampling point of the sampled time domain signal and the total number of sampling points;

[0064] Determine a sampling weighting coefficient corresponding to each sampling point of the sampled time domain signal based on a target window function, a sampling value corresponding to each sampling point, and a total number of sampling points;

[0065] The expression of the target window function is shown in the following formula (1):

[0066] (1);

[0067] In formula (1), represents the target window function (sampling weight coefficient), 、 、 、 are the first coefficient, second coefficient, third coefficient and fourth coefficient of the target window function respectively, Indicates the sampling value (i.e. signal value) corresponding to the current sampling point, Indicates the total number of sampling points of the sampled time domain signal.

[0068] The signal value of a digital signal is a discrete, quantized value, typically represented by a binary number (0 / 1) or a multi-base number. For example, after an ADC (analog-to-digital converter) converts an analog signal into a digital signal, the signal value is a binary-coded value (e.g., a 12-bit ADC outputs an integer from 0 to 4095).

[0069] First coefficient , the second coefficient , the third coefficient and the fourth coefficient They are determined based on fitting of a large amount of data, and their values ​​are 0.338951, 0.481982, 0.161061, and 0.018032 respectively.

[0070] As an example, the total number of sampling points can be calculated according to formula (2): :

[0071] (2);

[0072] In formula (2), Indicates the sampling duration, Indicates the sampling frequency.

[0073] As an example, a continuous digital signal The sampled time domain signal in a finite time [0,T] It can be expressed as formula (3):

[0074] (3);

[0075] In formula (3), n Indicates the sampling point index value, which ranges from 1 to (maximum sampling point index value), Indicates the sampling period.

[0076] By substituting the sampling value corresponding to each sampling point of the sampled time domain signal and the total number of sampling points into the above formula (1), the sampling weight coefficient corresponding to each sampling point can be calculated.

[0077] As an example, the sampled time domain signal can be smoothed according to the following formula (4) to obtain the time domain signal to be measured.

[0078] (4);

[0079] In formula (4), represents the time domain signal to be measured, represents the sampled time domain signal; Represents the sampling weight coefficient of each sampling point of the sampled time domain signal.

[0080] As an example, the time domain signal to be measured may be converted into a frequency domain signal to be measured by fast Fourier transform (FFT) or discrete Fourier transform (DFT).

[0081] In some embodiments, performing logarithmic and normalized processing on the frequency domain signal to be measured to obtain the spectrum data to be measured includes:

[0082] Extract the amplitude spectrum and phase spectrum of the frequency domain signal to be measured;

[0083] If the amplitude spectrum contains a zero value, performing zero-value smoothing processing on the amplitude spectrum to obtain first processed data;

[0084] performing logarithmic processing on the first processed data to obtain second processed data;

[0085] performing normalization processing on the second processed data to obtain third processed data;

[0086] The third processed data and the phase spectrum are combined to obtain the spectrum data to be measured.

[0087] Frequency domain signals usually contain amplitude spectrum and phase spectrum. Logarithmic transformation is only applicable to amplitude spectrum or power spectrum, and phase spectrum cannot be logarithmized (phase is an angle and has no logarithmic meaning).

[0088] As an example, the amplitude spectrum and phase spectrum of the frequency domain signal to be measured are extracted. Specifically, the frequency domain signal to be measured can be modulo calculated to obtain the amplitude corresponding to each frequency point, thereby obtaining the amplitude spectrum; the phase angle of the frequency domain signal to be measured can be taken to obtain the phase angle corresponding to each frequency point in the frequency domain signal to be measured, thereby obtaining the phase spectrum.

[0089] As an example, if the amplitude spectrum of the frequency domain signal to be measured contains zero values ​​(for example, the amplitude of some frequency components is 0), then it can be measured by adding a very small positive number , to avoid the situation where infinity (such as ln(0)=-∞) occurs when calculating logarithms.

[0090] The amplitude spectrum can be subjected to zero-value smoothing processing according to formula (5) to obtain the first processed data.

[0091] (5);

[0092] In formula (5), represents the first processed data, represents the amplitude spectrum of the frequency domain signal to be measured, Represents a very small positive number.

[0093] Next, the first processing data Perform logarithmic transformation processing (i.e., logarithmic processing) to obtain second processed data. Exemplarily, the first processed data can be logarithmically processed according to formula (6).

[0094] (6);

[0095] In formula (6), represents the second processed data, Indicates the first processed data.

[0096] Next, the second processed data is normalized to obtain third processed data, and then the third processed data is combined with the phase spectrum to obtain the spectrum data to be measured.

[0097] The technical solution of the embodiment of the present application can effectively reduce the errors and noise generated during signal transmission and processing by performing logarithmic and normalized processing on the frequency domain signal to be measured, thereby further improving the accuracy of the chip test results.

[0098] In some embodiments, determining a performance test result of the chip under test based on the spectrum data under test and a preset chip performance qualification index includes:

[0099] Find the highest signal frequency point in the spectrum data to be measured;

[0100] Determine the total harmonic power based on the maximum signal frequency corresponding to the highest signal frequency point;

[0101] Determine the total power of the noise signal of the spectrum data to be measured;

[0102] The performance test result of the chip to be tested is determined based on the total harmonic power, the total noise signal power and the preset chip performance qualification index.

[0103] As an example, the built-in function of a programming language or tool can be used to traverse the spectrum data to be measured and locate the frequency point corresponding to the maximum amplitude, which is the highest signal frequency point (also called the fundamental frequency).

[0104] In order to eliminate sidelobe interference and ensure that the highest signal frequency currently found is not a sidelobe caused by noise or frequency leakage, you can check whether the highest signal frequency is greater than the adjacent points (such as the left frequency point to the left of the highest signal frequency point and the right frequency point to the right of the highest signal frequency point).

[0105] In some embodiments, determining the total harmonic power based on the maximum signal frequency corresponding to the highest signal frequency point includes:

[0106] Generate a harmonic frequency list based on the maximum signal frequency corresponding to the highest signal frequency point, and determine all harmonic signal frequency points in the spectrum data to be measured according to the harmonic frequency list;

[0107] Determine the harmonic signal frequency power corresponding to each harmonic signal frequency point;

[0108] Determine the total harmonic power based on the power of the harmonic signal frequency points.

[0109] As an example, first, the harmonic signal frequency can be determined based on the maximum signal frequency corresponding to the highest signal frequency, where the harmonic signal frequency refers to the frequency that is an integer multiple of the fundamental signal frequency (i.e., the maximum signal frequency); then, the maximum harmonic order of the spectrum data to be measured is determined. N max ; Then, generate a harmonic frequency list based on the fundamental signal frequency and the maximum harmonic order.

[0110] For example, assuming that the spectrum data to be measured is integer harmonic spectrum data, the generated harmonic frequency list is shown in Table 1:

[0111] Table 1 Harmonic frequency list

[0112]

[0113] In Table 1 above f 0 represents the fundamental signal frequency (the maximum signal frequency corresponding to the highest signal frequency point).

[0114] According to Table 1 above, the harmonic signal frequency points corresponding to the respective harmonic frequencies in the spectrum data to be measured can be determined.

[0115] Next, the harmonic signal frequency power corresponding to each harmonic signal frequency point is extracted from the spectrum data to be measured, and then the total harmonic power is calculated according to formula (7).

[0116] (7);

[0117] In formula (7), Indicates the total harmonic power; Indicates the maximum harmonic order; Indicates the index of summation, its value is 2,3,..., ; Indicates the i The harmonic signal frequency power corresponding to each harmonic signal frequency point.

[0118] In some embodiments, determining the total power of the noise signal of the spectrum data to be measured includes:

[0119] Determine the signal frequencies other than the highest signal frequency and the harmonic signal frequency in the spectrum data to be measured as the remaining signal frequencies;

[0120] Determine the residual signal frequency power corresponding to each residual signal frequency;

[0121] Based on the power of each remaining signal frequency point, the total power of the noise signal is calculated.

[0122] In the spectrum data to be measured, the remaining signal frequencies except the highest signal frequency and the harmonic signal frequency are generally noise or non-target signals.

[0123] As an example, we can traverse the spectrum data to be measured, mark and exclude the highest signal frequency and harmonic signal frequency, and obtain the remaining unmarked signal frequency points. Then, we extract the remaining signal frequency power corresponding to each remaining signal frequency point, and then calculate the total noise signal power according to formula (8).

[0124] (8);

[0125] In formula (8), represents the total power of the noise signal; j Indicates the index of summation, its value is 1,2,..., k , k represents the total number of remaining signal frequencies, Represents the residual signal frequency power corresponding to the jth residual signal frequency.

[0126] In some embodiments, determining a performance test result of the chip to be tested based on the total harmonic power and the total noise signal power and a preset chip performance qualification index includes:

[0127] Determine the signal-to-noise ratio and total harmonic distortion rate of the digital signal under test output by the chip under test according to the total harmonic power and the total power of the noise signal;

[0128] If the signal-to-noise ratio and the total harmonic distortion rate meet the preset chip performance qualification index, the performance test result of the chip to be tested is determined to be qualified; otherwise, the performance test result of the chip to be tested is unqualified.

[0129] The signal-to-noise ratio (SNR) measures the purity of the digital signal output by the chip under test. A higher SNR indicates a stronger signal component relative to the noise component in the digital signal output by the chip under test.

[0130] Total harmonic distortion (THD) refers to the main harmonic components of the output signal that are greater than the input signal, which is caused by the system's incomplete linearity.

[0131] The preset chip performance qualification indicators include that the signal-to-noise ratio of the digital signal output by the chip is greater than the preset signal-to-noise ratio threshold (which can be flexibly set according to actual conditions), and the total harmonic distortion rate is less than the preset total harmonic distortion rate threshold (which can be flexibly set according to actual conditions).

[0132] As an example, the signal-to-noise ratio of the digital signal under test output by the chip under test can be calculated according to formula (9).

[0133] (9);

[0134] In formula (9), Indicates the signal-to-noise ratio of the digital signal under test output by the chip under test; Indicates the total harmonic power; represents the total power of the noise signal; Indicates the maximum signal power corresponding to the highest signal frequency.

[0135] The total harmonic distortion rate of the digital signal under test output by the chip under test can be calculated according to formula (10).

[0136] (10);

[0137] In formula (10), Indicates the total harmonic distortion rate of the digital signal under test output by the chip under test; Indicates the total harmonic power; Indicates the maximum signal power corresponding to the highest signal frequency.

[0138] Next, based on the signal-to-noise ratio calculated by equation (9) and the total harmonic distortion rate calculated by equation (10), it is determined whether the performance test results of the chip under test are qualified.

[0139] If the signal-to-noise ratio of the digital signal under test output by the chip under test is greater than a preset signal-to-noise ratio threshold, and the total harmonic distortion rate is less than a preset total harmonic distortion rate threshold, the performance test result of the chip under test can be determined to be qualified. If the signal-to-noise ratio of the digital signal under test output by the chip under test is less than or equal to the preset signal-to-noise ratio threshold, and the total harmonic distortion rate is greater than or equal to the preset total harmonic distortion rate threshold, the performance test result of the chip under test can be determined to be unqualified.

[0140] In summary, the chip testing method provided in the embodiments of this application can solve the problem of spectral leakage after Fourier transform when the various components of the chip testing system lack clock synchronization. It can quickly process data and derive the required parameter results, thereby improving the accuracy of chip test results while also saving costs (no additional circuit design is required). This method can be widely applied in fields such as chip testing and electronic equipment testing, and has strong market demand and broad application prospects.

[0141] All of the above optional technical solutions can be combined in any way to form optional embodiments of the present application, and will not be described in detail here.

[0142] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0143] Figure 3 This is a schematic diagram of a chip testing device provided in an embodiment of the present application. Figure 3 The chip testing device 104 of this embodiment includes: a processor 301 and a memory 302, the memory 302 is used to store a computer program 303, and the processor 301 is used to execute the steps of the above-mentioned various method embodiments when calling the computer program 303.

[0144] The chip testing device 104 can be an electronic device such as a desktop computer, a notebook, a PDA, or a cloud server. The chip testing device 104 can include but is not limited to a processor 301 and a memory 302. Those skilled in the art will understand that Figure 3 The chip testing device 104 is merely an example and does not limit the chip testing device 104 . The chip testing device 104 may include more or fewer components than shown in the figure, or different components.

[0145] The processor 301 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0146] Memory 302 can be an internal storage unit of chip testing device 104, such as a hard drive or memory of chip testing device 104. Memory 302 can also be an external storage device of chip testing device 104, such as a plug-in hard drive, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. equipped on chip testing device 104. Memory 302 can also include both internal storage units of chip testing device 104 and external storage devices. Memory 302 is used to store computer programs and other programs and data required by electronic devices.

[0147] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0148] If the integrated module / unit is implemented as a software functional unit and sold or used as a standalone product, it can be stored in a readable storage medium. Based on this understanding, the present application can implement all or part of the process steps in the above-mentioned method embodiments by using a computer program to instruct the relevant hardware. The computer program can be stored in a readable storage medium, and when executed by a processor, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program can include computer program code, which can be in source code form, object code form, executable file, or some intermediate form. Computer-readable media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, removable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signals, telecommunications signals, and software distribution media. It should be noted that the content included in computer-readable media can be appropriately increased or decreased based on the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, based on legislation and patent practice, computer-readable media does not include electric carrier signals and telecommunications signals.

[0149] An embodiment of the present application further provides a computer-readable storage medium on which a program is stored. When the program is executed by a processor, the steps in the above-mentioned various method embodiments are implemented.

[0150] An embodiment of the present application further provides a program product. When the program product is run on a chip testing device, the chip testing device is caused to execute the steps in the above-mentioned various method embodiments.

[0151] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course can also be implemented by special hardware including application-specific integrated circuits, special CPUs, special memories, special components, etc. In general, all functions performed by computer programs can be easily implemented with corresponding hardware, and the specific hardware structures used to implement the same function can also be diverse, such as analog circuits, digital circuits or special circuits, etc. However, for the present application, software program implementation is a better implementation method in most cases. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., and includes a number of instructions to enable a computer device (which can be a personal computer, training equipment, or network equipment, etc.) to execute the methods described in each embodiment of the present application.

[0152] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0153] In the above embodiments, the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, training equipment or data center to another website, computer, training equipment or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a training device, data center, etc. that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0154] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A chip testing method, used in a chip testing device, characterized in that: include: Acquire a digital signal to be tested, wherein the digital signal to be tested is obtained by the chip to be tested performing signal processing on a preset analog signal; The digital signal to be measured is sampled to obtain a sampled time domain signal of finite length; if the sampled time domain signal is a non-integer periodic sampling signal, a target window function is called to smooth the sampled time domain signal to obtain a time domain signal to be measured; wherein the expression of the target window function is as follows: ； in, represents the target window function, 、 、 、 are the first coefficient, second coefficient, third coefficient and fourth coefficient of the target window function respectively, Indicates the sampling value corresponding to the current sampling point, Indicates the total number of sampling points of the sampled time domain signal; Extracting the amplitude spectrum and phase spectrum of the frequency domain signal to be measured; if the amplitude spectrum contains a zero value, performing zero-value smoothing processing on the amplitude spectrum to obtain first processed data; performing logarithmic processing on the first processed data to obtain second processed data; performing normalization processing on the second processed data to obtain third processed data; combining the third processed data with the phase spectrum to obtain frequency spectrum data to be measured; Based on the spectrum data to be tested and the preset chip performance qualification index, the performance test result of the chip to be tested is determined, wherein the preset chip performance qualification index is determined based on the performance parameters of the chip to be tested, and the preset chip performance qualification index is determined based on at least one of the following performance parameters: performance parameters of a preset excitation signal, performance parameters of digital-to-analog conversion, and performance parameters of the chip to be tested.

2. The method according to claim 1, characterized in that Calling a target window function to smooth the sampled time domain signal to obtain a time domain signal to be measured includes: Determining a sampling weighting coefficient corresponding to each sampling point of the sampled time domain signal based on a target window function; The sampled time domain signal is smoothed using the sampling weight coefficient corresponding to each sampling point to obtain a time domain signal to be measured.

3. The method according to claim 2, characterized in that Determining a sampling weighting coefficient corresponding to each sampling point of the sampled time domain signal based on a target window function includes: Determine a sampling value corresponding to each sampling point of the sampled time domain signal, and the total number of sampling points; Based on the target window function, the sampling value corresponding to each sampling point, and the total number of sampling points, a sampling weighting coefficient corresponding to each sampling point of the sampled time domain signal is determined.

4. The method according to claim 1, wherein Determining a performance test result of the chip to be tested based on the spectrum data to be tested and a preset chip performance qualification index includes: Finding the highest signal frequency point in the spectrum data to be measured; Determining the total harmonic power based on the maximum signal frequency corresponding to the highest signal frequency point; Determining the total power of the noise signal of the spectrum data to be measured; The performance test result of the chip to be tested is determined according to the total harmonic power, the total noise signal power and a preset chip performance qualification index.

5. The method according to claim 4, characterized in that Determining the total harmonic power based on the maximum signal frequency corresponding to the highest signal frequency point includes: generating a harmonic frequency list based on the maximum signal frequency corresponding to the highest signal frequency point, and determining all harmonic signal frequency points in the spectrum data to be measured according to the harmonic frequency list; Determining the harmonic signal frequency power corresponding to each of the harmonic signal frequencies; The total harmonic power is determined based on the power of the harmonic signal frequency points.

6. The method according to claim 4, characterized in that Determining the total power of the noise signal of the spectrum data to be measured includes: Determining the signal frequencies other than the highest signal frequency and the harmonic signal frequency in the spectrum data to be measured as remaining signal frequencies; Determining the residual signal frequency power corresponding to each of the residual signal frequencies; The total power of the noise signal is calculated based on the power of each of the remaining signal frequency points.

7. The method according to claim 5, characterized in that Determining a performance test result of the chip to be tested according to the total harmonic power, the total noise signal power, and a preset chip performance qualification index includes: Determining the signal-to-noise ratio and total harmonic distortion rate of the digital signal under test output by the chip under test according to the total harmonic power and the total noise signal power; If the signal-to-noise ratio and the total harmonic distortion rate meet the preset chip performance qualification index, the performance test result of the chip to be tested is determined to be qualified; otherwise, the performance test result of the chip to be tested is unqualified.

8. A chip testing system, characterized in that: include: Signal source transmitting device, digital-to-analog conversion device, chip to be tested and chip testing device; The signal source transmitting device is connected to the digital-to-analog conversion device, the digital-to-analog conversion device is connected to the chip to be tested, and the chip to be tested is connected to the chip testing device; The chip testing device is used to perform the method according to any one of claims 1 to 7.

9. A chip testing device, characterized in that: include: A memory and a processor, the memory being used to store a computer program; the processor being used to execute the method according to any one of claims 1 to 7 when calling the computer program.

10. A readable storage medium having a program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

11. A program product, characterized in that When the program product is run on a chip testing device, the chip testing device is caused to execute the method according to any one of claims 1 to 7.

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