On-chip band-pass filter with continuously reconfigurable frequency and bandwidth
Through the combination of mode switching transformer, varactor tube and negative resistance compensation technology, continuous reconfigurable frequency and bandwidth is achieved, solving the problem of limited adjustment range of existing filters, and meeting the high frequency and high integration requirements of modern wireless communication systems.
Patent Information
- Application Number
- CN202510523305.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-24
- Publication Date
- 2025-08-05
AI Technical Summary
The existing reconfigurable filter frequency and bandwidth adjustment range are limited, making it difficult to meet the needs of modern wireless communication systems for higher frequencies, smaller areas and higher integration.
The mode switching transformer is used to inductively coupled with the mode switching, and combined with the varactor tube and negative resistance compensation technology, the continuous frequency adjustment within the frequency range of 10-17GHz and the bandwidth adjustment greater than 500MHz are achieved. By controlling the coupling amount of the transformer in different inductance modes, the filter frequency and bandwidth can be freely reconstructed.
The continuous adjustability of frequency and bandwidth in the frequency range of 10-17GHz is achieved, which meets the needs of modern wireless communication systems for high frequency and high integration, reduces the filter insertion loss and improves the rectangular coefficient.
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Figure CN120433734A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of wireless communication systems, and in particular relates to an on-chip bandpass filter with continuously reconfigurable frequency and bandwidth. Background Art
[0002] Filters are commonly used passive circuits in modern wireless communication networks to filter out-of-band interference. With the development of wireless systems, RF front-end filters require higher frequencies, smaller footprints, and higher integration. CMOS-based on-chip reconfigurable filters not only offer higher integration and smaller size, but also feature reconfigurability, enabling the use of a single filter to achieve different frequency and bandwidth configurations.
[0003] Most existing reconfigurable filters are based on traditional coupled filter architectures, which have limited frequency and bandwidth adjustment ranges. Summary of the Invention
[0004] The present invention aims to provide an on-chip bandpass filter with continuously reconfigurable frequency and bandwidth. This filter utilizes a mode-switching transformer coupled with a mode-switching inductor to achieve continuous frequency adjustment between 10 and 17 GHz. A loaded coupling varactor controls the mode-switching transformer coupling in both modes. The filter achieves a bandwidth adjustment range greater than 500 MHz between 10 and 17 GHz. Negative resistance compensation is used to compensate for the resonator quality factor, resulting in a passband attenuation of less than 4 dB. This approach addresses the technical issues of limited frequency and bandwidth adjustment in existing reconfigurable filters.
[0005] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:
[0006] A frequency and bandwidth continuously reconfigurable on-chip bandpass filter, the bandpass filter comprises three mode switching inductors, the three mode switching inductors are respectively a first mode switching inductor MSI1, a second mode switching inductor MSI2, a third mode switching inductor MSI3, three mode switching switch units, six negative resistance compensation structures NR, a first varactor C1, a second varactor C2, a third varactor C3, a fourth varactor C4, a fifth varactor C5, a sixth varactor C6, two first and second varactor C 12 、4 second and third varactor tubes C 23 , 2 input varactors C in And 2 output varactors C out composition;
[0007] The excitation port of each mode switching inductor is connected to the mode switching switch unit; the first varactor C1 and the second varactor C2 are loaded to the two ends of the first mode switching inductor MSI1 to form a first resonator; the third varactor C3 and the fourth varactor C4 are loaded to the two ends of the second mode switching inductor MSI2 to form a second resonator; the fifth varactor C5 and the sixth varactor C6 are loaded to the two ends of the third mode switching inductor MSI3 to form a third resonator; the first mode switching inductor MSI1 and the second mode switching inductor MSI2 are close to each other to form a mode switching transformer; the two first and second varactor C 12 Loaded at both ends of the mode switching transformer, used to control the coupling between the second resonator and the third resonator; 4 second and third varactor tubes C 23 The first resonator is loaded between the second resonator and the third resonator to control the coupling between the second resonator and the third resonator; the excitation port of each mode switching inductor is connected to two negative resistance compensation structures NR; the first resonator is used as the input end of the bandpass filter, and the first resonator is connected to the second resonator through two input varactors C. in Connected to the differential signal; the third resonator serves as the output end of the filter, and the output passes through the output varactor C out Output to the outside.
[0008] Furthermore, the mode switching inductor is composed of 5 microstrip branches; the fifth microstrip branch L5 is a common microstrip branch, one end of the fifth microstrip branch is connected to the first microstrip branch L1 and one end of the second microstrip branch L2, and the other end of the fifth microstrip branch is connected to the third microstrip branch L3 and one end of the fourth microstrip branch L4; the first microstrip branch L1, the second microstrip branch L2 and the third microstrip branch L3, and the fourth microstrip branch L4 are symmetrical with respect to the perpendicular bisector of the fifth microstrip branch L5; the other end of the first microstrip branch L1 is the first excitation port P1, the other end of the second microstrip branch L2 is the second excitation port P2, the other end of the third microstrip branch L3 is the third excitation port P3, and the other end of the fourth microstrip branch L4 is the fourth excitation port P4.
[0009] Furthermore, the mode switching switch unit is composed of four PMOS switches; the source of the first PMOS switch M1 and the source of the fourth PMOS switch M4 are connected to the fourth excitation port P4, the drain of the first PMOS switch M1 and the drain of the third PMOS switch M3 are connected to the second excitation port P2, the source of the second PMOS switch M2 and the drain of the fourth PMOS switch M4 are connected to the third excitation port P3, the drain of the second PMOS switch M2 and the source of the third PMOS switch M3 are connected to the first excitation port P1, and the gate of the third PMOS switch M3 and the gate of the fourth PMOS switch M4 are connected to the first bias voltage V SW1, the gate of the first PMOS switch M1 and the gate of the first PMOS switch M2 are connected to the second bias voltage V SW2 .
[0010] Furthermore, the fifth microstrip branch L5 of the three mode switching inductors is connected to a DC bias voltage VDD; by controlling the first bias voltage V SW1 is low level, i.e. 0V, and the second bias voltage V SW2 The first bias voltage VDD is high, i.e., 2V, forming a voltage difference with the DC bias voltage VDD, so that the first PMOS switch tube M1 and the second PMOS switch tube M2 in the mode switching switch unit are turned on, and the gate of the third PMOS switch tube M3 and the fourth PMOS tube M4 are turned off, so that the first excitation port P1 is connected to the third excitation port P3, and the second excitation port P2 is connected to the fourth excitation port P4. At this time, the mode switching inductor is in the first inductor mode, and the bandpass filter operates in the low frequency band. By controlling the first bias voltage V SW1 is high level, i.e. 2V and the second bias voltage V SW2 It is a low level, i.e., 0V, forming a voltage difference with the DC bias voltage VDD, so that the first PMOS switch tube M1 and the second PMOS switch tube M2 in the mode switching switch unit are turned off, and the gate of the third PMOS switch tube M3 and the fourth PMOS tube M4 are turned on, so that the first excitation port P1 is connected to the second excitation port P2, and the third excitation port P3 is connected to the fourth excitation port P4. At this time, the mode switching inductor processes the second inductor mode, and the bandpass filter operates in the high frequency band.
[0011] Furthermore, one end of the first varactor C1 is connected to the first excitation port P1 of the first mode-switching inductor MSI1, and the other end is connected to the fourth excitation port P4 of the first mode-switching inductor MSI1. One end of the second varactor C2 is connected to the second excitation port P2 of the first mode-switching inductor MSI1, and the other end is connected to the third excitation port P3 of the first mode-switching inductor MSI1. One end of the third varactor C3 is connected to the first excitation port P1 of the second mode-switching inductor MSI2, and the other end is connected to the fourth excitation port P4 of the second mode-switching inductor MSI2. One end of the fourth varactor C4 is connected to the second excitation port P2 of the second mode-switching inductor MSI2, and the other end is connected to the third excitation port P3 of the second mode-switching inductor MSI2. One end of the fifth varactor C5 is connected to the first excitation port P1 of the third mode switching inductor MSI3, and the other end is connected to the fourth excitation port P4 of the third mode switching inductor MSI3; one end of the sixth varactor C6 is connected to the second excitation port P2 of the third mode switching inductor MSI3, and the other end is connected to the third excitation port P3 of the third mode switching inductor MSI3.
[0012] Furthermore, a first second varactor C 12One end of the first mode switching inductor MSI1 is connected to the first excitation port P1, and the other end is connected to the first excitation port P1 of the second mode switching inductor MSI2; another first second varactor C 12 One end of the transistor is connected to the fourth excitation port P4 of the first mode switching inductor MSI1 , and the other end of the transistor is connected to the fourth excitation port P4 of the second mode switching inductor MSI2 .
[0013] Furthermore, the first, second and third varactor tubes C 23 One end of the second mode switching inductor MSI2 is connected to the first excitation port P1, and the other end is connected to the first excitation port P1 of the third mode switching inductor MSI3; the second third varactor C 23 One end of the second mode switching inductor MSI2 is connected to the second excitation port P2, and the other end is connected to the second excitation port P2 of the third mode switching inductor MSI3; the third second third varactor C 23 One end of the fourth second third varactor C is connected to the third excitation port P3 of the second mode switching inductor MSI2, and the other end is connected to the third excitation port P3 of the third mode switching inductor MSI3; 23 One end of the transistor is connected to the fourth excitation port P4 of the second mode switching inductor MSI2, and the other end of the transistor is connected to the fourth excitation port P4 of the third mode switching inductor MSI3.
[0014] Furthermore, each negative resistance compensation structure NR includes two first NMOS transistors NMOS1 and a second NMOS transistor NMOS2; the source of the second NMOS transistor NMOS2 is grounded, and the gate of the second NMOS transistor NMOS2 is connected to the DC voltage V b The drain of the second NMOS transistor NMOS2 is connected to the sources of the two first NMOS transistors NMOS1, the gate of one of the two first NMOS transistors NMOS1 is connected to the drain of the other first NMOS transistor NMOS1, and then connected to the mode switching inductor as the two end points of the negative resistance compensation structure NR.
[0015] Furthermore, the ports of each mode-switching inductor are connected to two negative resistance compensation structures NR. One end of one negative resistance compensation structure NR is connected to the first excitation port P1, and the other end is connected to the fourth excitation port P4; one end of the other negative resistance compensation structure NR is connected to the second excitation port P2, and the other end is connected to the third excitation port P3.
[0016] Furthermore, the positive electrode of the differential signal is input to the varactor C in Connected to the first excitation port P1 of the first resonator, the negative pole of the differential signal is input through the varactor C inConnected to the fourth excitation port P4 of the first resonator; the first excitation port P1 of the third resonator is connected ... out As the positive electrode of the differential signal output, the fourth excitation port P4 of the third resonator is connected to the output varactor C out Serves as the negative pole of the differential signal output.
[0017] Compared with the existing technology, the present invention has the following beneficial technical effects: the present invention loads a varactor on the basis of a mode switching transformer, thereby realizing a continuous frequency adjustment range within the range of 10-17GHz; by controlling the inductive coupling of the mode switching transformer in the first inductive mode and the second inductive mode, the bandwidth in the two modes can be freely reconfigured. By controlling the coupling amount of the mode switching transformer in the two modes through the loaded varactor, the bandwidth adjustment of the filter in the entire frequency band can be realized. The present invention realizes the simultaneous adjustment of the frequency and attenuation of the chip filter in the frequency range of 10-17GHz. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in describing the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0019] Figure 1 The diagram is a schematic diagram showing the principle structure of an on-chip bandpass filter circuit with continuously reconfigurable frequency and bandwidth according to the present invention.
[0020] Figure 2 This is a schematic diagram of the physical structure of the on-chip bandpass filter with continuously reconfigurable frequency and bandwidth according to the present invention.
[0021] Figure 3 (a) and (b) are the transmission and reflection parameters of the filter with adjustable frequency from 10 to 17 GHz. The bandwidth of the low-band filter is fixed at 1.5 GHz, and the bandwidth of the high-band filter is fixed at 1 GHz.
[0022] Figure 4 This is a schematic diagram of the adjustable bandwidth of the filter of the present invention. DETAILED DESCRIPTION
[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0024] The present invention proposes an on-chip bandpass filter with continuously reconfigurable frequency and bandwidth, such as Figure 1 As shown, the bandpass filter consists of three mode switching inductors, three mode switching switch units, six negative resistance compensation structures NR, a first varactor C1, a second varactor C2, a third varactor C3, a fourth varactor C4, a fifth varactor C5, a sixth varactor C6, two first and second varactor C 12 、4 second and third varactor tubes C 23 , 2 input varactors C in And 2 output varactors C out composition.
[0025] The excitation port of each mode switching inductor is interconnected with the mode switching switch unit. The first varactor C1 and the second varactor C2 are loaded onto the two ends of the first mode switching inductor MSI1 to form a first resonator; the third varactor C3 and the fourth varactor C4 are loaded onto the two ends of the second mode switching inductor MSI2 to form a second resonator; the fifth varactor C5 and the sixth varactor C6 are loaded onto the two ends of the third mode switching inductor MSI3 to form a third resonator. The first mode switching inductor MSI1 and the second mode switching inductor MSI2 are close to each other to form a mode switching transformer. The first and second varactor C 12 Loaded at both ends of the mode switching transformer, used to control the coupling between the second resonator and the third resonator; 4 second and third varactor tubes C 23 The inductor is loaded between the second resonator and the third resonator to control the coupling between the second resonator and the third resonator. The excitation port of each mode switching inductor is connected to two negative resistance compensation structures NR.
[0026] The mode switching inductor is composed of five microstrip branches. The fifth microstrip branch L5 is a common microstrip branch. One end of the fifth microstrip branch connects the first microstrip branch L1 and one end of the second microstrip branch L2, and the other end of the fifth microstrip branch connects the third microstrip branch L3 and one end of the fourth microstrip branch L4. The first microstrip branch L1, the second microstrip branch L2, the third microstrip branch L3, and the fourth microstrip branch L4 are symmetrical with respect to the perpendicular bisector of the fifth microstrip branch L5. The other end of the first microstrip branch L1 is the first excitation port P1, the other end of the second microstrip branch L2 is the second excitation port P2, the other end of the third microstrip branch L3 is the third excitation port P3, and the other end of the fourth microstrip branch L4 is the fourth excitation port P4.
[0027] The three mode switching inductors are respectively a first mode switching inductor MSI1 , a second mode switching inductor MSI2 , and a third mode switching inductor MSI3 .
[0028] The fifth microstrip branch L5 of the three mode switching inductors is connected to a DC bias voltage VDD, which is 1.2V.
[0029] The mode switching switch unit is composed of four PMOS switches. The excitation port of each mode switching inductor is connected to the mode switching switch unit. The source of the first PMOS switch M1 and the source of the fourth PMOS switch M4 are connected to the fourth excitation port P4, the drain of the first PMOS switch M1 and the drain of the third PMOS switch M3 are connected to the second excitation port P2, the source of the second PMOS switch M2 and the drain of the fourth PMOS switch M4 are connected to the third excitation port P3, the drain of the second PMOS switch M2 and the source of the third PMOS switch M3 are connected to the first excitation port P1, and the gate of the third PMOS switch M3 and the gate of the fourth PMOS switch M4 are connected to the first bias voltage V SW1 , the gate of the first PMOS switch M1 and the gate of the first PMOS switch M2 are connected to the second bias voltage V SW2 .
[0030] By controlling the first bias voltage V SW1 is low level, i.e. 0V, and the second bias voltage V SW2 The first bias voltage VDD is high, i.e. 2V, forming a voltage difference with the DC bias voltage VDD, so that the first PMOS switch tube M1 and the second PMOS switch tube M2 in the mode switching switch unit are turned on, and the gate of the third PMOS switch tube M3 and the fourth PMOS tube M4 are turned off, so that the first excitation port P1 is connected to the third excitation port P3, and the second excitation port P2 is connected to the fourth excitation port P4. At this time, the mode switching inductor is in the first inductor mode, and the bandpass filter operates in the low frequency band. By controlling the first bias voltage V SW1 is high level, i.e. 2V and the second bias voltage V SW2 It is a low level, i.e., 0V, forming a voltage difference with the DC bias voltage VDD, so that the first PMOS switch tube M1 and the second PMOS switch tube M2 in the mode switching switch unit are turned off, and the gate of the third PMOS switch tube M3 and the fourth PMOS tube M4 are turned on, so that the first excitation port P1 is connected to the second excitation port P2, and the third excitation port P3 is connected to the fourth excitation port P4. At this time, the mode switching inductor processes the second inductor mode, and the bandpass filter operates in the high frequency band.
[0031] The first and second varactors C1 and C2 are connected across the first mode-switching inductor MSI1 to form a first resonator. The third and fourth varactors C3 and C4 are connected across the second mode-switching inductor MSI2 to form a second resonator. The fifth and sixth varactors C5 and C6 are connected across the third mode-switching inductor MSI3 to form a third resonator. The first and second varactors C1 and C2 are used to change the resonant frequency of the first resonator; the third and fourth varactors C3 and C4 are used to change the resonant frequency of the second resonator; and the fifth and sixth varactors C5 and C6 are used to change the resonant frequency of the third resonator.
[0032] Specifically, one end of the first varactor C1 is connected to the first excitation port P1 of the first mode-switching inductor MSI1, and the other end is connected to the fourth excitation port P4 of the first mode-switching inductor MSI1. One end of the second varactor C2 is connected to the second excitation port P2 of the first mode-switching inductor MSI1, and the other end is connected to the third excitation port P3 of the first mode-switching inductor MSI1. One end of the third varactor C3 is connected to the first excitation port P1 of the second mode-switching inductor MSI2, and the other end is connected to the fourth excitation port P4 of the second mode-switching inductor MSI2. One end of the fourth varactor C4 is connected to the second excitation port P2 of the second mode-switching inductor MSI2, and the other end is connected to the third excitation port P3 of the second mode-switching inductor MSI2. One end of the fifth varactor C5 is connected to the first excitation port P1 of the third mode switching inductor MSI3, and the other end is connected to the fourth excitation port P4 of the third mode switching inductor MSI3; one end of the sixth varactor C6 is connected to the second excitation port P2 of the third mode switching inductor MSI3, and the other end is connected to the third excitation port P3 of the third mode switching inductor MSI3.
[0033] The first mode-switching inductor MSI1 and the second mode-switching inductor MSI2 are positioned close together to form a mode-switching transformer. The coupling of the mode-switching transformer is determined by the overlap distance S1 between the first mode-switching inductor MSI1 and the second mode-switching inductor MSI2. By designing the overlap distance S1, the inductive coupling between the first resonator and the second resonator in both inductive modes can be controlled.
[0034] 2 first and second varactors C 12 Loaded at both ends of the mode switching transformer, it is used to control the capacitive coupling between the first resonator and the second resonator. The capacitive coupling and the inductive coupling formed by the transformer jointly determine the coupling amount between the first resonator and the second resonator. Specifically, a first second varactor C 12 One end of the first mode switching inductor MSI1 is connected to the first excitation port P1, and the other end is connected to the first excitation port P1 of the second mode switching inductor MSI2; another first second varactor C12 One end of the transistor is connected to the fourth excitation port P4 of the first mode switching inductor MSI1 , and the other end of the transistor is connected to the fourth excitation port P4 of the second mode switching inductor MSI2 .
[0035] 4 second and third varactor tubes C 23 The first second third varactor C is loaded between the second resonator and the third resonator to control the coupling between the second resonator and the third resonator. 23 One end of the second mode switching inductor MSI2 is connected to the first excitation port P1, and the other end is connected to the first excitation port P1 of the third mode switching inductor MSI3; the second third varactor C 23 One end of the second mode switching inductor MSI2 is connected to the second excitation port P2, and the other end is connected to the second excitation port P2 of the third mode switching inductor MSI3; the third second third varactor C 23 One end of the fourth second third varactor C is connected to the third excitation port P3 of the second mode switching inductor MSI2, and the other end is connected to the third excitation port P3 of the third mode switching inductor MSI3; 23 One end of the transistor is connected to the fourth excitation port P4 of the second mode switching inductor MSI2, and the other end of the transistor is connected to the fourth excitation port P4 of the third mode switching inductor MSI3.
[0036] 2 first and second varactors C 12 and 4 second and third varactor tubes C 23 Used to change the bandwidth of the filter.
[0037] The negative resistance compensation structure NR is connected at both ends of the resonator to compensate for the loss introduced by the low-quality resonator on the chip, reducing the filter insertion loss while improving the filter's rectangular coefficient. Each negative resistance compensation structure NR includes two first NMOS transistors NMOS1 and one second NMOS transistor NMOS2. The size of the first NMOS transistor NMOS1 is 10um / 60nm, and the size of the second NMOS transistor NMOS2 is 15um / 60nm. Specifically, the source of the second NMOS transistor NMOS2 is grounded, and the gate of the second NMOS transistor NMOS2 is connected to the DC voltage V b The drain of the second NMOS transistor NMOS2 is connected to the source of the two first NMOS transistors NMOS1, and the gate of one of the two first NMOS transistors NMOS1 is connected to the drain of the other first NMOS transistor NMOS1, and then connected to the mode switching inductor as the two ends of the negative resistance compensation structure NR. By controlling the DC voltage V b The size of the negative resistance can be changed by controlling the current.
[0038] The excitation port of each mode-switching inductor is connected to two negative resistance compensation structures NR. One negative resistance compensation structure NR has one end connected to the first excitation port P1 and the other end connected to the fourth excitation port P4. The other negative resistance compensation structure NR has one end connected to the second excitation port P2 and the other end connected to the third excitation port P3.
[0039] The first resonator is used as the input of the filter, and the two input varactors C in Connected to the differential signal; that is, the positive pole of the differential signal passes through the input varactor C in Connected to the first excitation port P1 of the first resonator, the negative pole of the differential signal is input through the varactor C in Connected to the fourth excitation port P4 of the first resonator. The third resonator serves as the output end of the filter, and the output is transmitted through the output varactor C out Output to the outside; that is, the first excitation port P1 of the third resonator is output through the output varactor C out As the positive electrode of the differential signal output, the fourth excitation port P4 of the third resonator is connected to the output varactor C out Serves as the negative pole of the differential signal output.
[0040] The present invention loads a varactor at both ends of the mode switching transformer, and controls the first and second varactors C 12 The voltage controls the overall coupling between the first resonator and the second resonator in the two modes, and controls the four second and third varactor tubes C 23 The coupling between the second resonator and the third resonator is realized. The resonator frequency of the filter is determined by the mode switching inductor and the first capacitor C1 to the sixth capacitor C6 between the resonators. The bandwidth of the filter is determined by the coupling of the mode switching transformer and the first and second varactor tubes C1 loaded. 12 and the second and third varactor C 23 The introduction of capacitive coupling is jointly determined.
[0041] When the first mode switching inductor MSI1 and the second mode switching inductor MSI2 operate in the second inductive mode, the inductive coupling between the first resonator and the second resonator is zero, and the coupling amount is entirely determined by the capacitive coupling. By rationally designing the inductance values of the three mode switching inductors in the two inductive modes and the size of the resonant capacitor, the frequency can be continuously adjusted in the two inductive modes. The resonant frequency of the filter is controlled by adjusting the bias voltage of the first varactor C1, the second varactor C2, the third varactor C3, the fourth varactor C4, the fifth varactor C5, and the sixth varactor C6. By controlling the input varactor C in 、The first and second varactor C 12 、Second and third varactor C 23 , output varactor C out The size of the bias voltage controls the bandwidth of the filter.
[0042] The adjustment range and design dimensions of the varactor are shown in Table 1:
[0043] Table 1 Adjustment range and design dimensions of varactor
[0044]
[0045]
[0046] The present invention adopts 65nm CMOS technology to carry out chip processing, and the microphotograph of the bandpass filter chip is as follows: Figure 2 As shown, its size is 0.78*0.42mm 2 The distances between the mode switching inductor microstrip branches are D1 = 81 um, D2 = 60 um, D3 = 111 um, and D4 = 138 um. The overlapping distance between the first mode switching inductor MSI1 and the second mode switching inductor MSI2 is S1 = 25 um. The width of the mode switching inductor microstrip branch is W1 = 10 um.
[0047] Use GSGSG differential probe to test, the DC bias voltage VDD is 1.2V, set the first bias voltage V SW1 is 0V, the second bias voltage V SW2 is 2V, the three mode switching inductors work in the first inductor mode, and the filter works in the low frequency band; set the first bias voltage V SW1 The first varactor C1, the second varactor C2, the third varactor C3, the fourth varactor C4, the fifth varactor C5, the sixth varactor C6 and the input varactor C in 、The first and second varactor C 12 、Second and third varactor C 23 , output varactor C out The bias voltage is set to achieve continuous adjustment of the filter frequency and bandwidth. The frequency adjustment effect of the tested chip filter is as follows: Figure 3 As shown, Figure 3 (a) and (b) are the transmission parameters and reflection parameters of the filter with adjustable frequency from 10 to 17 GHz, respectively. The center frequency can be adjusted from 10 GHz to 17 GHz. The bandwidth and frequency can be adjusted simultaneously. Figure 4 As shown, Figure 4 The effects of filter bandwidth changes when the filter frequency is fixed at 11.7 GHz, 14 GHz, and 17 GHz are given. It can be seen that the bandwidth adjustment range of the filter in each frequency band is greater than 500 MHz, verifying the frequency and bandwidth reconstruction function of the proposed structure.
[0048] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.
Claims
1. An on-chip bandpass filter with continuously reconfigurable frequency and bandwidth, characterized in that: The bandpass filter comprises three mode switching inductors, the three mode switching inductors are respectively a first mode switching inductor MSI1, a second mode switching inductor MSI2, and a third mode switching inductor MSI3, three mode switching switch units, six negative resistance compensation structures NR, a first varactor C1, a second varactor C2, a third varactor C3, a fourth varactor C4, a fifth varactor C5, a sixth varactor C6, two first and second varactor C 12 、4 second and third varactor tubes C 23 , 2 input varactors C in And 2 output varactors C out composition; The excitation port of each mode switching inductor is connected to the mode switching switch unit; the first varactor C1 and the second varactor C2 are loaded to the two ends of the first mode switching inductor MSI1 to form a first resonator; the third varactor C3 and the fourth varactor C4 are loaded to the two ends of the second mode switching inductor MSI2 to form a second resonator; the fifth varactor C5 and the sixth varactor C6 are loaded to the two ends of the third mode switching inductor MSI3 to form a third resonator; the first mode switching inductor MSI1 and the second mode switching inductor MSI2 are close to each other to form a mode switching transformer; the two first and second varactor C 12 loaded at both ends of the mode switching transformer for controlling the coupling between the second resonator and the third resonator; 4 second and third varactor tubes C 23 The first resonator is loaded between the second resonator and the third resonator to control the coupling between the second resonator and the third resonator; the excitation port of each mode switching inductor is connected to two negative resistance compensation structures NR; the first resonator is used as the input end of the bandpass filter, and the first resonator is connected to the second resonator through two input varactors C. in Connected to the differential signal; the third resonator serves as the output end of the filter, and the output passes through the output varactor C out Output to the outside.
2. The on-chip bandpass filter with continuously reconfigurable frequency and bandwidth according to claim 1, characterized in that: The mode switching inductor is composed of 5 microstrip branches; the fifth microstrip branch L5 is a common microstrip branch, one end of the fifth microstrip branch is connected to the first microstrip branch L1 and one end of the second microstrip branch L2, and the other end of the fifth microstrip branch is connected to the third microstrip branch L3 and one end of the fourth microstrip branch L4; the first microstrip branch L1, the second microstrip branch L2, the third microstrip branch L3, and the fourth microstrip branch L4 are symmetrical with respect to the perpendicular bisector of the fifth microstrip branch L5; the other end of the first microstrip branch L1 is the first excitation port P1, the other end of the second microstrip branch L2 is the second excitation port P2, the other end of the third microstrip branch L3 is the third excitation port P3, and the other end of the fourth microstrip branch L4 is the fourth excitation port P4.
3. The on-chip bandpass filter with continuously reconfigurable frequency and bandwidth according to claim 2, characterized in that: The mode switching unit is composed of four PMOS switches; the source of the first PMOS switch M1 and the source of the fourth PMOS switch M4 are connected to the fourth excitation port P4, the drain of the first PMOS switch M1 and the drain of the third PMOS switch M3 are connected to the second excitation port P2, the source of the second PMOS switch M2 and the drain of the fourth PMOS switch M4 are connected to the third excitation port P3, the drain of the second PMOS switch M2 and the source of the third PMOS switch M3 are connected to the first excitation port P1, and the gate of the third PMOS switch M3 and the gate of the fourth PMOS switch M4 are connected to the first bias voltage V SW1 , the gate of the first PMOS switch M1 and the gate of the first PMOS switch M2 are connected to the second bias voltage V SW2 .
4. The on-chip bandpass filter with continuously reconfigurable frequency and bandwidth according to claim 3, characterized in that: The fifth microstrip branch L5 of the three mode switching inductors is connected to the DC bias voltage VDD; by controlling the first bias voltage V SW1 is low level, i.e. 0V, and the second bias voltage V SW2 The first bias voltage VDD is high, i.e., 2V, forming a voltage difference with the DC bias voltage VDD, so that the first PMOS switch tube M1 and the second PMOS switch tube M2 in the mode switching switch unit are turned on, and the gate of the third PMOS switch tube M3 and the fourth PMOS tube M4 are turned off, so that the first excitation port P1 is connected to the third excitation port P3, and the second excitation port P2 is connected to the fourth excitation port P4. At this time, the mode switching inductor is in the first inductor mode, and the bandpass filter operates in the low frequency band. By controlling the first bias voltage V SW1 is high level, i.e. 2V and the second bias voltage V SW2 It is a low level, i.e., 0V, forming a voltage difference with the DC bias voltage VDD, so that the first PMOS switch tube M1 and the second PMOS switch tube M2 in the mode switching switch unit are turned off, and the gate of the third PMOS switch tube M3 and the fourth PMOS tube M4 are turned on, so that the first excitation port P1 is connected to the second excitation port P2, and the third excitation port P3 is connected to the fourth excitation port P4. At this time, the mode switching inductor processes the second inductor mode, and the bandpass filter operates in the high frequency band.
5. The on-chip bandpass filter with continuously reconfigurable frequency and bandwidth according to claim 2, characterized in that: One end of the first varactor C1 is connected to the first excitation port P1 of the first mode-switching inductor MSI1, and the other end is connected to the fourth excitation port P4 of the first mode-switching inductor MSI1; one end of the second varactor C2 is connected to the second excitation port P2 of the first mode-switching inductor MSI1, and the other end is connected to the third excitation port P3 of the first mode-switching inductor MSI1; one end of the third varactor C3 is connected to the first excitation port P1 of the second mode-switching inductor MSI2, and the other end is connected to the fourth excitation port P4 of the second mode-switching inductor MSI2; one end of the fourth varactor C4 is connected to the second excitation port P2 of the second mode-switching inductor MSI2, and the other end is connected to the third excitation port P3 of the second mode-switching inductor MSI2; one end of the fifth varactor C5 is connected to the first excitation port P1 of the third mode-switching inductor MSI3, and the other end is connected to the fourth excitation port P4 of the third mode-switching inductor MSI3; one end of the sixth varactor C6 is connected to the second excitation port P2 of the third mode-switching inductor MSI3, and the other end is connected to the third excitation port P3 of the third mode-switching inductor MSI3.
6. The on-chip bandpass filter with continuously reconfigurable frequency and bandwidth according to claim 2, characterized in that: A first second varactor C 12 One end of the first mode switching inductor MSI1 is connected to the first excitation port P1, and the other end is connected to the first excitation port P1 of the second mode switching inductor MSI2; another first second varactor C 12 One end of the transistor is connected to the fourth excitation port P4 of the first mode switching inductor MSI1 , and the other end of the transistor is connected to the fourth excitation port P4 of the second mode switching inductor MSI2 .
7. The on-chip bandpass filter with continuously reconfigurable frequency and bandwidth according to claim 2, characterized in that: The first, second and third varactor C 23 One end of the second mode switching inductor MSI2 is connected to the first excitation port P1, and the other end is connected to the first excitation port P1 of the third mode switching inductor MSI3; the second third varactor C 23 One end of the second mode switching inductor MSI2 is connected to the second excitation port P2, and the other end is connected to the second excitation port P2 of the third mode switching inductor MSI3; the third second third varactor C 23 One end of the fourth second third varactor C is connected to the third excitation port P3 of the second mode switching inductor MSI2, and the other end is connected to the third excitation port P3 of the third mode switching inductor MSI3; 23 One end of the transistor is connected to the fourth excitation port P4 of the second mode switching inductor MSI2, and the other end of the transistor is connected to the fourth excitation port P4 of the third mode switching inductor MSI3.
8. The on-chip bandpass filter with continuously reconfigurable frequency and bandwidth according to claim 2, characterized in that: Each negative resistance compensation structure NR includes two first NMOS transistors NMOS1 and a second NMOS transistor NMOS2; the source of the second NMOS transistor NMOS2 is grounded, and the gate of the second NMOS transistor NMOS2 is connected to a DC voltage V b The drain of the second NMOS transistor NMOS2 is connected to the sources of the two first NMOS transistors NMOS1, the gate of one of the two first NMOS transistors NMOS1 is connected to the drain of the other first NMOS transistor NMOS1, and then connected to the mode switching inductor as the two end points of the negative resistance compensation structure NR.
9. The on-chip bandpass filter with continuously reconfigurable frequency and bandwidth according to claim 7, characterized in that: The ports of each mode switching inductor are connected to two negative resistance compensation structures NR; one end point of one negative resistance compensation structure NR is connected to the first excitation port P1, and the other end point is connected to the fourth excitation port P4; one end point of the other negative resistance compensation structure NR is connected to the second excitation port P2, and the other end point is connected to the third excitation port P3.
10. The on-chip bandpass filter with continuously reconfigurable frequency and bandwidth according to claim 2, characterized in that: The positive electrode of the differential signal is input through the variable capacitance tube C in Connected to the first excitation port P1 of the first resonator, the negative pole of the differential signal is input through the varactor C in Connected to the fourth excitation port P4 of the first resonator; the first excitation port P1 of the third resonator is connected ... out As the positive electrode of the differential signal output, the fourth excitation port P4 of the third resonator is connected to the output varactor C out Serves as the negative pole of the differential signal output.