Preparation method of solar cell and solar cell

Abstract

The invention discloses a preparation method of a solar cell and the solar cell. The preparation method comprises the following steps: preparing a silicon oxide frame with a net-shaped structure on the main surface of a battery substrate in a laser treatment mode; and depositing an oxide layer on the main surface of the silicon oxide frame with the net structure of the battery substrate in a chemical deposition mode, and filling the inner region of the silicon oxide frame with the oxide layer, so that the silicon oxide frame and the oxide layer form a tunneling oxide layer. According to the preparation method, the uniformity of the tunneling oxide layer can be effectively improved, so that the tunneling passivation effect of the tunneling oxide layer is improved.

Description

Technical Field

[0001] The invention relates to a method for preparing a solar cell and the solar cell. Background Art

[0002] For tunnel oxide passivating contact (TOPCon) solar cells or interdigitated back contact (IBC) solar cells, passivation performance is generally achieved through a tunnel oxide layer.

[0003] Currently, tunnel oxide layers are primarily deposited via chemical vapor deposition (CVD), such as low-pressure CVD and low-temperature plasma CVD. However, the deposition process cannot control the thickness of the deposited CVD at different locations on the substrate, resulting in poor uniformity. This is particularly difficult to control for large-scale solar cells, making the uniformity of the CVD even more difficult to control. This poor uniformity leads to poor passivation performance. Summary of the Invention

[0004] In view of this, the present invention provides a method for preparing a solar cell and a solar cell. The preparation method can effectively improve the uniformity of a tunneling oxide layer, thereby improving the tunneling passivation effect of the tunneling oxide layer.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] In a first aspect, an embodiment of the present invention provides a method for preparing a solar cell, comprising:

[0007] Step 1: Prepare a silicon oxide framework with a mesh structure on the main surface of the battery substrate by laser processing;

[0008] Step 2: depositing an oxide layer on the main surface of the silicon oxide frame having the mesh structure of the battery substrate by chemical deposition, wherein the oxide layer fills the inner area of the silicon oxide frame so that the silicon oxide frame and the oxide layer constitute a tunneling oxide layer.

[0009] In a second aspect, an embodiment of the present invention provides a solar cell, comprising: a cell substrate, and a tunneling oxide layer disposed on a main surface of the cell substrate, wherein:

[0010] The tunneling oxide layer includes a silicon oxide frame with a mesh structure and an oxide layer filled in the silicon oxide frame.

[0011] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects:

[0012] The solar cell preparation method provided by the embodiment of the present invention first prepares a mesh-structured silicon oxide framework on the main surface of the cell substrate by laser processing, so that the silicon oxide framework is evenly distributed in various areas of the main surface of the cell substrate, which provides the basis for constructing a uniform tunneling oxide layer. In the subsequent chemical deposition process, the evenly distributed silicon oxide framework can, on the one hand, confine oxygen atoms within the silicon oxide framework, so that oxygen contacts the main surface of the cell substrate to form part of the oxide layer, and the oxide layer is deposited and grown along the silicon oxide framework. It forms an integral part with the silicon oxide framework, which can effectively reduce the impact of surface differences of the cell substrate on the deposition of the oxide layer. On the other hand, the evenly distributed silicon oxide framework provides a relatively balanced environment for contact with oxygen atoms for the exposed main surface of the cell substrate. Regardless of whether the oxygen atoms have a high concentration or a low concentration, the number of oxygen atoms that can enter the narrow area at the same time is limited, so that the oxygen atoms deposited in each small area within the silicon oxide framework are relatively balanced, and there is no large difference in deposition thickness due to high and low concentrations of oxygen atoms, thereby ensuring the uniformity of the tunneling oxide layer finally formed. Furthermore, since the number of oxygen atoms entering the narrow area at the same time is limited, most of the oxygen atoms have sufficient time to redistribute, thereby improving the uniformity of the oxygen atom concentration distribution, which helps to further improve the uniformity of the formed tunnel oxide layer.

[0013] In addition, since the oxide in the silicon oxide framework is a relatively stable structure, after the oxygen atoms come into contact with it, they remain in a free state and either react with the battery matrix adjacent to the silicon oxide framework or redistribute. Therefore, during the chemical deposition process, the oxygen atoms do not affect the silicon oxide framework, and the silicon oxide framework can redistribute the oxygen atoms in a small range, which helps to further improve the uniformity of the tunneling oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of the main process of a method for preparing a solar cell according to an embodiment of the present invention;

[0015] Figure 2 is a schematic diagram of a first structural change corresponding to the preparation method according to an embodiment of the present invention;

[0016] Figure 3 is a schematic diagram of a second structural change corresponding to the preparation method according to an embodiment of the present invention;

[0017] Figure 4 is a partial structural cross-sectional schematic diagram of a first structure of a solar cell according to an embodiment of the present invention;

[0018] Figure 5 is a partial structural cross-sectional schematic diagram of a second structure of a solar cell according to an embodiment of the present invention;

[0019] Figure 6 PL test grayscale images of multiple products produced according to the embodiments and comparative examples of the present invention;

[0020] Figure 7 2. It is a schematic diagram of the square resistance test results of multiple products produced according to the embodiments of the present invention and comparative examples;

[0021] Figure 8 is a comparison diagram of open circuit voltage according to an embodiment of the present invention and a comparative example;

[0022] Figure 9 is a comparison diagram of minority carrier lifetimes according to an embodiment of the present invention and a comparative example;

[0023] Figure 10 3 is a comparison diagram of composite carrier current density according to an embodiment of the present invention and a comparative example.

[0024] Reference numerals:

[0025] 10 - battery substrate; 11 - single crystal silicon wafer; 12 - emitter; 20 - tunneling oxide layer; 21 - silicon oxide frame; 22 - oxide layer; 30 - doped polysilicon layer. DETAILED DESCRIPTION

[0026] The tunneling oxide layer is a key part of solar cells with a passivated contact structure (such as TOPCon cells and IBC cells). It mainly allows electron carriers to pass through and blocks hole carriers through the tunneling effect. Among them, the thickness of the tunneling oxide layer will affect its effect. For example, if the tunneling oxide layer is too thick, it will hinder the tunneling of electron carriers, while if it is too thin, it will cause leakage. Therefore, it is generally necessary to control the tunneling oxide layer within a certain thickness range. For the current process of directly depositing the tunneling oxide layer on the battery substrate using chemical deposition methods (such as plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, etc.), especially for large-sized battery substrates, due to the influence of the gas outlet arrangement in the chemical deposition reaction chamber, oxygen diffusion and the surface state of the battery substrate, the thickness uniformity of the deposited tunneling oxide layer will be poor, that is, the thickness of the tunneling oxide layer deposited in some areas is just in the thickness range suitable for achieving the tunneling effect, while some areas are too thin or too thick, which will lead to poor carrier transport capacity of the prepared solar cell. In addition, even if the thickness of each area of the battery substrate is controlled to be within a suitable thickness range for achieving the tunneling effect, the uneven thickness and density differences at each location will also cause different tunneling effects at each location, which will have an adverse effect on the overall carrier transport capacity of the solar cell. Moreover, the uneven thickness of the deposited tunneling oxide layer will also lead to uneven thickness of other functional layers (such as doped polysilicon layer, passivation anti-reflection layer, etc.) formed based on the tunneling oxide layer, or uneven doping of the doped polysilicon layer, which will also have a cumulative adverse effect on the passivation and contact performance of the solar cell. In addition, the existing process of directly depositing the tunneling oxide layer on the battery substrate using chemical deposition will also cause process deviations between the tunneling oxide layers of different solar cells produced on the same production line. This process deviation will cause differences in tunneling effects and carrier transport capabilities between different solar cells. This difference will lead to low photoelectric conversion rates of photovoltaic modules assembled from solar cells produced by the same production process.

[0027] To address the aforementioned issues in the prior art, embodiments of the present invention provide a method for fabricating a solar cell and a solar cell. Specifically, the method primarily improves the tunneling oxide layer fabrication process, particularly for large-scale solar cells. Based on the improved tunneling oxide layer, the doped polysilicon layer and passivation anti-reflection layer can also be improved while maintaining the subsequent processes.

[0028] It is worth noting that the method for preparing a tunneling oxide layer provided in the embodiment of the present invention is not only applicable to solar cells, but the technical solution provided in the embodiment of the present invention is also applicable to preparing a uniform tunneling oxide layer for any other electronic device or semiconductor device.

[0029] Specifically, Figure 1The main flow chart of the method for preparing a solar cell provided by an embodiment of the present invention is shown. Figure 1 As shown, the method for preparing the solar cell may include the following steps:

[0030] Step S101: preparing a silicon oxide frame 21 with a mesh structure on the main surface of the battery substrate 10 by laser processing.

[0031] In the embodiment of the present invention, the battery substrate 10 may be a single crystal silicon wafer (such as an N-type single crystal silicon wafer or a P-type single crystal silicon wafer), or the battery substrate 10 may be a structure composed of a single crystal silicon wafer and other functional layers. Figure 4 and Figure 5 As shown, the battery substrate 10 is a structure composed of a single crystal silicon wafer 11 and an emitter 12 stacked on one main surface of the single crystal silicon wafer 11. It can be understood that the emitter 12 can be formed by diffusion of doping elements. In addition, the battery substrate 10 can also include more functional layers (such as the passivation layer 30 stacked on the emitter 12 can also be part of the battery substrate 10). In other words, the battery substrate 10 is a general term for the single crystal silicon wafer and the functional layers already present on the single crystal silicon wafer before the silicon oxide frame 21 is prepared. Among them, the single crystal silicon wafer can be an N-type single crystal silicon wafer or a P-type single crystal silicon wafer. The thickness of the single crystal silicon wafer is generally 100μm to 500μm. Illustratively, the thickness of the single crystal silicon wafer may be 100μm, 120μm, 150μm, 180μm, 200μm, 220μm, 250μm, 280μm, 300μm, 350μm, 380μm, 400μm, 420μm, 450μm, 480μm or 500μm, etc.

[0032] Specifically, for step S101, the main surface of the battery substrate 10 is processed with a laser having a laser power of 1W to 5W according to the pattern of the mesh structure. For example, the laser power can be 1W, 2W, 3W, 4W or 5W. The laser processing can be carried out in an atmospheric environment or a pure oxygen environment. The mesh structure can be Figure 2 The grid of square structure shown can also be Figure 3The laser beam is formed by a grid of any shape such as a rhombus and an edge triangle as shown. In addition, the grid structure can be formed by a grid of any shape such as a circular grid and a hexagonal grid. The grid shape in the grid structure is not limited here. By controlling the laser power, the damage of the laser to the battery matrix 10 can be controlled to a minimum, and a uniform and dense grid structure of silicon oxide can be formed on the surface of the battery matrix 10. That is, by controlling the laser power, the silicon atoms on the main surface of the battery matrix 10 can be excited according to the pattern of the grid structure, so that the excited silicon atoms react with oxygen in the air or pure oxygen environment to form a silicon oxide frame 21 with a grid structure, and the density, pinhole density and uniformity of the silicon oxide on the silicon oxide frame 21 can be effectively controlled, so that the density and pinhole density of the silicon oxide on the silicon oxide frame 21 can meet the carrier tunneling requirements while achieving a relatively good passivation effect.

[0033] There are two specific implementations for laser processing the main surface of the battery substrate 10 according to the above-mentioned mesh structure pattern. One is that the pattern of the pattern-shaped laser irradiated onto the main surface of the battery substrate 10 is a mesh structure pattern. The other is that according to the grid lines included in the pattern, the linear laser irradiates linear silicon oxide corresponding to the grid lines on the main surface of the battery substrate 10, and each linear silicon oxide constitutes a mesh structure silicon oxide frame 21. With respect to the grid lines included in the pattern, the linear laser irradiates linear silicon oxide corresponding to the grid lines on the main surface of the battery substrate 10 one by one. The grid lines include a plurality of first grid lines along a first direction and a plurality of second grid lines along a second direction, and the first grid lines and the second grid lines intersect; wherein the first direction can be parallel to a side edge of the battery substrate 10, or can be at an angle of 40° to 50° with the side edge of the battery substrate 10. For example, the angle between the first direction and the side edge of the battery substrate 10 is 40°, 45°, or 50°, etc. Preferably, the angle between the first direction and one side edge of the battery matrix 10 is 45°. The first direction and the second direction may intersect at any angle. Preferably, the first direction and the second direction are perpendicular to each other.

[0034] Step S102 : depositing an oxide layer 22 on the main surface of the silicon oxide frame 21 having a mesh structure of the battery substrate 10 by chemical deposition, wherein the oxide layer 22 fills the inner area of the silicon oxide frame 21 , so that the silicon oxide frame 21 and the oxide layer 22 constitute a tunneling oxide layer 20 .

[0035] The structural changes corresponding to step S101 and step S102 are as follows: Figure 2 and Figure 3 shown. Figure 2 and Figure 3 The formation of network structures with different grid shapes and the formation of the oxide layer 22 based on the network structures are respectively exemplified.

[0036] The oxide layer 22 may be silicon oxide, or other oxides capable of achieving a tunneling effect, such as nitrogen-doped silicon oxide (SiON).

[0037] The chemical deposition process used in step S102 can be directly selected from commonly used processes for existing solar cells, such as plasma enhanced chemical deposition, low temperature chemical deposition, atomic chemical deposition, etc.

[0038] A specific embodiment of step S102 may include placing the battery substrate 10 having the silicon oxide frame 21 with a mesh structure in a low-pressure chemical deposition device, and depositing the oxide layer 22 at 550° C. to 650° C. through an O2 atmosphere with a flow rate of 500 sccm to 3000 sccm. For example, the O2 flow rate may be 500 sccm, 800 sccm, 900 sccm, 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm, 2000 sccm, 2200 sccm, 2500 sccm, 2800 sccm, or 3000 sccm. By controlling the O2 flow rate, sufficient O2 atmosphere can be provided for depositing the oxide layer 22, and O2 waste can be minimized. For example, the deposition temperature required to deposit the oxide layer 22 may be 550°C, 570°C, 580°C, 590°C, 600°C, 610°C, 620°C, 630°C, 640°C, or 650°C. By controlling the deposition temperature, the silicon atoms on the surface of the silicon substrate between the reticular structures can be effectively activated to ensure that the oxide layer 22 is formed between the reticular structures. In addition, controlling the temperature within the range of 550°C to 650°C can ensure the stability of the oxide formed by the silicon oxide framework 21 of the reticular structure and avoid secondary reactions of the silicon oxide framework 21, so that the processing of step S102 is concentrated within the grids between the reticular structures.

[0039] Furthermore, the step S102 further includes: switching the O2 atmosphere to SiH4 with a flow rate of 1000 sccm to 5000 sccm, and forming an intrinsic polysilicon layer on the tunnel oxide layer 20 by low-pressure chemical deposition at 550° C. to 650° C. Illustratively, the flow rate of SiH4 can be 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm, 2000 sccm, 2200 sccm, 2500 sccm, 2800 sccm, 3000 sccm, 3300 sccm, 3500 sccm, 3800 sccm, 4000 sccm, 4200 sccm, 4400 sccm, 4500 sccm, 4800 sccm, or 5000 sccm. The temperature used to prepare the intrinsic polysilicon layer can be 550°C, 570°C, 580°C, 590°C, 600°C, 610°C, 620°C, 630°C, 640°C, or 650°C, etc. This ensures that the intrinsic polysilicon layer is formed on the basis of the tunneling oxide layer. By controlling the flow rate of SiH4, the formed intrinsic polysilicon layer can be made into a hydrogen-rich intrinsic polysilicon layer, and the thickness of the formed intrinsic polysilicon layer can be effectively controlled. In addition, on the basis of forming a uniform tunneling oxide layer, the flow rate of SiH4 can be coordinated to ensure the uniformity of the formation of the hydrogen-rich intrinsic polysilicon layer.

[0040] In addition, the thickness of the intrinsic polysilicon layer prepared in this step may be 100 nm to 500 nm. For example, the thickness of the intrinsic polysilicon layer may be 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 240 nm, 250 nm, 270 nm, 290 nm, 300 nm, 320 nm, 350 nm, 370 nm, 400 nm, 430 nm, 450 nm, 480 nm, or 500 nm. By controlling the thickness of the intrinsic polysilicon layer, the uniformity and consistency of the doped polysilicon layer subsequently formed based on the intrinsic polysilicon layer can be ensured.

[0041] In particular, when the oxide layer 22 is silicon oxide, only an O2 atmosphere may be provided during the deposition process. Some silicon atoms in the silicon oxide originate from the surface of the battery substrate 10, thereby ensuring the reliability of the bonding between the oxide layer 22 and the surface of the battery substrate 10. When the oxide layer 22 is an oxide other than silicon oxide, in addition to providing an O2 atmosphere, a gas source required for the other oxide may also be provided during the deposition process. The flow rate of the gas source may be regulated based on the flow rate of the O2 atmosphere.

[0042] With respect to the technical solution provided in the above embodiment, a mesh-structured silicon oxide frame 21 is first prepared on the main surface of the battery substrate 10 by laser processing, so that a uniformly distributed silicon oxide frame 21 exists in each area of the main surface of the battery substrate 10, which provides a basis for constructing a uniform tunneling oxide layer 20. In the subsequent chemical deposition process, the uniformly distributed silicon oxide frame 21 can, on the one hand, confine oxygen atoms within the silicon oxide frame 21, and oxygen contacts the main surface of the battery substrate 10 to form a part of the oxide layer 22, and the oxide layer 22 is deposited and grown along the silicon oxide frame 21, which is in contact with the silicon oxide frame. The frame 21 is formed as a whole, which can effectively reduce the impact of surface differences of the battery substrate 10 on the deposition of the oxide layer 22. On the other hand, the evenly distributed silicon oxide frame 21 provides a relatively balanced environment for contact with oxygen atoms for the main surface of the exposed battery substrate 10. Regardless of whether it is a high-concentration oxygen atom or a low-concentration oxygen atom, the number of oxygen atoms that can enter the narrow area at the same time is limited, so that the oxygen atoms deposited in each small area within the silicon oxide frame 21 are relatively balanced, and there will not be a large difference in deposition thickness due to high-concentration oxygen atoms and low-concentration oxygen atoms, thereby ensuring the uniformity of the tunnel oxide layer 20 formed. Furthermore, since the number of oxygen atoms that enter the narrow area at the same time is limited, most of the oxygen atoms have sufficient time to redistribute, thereby improving the uniformity of the oxygen atom concentration distribution, which helps to further improve the uniformity of the formed tunnel oxide layer 20.

[0043] In addition, since the oxide in the silicon oxide frame 21 is a relatively stable structure, after the oxygen atoms come into contact with it, the oxygen atoms are still in a free state. They will either react with the battery substrate 10 adjacent to the silicon oxide frame 21 or be redistributed. Therefore, during the chemical deposition process, the oxygen atoms will not affect the silicon oxide frame 21, and the silicon oxide frame 21 can redistribute the oxygen atoms in a small range, which helps to further improve the uniformity of the tunneling oxide layer 20.

[0044] In addition to the above-mentioned reaction condition control, factors affecting the uniformity of the tunneling oxide layer 20 include the state of the main surface of the battery substrate 10, the parameters of the silicon oxide frame 21 (such as the thickness of the silicon oxide frame 31, the size of each grid enclosed by the silicon oxide frame 21, the grid line spacing, etc.) and the thickness of the oxide layer 22.

[0045] Specifically, the main surface of the battery substrate 10 is generally a polished surface with a tower base of 3μm to 50μm. For example, the tower base size on the polished surface can be 3μm, 5μm, 10μm, 15μm, 20μm, 25μm, 28μm, 30μm, 35μm, 40μm, 45μm, 48μm, or 50μm. Forming the tunnel oxide layer 20 on the polished surface helps further improve the uniformity of the tunnel oxide layer 20. In addition, the polished surface is only a preferred structure, and the main surface of the battery substrate 10 can also be a velvet structure. The preparation method provided in the embodiment of the present invention is for the velvet structure. Compared with directly depositing the tunneling oxide layer on the large-sized velvet structure, the technical solution provided in the embodiment of the present invention divides the main surface of the battery substrate 10 into small grids through a mesh structure. The small grids can be regarded as independent structures, which can reduce the difference between the depressions and protrusions of the velvet structure, so that the thickness and density of the tunneling oxide layer 20 formed in the depressions and protrusions of the velvet structure are basically consistent.

[0046] In addition, the thickness of the silicon oxide frame 21 prepared in step S101 above may be 1.3 nm to 2 nm. For example, the thickness of the silicon oxide frame 21 may be 1.3 nm, 1.5 nm, 1.8 nm, or 2 nm. By controlling the thickness of the silicon oxide frame 21, the silicon oxide frame 21 can play an isolation effect, and by coordinating with the size of the grid, the oxygen atoms entering each grid can be basically consistent, so that the oxide layer 22 formed by each grid can be basically consistent. In addition, controlling the thickness can also ensure the tunneling effect and passivation effect of the silicon oxide frame 21.

[0047] Furthermore, the size of each grid included in the mesh structure can be 0.01mm 2 ~9mm 2 For example, the size of each grid included in the mesh structure may be 0.01mm 2 , 0.05mm 2 , 0.08mm 2 , 0.1mm 2 , 0.5mm 2 , 1mm 2 , 1.5mm 2 , 2mm 2 , 2.5mm 2 , 2.8mm 2 , 3mm 2 , 4mm 2 , 5mm 2 , 6mm 2 , 7mm 2 , 8mm 2 or 9mm 2By controlling the size of each grid, the oxygen atoms entering each grid can be kept substantially consistent, so that the oxide layers 22 formed by each grid can be kept substantially consistent.

[0048] In particular, in the mesh-structured silicon oxide frame 21 formed in step S101 above, the mesh size of the silicon oxide frame 21 provided on the third region of the main surface of the battery substrate 10 is generally smaller than the mesh size of the silicon oxide frame 21 included in the fourth region of the main surface of the battery substrate 10. Preferably, the third region of the main surface of the battery substrate 10 is generally the edge region of the main surface of the battery substrate 10, and the fourth region of the main surface of the battery substrate 10 is generally the other region of the main surface of the battery substrate 10 excluding the edge region.

[0049] Generally speaking, during the deposition process of the oxide layer 22 by a deposition device, uneven deposition occurs, resulting in relatively thin deposition thickness in all or part of the edge regions. Therefore, the third region of the main surface of the battery substrate 10 can be determined based on the deposition thickness at different locations during the deposition process of the actual deposition device. The region with relatively thin deposited oxide layer 22 is defined as the third region of the main surface of the battery substrate 10. Providing a grid with a relatively small grid size in the third region of the main surface of the battery substrate 10 helps to increase the thickness of the oxide layer 22 deposited in the third region of the main surface of the battery substrate 10, thereby improving the overall thickness uniformity of the tunneling oxide layer 20 and further enhancing the tunneling effect at various locations of the tunneling oxide layer 20.

[0050] On this basis, the tunneling oxide layer 20 generally includes: a first region of the tunneling oxide layer 20 corresponding to the third region of the main surface of the battery substrate 10, and a second region of the tunneling oxide layer 20 corresponding to the fourth region of the main surface of the battery substrate 10, wherein the mesh size of the silicon oxide frame 21 included in the first region of the tunneling oxide layer 20 is smaller than the mesh size of the silicon oxide frame 21 included in the second region of the tunneling oxide layer 20, so as to improve the overall uniformity of the tunneling oxide layer 20 and the consistency of the tunneling effect, thereby improving the efficiency of the solar cell.

[0051] Furthermore, for a structure in which the mesh structure is formed by a plurality of grid lines, the spacing between adjacent grid lines in the mesh structure is 0.1 mm to 5 mm. For example, the spacing between adjacent grid lines may be 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm or 5 mm, etc. Preferably, the spacing between adjacent grid lines in the mesh structure is 0.1 mm to 3 mm. By controlling the spacing between adjacent grid lines in the mesh structure, it is possible to ensure that the grid lines control the amount of oxygen atoms entering the grid from all directions, which helps to further improve the uniformity and density of the tunnel oxide layer 20 formed. It is worth noting that the spacing between adjacent grid lines generally refers to the spacing between adjacent grid lines that are oriented in the same direction (such as both oriented in the first direction or the second direction).

[0052] In addition, the laser-processed area accounts for 10% to 40% of the area of one main surface of the battery substrate 10. For example, the laser-processed area may account for 10%, 14%, 15%, 18%, 20%, 25%, 30%, 35% or 40% of the area of one main surface of the battery substrate 10.

[0053] Furthermore, the thickness of the oxide layer 22 may be 1.3 nm to 2 nm. For example, the thickness of the oxide layer 22 may be 1.3 nm, 1.5 nm, 1.8 nm, or 2 nm, etc., so that the thickness of the oxide layer 22 is consistent with the thickness of the silicon oxide frame 21, further improving the uniformity of the tunnel oxide layer 20.

[0054] Furthermore, the pinhole density of the tunnel oxide layer 20 formed by the silicon oxide frame 21 and the oxide layer 22 is 5E6 / cm 2 ~5E18 pieces / cm 2 (where aEb represents a×10 b For example, the pinhole density of the tunnel oxide layer 20 may be 5E6 / cm 2 , 5E7 pieces / cm 2 , 5E8 pieces / cm 2 , 5E9 pieces / cm 2 、6E10 / cm 2 , 8E12 pieces / cm 2 、8E13 pieces / cm 2 , 9E14 pieces / cm 2 , 9E15 pieces / cm 2 、6E16 pieces / cm 2 , 7E17 pieces / cm 2 , 1E18 pieces / cm 2 、3E18 pieces / cm 2 or 5E18 pieces / cm2 The above preparation method can make the pinhole density of the tunnel oxide layer 20 5E6 / cm 2 ~5E18 pieces / cm 2 , to ensure the tunneling effect and passivation effect of the tunnel oxide layer 20.

[0055] The pinhole density of the tunneling oxide layer 20 is determined by measuring the pinhole density in multiple regions of the tunneling oxide layer 20 and calculating an average of the pinhole densities based on the measured pinhole densities in the multiple regions, which is the pinhole density of the tunneling oxide layer 20. The region for measuring the pinhole density is randomly selected and generally covers a portion of the silicon oxide frame 21.

[0056] Furthermore, after forming the intrinsic polysilicon layer in the above step S102, the process further includes: diffusing doping elements in the intrinsic polysilicon layer at 700°C to 1100°C to form a doped polysilicon layer 30. Exemplarily, the doping temperature may be 700°C, 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C, 1050°C, or 1100°C. Based on the uniform tunneling oxide layer 20 and the uniform intrinsic polysilicon layer formed above, the uniformity of the formed doped polysilicon layer 30 can be ensured, and the consistency of the photoelectric conversion efficiency and carrier transport capability at each position of the solar cell can be ensured, thereby further improving the overall photoelectric conversion efficiency and carrier transport capability of the prepared solar cell.

[0057] In addition, during the process of diffusing the doping elements into the intrinsic polysilicon layer, in addition to forming the doped polysilicon layer 30, a doped element silicon glass layer is also formed on the surface of the doped polysilicon layer 30. For example, if the doping element is a P-type doping element, the doped element silicon glass layer is a borosilicate glass layer; if the doping element is an N-type doping element, the doped element silicon glass layer is a phosphosilicate glass layer. Both the borosilicate glass layer and the phosphosilicate glass layer can be removed by treating with a 5% to 30% HF solution to obtain the doped polysilicon layer 30. For example, the mass concentration of HF in the HF solution can be 5%, 8%, 10%, 12%, 15%, 20%, 22%, 25%, 28%, or 30%, etc.

[0058] The concentration of the doping element in the doped polysilicon layer 30 may be 3E20 atmos / cm 3 ~9E20atmos / cm 3 (xEyatmos / cm 3 It means that each unit volume contains x×10 y For example, the concentration of the doping element in the doped polysilicon layer 30 may be 3E20 atmos / cm 3、5E20atmos / cm 3 、6E20atmos / cm 3 、7E20atmos / cm 3 or 9E20atmos / cm 3 wait.

[0059] It is understandable that the doping element in the emitter 12 included in the battery substrate 10 is of opposite type to the doping element in the doped polysilicon layer 30. For example, the single crystal silicon wafer 11 is N-type single crystal silicon, the doping element in the emitter 12 is a P-type doping element (such as boron), and the doping element in the doped polysilicon layer 30 is an N-type doping element (such as phosphorus); or the single crystal silicon wafer 11 is P-type single crystal silicon, the doping element in the emitter 12 is an N-type doping element (such as phosphorus), and the doping element in the doped polysilicon layer 30 is a P-type doping element (such as boron).

[0060] In addition, the above preparation method may also include more preparation steps of the functional layer such as Figure 5 Taking the TOPCon structure shown (the tunneling oxide layer 20 and the doped polysilicon layer 30 are located on the back of the solar cell) as an example, the preparation method may also include the preparation process of the front passivation layer 40, the preparation process of the front passivation anti-reflection layer 50 and the back passivation anti-reflection layer 60, and the preparation process of the front metal electrode 70 and the back metal electrode 80.

[0061] It is worth noting that the technical solution provided by the embodiments of the present invention can also be applied to solar cell structures in which tunnel oxide layers are formed on both sides. For structures in which tunnel oxide layers are formed on both sides, steps S101 and S102 provided in the above technical solution can be performed after the tunnel oxide layer is formed on one main surface, and then steps S101 and S102 can be performed again to form a tunnel oxide layer on the other main surface.

[0062] Furthermore, an embodiment of the present invention also provides a solar cell. Specifically, Figures 2 to 5 As shown, the solar cell may include: a cell substrate 10 and a tunneling oxide layer 20 arranged on the main surface of the cell substrate 10; the tunneling oxide layer 20 includes: a silicon oxide frame 21 with a mesh structure, and an oxide layer 22 filled in the silicon oxide frame 21.

[0063] The battery substrate 10 may be a single crystal silicon wafer (such as an N-type single crystal silicon wafer or a P-type single crystal silicon wafer), and the battery substrate 10 is a structure composed of a single crystal silicon wafer and other functional layers. For example, Figure 4 and Figure 5 As shown, the battery substrate 10 is a structure composed of a single crystal silicon wafer 11 and an emitter 12 stacked on one main surface of the single crystal silicon wafer 11.

[0064] Further, if Figure 5 As shown, the above-mentioned solar cell may also include: a doped polysilicon layer 30 stacked on the tunneling oxide layer 20, a back passivation anti-reflection layer 60 stacked on the doped polysilicon layer 30; a passivation layer 40 stacked on the emitter 12; a front passivation anti-reflection layer 50 stacked on the passivation layer, a back metal electrode 80 electrically connected to the doped polysilicon layer 30, and a front metal electrode 70 electrically connected to the emitter 12.

[0065] The oxide layer 22 and silicon oxide frame 21 provided by the above-mentioned solar cell constitute the tunneling oxide layer 20 of the solar cell, which can effectively improve the uniformity and density of the tunneling oxide layer 20, thereby helping to improve the tunneling effect and passivation effect of the tunneling oxide layer 20, thereby improving the photoelectric conversion efficiency and carrier transport capability of the solar cell.

[0066] Preferably, the oxide layer 22 is a silicon oxide layer. The oxide layer 22 may also be other oxides capable of achieving a tunneling effect, such as nitrogen-doped silicon oxide (SiON).

[0067] The tunneling oxide layer 20 is generally disposed on the back side or both sides (i.e., the front and back sides) of the battery substrate 10. In the case where the tunneling oxide layer 20 is generally disposed on the back side of the battery substrate 10, the conductive type of the doping element of the doped polysilicon 20 stacked on the outside of the tunneling oxide layer 20 on the back side of the battery substrate 10 is the same as that of the battery substrate 10.

[0068] The mesh-structured silicon oxide frame 21 has a thickness of 1.3 nm to 2 nm. For example, the thickness of the silicon oxide frame 21 can be 1.3 nm, 1.5 nm, 1.8 nm, or 2 nm. Controlling the thickness of the silicon oxide frame 21 allows it to function as an isolation layer. This, combined with the size of the mesh, ensures that the oxygen atoms entering each mesh remain substantially consistent, thereby ensuring that the oxide layer 22 formed by each mesh remains substantially consistent. Furthermore, controlling this thickness can ensure the tunneling effect and passivation effects of the silicon oxide frame 21.

[0069] The silicon oxide frame 21 of the mesh structure may include a plurality of first grid lines arranged along a first direction and a plurality of second grid lines arranged along a second direction, wherein the first grid lines and the second grid lines intersect with each other. It can be understood that the first grid lines and the second grid lines contain silicon oxide.

[0070] Preferably, the first direction is parallel to a side edge of the battery substrate 10; or, the first direction forms an angle of 40° to 50° with a side edge of the battery substrate 10. For example, the angle between the first direction and a side edge of the battery substrate 10 is 40°, 45°, or 50°. Preferably, the angle between the first direction and a side edge of the battery substrate 10 is 45°.

[0071] The intersecting first direction and the second direction may intersect at any angle. Preferably, the first direction and the second direction are perpendicular to each other.

[0072] In another embodiment of the present invention, the spacing between adjacent first grid lines is 0.1 mm to 5 mm, and the spacing between adjacent second grid lines is 0.1 mm to 5 mm; illustratively, the spacing between adjacent first grid lines or the spacing between adjacent second grid lines may be 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm or 5 mm, etc. Preferably, the spacing between adjacent first grid lines or the spacing between adjacent second grid lines is 0.1 mm to 3 mm. By controlling the spacing between adjacent grid lines in the mesh structure, it is possible to ensure that the grid lines control the amount of oxygen atoms entering the grid from all directions, which helps to further improve the uniformity and density of the formed tunnel oxide layer 20.

[0073] The size of each grid in the mesh structure is 0.01mm 2 ~9mm 2 For example, the size of each grid included in the mesh structure may be 0.01mm 2 , 0.05mm 2 , 0.08mm 2 , 0.1mm 2 , 0.5mm 2 , 1mm 2 , 1.5mm 2 , 2mm 2 , 2.5mm 2 , 2.8mm 2 , 3mm 2 , 4mm 2 , 5mm 2 , 6mm 2 , 7mm 2 , 8mm 2 or 9mm 2 By controlling the size of each grid, the oxygen atoms entering each grid can be kept substantially consistent, so that the oxide layers 22 formed by each grid can be kept substantially consistent.

[0074] In addition, the tunneling oxide layer 20 provided in the embodiment of the present invention includes a first region and a second region. The mesh size of the mesh structure included in the first region is smaller than the mesh size of the mesh structure included in the second region. Preferably, the first region is located at the edge region of the tunneling oxide layer 20. This further improves the overall uniformity of the tunneling oxide layer 20 and the consistency of the tunneling effect, thereby improving the efficiency of the solar cell.

[0075] Furthermore, the thickness of the oxide layer 22 is 1.3 nm to 2 nm. For example, the thickness of the oxide layer 22 can be 1.3 nm, 1.5 nm, 1.8 nm, or 2 nm, etc., so that the thickness of the oxide layer 22 is consistent with the thickness of the silicon oxide frame 21, further improving the uniformity of the tunnel oxide layer 20.

[0076] In addition, the pinhole density of the tunnel oxide layer 20 is 5E6 / cm 2 ~5E18 pieces / cm 2 For example, the pinhole density of the tunnel oxide layer 20 may be 5E6 pinholes / cm 2 , 5E7 pieces / cm 2 , 5E8 pieces / cm 2 , 5E9 pieces / cm 2 、6E10 / cm 2 , 8E12 pieces / cm 2 、8E13 pieces / cm 2 , 9E14 pieces / cm 2 , 9E15 pieces / cm 2 、6E16 pieces / cm 2 , 7E17 pieces / cm 2 , 1E18 pieces / cm 2 、3E18 pieces / cm 2 or 5E18 pieces / cm 2 By controlling the pinhole density of the tunnel oxide layer 20 to 5E6 / cm 2 ~5E18 pieces / cm 2 , to ensure the tunneling effect and passivation effect of the tunneling oxide layer 20. The pinhole density of the tunneling oxide layer 20 is determined by measuring the pinhole density in multiple regions of the tunneling oxide layer 20 and calculating the average pinhole density based on the pinhole densities measured in the multiple regions, which is the pinhole density of the tunneling oxide layer 20. The region for measuring the pinhole density is randomly selected and generally covers a portion of the silicon oxide frame 21.

[0077] Furthermore, for the tunneling oxide layer 20, the density of the silicon oxide frame 21 included therein is higher than the density of the oxide layer 22. Preferably, the pinhole density of the silicon oxide frame 21 is lower than the pinhole density of the oxide layer 22. By matching the pinhole density of the silicon oxide frame 21 with the pinhole density of the oxide layer 22, the pinhole density of the tunneling oxide layer 20 can be better controlled to 5E6 pinholes / cm 2 ~5E18 pieces / cm 2 within the range.

[0078] Furthermore, the solar cell further includes a doped polysilicon layer 30 disposed on the tunneling oxide layer 20 .

[0079] Among them, the thickness of the doped polysilicon layer 30 is 100nm to 500nm; illustratively, the thickness of the intrinsic polysilicon layer may be 100nm, 120nm, 150nm, 180nm, 200nm, 240nm, 250nm, 270nm, 290nm, 300nm, 320nm, 350nm, 370nm, 400nm, 430nm, 450nm, 480nm or 500nm, etc. By controlling the thickness of the intrinsic polysilicon layer, the uniformity and consistency of the doped polysilicon layer subsequently formed based on the intrinsic polysilicon layer can be guaranteed.

[0080] Furthermore, the doping concentration of the doping element in the doped polysilicon layer 30 is 3E20 atoms / cm 3 ~9E20atoms / cm 3 ; For example, the concentration of the doping element in the doped polysilicon layer 30 may be 3E20atmos / cm 3 、5E20atmos / cm 3 、6E20atmos / cm 3 、7E20atmos / cm 3 or 9E20atmos / cm 3 wait.

[0081] The following describes in detail the technical solutions and beneficial effects provided by the embodiments of the present invention using an embodiment and a comparative example.

[0082] Example:

[0083] Step A1: Perform texturing and polishing on an N-type silicon wafer having a resistivity of 1 Ωcm and a thickness of 140 μm to form a polished surface.

[0084] Step B1: Place the dried silicon wafer on the laser machine table and use a 1W laser beam to perform patterning on the surface of the silicon wafer to prepare a silicon oxide frame with a mesh structure on the main surface of the silicon wafer.

[0085] Step C1: Place the laser-treated silicon wafer in an LPCVD device, heat it to 600°C, and introduce 1000 sccm of oxygen. The oxygen is enriched and grown on the silicon oxide frame to form SiO2 with a thickness of about 1.5 nm, forming a tunneling oxide layer.

[0086] Step D1: Replace the oxygen atmosphere with SiH 4 at a flow rate of 3000 sccm, and deposit a polysilicon layer on the tunnel oxide layer.

[0087] Step E1: Place the silicon wafer in a high-temperature tubular diffusion furnace to undergo phosphorus diffusion to convert the doped polysilicon into doped polysilicon (i.e., N +Poly-Si), and the phosphorus source is deposited and advanced at 900°C.

[0088] Step F1: At 250° C., trimethylaluminum and water vapor are introduced to grow a 5 nm thick Al 2 O 3 layer.

[0089] Step G1: In a plasma enhanced chemical vapor deposition apparatus, silane and ammonia are introduced at 540°C to complete a SiN deposition process with a thickness of 85 nm. x Thin film deposition to obtain efficient double-sided N + -Poly Si / SiO2 passivation contact structure.

[0090] Comparative Example:

[0091] The difference between this comparative example and the embodiment is that there is no step B1. After step A1, step C1 is directly performed, that is, the silicon wafer is directly placed in a low-temperature plasma device to grow a tunneling oxide layer under an oxygen atmosphere. The subsequent steps are the same as the above steps D1 to G1.

[0092] It is worth noting that the process of preparing the tunneling oxide layer in the comparative example and the process of performing step C1 in the embodiment are performed in the same low-temperature plasma equipment, using the same deposition parameters. Moreover, the process of preparing the polysilicon layer, N-type doped polysilicon layer, aluminum oxide passivation layer, and silicon nitride passivation anti-reflective layer in the comparative example are also respectively performed in the same equipment as the above-mentioned steps D1 to G1, using the same parameters. In addition, both the embodiment and the comparative example prepare the tunneling oxide layer and the doped polysilicon layer on both sides of the silicon wafer. By preparing the tunneling oxide layer and the doped polysilicon layer on both sides, a double-sided symmetrical structure is ensured, so that the influence of other functional layers on the test results can be eliminated in the subsequent testing process, so that the test results can more intuitively reflect the performance of the tunneling oxide layer and the doped polysilicon layer. Furthermore, in order to meet the testing requirements and improve the accuracy of the test results, multiple products are produced based on the solutions provided in the embodiment and the comparative example, and the multiple products produced are tested separately.

[0093] The four products 1-1, 1-2, 1-3, and 1-4 produced in the examples, and the four products 2-1, 2-2, 2-3, and 2-4 produced in the comparative examples were subjected to multiple photoluminescence (PL) tests, sheet resistance tests, open circuit voltage, minority carrier lifetime, and composite current density tests. These tests were all completed using existing testing methods. For example, the photoluminescence (PL) test was completed using an existing photoluminescence detector; the sheet resistance test was completed using a four-probe probe tester; the open circuit voltage was measured under standard test conditions using a light source of a specific light intensity and a multimeter under no load; the minority carrier lifetime test was mainly performed using a WCT120 lifetime minority carrier lifetime tester, and the composite current density test was mainly performed using IV detection equipment.

[0094] For the photoluminescence (PL) test, the grayscale images of the four products 1 and the grayscale images of the four products 2 are as follows: Figure 6 The grayscale mean of the same product tested (the grayscale mean of the same product (such as product 1-1) refers to the average value obtained by multiple tests on the same product, mean Value), grayscale mean of the same type of products (such as products 1-1, 1-2, 1-3 and 1-4 are the same type of products) (the grayscale mean of the same type of products refers to the average value of the same grayscale of the same type of products (such as products 1-1, 1-2, 1-3 and 1-4), which can be the average value of the grayscale mean or the average value of the grayscale maximum value; for example, the average value of the grayscale mean of the same type of products produced in the embodiment refers to the average value of the grayscale mean of the same type of products produced in the embodiment calculated by using the grayscale mean of products 1-1, 1-2, 1-3 and 1-4; the average value of the grayscale maximum value refers to the average value calculated for the grayscale maximum value of the same type of products, for example, the average value of the grayscale maximum value of the same type of products produced in the embodiment refers to the average value of the grayscale maximum value of the same type of products produced in the embodiment calculated by using the grayscale maximum values of products 1-1, 1-2, 1-3 and 1-4), grayscale maximum value (the grayscale maximum value refers to the maximum value in multiple tests on the same product (such as product 1-1), max Value), the standard deviation of the grayscale maximum value (the standard deviation of the grayscale maximum value is calculated by using the grayscale maximum values corresponding to multiple products of the same type of product and the average value of the grayscale maximum values corresponding to multiple products of the same type of product), and the standard deviation of the average value (the standard deviation of the grayscale mean is calculated by using the grayscale mean values corresponding to multiple products of the same type of product and the average value of the grayscale mean values corresponding to multiple products of the same type of product). Specifically, the standard deviation of the grayscale maximum value is calculated using the following calculation formula (1), and the standard deviation of the grayscale mean is calculated using the following calculation formula (2).

[0095]

[0096] Among them, STD max Indicates the standard deviation of the maximum grayscale values of multiple products of the same type; G max-i Indicates the maximum grayscale value of the i-th product of the same type; Indicates the average value of the grayscale maximum values of multiple products of the same type N represents the total number of products of the same type; STD mean Indicates the standard deviation of the grayscale mean of multiple products of the same type; G mean-i Represents the grayscale mean of the i-th product of the same type; Indicates the average grayscale mean of multiple products of the same type

[0097] Among them, the grayscale related parameters of products 1-1, 1-2, 1-3 and 1-4 corresponding to the embodiments and products 2-1, 2-2, 2-3 and 2-4 produced in the comparative examples are shown in Table 1 below.

[0098] Table 1

[0099]

[0100] Generally speaking, the larger the grayscale value, the brighter the image captured by the PL test, and the better the passivation effect. Figure 6 The PL images of the four products 1-1, 1-2, 1-3, and 1-4 produced in the embodiment and the PL images of the four products 2-1, 2-2, 2-3, and 2-4 produced in the comparative example show that the brightness of the PL images of the four products 1-1, 1-2, 1-3, and 1-4 produced in the embodiment is higher than the brightness of the PL images of the four products 2-1, 2-2, 2-3, and 2-4 produced in the comparative example. Comparing the data in Table 1, it can be seen that the grayscale maximum value, grayscale mean, average of the grayscale maximum value, and average of the grayscale mean of the four products 1-1, 1-2, 1-3, and 1-4 produced in the embodiment are all higher than the grayscale maximum value, grayscale mean, average of the grayscale maximum value, and average of the grayscale mean of the four products 2-1, 2-2, 2-3, and 2-4 produced in the comparative example. Based on this, it can be seen that the products produced by the technical solutions provided by the embodiments of the present invention have better passivation effect and quality, and are more conducive to generating more photogenerated carriers. In addition, the standard deviation of the grayscale maximum value and the standard deviation of the grayscale mean in the test results of the embodiment are lower than the standard deviation of the grayscale maximum value and the standard deviation of the grayscale mean in the test results of the comparative example. It can be concluded that the products produced by the technical method provided by the embodiment of the present invention have better uniformity and higher product process stability.

[0101] Furthermore, the square resistance tests were performed on the products 1-1, 1-2, 1-3 and 1-4 produced in the examples and the products 2-1, 2-2, 2-3 and 2-4 produced in the comparative examples, respectively. The test results are as follows: Figure 7 and as shown in Table 2 below.

[0102] Table 2

[0103]

[0104] It can be seen from Table 2 above that although the minimum square resistance of the products (1-1, 1-2, 1-3 and 1-4) produced in the embodiment is greater than the minimum square resistance of the products (2-1, 2-2, 2-3 and 2-4) produced in the comparative example, the average square resistance of the products (1-1, 1-2, 1-3 and 1-4) produced in the embodiment is lower than the average square resistance of the products (2-1, 2-2, 2-3 and 2-4) produced in the comparative example, or the average square resistance of the products (1-1, 1-2, 1-3 and 1-4) produced in the embodiment is substantially the same as the average square resistance of the products (2-1, 2-2, 2-3 and 2-4) produced in the comparative example. The maximum square resistance, standard deviation (StdDeviation) and square resistance range of the products (1-1, 1-2, 1-3 and 1-4) produced by the embodiment of the present invention are much lower than the maximum square resistance, standard deviation (StdDeviation) and square resistance range of the products (2-1, 2-2, 2-3 and 2-4) produced by the comparative example, indicating that the square resistance uniformity of the products (1-1, 1-2, 1-3 and 1-4) produced by the embodiment of the present invention is significantly improved, which also indicates that the uniformity of the tunnel oxide layer and the uniformity of the doped polysilicon layer of the produced products are significantly improved. This is because the uniform tunnel oxide layer formed improves the uniformity of the polysilicon layer, diffuses the doping elements in the uniform polysilicon layer, and ensures the consistency of the diffusion degree of the doping elements diffused in the polysilicon layer.

[0105] In addition, from Figure 7 It can be clearly seen from the square resistance test chart that compared with products 2-1, 2-2, 2-3 and 2-4, the color differences in each area of products 1-1, 1-2, 1-3 and 1-4 do not change much. Combined with the square resistance standard deviation (StdDeviation) and square resistance range given in Table 2, it can be seen that products 1-1, 1-2, 1-3 and 1-4 have better square resistance uniformity, while products 2-1, 2-2 and 2-3 all have locally very dark areas, which indicates that the square resistance difference is large.

[0106] Furthermore, the open circuit voltage (Voc_(V)) comparison diagram of the product produced by the embodiment of the present invention and the product produced by the comparative example is shown in FIG. Figure 8 As shown in the figure, the minority carrier lifetime (Lifetime_(us)) comparison of the product produced by the embodiment of the present invention and the product produced by the comparative example is shown in the figure. Figure 9As shown, the composite carrier current density (J0_(fa / cm 2 ))Comparison chart as follows Figure 10 shown.

[0107] from Figure 8 It can be seen that the open circuit voltage of the product produced by the embodiment of the present invention is significantly higher than the open circuit voltage of the product produced by the comparative example, which shows that the technical solution provided by the embodiment of the present invention is conducive to improving the open circuit voltage of the solar cell, and also shows that the technical solution provided by the embodiment of the present invention is conducive to improving the photoelectric conversion efficiency of the solar cell.

[0108] from Figure 9 It can be seen that the minority carrier lifetime of the product produced by the embodiment of the present invention is significantly higher than that of the product produced by the comparative example; the longer the minority carrier lifetime, the better the passivation effect. Figure 9 The test results show that the technical solution provided by the embodiment of the present invention is beneficial to improving the passivation effect of the tunnel oxide layer of the solar cell.

[0109] from Figure 10 It can be seen that the composite carrier current density of the product produced by the embodiment of the present invention is significantly lower than the composite carrier current density of the product produced by the comparative example. The smaller the composite carrier current density, the smaller the carrier recombination. Therefore, it is shown that the technical solution provided by the embodiment of the present invention is beneficial to reducing the carrier recombination of solar cells.

[0110] Based on the above test results, it can be seen that the solar cell prepared by the technical solution provided by the embodiment of the present invention has good square resistance uniformity and reduced carrier recombination, which indirectly indicates that the uniformity and density of the laser-induced oxide layer growth are improved, resulting in better passivation performance of the tunneling oxidation passivation contact structure, which is beneficial to improving the quality of solar cells and the electrical performance of solar cells.

[0111] The above steps are merely provided to help understand the structure, method, and core concept of the present invention. It will be apparent to those skilled in the art that various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: include: Step 1: preparing a silicon oxide frame (21) with a mesh structure on the main surface of the battery substrate (10) by laser processing; Step 2: depositing an oxide layer (22) on the main surface of the silicon oxide frame (21) having the mesh structure of the battery substrate (10) by chemical deposition, wherein the oxide layer (22) fills the inner area of the silicon oxide frame (21), so that the silicon oxide frame (21) and the oxide layer (22) constitute a tunneling oxide layer (20).

2. The method for preparing a solar cell according to claim 1, wherein: Step 1 comprises: treating the main surface of the battery substrate (10) with a laser having a laser power of 1W to 5W according to a pattern of a mesh structure; and / or, The thickness of the silicon oxide frame (21) prepared in step 1 is 1.3 nm to 2 nm; and / or, The size of each grid included in the mesh structure is 0.01mm 2 ~9mm 2 ; and / or, The mesh structure is a structure formed by a plurality of mesh lines, and the spacing between adjacent mesh lines in the mesh structure is 0.1 mm to 5 mm. Preferably, the spacing between adjacent mesh lines in the mesh structure is 0.1 mm to 3 mm. and / or, The thickness of the oxide layer (22) is 1.3 nm to 2 nm; and / or, The oxide layer (22) is a silicon oxide layer.

3. The method for preparing a solar cell according to claim 1 or 2, characterized in that: The pinhole density of the tunneling oxide layer (20) is 5E6 / cm 2 ~5E18 pieces / cm 2 ; and / or, The main surface of the battery matrix (10) is a polished surface with a tower base of 3 μm to 50 μm.

4. The method for preparing a solar cell according to claim 1 or 2, characterized in that: Step 2 includes: Placing the battery substrate (10) having the silicon oxide frame (21) of the mesh structure in a low-pressure chemical deposition device, and depositing an oxide layer (22) at 550° C. to 650° C. in an O2 atmosphere with a flow rate of 500 sccm to 3000 sccm; Preferably, step 2 further includes: Switching the O2 atmosphere to SiH4 with a flow rate of 1000 sccm to 5000 sccm, and preparing an intrinsic polysilicon layer on the tunneling oxide layer (20) by low-pressure chemical deposition; Preferably, the thickness of the prepared intrinsic polysilicon layer is 100 nm to 500 nm.

5. The method for preparing a solar cell according to claim 4, wherein: The preparation method further comprises: step 3, diffusing doping elements in the intrinsic polysilicon layer at 700° C. to 1100° C. to form a doped polysilicon layer (30).

6. The method for preparing a solar cell according to claim 5, wherein: The doping element concentration in the doped polysilicon layer (30) is 3E20 atoms / cm 3 ~9E20atoms / cm 3 ; and / or, Step 3 also includes: after diffusing the doping elements, removing the doped element silicon glass layer formed on the surface to obtain a doped polysilicon layer (30).

7. A solar cell, characterized in that: include: A battery substrate (10), and a tunneling oxide layer (20) disposed on a major surface of the battery substrate (10); The tunneling oxide layer (20) comprises: a silicon oxide frame (21) with a mesh structure, and an oxide layer (22) filled in the silicon oxide frame (21).

8. The solar cell according to claim 7, characterized in that The oxide layer (22) is a silicon oxide layer; and / or, The thickness of the silicon oxide frame (21) is 1.3 nm to 2 nm, and preferably, the thickness of the oxide layer (22) is 1.3 nm to 2 nm; and / or, The density of the silicon oxide frame (21) is higher than the density of the oxide layer (22), and preferably, the pinhole density of the silicon oxide frame (21) is lower than the pinhole density of the oxide layer (22); Preferably, the pinhole density of the tunnel oxide layer (20) is 5E6 pinholes / cm 2 ~5E18 pieces / cm 2 .

9. The solar cell according to claim 7, wherein: The tunneling oxide layer (20) comprises a first region and a second region, the mesh size of the mesh structure included in the first region is smaller than the mesh size of the mesh structure included in the second region, preferably, the first region is located at an edge region of the tunneling oxide layer (20); and / or, The size of each grid included in the mesh structure is 0.01mm 2 ~9mm 2 ; and / or, The mesh structure includes a plurality of first grid lines arranged along a first direction and a plurality of second grid lines arranged along a second direction, wherein the first grid lines and the second grid lines intersect; Preferably, the spacing between adjacent first grid lines is 0.1 mm to 5 mm, and the spacing between adjacent second grid lines is 0.1 mm to 5 mm; Preferably, the spacing between adjacent first grid lines is 0.1 mm to 3 mm, and the spacing between adjacent second grid lines is 0.1 mm to 3 mm; Preferably, the first direction and the second direction are perpendicular; Preferably, the first direction is parallel to one side edge of the battery matrix (10); or, the first direction forms an angle of 40° to 50° with one side edge of the battery matrix (10); Preferably, the first direction forms an angle of 45° with one side edge of the battery matrix (10).

10. The solar cell according to claim 7, wherein The solar cell further comprises: a doped polysilicon layer (30) disposed on the tunneling oxide layer (20); Preferably, the thickness of the doped polysilicon layer (30) is 100 nm to 500 nm; Preferably, the doping concentration of the doping element in the doped polysilicon layer (30) is 3E20 atoms / cm 3 ~9E20atoms / cm 3 ; Preferably, the tunneling oxide layer (20) is arranged on the back side or both sides of the battery substrate (10), and the conductivity type of the doping element of the doped polysilicon (20) is the same as the conductivity type of the battery substrate (10).

Images