Method and device for processing hypercomplex numbers

Abstract

The embodiment of the invention provides a method and a device for processing hypercomplex numbers. According to the proposed scheme, one of the operands of a first operation is negated prior to performing the first operation (e.g., a subtraction operation, a multiplication operation or a convolution operation). The scheme can be applied to any product requiring subtraction, without the need for dedicated subtraction logic or subtraction instructions, such as application to complex valued matrix (or one-dimensional vector) multiplication or convolution. By means of the proposed scheme, the operations on the complex valued matrix and the CVNN can be simulated with the maximum time and area efficiency. In addition, the operation can be simulated with the maximum time and area efficiency on a matrix of high-order algebra needing subtraction.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technology, and more particularly, to a method and apparatus for processing hypercomplex numbers. Background Art

[0002] Traditional implementations of neural networks (NNs) have primarily focused on real-valued neural networks (RVNNs). Recent research has shown that complex-valued neural networks (CVNNs) can achieve higher accuracy than RVNNs. However, to this day, most computers are still unable to process complex numbers directly. Operations on complex numbers are simulated by performing multiple operations on real numbers, which are component representations of complex numbers. This simulation slows down computation and increases the cost of using complex numbers, namely, increased processing time and power consumption. Complex number multiplication or convolution is particularly expensive in these respects. Due to the lack of matrix subtraction, operations on complex numbers, especially multiplication and convolution, are very inefficient. Summary of the Invention

[0003] The embodiments of the present invention provide a method and apparatus for processing hypercomplex numbers, which can be applied to any product requiring matrix (or vector) subtraction, thereby efficiently simulating operations on hypercomplex numbers.

[0004] According to a first aspect, there is provided a method for processing a hypercomplex number, the method comprising:

[0005] negating a sign of a first operand of a first operation, wherein negating the sign of the first operand comprises negating the signs of all elements of the first operand, the first operation comprises any one of the following operations: a subtraction operation, a multiplication operation, or a convolution operation, and the operand of the first operation comprises a matrix or a one-dimensional vector;

[0006] The first operation is performed based on inverting the sign of the first operand.

[0007] According to the method proposed in the first aspect, before the first operation, the sign of one of the operands of the first operation is negated. Operations on operands, such as matrices (or vectors) of hypercomplex numbers (e.g., complex numbers, quaternions, or octonions), can be efficiently simulated in terms of processing time, area savings, power consumption, etc.

[0008] In an embodiment of the first aspect, the elements in the matrix or the vector include hypercomplex numbers, each hypercomplex number includes at least two components, and each element in the matrix or the vector includes one of the at least two components.

[0009] It should be noted that in the present invention, each matrix (or vector) represents a component of a hypercomplex number. For example, matrix A includes the real part of a complex number, and matrix B includes the imaginary part of a complex number.

[0010] The proposed scheme can be applied to any product that requires subtraction, such as operations on hypercomplex numbers, which can be efficiently simulated on computers.

[0011] In an embodiment of the first aspect, the first operation is a multiplication operation; and the method further comprises:

[0012] performing the multiplication operation on a first input and a second input to obtain a product, wherein the first input is an output of negating the sign of the first operand, the first operand is either operand of the two operands of the multiplication, and the second input is the second operand of the two operands;

[0013] A result of the multiplication operation is obtained according to the product.

[0014] The proposed scheme can be applied to the multiplication of hypercomplex matrices or vectors without the need for dedicated subtraction logic or subtraction instructions, and has high efficiency for the multiplication of hypercomplex matrices (or vectors).

[0015] In an embodiment of the first aspect, the first operation is a convolution operation;

[0016] The method further comprises:

[0017] performing a convolution operation on a first input and a second input to obtain a product, wherein the first input is the output of negating the sign of the first operand, the first operand is either operand of the convolution operation, and the second input is the second operand of the two operands;

[0018] A result of the convolution operation is obtained according to the accumulation operation and the product.

[0019] For the convolution operation of a hypercomplex matrix or vector, if a subtraction operation exists but there is no dedicated subtraction logic or subtraction instruction, the proposed scheme can be used to efficiently simulate the convolution operation of the matrix (or vector).

[0020] In an embodiment of the first aspect, the method further comprises:

[0021] receiving an instruction, wherein the instruction instructs one of the operands to be negated in the first operation;

[0022] The inverting the sign of the first operation includes:

[0023] In case the instruction indicates to perform the inverted first operand, the sign of the first operand is inverted.

[0024] In this embodiment, the inverting of the sign of the first operand may be controlled by an instruction from a control logic. In addition, another possible method is provided to implement the proposed solution.

[0025] According to a second aspect, there is provided a method for processing a hypercomplex number, the method comprising:

[0026] performing a multiplication operation on two operands to obtain an output, wherein each of the two operands and the output is a matrix or a vector, elements of the matrix or the vector include hypercomplex numbers, each hypercomplex number includes at least two components, and each element of the matrix or the vector includes one of the at least two components;

[0027] The sign of the output is negated, wherein the negating the sign of the output comprises negating the signs of all elements of the output.

[0028] The method proposed in the second aspect can be applied to the multiplication or convolution of hypercomplex matrices (or vectors). The sign of the output of the multiplication operation can be reversed, and the sign of the output of the multiplication part of the convolution can also be reversed before accumulation. In addition, another possible method is provided to implement subtraction in the absence of dedicated hardware logic or subtraction instructions. The multiplication or convolution operation of hypercomplex numbers has high efficiency in terms of processing time, area saving, power saving, etc.

[0029] In an embodiment of the second aspect, the multiplication operation is a multiplication portion of a convolution operation;

[0030] The method further comprises:

[0031] A result of the convolution operation is obtained according to the accumulation operation and the output.

[0032] Compared with the multiplication operation, the convolution operation has an additional accumulation operation, which can efficiently simulate the convolution operation.

[0033] According to a third aspect, there is provided a method for processing a hypercomplex number, the method comprising:

[0034] negating a sign of an operand of a first operation according to a control instruction, wherein negating the sign of the operand comprises negating the signs of all elements of the operand, the first operation involving subtraction or not involving subtraction, and the control instruction being associated with the first operation involving subtraction or not involving subtraction;

[0035] The first operation is performed based on inverting the sign of the operand.

[0036] In an embodiment of the third aspect, the control instruction is associated with the first operation involving subtraction or not involving subtraction, including:

[0037] The control instruction instructs, when the first operation does not involve subtraction, to negate two operands of the first operation;

[0038] Wherein, inverting the sign of the operand of the first operation according to the control instruction includes:

[0039] According to the control instruction, the signs of the two operands of the first operation are inverted.

[0040] In an embodiment of the third aspect, the control instruction is associated with the first operation involving subtraction or not involving subtraction, including:

[0041] The control instruction instructs, when the first operation involves a subtraction, to negate one of two operands of the first operation;

[0042] Wherein, inverting the sign of the operand of the first operation according to the control instruction includes:

[0043] According to the control instruction, a sign of a first operand of two operands of the first operation is inverted, wherein the first operand is any one of the two operands.

[0044] The technical effects can refer to the technical effects of the first or second aspect and will not be repeated here.

[0045] According to a third aspect, a device for processing hypercomplex numbers is provided. The device has the functionality to implement the method of the first aspect and any possible implementation of the first aspect. The functionality can be implemented by hardware. The hardware includes one or more circuits corresponding to the functionality.

[0046] According to a fourth aspect, a device for processing hypercomplex numbers is provided. The device has the function of implementing the method in the second aspect and any possible implementation of the second aspect. The function can be implemented by hardware. The hardware includes one or more circuits corresponding to the above-mentioned function.

[0047] According to a fifth aspect, a chip (or chip system) is provided, comprising a first register, a sign inversion circuit, a multiplication circuit, control logic, and a second register for implementing the method of the first aspect, the second aspect, or any possible implementation of the first aspect or the second aspect. Specific details are provided in the specification and are not further described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] One or more embodiments are exemplarily described by corresponding drawings, and these exemplary descriptions and drawings do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are described as similar elements, and the scale of the drawings is not limited. In the drawings:

[0049] Figure 1 It is an example of a circuit for matrix multiplication and matrix convolution based on the prior art;

[0050] Figure 2 is a flow chart of a method (200) for processing hypercomplex numbers according to the present invention;

[0051] Figure 3 is an example of a method (200) for processing hypercomplex numbers according to the present invention;

[0052] Figure 4 is another example of the method (200) for processing hypercomplex numbers according to the present invention;

[0053] Figure 5 is a flow chart of a method (300) for processing hypercomplex numbers according to the present invention;

[0054] Figure 6 is another example of the method (300) for processing hypercomplex numbers according to the present invention;

[0055] Figure 7 is a flow chart of a method (500) for processing hypercomplex numbers according to the present invention;

[0056] Figure 8 is another example of the method for processing hypercomplex numbers according to the present invention;

[0057] Figure 9 It is a schematic block diagram of the chip (or chip system) proposed in the present invention. DETAILED DESCRIPTION

[0058] In order to understand the features and technical contents of each embodiment of the present application in more detail, the implementation of each embodiment of the present application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are only used for reference and illustration and are not intended to limit the embodiments of the present application. In the following technical description, for ease of explanation, many details will be set forth to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be implemented without these details. In other cases, in order to simplify the drawings, well-known structures and devices may be simplified for display.

[0059] Real numbers consist of one type of value, the real value. Complex numbers can be written as equation (1):

[0060]

[0061] in, i is the imaginary unit i that satisfies the equation 2 =-1.

[0062] The multiplication of two complex numbers can be expressed by the following equation (2):

[0063] (f+ig)=(a+ib)(c+id) (2)

[0064] This means that the values of the components f and g can be calculated as follows:

[0065] f=a*cb*d,g=a*d+b*c (3)

[0066] If A, B, C, D, E, F, and G are matrices, the same rules apply:

[0067] (F+iG)=(A+iB)(C+iD) (4)

[0068] The real-valued matrices F and G can be calculated in the same way as the real-valued numbers f and g, as shown in equation (3).

[0069] Computer programming languages such as Python, C, C++, and many other languages have a special symbol to represent "arithmetic assignment" operators, such as "+=" and "-=". For example, the following example:

[0070] a+=b≡a=a+b (5)

[0071] a-=b≡a=ab (6)

[0072] a*=b≡a=a*b (7)

[0073] The multiply-accumulate instruction, also known as the "MAC" instruction or the "FMA" instruction, performs the following operation:

[0074] c+=a*b≡c=c+a*b (8)

[0075] Where c is the accumulator register in equation (8).

[0076] Some arithmetic logic units (ALUs) have multiple accumulator registers.

[0077] Using the “arithmetic assignment” operator, the calculation (9) can also be expressed as the equation in (10):

[0078] f=a*cb*d,g=a*d+b*c (9)

[0079]

[0080] Equation (10) performs the addition or subtraction operation in (9) through the accumulator register. The addition or subtraction operation is performed simultaneously with the multiplication operation, without using a separate "add" or "subtract" instruction. In most cases, the addition or subtraction operation is also performed in the same clock cycle as the multiplication operation, making it faster than using a separate "add" statement or a separate "subtract" statement. A separate "add" statement or a separate "subtract" statement results in the execution of a separate "add" instruction or "subtract" instruction. The "add" instruction or "subtract" instruction must be loaded from memory into the cache, fetched from the cache, decoded, executed, etc., resulting in increased memory utilization, increased demand for memory bandwidth, reduced performance, increased power consumption, and ultimately increased cost of ownership.

[0081] These combined instructions optimize various aspects of the operation. In convolution operations with many multiply-add operations, the cost savings can be significant.

[0082] The problem is that many computer architectures do not have a "-=" operation. Such an operation must be simulated in software, as described in equation (11) below:

[0083]

[0084] The method shown in Equation (11) is one way to simulate complex-valued convolution. There are many other methods with similar complexity to Equation (11). Simulation is transparent to the programmer but incurs additional resource usage and performance penalties.

[0085] In view of this, the present invention utilizes the fact that equations (12) and (13) are valid in commutative algebras such as complex and real numbers.

[0086] -b=(-1)*b (12)

[0087]

[0088] Equations (12) and (13) mean that if b is negated before (5), then (6) is actually being executed instead of (5). This is exactly what is desired, except that there is no instruction to negate b, and such an instruction would also take up space in the executable code and would have to be loaded, fetched, decoded, executed, etc.

[0089] Then, the multiplication operation can be expressed as the following equation (14):

[0090]

[0091] By combining equations (5), (6), (12), (13), and (14), it can be noted that if one (and only one) of the operands of the multiplication is negated before the multiplication operation, then the multiplication and addition of the accumulator becomes the multiplication and subtraction of the accumulator. This is the essence of the present invention, which will be explained in detail in the subsequent embodiments.

[0092] Another way to represent complex numbers is to use a "matrix representation," as shown in equation (15):

[0093]

[0094] As shown in (15), the matrix representation requires four real numbers to represent a complex number. In the matrix representation, the real component x is repeated twice, and the imaginary component y is also repeated twice, such as y and -y.

[0095] Then, a matrix of complex values becomes a large n×n matrix, in which smaller matrices, each of size 2 × 2 elements, as shown in (16).

[0096]

[0097] To date, complex numbers in NNs cannot be processed directly in modern SIMD processors. These complex numbers must be simulated by two real numbers, one representing the "real" component of the complex number and the other representing the "imaginary" component of the complex number. If the complex values are represented as matrices, any real-valued matrix processor can perform complex-valued matrix multiplication, as shown in (15) and (16).

[0098] The analog of complex-valued multiplication like in (4) is known and requires matrix subtraction as shown in (3). Although (3) operates on real numbers rather than real-valued matrices, the matrix equation (3) is the same.

[0099] Many matrix processors can only perform matrix multiplication and matrix convolution. The lack of matrix subtraction and matrix inversion means that the operations on complex numbers in (4) and other high-order algebraic operations become inefficient. The reason for this is that it is more economical to implement only multiplication and accumulation operations because it saves area and power, ultimately reducing chip cost and cost of ownership. Compared with the solution that only implements multiplication and accumulation, a matrix multiplication processor with general matrix-ALU functions (which can also perform subtraction and inversion) is larger in area, consumes more power, and is more expensive.

[0100] General purpose graphics processing units (GPGPUs) are more expensive in terms of functional logic, number of instructions, more complex control logic, energy consumption, and ultimately chip cost and cost of ownership.

[0101] Many matrix processors today can perform complex-valued matrix multiplication, as shown in (15) and (16). However, the "matrix representation" of complex numbers requires four real numbers to represent one complex number. This results in a doubling of memory consumption and, consequently, a requirement for double the memory bandwidth. As a result, the power consumption of the arithmetic portion of the operation roughly doubles. Furthermore, there are other operations whose energy consumption does not double, but in NNs, arithmetic operations account for the vast majority of all operations. More than 99% of operations are multiplications and accumulations.

[0102] In summary, when processing complex-valued arithmetic and other high-order algebra or algorithms that require matrix subtraction, implementing the instructions for performing matrix subtraction operations consumes a significant amount of area, while not executing the instructions consumes a significant amount of performance (e.g., processing time). These high-order algebra requiring subtraction are hypercomplex numbers (HCNs), such as complex numbers, quaternions, and octonions.

[0103] In view of this, the present invention provides a method and apparatus for implementing convolution or multiplication of hypercomplex numbers (e.g., complex numbers, quaternions, octonions). In matrix convolution, some products can be subtracted from the convolution result, while other products are added, without the need to implement a separate matrix subtraction function and without allocating instructions and processing time for such subtraction. This means that in channelized hypercomplex matrix convolutions, which are common in certain types of CVNNs, channelized hypercomplex matrix convolutions (or multiplications) can be implemented quickly and efficiently with minimal hardware overhead and no performance overhead due to simulation.

[0104] The solution proposed in the present invention can be applied to all hardware implementations of hypercomplex matrix convolution (or multiplication) and hypercomplex one-dimensional vector convolution (or multiplication).

[0105] For the sake of brevity, a list of elements of the drawings in the present invention is first given, as shown in Table 1.

[0106] Table 1

[0107] element DETAILED DESCRIPTION 101 Source, register, register file, queue, or similar element of one operand A of the matrix multiplication 102 Source, register, register file, queue, or similar element of one operand B of a matrix multiplication 103 Operand A sign inversion logic 104 Operand B sign negation logic 105 Matrix multiplication circuit 106 Sign negation logic for matrix product 107 Accumulation register for matrix convolution 108 Control Logic

[0108] Figure 1 This is an example circuit for matrix multiplication and matrix convolution based on prior art. Operand source 101 and operand source 102 can be independent registers, each containing a matrix, or independent register files, each containing multiple registers, or a common register file containing multiple matrices, with the register file capable of reading both operands simultaneously. Elements 101 and 102 can also be first-input, first-output (FIFO) queues, which can input matrices into matrix multiplier 105. Therefore, elements 101 and 102 should be understood as sources of operands, not necessarily storage locations for operand matrices. Element 107 is an output accumulator register. Control logic 108 generates one or more output signals based on decoding the instruction code for the matrix operation instruction. Matrix multiplication enables the accumulator to load the matrix product into the accumulator, overwriting the existing value. Matrix convolution enables the accumulator to add the matrix product to the accumulated value already in the accumulator.

[0109] also, Figure 1 No assumptions are made about how and where the results are stored and the present invention is therefore not concerned with this.

[0110] Figure 2 1 is a flow chart of a method (200) for processing hypercomplex numbers according to the present invention; the method (200) can be applied to any product requiring a subtraction operation. For example, the method (200) is applied to matrix subtraction, vector subtraction, matrix multiplication, matrix convolution, one-dimensional vector multiplication, or one-dimensional vector convolution. The elements in the matrix or vector include hypercomplex numbers (e.g., complex numbers, quaternions, or octonions). A hypercomplex number includes at least two components, and each element in the matrix or vector includes one of the at least two components.

[0111] It should be understood that in the present invention, hypercomplex numbers include complex numbers, quaternions, octonions, and z=a+bi+cε+diε, where i 2 =-1,ε 2 = 0, ε ≠ 0. In other words, "hypercomplex numbers" include all algebraic numbers higher than the first (real) order.

[0112] Furthermore, the proposed scheme can be used in many fields involving hypercomplex numbers. Some applications of the proposed scheme include signal processing, communication systems, image processing, quantum computing, antenna design, control systems, etc. These are just a few examples, and the application of hypercomplex numbers can also be used in different fields to solve practical problems.

[0113] The method (200) specifically comprises the following steps:

[0114] Step 210: Negate the sign of a first operand of a first operation, wherein negating the sign of the first operand includes negating the signs of all elements of the first operand such that each element has a negative sign, the first operand includes any one of the following operations: a subtraction operation, a multiplication operation, and a convolution operation, and the operand of the first operation includes a matrix or a one-dimensional vector.

[0115] Step 220: Perform a first operation based on inverting the sign of the first operand.

[0116] For example, the elements in the matrix or vector include hypercomplex numbers, because simulating hypercomplex numbers requires a subtraction operation. In other words, the first operation is performed on the matrix of hypercomplex numbers, or the first operation is performed on the vector of hypercomplex numbers.

[0117] In one embodiment, the first operation includes matrix subtraction or vector subtraction. It should be understood that subtraction can be implemented as addition by negating the sign of the subtrahend. For example, an operation of subtracting matrix A from matrix B is performed. First, the sign of matrix A is negated to obtain a negated result, and then the negated result is added to matrix B to obtain the output of the matrix subtraction.

[0118] In another embodiment, the first operation includes matrix multiplication. The sign of the first operand is negated to obtain a first input of the matrix multiplication, wherein the first operand is either operand of the two operands of the matrix multiplication. Matrix multiplication is performed on the first input and the second input to obtain a product, wherein the second input is the second operand of the two operands. A result of the multiplication operation can be obtained based on the product. Vector multiplication is similar to matrix multiplication and will not be described in detail here. Each element of the two operands and the result of the multiplication operation include one component of at least two components of the hypercomplex number.

[0119] In another embodiment, the first operation includes matrix convolution. The multiplication portion of the matrix convolution is the same as the matrix multiplication described above, but the products are also accumulated to obtain the result of the matrix convolution. Vector convolution is similar to matrix convolution and will not be described in detail here.

[0120] Some hardware implementations of method (200) are given below.

[0121] Figure 3 is an example of a method (200) for processing hypercomplex numbers according to the present invention. Specifically, Figure 3Matrix multiplication and convolution circuitry is shown with a sign negation module 103 on operand A. Element 103 is controlled by control logic 108. Control signals from 108 to 103 instruct element 103 to negate (or invert) the sign of operand A or not to negate (or invert) the sign of operand A. Control circuitry 108 generates the control signals based on information in the instruction code of the matrix instruction.

[0122] Figure 4 is another example of the method (200) for processing hypercomplex numbers according to the present invention. Figure 4 In the example, element 104 is the sign negation module on operand B. Element 104 is the sign negation module on operand B. Figure 3 , except that element 103 negates the sign of operand A and element 104 negates the sign of operand B.

[0123] According to the present invention, it is not necessary to invert the signs of A and B; only the sign of one operand needs to be inverted. If both operands A and B are inverted, the signs of all elements of the matrix multiplication result will be inverted. This again means that the result of the matrix multiplication will be subtracted from the accumulator register as in equation (6), rather than added to the accumulator register as in equation (5).

[0124] If the first operation is matrix multiplication, matrix convolution, vector multiplication, or vector convolution, the output of the multiplication part of the convolution can be directly negated, see Figure 5 .

[0125] Figure 5 is a flow chart of a method (300) for processing hypercomplex numbers according to the present invention. The method (300) comprises the following steps:

[0126] Step 310: Perform a multiplication operation on two operands to obtain an output, where each of the two operands and the output is a matrix or vector, and the elements of the matrix or vector include hypercomplex numbers (e.g., complex numbers, quaternions, or octonions). A hypercomplex number includes at least two components, and each element of the matrix or vector includes one of the at least two components. The output of the multiplication operation includes a product generated by the multiplication operation.

[0127] Step 320: invert the sign of the output, wherein inverting the sign of the output includes inverting the signs of all elements of the output.

[0128] The product is loaded into the accumulator, overwriting the existing value in the case of applying the method (300) in a matrix multiplication or vector multiplication.

[0129] In another embodiment, if the method (300) is applied to matrix convolution or vector convolution, the multiplication operation is the multiplication part of the convolution operation. The method (300) further comprises step 330 as described below.

[0130] Step 330: Obtain the result of the convolution operation according to the accumulation operation and output.

[0131] Specifically, the product of the multiplication part of the convolution operation is added to the accumulated value to obtain the result of the convolution operation.

[0132] Figure 6 is an example of a method (300) for processing hypercomplex numbers according to the present invention. A sign inversion module 106 is provided at the output of element 105. This may be obvious, but in fact, in many cases, the position of element 106 imposes a greater constraint on the timing budget than the positions of elements 103 and 104.

[0133] Figure 7 is a flow chart of a method (500) for processing hypercomplex numbers according to the present invention. The method (500) comprises the following steps:

[0134] Step 510: Invert the sign of the operand of the first operation according to the control instruction, wherein inverting the sign of the operand includes inverting the signs of all elements of the operand, the first operation involves subtraction or does not involve subtraction, and the control instruction is related to the first operation involving subtraction or not involving subtraction.

[0135] Step 520: Perform a first operation based on inverting the sign of the operand.

[0136] The explanation of the operands for the first operation, the matrix, the one-dimensional vector, and the elements in the matrix (or vector) is similar to that of method (200) or method (300). Please refer to the embodiments of method (200) or method (300) and will not be repeated here.

[0137] Another example is Figure 8 This embodiment refers to a hardware structure applicable to both method (200) and method (500). Whether the hardware structure executes method (200) or method (500) depends on the specific control method. This embodiment will be described in detail below.

[0138] Figure 8 is another example of the method for processing hypercomplex numbers according to the present invention.

[0139] It should be noted that Figure 8 As another embodiment of the method (200), the control logic 108 can be used to select the sign of the inverted operand A or operand B. The embodiment of the method (200) is Figure 8 The first embodiment, where subtraction is required. Figure 8 In the first embodiment, it is not necessary to have a sign inversion module on both operand A and operand B, but a sign inversion module can be added on operand A and operand B, and the control logic 108 can choose to invert the sign on operand A or operand B. Specifically, the control logic 108 sends instructions to element 103 and element 104 respectively, one of which indicates that the sign of the corresponding operand is inverted, and the other indicates that the sign of the corresponding operand is not inverted. For example, if the instruction sent to element 103 indicates that the sign of operand 101 is inverted, the instruction sent to element 104 indicates that the sign of operand 102 is not inverted. The instructions sent to element 103 and element 104 can be exchanged and are not subject to hard restrictions. It should be noted that it is not important how the control logic 108 selects the operand to be inverted. What is important is that element 108 can select one of the two operands 101 and 102 to be inverted. In addition, the present invention covers one or more schemes for selecting operands to be inverted, including but not limited to the following:

[0140] Controlled by instruction code;

[0141] Controlled by control bits in different data registers or control registers;

[0142] Controlled by external logic signals;

[0143] Permanently selects to invert the sign of operand A or operand B;

[0144] Alternately invert the sign of operand A or operand B. The alternation can be any concept of alternation, including but not limited to:

[0145] Cycle alternation;

[0146] Any type of pseudo-random algorithm;

[0147] Random number generation;

[0148] Any repeating alternating pattern (i.e., any pattern based on the output of a counter, final state machine, or similar structure with a finite number of states).

[0149] Figure 8The second embodiment is an embodiment of the method (500). In the second embodiment, in the normal case (i.e., by default) when the first operation does not involve subtraction, the signs of operands A and B are inverted, and in the case when the first operation involves subtraction, the sign of one operand is inverted. For example, in the normal case, the control logic 108 sends a first instruction and a second instruction to element 103 and element 104, respectively, the first instruction instructing to invert the sign of operand A and the second instruction instructing to invert the sign of operand B. Outputs -A and -B are obtained from element 103 and element 104, respectively.

[0150] In another case, excluding the normal case requiring subtraction, control logic 108 chooses to perform a sign inversion on operand A or operand B. For example, control logic 108 sends a first instruction to invert the sign of operand A and a second instruction to not invert the sign of operand B. Thus, outputs of -A and -B are obtained from element 103 and element 104, respectively. Alternatively, the instructions sent to element 103 and element 104 can be swapped, resulting in outputs of A and -B, respectively.

[0151] That is to say, Figure 8 The second embodiment includes a normal case and a case excluding the normal case. In the normal case, the signs of the two operands A and B are inverted, while in the case excluding the normal case (for example, a case where subtraction is required), only the sign of one operand is inverted.

[0152] Figure 8 The hardware structures of the two embodiments described above are shown. It can be seen that the two embodiments are identical in hardware structure but differ in their internal control methods. Control logic 108 controls whether to perform inversion on one operand or on both operands. In other words, to a certain extent, it is controlled by whether the first operation involves subtraction, i.e., whether only one operand is inverted or both operands are inverted.

[0153] It is not important whether the control logic for element 103 is physically integrated or separate from the control logic for element 104. For example, the control logic for element 103 and the control logic for element 104 are integrated as Figure 8 In either case, control logic 108 represents control functionality for element 103 and element 104, regardless of whether the control functionality for element 103 and element 104 are physically combined in an implementation.

[0154] In another embodiment, Figure 3 、 Figure 4 and Figure 8In the example, the input to element 105 is a one-dimensional vector of length n, where n is a positive integer. In other words, the input to element 105 is a vector consisting of n elements, rather than an n×n matrix. In this embodiment, element 105 can also be referred to as a vector multiplication circuit. In this embodiment, one of operands A and B input to vector multiplication circuit 105 undergoes sign inversion by element 103 or 104.

[0155] In another embodiment, Figure 6 In the embodiment, the output of element 105 is a one-dimensional vector of a certain length n, where n is a positive integer. In this embodiment, the output of vector multiplication circuit 105 is sign-inverted by element 106 before entering vector accumulation register 107.

[0156] According to the present invention, the product is subtracted from the accumulation register by negating one of the operands in the multiplication part of the convolution before multiplication, or by negating the output of the multiplication part of the convolution before accumulation. The proposed method can be implemented without the need for dedicated subtraction logic or subtraction operations. On this basis, operations on hypercomplex matrices and CVNNs can be efficiently simulated in terms of processing time, area saving, power saving, etc. In addition, operations on matrices (or vectors) of other high-order algebras that require subtraction can also be efficiently simulated.

[0157] The above is an introduction to various embodiments of the method. The following describes various embodiments of the device.

[0158] In one embodiment of the present invention, a chip (or chip system) is provided. The chip may include a first register, a sign inversion circuit, an operation circuit, and a second register. The first register is used to provide two operands for a first operation, wherein the first operation includes any of the following operations: subtraction, multiplication, or convolution, and each of the two operands includes a matrix or a one-dimensional vector. The sign inversion circuit is used to invert the sign of the first operand of the two operands, wherein inverting the sign of the first operand includes inverting the signs of all elements of the first operand. The operation circuit is used to perform the first operation based on inverting the sign of the first operand to obtain an output, and the second register is used to cache or store the output. The chip has the function of implementing any method proposed in the present invention or any possible implementation of any method. The function can be implemented by hardware. The hardware includes one or more circuits corresponding to the above functions.

[0159] Figure 9 FIG. 1 is an example of a schematic block diagram of the chip (or chip system) 10 proposed in the present invention. Figure 9As shown, the chip (or chip system) may include part or all of the following hardware: a first register 11 , a sign inversion circuit 12 , a multiplication circuit 13 , a control logic 14 and a second register 15 .

[0160] The first register 11 is used to provide two operands. The sign inversion circuit 12 is used to perform a sign inversion operation on corresponding operands of the two operands. The multiplication circuit 13 is used to perform matrix multiplication or vector multiplication. The control logic 14 is used to send instructions to the sign inversion circuit 12 and the second register 15. The second register 15 is used to receive instructions from the control logic 14, load the output of the multiplication circuit 13 including the product, and overwrite the existing value when the instruction from the control logic 14 indicates a multiplication operation, such as a matrix multiplication operation or a vector multiplication operation. The second register 15 is used to receive instructions from the control logic 14, load the output of the multiplication circuit 13 including the product, and when the instruction from the control logic 14 indicates a convolution operation, such as a matrix convolution operation or a vector convolution operation, accumulate the product to obtain the result of the convolution operation.

[0161] In short, the first register is used to provide operands for the multiplication or convolution operation, and the second register is used to cache or store the output of the multiplication or convolution operation. The number of the first registers 11 can be one or more, and the number of the second registers can be one or more, which is not limited by the present invention.

[0162] For example, the first register includes element 101 and element 102, and the second register is element 107. The sign inversion circuit includes element 103, element 104, or element 106. The multiplication circuit is element 105. The control logic is element 108, as shown in the above embodiment.

[0163] In addition, the number of the sign inversion circuit 12 can be one or two, which is not limited by the present invention. Figure 3 Element 103 in Figure 4 Element 104 in, or Figure 6 The number of the sign inversion circuits 12 in these cases is one. Alternatively, the sign inversion circuit 12 may be Figure 8 In these cases, the number of the sign inversion circuits 12 is two. For details, please refer to the specific contents of each embodiment of the method, which will not be repeated here.

[0164] The foregoing description is merely a list of specific implementations of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications or substitutions readily conceivable by a person skilled in the art within the technical scope disclosed herein should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A method for processing hypercomplex numbers, characterized in that The method comprises: negating a sign of a first operand of a first operation, wherein negating the sign of the first operand comprises negating the signs of all elements of the first operand, the first operation comprises any one of the following operations: a subtraction operation, a multiplication operation, or a convolution operation, and the operand of the first operation comprises a matrix or a one-dimensional vector; The first operation is performed based on inverting the sign of the first operand.

2. The method according to claim 1, characterized in that The elements in the matrix or the vector include hypercomplex numbers, each hypercomplex number includes at least two components, and each element in the matrix or the vector includes one of the at least two components.

3. The method according to claim 1 or 2, characterized in that The first operation is a multiplication operation; the method further comprises: performing the multiplication operation on a first input and a second input to obtain a product, wherein the first input is an output of inverting the sign of the first operand, the first operand is either operand of the two operands of the multiplication operation, and the second input is the second operand of the two operands; A result of the multiplication operation is obtained according to the product.

4. The method according to claim 1 or 2, characterized in that The first operation is a convolution operation; the method further comprises: performing a convolution operation on a first input and a second input to obtain a product, wherein the first input is the output of negating the sign of the first operand, the first operand is either operand of the convolution operation, and the second input is the second operand of the two operands; A result of the convolution operation is obtained according to the accumulation operation and the product.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: receiving an instruction, wherein the instruction instructs to negate one of the operands of the first operation; The inverting the sign of the first operation includes: In case the instruction indicates to perform the inverted first operand, the sign of the first operand is inverted.

6. A method for processing hypercomplex numbers, characterized in that The method comprises: performing a multiplication operation on two operands to obtain an output, wherein each of the two operands and the output comprises a matrix or a vector, elements of the matrix or the vector comprise hypercomplex numbers, each hypercomplex number comprises at least two components, and each element of the matrix or the vector comprises one of the at least two components; The sign of the output is negated, wherein the negating the sign of the output comprises negating the signs of all elements of the output.

7. The method according to claim 6, characterized in that The multiplication operation is a multiplication portion of a convolution operation; the method further comprising: A result of the convolution operation is obtained according to the accumulation operation and the output.

8. A method for processing hypercomplex numbers, characterized in that The method comprises: negating a sign of an operand of a first operation according to a control instruction, wherein negating the sign of the operand comprises negating the signs of all elements of the operand, the first operation involving subtraction or not involving subtraction, and the control instruction being associated with the first operation involving subtraction or not involving subtraction; The first operation is performed based on inverting the sign of the operand.

9. The method according to claim 8, characterized in that The operand of the first operation includes a matrix or a one-dimensional vector, the elements of the matrix or the vector include hypercomplex numbers, each hypercomplex number includes at least two components, and each element of the matrix or the vector includes one of the at least two components.

10. The method according to claim 8 or 9, characterized in that The control instruction is related to the first operation involving subtraction or not involving subtraction, including: The control instruction instructs, when the first operation does not involve subtraction, to negate two operands of the first operation; Wherein, inverting the sign of the operand of the first operation according to the control instruction includes: According to the control instruction, the signs of the two operands of the first operation are inverted.

11. The method according to claim 8 or 9, characterized in that The control instruction is related to the first operation involving subtraction or not involving subtraction, including: The control instruction instructs, when the first operation involves a subtraction, to negate one of two operands of the first operation; Wherein, inverting the sign of the operand of the first operation according to the control instruction includes: According to the control instruction, the sign of a first operand of the two operands of the first operation is inverted, the first operand being any one of the two operands.

12. A hypercomplex number processing device, characterized in that: include: a first register for providing two operands for a first operation, the first operation comprising any one of the following operations: a subtraction operation, a multiplication operation, or a convolution operation, each of the two operands comprising a matrix or a one-dimensional vector; a sign inversion circuit, configured to invert a sign of a first operand of the two operands, wherein inverting the sign of the first operand includes inverting the signs of all elements of the first operand; An operation circuit is configured to perform the first operation based on inverting the sign of the first operand.

13. The device according to claim 11, characterized in that The elements in the matrix or the vector include hypercomplex numbers, each hypercomplex number includes at least two components, and each element in the matrix or the vector includes one of the at least two components.

14. The device according to claim 12 or 13, characterized in that The first operation is a multiplication operation; the operation circuit includes: Multiplication circuits for: performing the multiplication operation on a first input and a second input to obtain a product, wherein the first input is an output of inverting the sign of the first operand, the first operand is either operand of the two operands of the multiplication operation, and the second input is the second operand of the two operands; Obtaining a result of the multiplication operation according to the product; The second register is used to: receiving a result of the multiplication operation from the multiplication circuit; The result of the multiplication operation is cached or stored.

15. The device according to claim 12 or 13, characterized in that The first operation is a convolution operation; the operation circuit includes: Multiplication circuits for: performing a multiplication operation of the convolution operation on a first input and a second input to obtain a product, wherein the first input is an output of negating the sign of the first operand, the first operand is either operand of the two operands of the convolution operation, and the second input is the second operand of the two operands; Obtaining a result of the convolution operation according to the accumulation operation and the product; The second register is used to: receiving a result of the convolution operation from the multiplication circuit; The result of the convolution operation is cached or stored.

16. The device according to any one of claims 12 to 15, characterized in that The sign inversion circuit further includes a first sign inversion circuit and a second sign inversion circuit; the device further includes: control logic for sending instructions to the first sign inversion circuit and the second sign inversion circuit, respectively, wherein one of the instructions sent to the first sign inversion circuit instructs to invert the sign of the first operand, and another instruction sent to the second sign inversion circuit instructs not to invert the sign of the second operand; The first sign inversion circuit and the second sign inversion circuit are further configured to: The signs of the corresponding operands are inverted or not inverted according to the instruction from the control logic.

17. A device for processing hypercomplex numbers, characterized in that include: The first register is used to provide two operands; a multiplication circuit configured to perform a multiplication operation on the two operands to obtain an output, wherein each of the two operands and the output is a matrix or a vector, elements of the matrix or vector include hypercomplex numbers, each hypercomplex number includes at least two components, and each element of the matrix or vector includes one of the at least two components; a sign inversion circuit, configured to invert the sign of the output, wherein inverting the sign of the output comprises inverting the signs of all elements of the output; The second register is used to buffer or store the output.

18. The device according to claim 17, characterized in that The multiplication operation is the multiplication part of the convolution operation; The second register is further used for: Obtaining a result of the convolution operation according to the accumulation operation and the output; The result of the convolution operation is cached or stored.

19. A device for processing hypercomplex numbers, characterized in that include: A first register for providing an operand to a first operation; a sign negation circuit, configured to negate the sign of the operand according to a control instruction, wherein negating the sign of the operand comprises negating the signs of all elements of the operand, and the first operation involves subtraction or does not involve subtraction; control logic for sending the control instruction to the sign inversion circuit, wherein the control instruction is related to the first operation involving subtraction or not involving subtraction; An operation circuit is used to perform the first operation according to inverting the sign of the operand.

20. The device according to claim 19, characterized in that The operand of the first operation includes a matrix or a one-dimensional vector, the elements of the matrix or the vector include hypercomplex numbers, each hypercomplex number includes at least two components, and each element of the matrix or the vector includes one of the at least two components.

21. The device according to claim 19 or 20, characterized in that The sign inversion circuit is further used for: In a case where the control instruction indicates that two operands are to be inverted, the signs of the two operands are inverted according to the control instruction, wherein the first operation does not involve subtraction.

22. The device according to claim 19 or 20, characterized in that The sign inversion circuit is further used for: In a case where the control instruction indicates that one of the two operands is to be inverted, the sign of the first operand of the two operands is inverted according to the control instruction, wherein the first operation involves the subtraction and the first operand is either one of the two operands.

23. A chip or a chip system, characterized in that: The chip or chip system comprises the device according to any one of claims 8 to 14.

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