Sub-regulator circuit

Abstract

The invention relates to a sub-regulator circuit. A circuit includes a first transistor (108), a second transistor (110), a third transistor (206), and a current mirror circuit (210). The first transistor (108) has a first terminal, a second terminal, and a control terminal. The second transistor (110) has a first terminal coupled to the control terminal of the first transistor (108), a second terminal, and a control terminal coupled to the second terminal of the first transistor (108). The third transistor (206) has a control terminal coupled to the control terminal of the first transistor (108), a first terminal coupled to a current source (220), and a second terminal coupled to the second terminal of the first transistor (108). The current mirror circuit (210) includes a fourth transistor (212) and a fifth transistor (214). The fourth transistor (212) is coupled between the second terminal of the third transistor (206) and a reference voltage terminal. The fifth transistor (214) is coupled between the current source (220) and the reference voltage terminal.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and more particularly, to sub-regulator circuits. Background Art

[0002] The operating voltage provided to power an electronic circuit can be limited to a selected range to achieve the desired operation of the electronic circuit. For example, an electronic circuit system may operate properly if the voltage powering the circuit is within a given range. Switching regulators and linear regulators are examples of voltage regulation circuits that can be used to limit the operating voltage provided to an electronic circuit. Summary of the Invention

[0003] In one example, a circuit includes a first transistor, a second transistor, a third transistor, and a current mirror circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The second transistor has a first terminal coupled to the control terminal of the first transistor, a second terminal, and a control terminal coupled to the second terminal of the first transistor. The third transistor has a control terminal coupled to the control terminal of the first transistor, a first terminal coupled to a current source, and a second terminal coupled to the second terminal of the first transistor. The current mirror circuit includes a fourth transistor and a fifth transistor. The fourth transistor is coupled between the second terminal of the third transistor and a reference voltage terminal. The fifth transistor is coupled between the current source and the reference voltage terminal.

[0004] In another example, a circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a resistor. The first transistor has a first terminal, a second terminal, and a control terminal. The second transistor has a first terminal coupled to the control terminal of the first transistor, a second terminal, and a control terminal coupled to the second terminal of the first transistor. The third transistor has a first terminal coupled to the first terminal of the first transistor, a second terminal coupled to the second terminal of the first transistor, and a control terminal. The fourth transistor has a first terminal coupled to the first terminal of the first transistor, a second terminal coupled to the control terminal of the third transistor, and a control terminal. The capacitor is coupled between the control terminal of the fourth transistor and the second terminal of the fourth transistor. The resistor is coupled between the first terminal of the fourth transistor and the control terminal of the fourth transistor.

[0005] In another example, a subregulator circuit includes a subregulator loop circuit, a transconductance maintainer circuit, and an initialization boost circuit. The subregulator loop circuit includes a first pass transistor configured to provide a regulated output voltage at a voltage output terminal. The transconductance maintainer circuit is coupled to the voltage output terminal. The transconductance maintainer circuit is configured to sense a first current flowing through the pass transistor and, in response to the first current being less than a threshold current, draw a second current from the voltage output terminal. The initialization boost circuit is coupled to the voltage output terminal. The initialization boost circuit includes a second pass transistor configured to provide a third current to the voltage output terminal during an initialization interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of the example sub-regulator circuit.

[0007] Figure 2 Is suitable for Figure 1 Schematic diagram of a transconductance maintainer circuit in an example of a sub-regulator circuit.

[0008] Figure 3 Is suitable for Figure 1 An example of the sub-regulator circuit is shown in the schematic diagram of the initialization boost circuit.

[0009] Figure 4 is included Figure 1 Block diagram of a voltage reference circuit with an example of a sub-regulator circuit. DETAILED DESCRIPTION

[0010] Figure 1is a block diagram of an example sub-regulator circuit 100. Sub-regulator circuit 100 includes a sub-regulator loop circuit 102, a transconductance maintainer circuit 104, and an initialization boost circuit 106. Sub-regulator loop circuit 102 includes a transistor 108, a transistor 110, a transistor 112, a capacitor 114, a capacitor 116, and a current source 118. Transistor 108 and sub-regulator circuit 100 may be n-channel field-effect transistors (NFETs), and transistor 112 may be a p-channel field-effect transistor (PFET). Transistor 108 functions as a pass transistor that conducts current from a power supply terminal VIN to an output terminal AVDD_SR. Transistor 108 includes a first current terminal (e.g., a drain) coupled to VIN and a second current terminal (e.g., a source) coupled to AVDD_SR. A control terminal (e.g., a gate) of transistor 108 is coupled to the output of current source 118, and an input of current source 118 is coupled to VIN. Capacitor 114 is coupled between the control terminal of transistor 108 and a reference voltage terminal or ground terminal (AVSS) to filter the control voltage provided to transistor 108. Capacitor 116 is coupled between the second current terminal of transistor 108 and AVSS to filter the output voltage of subregulator loop circuit 102.

[0011] Transistor 110 controls the voltage at the control terminal of transistor 108 based on the voltage at the output terminal to regulate the voltage at AVDD_SR. A first current terminal (e.g., drain) of transistor 110 is coupled to the control terminal of transistor 108, and a second current terminal (e.g., source) of transistor 110 is coupled to transistor 112. A control terminal (e.g., gate) of transistor 110 is coupled to the second current terminal of transistor 110.

[0012] Transistor 112 defines the voltage provided at AVDD_SR based on a reference voltage provided at a voltage reference terminal (VREF). A first current terminal (e.g., source) of transistor 112 is coupled to a second current terminal of transistor 110, and a second current terminal of transistor 112 is coupled to AVSS. A control terminal (e.g., gate) of transistor 112 is coupled to voltage reference terminal VREF.

[0013] A transconductance maintainer circuit 104 is coupled to the sub-regulator loop circuit 102. A first input of the transconductance maintainer circuit 104 is coupled to the output terminal AVDD_SR of the sub-regulator loop circuit 102, a second input of the transconductance maintainer circuit 104 is coupled to the control terminal of transistor 108, and a third input of the transconductance maintainer circuit 104 is coupled to the power supply terminal VIN. The transconductance maintainer circuit 104 stabilizes the sub-regulator loop circuit 102 by drawing a minimum current from transistor 108. In practice, after the output voltage of the sub-regulator loop circuit 102 is sufficient to power the load, the current drawn by the load circuit coupled to the sub-regulator circuit 100 stabilizes the sub-regulator loop circuit 102. If the load current is too low before the output voltage of the sub-regulator loop circuit 102 has risen to a level sufficient to power the load, the sub-regulator loop circuit 102 may become unstable and oscillate. The transconductance maintainer circuit 104 ensures that a sufficient load current is drawn to stabilize the sub-regulator loop circuit 102 during initialization. The current drawn by the transconductance maintainer circuit 104 varies based on the current drawn by the load circuit coupled to the sub-regulator loop circuit 102. As the current drawn by the load circuit increases, the current drawn by the transconductance maintainer circuit 104 decreases. When the current drawn by the load circuit exceeds a threshold sufficient for stable operation of the sub-regulator loop circuit 102, the transconductance maintainer circuit 104 may draw little or no current from the sub-regulator loop circuit 102. Figure 2 Further explanation of an example of the transconductance maintainer circuit 104 is provided.

[0014] An initialization boost circuit 106 is coupled to the sub-regulator loop circuit 102. A first input of the initialization boost circuit 106 is coupled to the output terminal AVDD_SR of the sub-regulator loop circuit 102, a second input of the initialization boost circuit 106 is coupled to the control terminal of the transistor 108, and a third input of the initialization boost circuit 106 is coupled to the power supply terminal VIN. A fourth input of the initialization boost circuit 106 is coupled to an enable circuit 120 that provides an enable signal (ENABLE) for enabling and disabling the initialization boost circuit 106. The initialization boost circuit 106 provides current to the output terminal AVDD_SR of the sub-regulator loop circuit 102 during an initialization interval defined by ENABLE. The current provided by the initialization boost circuit 106 can reduce the time required to charge the capacitor 116 and the capacitor 114, and provide power to the load circuit during the initialization interval. Reference Figure 3 Further explanation of an example of initializing the boost circuit 106 is provided.

[0015] Figure 2FIG2 is a schematic diagram of an example transconductance maintainer circuit 204. Transconductance maintainer circuit 204 is an implementation of transconductance maintainer circuit 104. Transconductance maintainer circuit 204 includes transistors 206 and 208, a current mirror circuit 210, a capacitor 218, and a current source 220. Transistor 206 can be an NFET, and transistor 208 can be a PFET. Transistor 206 is a sense transistor coupled in parallel with transistor 108. A first current terminal (e.g., drain) of transistor 206 is coupled to current source 220. A second current terminal (e.g., source) of transistor 206 is coupled to a second current terminal of transistor 108 and to current mirror circuit 210. A control terminal (e.g., gate) of transistor 206 is coupled to a control terminal of transistor 108. Transistor 206 is a scaled replica of transistor 108 and conducts a current that is proportional to (e.g., a fraction of) the current flowing through transistor 108. For example, the channel width of transistor 206 may be 1 / N (eg, 1 / 16) the channel width of transistor 108 , and the current conducted by transistor 206 may be 1 / N the current conducted by transistor 108 .

[0016] The current provided by current source 220 can be relatively small (e.g., tens of nanoamperes) and defines the current through transistor 108 required to stabilize sub-regulator loop circuit 102. The current provided by current source 220 that does not flow through transistor 206 flows through transistor 208. A first current terminal (e.g., source) of transistor 208 is coupled to a first current terminal of transistor 206, and a second current terminal (e.g., drain) of transistor 208 is coupled to current mirror circuit 210. A control terminal (e.g., gate) of transistor 208 is coupled to a second current terminal of transistor 206.

[0017] Current mirror circuit 210 includes transistors 212, 214, and 216. Transistors 212, 214, and 216 may be NFETs. Transistors 212 and 214 may be scaled so that the current flowing through transistor 212 is an integer multiple of the current flowing through transistor 214. For example, the channel width of transistor 212 may be 16 times the channel width of transistor 214. A first current terminal (e.g., drain) of transistor 212 is coupled to a second current terminal of transistor 206, and a second current terminal (e.g., source) of transistor 212 is coupled to AVSS. A control terminal (e.g., gate) of transistor 212 is coupled to a second current terminal of transistor 208. The current flowing through transistor 206 flows through transistor 212 to AVSS, or to a load circuit.

[0018] A first current terminal (e.g., drain) of transistor 216 is coupled to a second current terminal (e.g., drain) of transistor 208 and a control terminal (e.g., gate) of transistor 216. A second current terminal (e.g., source) of transistor 216 is coupled to a first current terminal (e.g., drain) of transistor 214. A second current terminal (e.g., source) of transistor 214 is coupled to a second current terminal of transistor 212. The control terminal of transistor 214 is coupled to the control terminal of transistor 212. Capacitor 218 is coupled between the first current terminal of transistor 216 and the second current terminal of transistor 214 to filter the voltage across transistors 214 and 216.

[0019] If the current flowing through transistor 108 is small (e.g., the current drawn by the load circuit is less than the current required to stabilize sub-regulator loop circuit 102), the current flowing through transistor 206 is small, and the current flowing through transistor 208 is large (e.g., a larger percentage of the current provided by current source 220). The large current flowing through transistors 208, 214, and 216 causes transistor 212 to draw a large current from transistor 108 to stabilize sub-regulator loop circuit 102. When the load circuit draws more current from sub-regulator loop circuit 102, more current provided by current source 220 flows through transistor 206 and less flows through transistor 208, which reduces the current drawn by transistor 212 from transistor 108. If the current drawn by the load circuit exceeds a threshold (defined by current source 220), transistor 212 draws little or no current from transistor 108. Thus, when the load circuit is operating, the transconductance maintainer circuit 204 stabilizes the sub-regulator loop circuit 102 while consuming little or no power.

[0020] Figure 3is a schematic diagram of an example initialization boost circuit 300. Initialization boost circuit 300 is an implementation of initialization boost circuit 106. Initialization boost circuit 300 includes transistors 302, 304, 310, 316, 318, 322, 324, 326, 328, 330, 334, and 338, capacitors 306 and 314, resistors 308, 312, 320, 332, and 340, a logic gate 336, and a clamp circuit 342. Transistors 302, 304, 310, 316, 318, 322, 324, 326, and 328 can be PFETs. Transistors 330, 334, and 338 can be NFETs. When turned on, transistor 302 provides current at AVDD_SR. A first current terminal (e.g., source) of transistor 302 is coupled to VIN. A second current terminal (e.g., drain) of transistor 302 is coupled to AVDD_SR. A control terminal (e.g., gate) of transistor 302 is coupled to transistors 330 and 318. Capacitor 314 is coupled between the control terminal of transistor 302 and VIN to filter the voltage at the control terminal of transistor 302. Transistor 318, transistor 316, and resistor 320 are coupled in series as a current source. Transistor 316 and transistor 318 are diode-connected. A first current terminal (e.g., drain) of transistor 318 is coupled to the control terminal of transistor 302 and the control terminal (e.g., gate) of transistor 318. A first current terminal (e.g., drain) of transistor 316 is coupled to a second current terminal (e.g., source) of transistor 318 and the control terminal (e.g., gate) of transistor 316. Resistor 320 is coupled between VIN and the second current terminal (e.g., source) of transistor 316. Transistor 330 turns on transistor 302 to enable current to flow from VIN to AVDD_SR. A first current terminal (e.g., drain) of transistor 330 is coupled to the control terminal of transistor 302, and a second current terminal (e.g., source) of transistor 330 is coupled to a current source (not shown). The control terminal (e.g., gate) of transistor 330 is coupled to enable circuit 120 for receiving ENABLE. Resistor 332 is coupled between the control terminal of transistor 330 and AVSS. The ENABLE signal turns on transistor 330, which in turn pulls down the control terminal of transistor 302 to enable current flow from VIN to AVDD_SR through transistor 302. During initialization of sub-regulator circuit 100, enable circuit 120 may provide ENABLE (initialization signal) in an on state.

[0021] When ENABLE is in the off state, transistor 304 is coupled to transistor 302 to turn off transistor 302. A first current terminal (e.g., source) of transistor 304 is coupled to VIN, and a second current terminal (e.g., drain) of transistor 304 is coupled to the control terminal of transistor 302. The control terminal (e.g., gate) of transistor 304 is coupled to VIN through resistor 308 and to transistor 334. Transistor 334 controls the turning on of transistor 304. A first current terminal (e.g., drain) of transistor 334 is coupled to the control terminal of transistor 304, and a second current terminal (e.g., source) of transistor 334 is coupled to a current source (not shown). The control terminal (e.g., gate) of transistor 334 is coupled to the output of logic gate 336. When ENABLE and VSUB_AVDD_B are in the off state, logic gate 336 turns on transistor 334, which in turn turns on transistor 304. A first input of logic gate 336 is coupled to enable circuit 120 for receiving ENABLE. A second input of logic gate 336 receives signal VSUB_AVDD_B. VSUB_AVDD_B may be in an on state if the voltage on AVDD_SR needs to be higher than the voltage provided by sub-regulator loop circuit 102. For example, programming memory cells powered by sub-regulator circuit 100 may use a higher voltage than provided by sub-regulator loop circuit 102. When such a higher voltage is required, ENABLE may be in an on state to turn on transistor 302, and VSUB_AVDD_B may be in an on state to turn off transistor 304.

[0022] In the event that the VIN voltage increases rapidly and transistor 302 is intended to be off (e.g., the ENABLE signal is in an off state), the increase in VIN voltage may turn on transistor 302 if transistor 304 is off (e.g., the current source coupled to transistor 334 is not already operating). To prevent such unintended turning on of transistor 302, capacitor 306 is coupled between the control terminal of transistor 304 and the second current terminal of transistor 304. Capacitor 306 diode-connects transistor 304 with respect to transients on VIN. Thus, when the VIN voltage increases rapidly to keep the voltage at the control terminal of transistor 302 close to VIN (keeping transistor 302 off), capacitor 306 causes transistor 304 to act as a diode.

[0023] When transistor 302 is to be turned on, transistor 304 should be turned off. Transistor 310 controls the turning off of transistor 304. A first current terminal (e.g., source) of transistor 310 is coupled to VIN, and a second current terminal (e.g., drain) of transistor 310 is coupled to the control terminal of transistor 304. The control terminal (e.g., gate) of transistor 310 is coupled to VIN through resistor 312 and to transistor 338. Transistor 338 controls the turning on of transistor 310. A first current terminal (e.g., drain) of transistor 338 is coupled to the control terminal of transistor 310, and a second current terminal (e.g., source) of transistor 334 is coupled to AVSS via resistor 340. The control terminal (e.g., gate) of transistor 338 is coupled to enable circuit 120. When ENABLE is in the on state, transistor 338 and transistor 310 are turned on, and transistor 304 is turned off.

[0024] Transistors 322, 324, 326, and 328 are diode-connected and connected in series between VIN and the control terminal of transistor 304 to clamp the voltage at the control terminal of transistor 304 below the voltage at VIN. A first current terminal (e.g., source) of transistor 322 is coupled to VIN, and a second current terminal (e.g., drain) of transistor 322 is coupled to the control terminal (e.g., gate) of transistor 322. A first current terminal (e.g., source) of transistor 324 is coupled to the second current terminal of transistor 322, and a second current terminal (e.g., drain) of transistor 324 is coupled to the control terminal (e.g., gate) of transistor 324. A first current terminal (e.g., source) of transistor 326 is coupled to the second current terminal of transistor 324, and a second current terminal (e.g., drain) of transistor 326 is coupled to the control terminal (e.g., gate) of transistor 326. A first current terminal (eg, source) of transistor 328 is coupled to a second current terminal of transistor 326 , and a second current terminal (eg, drain) of transistor 328 is coupled to a control terminal (eg, gate) of transistor 328 and a control terminal of transistor 304 .

[0025] Clamp circuit 342 is coupled to AVDD_SR. When transistor 302 is turned on, the voltage on AVDD_SR may increase to a voltage greater than the safe operating voltage of the load circuit coupled to sub-regulator circuit 100. To prevent damage due to excessive voltage, clamp circuit 342 sinks current from AVDD_SR if the voltage on AVDD_SR exceeds a threshold. Clamp circuit 342 may be implemented using various circuits. Figure 3, clamp circuit 342 is implemented using transistors 344 and 346, capacitor 348, and resistor 350. Transistor 344 can be a PFET, and transistor 346 can be an NFET. A first current terminal (e.g., source) of transistor 344 is coupled to AVDD_SR. A control terminal (e.g., gate) of transistor 344 is coupled to the gate of transistor 108. A second current terminal (e.g., drain) of transistor 344 is coupled to a control terminal (e.g., gate) of transistor 346. A first current terminal (e.g., drain) of transistor 346 is coupled to AVDD_SR, and a second current terminal of transistor 346 is coupled to AVSS. Capacitor 348 is coupled between AVDD_SR and the control terminal of 346, and resistor 350 is coupled between the control terminal of 346 and AVSS.

[0026] As the voltage on AVDD_SR increases (e.g., due to current flowing through transistor 302), transistor 344 turns on and current flows through 350, generating a voltage that turns on transistor 346. The current flowing through transistor 346 reduces the voltage on AVDD_SR. Capacitor 348 and resistor 350 form a high-pass filter that passes fast transients in the voltage on AVDD_SR to the control terminal of 346.

[0027] Figure 4 is a block diagram of an example voltage reference circuit 400 that includes the sub-regulator circuit 100. The voltage reference circuit 400 includes the sub-regulator circuit 100, a digital circuit 402, and a reference voltage circuit 404. The sub-regulator circuit 100 generates AVDD_SR as described herein and provides AVDD_SR to power the digital circuit 402. The digital circuit 402 may include circuitry, such as logic and data storage devices, for configuring the reference voltage circuit 404. The reference voltage circuit 404 may include a bandgap circuit, a driver circuit, and scaling circuitry to generate a reference voltage at VREF.

[0028] Although voltage reference circuit 400 is provided as an example to illustrate the use of sub-regulator circuit 100, implementations of sub-regulator circuit 100 may be used in any application where a sub-regulator is implemented to power circuitry on an integrated circuit.

[0029] As used herein, the term "coupled" may encompass any connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between devices A and B such that device B is controlled by device A via the control signal generated by device A.

[0030] Moreover, in this specification, the statement “based on” means “based, at least in part, on.” Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0031] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or through a combination thereof.

[0032] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection between or terminations of a device element, circuit element, integrated circuit, device, or other electronic device or semiconductor component.

[0033] Circuits or devices described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacture, for example, by an end user and / or a third party.

[0034] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0035] In the claims, reference may be made to the control input of a transistor and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0036] References herein to a FET being "on" or "enabled" mean that the FET's conductive channel exists and drain current can flow through the FET. References herein to a FET being "off" or "disabled" mean that the conductive channel does not exist, and therefore drain current does not flow through the FET. However, an "off" FET can have current flowing through the transistor's body diode.

[0037] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available before the components were replaced. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0038] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Furthermore, some or all of the features described as being external to the integrated circuit may be included in the integrated circuit, and / or some features described as being internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0039] The use of the phrase "ground" in the foregoing description includes chassis ground, ground line ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, the word "about," "substantially," or "substantially" preceding a parameter means within + / - 10% of the parameter, or if the parameter is zero, then within a reasonable range of values about zero.

[0040] Modifications may be made in the described examples, and other examples are possible, within the scope of the claims.

[0041] Modifications may be made in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A circuit comprising: a first transistor having a first terminal, a second terminal, and a control terminal; A second transistor having: a first terminal coupled to the control terminal of the first transistor; Second terminal; and a control terminal coupled to the second terminal of the first transistor; A third transistor having: a control terminal coupled to the control terminal of the first transistor; a first terminal coupled to a current source; a second terminal coupled to the second terminal of the first transistor; as well as A current mirror circuit comprising: a fourth transistor coupled between the second terminal of the third transistor and a reference voltage terminal; and A fifth transistor is coupled between the current source and the reference voltage terminal.

2. The circuit of claim 1 , further comprising: a sixth transistor having: a first terminal coupled to the first terminal of the third transistor; a second terminal coupled to the fifth transistor; and A control terminal is coupled to the second terminal of the third transistor.

3. The circuit of claim 2 , wherein the current mirror circuit comprises: a seventh transistor having: a first terminal coupled to the second terminal of the sixth transistor; and a control terminal coupled to the first terminal of the seventh transistor; and A second terminal is coupled to the fifth transistor.

4. The circuit of claim 1 , wherein: The fourth transistor has: a first terminal coupled to the second terminal of the third transistor; a second terminal coupled to the reference voltage terminal; and control terminals; and The fifth transistor has: The first terminal is coupled to a second terminal coupled to the second terminal of the fourth transistor; and A control terminal is coupled to the control terminal of the fourth transistor.

5. The circuit of claim 1 , further comprising: a sixth transistor having: a first terminal coupled to the second terminal of the second transistor; a second terminal coupled to the reference voltage terminal; and A control terminal is coupled to a voltage reference circuit.

6. The circuit of claim 1 , further comprising: a sixth transistor having: a first terminal coupled to the first terminal of the first transistor; a second terminal coupled to the second terminal of the first transistor; and Control terminals; a seventh transistor having: a first terminal coupled to the first terminal of the first transistor; a second terminal coupled to the control terminal of the sixth transistor; and Control terminals; a capacitor coupled between the control terminal of the seventh transistor and the second terminal of the seventh transistor; and A resistor is coupled between the first terminal of the seventh transistor and the control terminal of the seventh transistor.

7. The circuit of claim 6, further comprising: eighth, ninth, tenth, and eleventh transistors connected as diodes and coupled in series between the first terminal of the seventh transistor and the control terminal of the seventh transistor; as well as A twelfth transistor having: a first terminal coupled to the first terminal of the seventh transistor; a second terminal coupled to the control terminal of the seventh transistor; and Control terminals; as well as A resistor is coupled between the first terminal of the twelfth transistor and the control terminal of the twelfth transistor.

8. A circuit comprising: a first transistor having a first terminal, a second terminal, and a control terminal; A second transistor having: a first terminal coupled to the control terminal of the first transistor; Second terminal; and a control terminal coupled to the second terminal of the first transistor; A third transistor having: a first terminal coupled to the first terminal of the first transistor; a second terminal coupled to the second terminal of the first transistor; and Control terminals; a fourth transistor having: a first terminal coupled to the first terminal of the first transistor; a second terminal coupled to the control terminal of the third transistor; and Control terminals; a capacitor coupled between the control terminal of the fourth transistor and the second terminal of the fourth transistor; as well as A resistor is coupled between the first terminal of the fourth transistor and the control terminal of the fourth transistor.

9. The circuit of claim 8, further comprising: fifth, sixth, seventh, and eighth transistors connected as diodes and coupled in series between the first terminal of the fourth transistor and the control terminal of the fourth transistor; as well as a ninth transistor having: a first terminal coupled to the first terminal of the fourth transistor; a second terminal coupled to the control terminal of the fourth transistor; and Control terminals; as well as A resistor is coupled between the first terminal of the ninth transistor and the control terminal of the ninth transistor.

10. The circuit of claim 8, further comprising: a fifth transistor having: a control terminal coupled to the control terminal of the first transistor; a first terminal coupled to a current source; a second terminal coupled to the second terminal of the first transistor; as well as A current mirror circuit comprising: a sixth transistor coupled between the second terminal of the fifth transistor and a reference voltage terminal; and A seventh transistor is coupled between the current source and the reference voltage terminal.

11. The circuit of claim 10, further comprising: an eighth transistor having: a first terminal coupled to the first terminal of the fifth transistor; a second terminal coupled to the seventh transistor; and A control terminal is coupled to the second terminal of the fifth transistor.

12. The circuit of claim 11 , wherein the current mirror circuit comprises: a ninth transistor having: a first terminal coupled to the second terminal of the eighth transistor; and a control terminal coupled to the first terminal of the ninth transistor; and A second terminal is coupled to the seventh transistor.

13. The circuit of claim 12, wherein: The sixth transistor has: a first terminal coupled to the second terminal of the fifth transistor; a second terminal coupled to the reference voltage terminal; and control terminals; and The seventh transistor has: a first terminal coupled to the second terminal of the ninth transistor; a second terminal coupled to the second terminal of the sixth transistor; and A control terminal is coupled to the control terminal of the sixth transistor.

14. The circuit of claim 8, further comprising: a fifth transistor having: a first terminal coupled to the second terminal of the second transistor; a second terminal coupled to a reference voltage terminal; and A control terminal is coupled to the voltage reference terminal.

15. A sub-regulator circuit comprising: a sub-regulator loop circuit comprising a first pass transistor configured to provide a regulated output voltage at a voltage output terminal; a transconductance maintainer circuit coupled to the voltage output terminal, the transconductance maintainer circuit being configured to: sensing a first current flowing through the first pass transistor; as well as drawing a second current from the voltage output terminal in response to the first current being less than a threshold current; as well as An initialization boost circuit is coupled to the voltage output terminal, the initialization boost circuit including a second pass transistor configured to provide a third current to the voltage output terminal in an initialization interval.

16. The sub-regulator circuit of claim 15 , wherein the transconductance maintainer circuit comprises: a sense transistor coupled to the first pass transistor, the sense transistor configured to pass a current proportional to the first current; and A current mirror circuit is coupled to the voltage output terminal and the sense transistor, the current mirror circuit being configured to draw the second current from the voltage output terminal, wherein the second current is the threshold current less than the first current. 17 . The sub-regulator circuit of claim 16 , wherein the transconductance maintainer circuit is configured to not draw current from the voltage output terminal in response to the first current exceeding the threshold current.

18. The sub-regulator circuit of claim 15, wherein the initializing the boost circuit comprises: a first transistor having a first terminal coupled to a power supply terminal, a second terminal coupled to the voltage output terminal, and a control terminal, wherein the first transistor is configured to provide current to the voltage output terminal in response to an initialization signal being in an on-state; a second transistor having a first terminal coupled to the power terminal, a second terminal coupled to the control terminal of the first transistor, and a control terminal, the second transistor being configured to turn off the first transistor in response to the initialization signal being in an off state; as well as A capacitor having a first terminal coupled between the control terminal of the second transistor and the second terminal of the second transistor, the capacitor being configured to diode-connect the second transistor.

19. The sub-regulator circuit of claim 18 , wherein the initialization boost circuit comprises a third transistor having a first terminal coupled to the power terminal and a second terminal coupled to the control terminal of the second transistor, the third transistor being configured to turn off the second transistor in response to the initialization signal being in the on-state.

20. The sub-regulator circuit of claim 18, wherein the initialization boost circuit comprises third, fourth, fifth, and sixth transistors connected as diodes and coupled in series between the first terminal of the second transistor and the control terminal of the second transistor.

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