System, server, method, medium and program product for sharing memory resource pool

Abstract

This application discloses a system, server, method, medium, and program product for sharing a memory resource pool, relating to the field of artificial intelligence. The system includes: connecting multiple switching components of a switch to processors and a memory resource pool of multiple computer devices, with multiple computer devices sharing the memory resources of the memory resource pool through the switch to allocate different memory capacities based on the needs of the computer devices. This not only enables dynamic allocation and efficient sharing of memory resources, improving overall system memory utilization, but also reduces the latency of computer devices accessing memory, ensuring the consistency of shared memory across multiple computer devices, and meeting the needs of various computing scenarios. This solves technical problems in existing server collaborative computing methods based on RDMA (Remote Direct Memory Access) technology, such as high transmission latency, inability to meet the needs of various computing scenarios, inability to ensure the consistency of shared memory across multiple computer devices, and low resource utilization.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence technology, and in particular to a system, server, method, medium, and program product for a shared memory resource pool. Background Art

[0002] With the rapid development of artificial intelligence, from the explosive popularity of ChatGPT to the rise of large multimodal models, AI technology is reshaping various industries. Against this backdrop, distributed computing and reasoning technologies are also facing new challenges and opportunities. On the one hand, computing systems require high-performance CPUs (Central Processing Units), and on the other hand, they also require high-bandwidth, low-latency memory systems as support.

[0003] Among related technologies, most traditional server collaborative computing systems use RDMA (Remote Direct Memory Access) technology. RDMA technology allows networked computer devices to directly access each other's main memory without involving the processor, cache or operating system, thereby reducing the CPU load. It is very suitable for high-performance applications that require high-speed data transmission. However, the latency of RMDA transmission is relatively large, basically at the us level, which does not meet computing scenarios such as fast response, real-time analysis, and distributed databases. It also cannot guarantee the consistency of shared memory among multiple computer devices. When multiple processors or nodes try to access the same memory area at the same time, the cache of each processor or node may store different versions of the same memory address, which will lead to inconsistent cached data and cannot be applied to high-performance collaborative computing scenarios. Summary of the Invention

[0004] The present application provides a system, server, method, medium and program product for a shared memory resource pool to at least address the problems of server collaborative computing methods based on RDMA technology in related technologies, such as large transmission delays, inability to meet the needs of various computing scenarios, inability to ensure the consistency of shared memory of multiple computer devices, and low resource utilization.

[0005] The present application provides a system for sharing a memory resource pool, comprising: a memory resource pool, the memory resource pool including multiple memory sticks; multiple computer devices, each computer device including multiple processors; a switch, the switch including multiple switching components, different processors of each computer device connected to different switching components, each switching component including multiple uplink ports and multiple downlink ports, each uplink port of each switching component connected to a different computer device, and each downlink port of each switching component connected to a different memory stick, the multiple computer devices share memory resources of the memory resource pool through the switch, the multiple switching components are redundant components, and when any switching component fails, the computer device obtains memory resources of the memory resource pool through other switching components.

[0006] The present application also provides a server, including: a system of a shared memory resource pool as in the above embodiment.

[0007] The present application also provides a system memory allocation method for a shared memory resource pool, which is applied to the system of the shared memory resource pool of the above embodiment, and the switch is correspondingly provided with a command line interface, and the user selects the memory allocation working mode of the memory resource pool through the command line interface, wherein the memory allocation working mode includes any one of a direct memory allocation mode, a pooled memory allocation mode and a shared memory allocation mode, including: if the memory allocation working mode is the direct memory allocation mode, detecting whether the downlink port of the switching component recognizes the memory stick; if the downlink port of the switching component recognizes the memory stick, using multiple direct memory allocation units to determine the memory allocation path, wherein each memory allocation path is: the direct memory allocation unit is respectively connected to a memory stick and a computer device; a memory stick is allocated to a computer device through the memory allocation path; if the memory allocation working mode is the pool When the memory allocation mode is the shared memory allocation mode, it is detected whether the downstream port of the switching component recognizes the memory stick. If the downstream port of the switching component recognizes the memory stick, the address of the memory stick is divided into multiple segments, and multiple pooled memory allocation units are used to determine the memory allocation path. Each memory allocation path is: multiple pooled memory allocation units allocate and connect one memory stick and multiple computer devices, and each segment is allocated to one computer device through the memory allocation path; if the memory allocation working mode is the shared memory allocation mode, it is detected whether the downstream port of the switching component recognizes the memory stick. If the downstream port of the switching component recognizes the memory stick, multiple shared memory allocation units are used to determine the memory allocation path, wherein each memory allocation path is: multiple shared memory allocation units allocate and connect one memory stick and multiple computer devices, and one memory stick is simultaneously allocated to multiple computer devices through the memory allocation path.

[0008] The present application also provides a system power-on method for a shared memory resource pool, which is applied to the system of the shared memory resource pool of the above embodiment, including: connecting multiple computer devices, switches and memory resource pools to a power supply; pressing the power button of the switch, the control unit of the switch controls the switch to start power-on initialization, and the control unit sends switch initialization completion information to the first baseboard management controller of the switch; after the first baseboard management controller recognizes the switch initialization completion information, it sends a power-on instruction to the second baseboard management controller of the memory resource pool, the second baseboard management controller of the memory resource pool controls the memory resource pool to start power-on initialization, and the second baseboard management controller sends memory resource pool initialization completion information to the first baseboard management controller; after the first baseboard management controller recognizes the memory resource pool initialization completion information, it scans multiple memory bars in the memory resource pool and allocates memory to each upstream port according to a pre-set memory allocation mode; the first baseboard management controller sends a power-on instruction to each computer device, each computer device starts power-on initialization, and after each computer device is initialized, it obtains memory from each upstream port.

[0009] This application connects multiple computer processors and memory resource pools through multiple switching components of a switch. Multiple computer devices share the memory resources of the memory resource pool through the switch to allocate different memory capacities according to the needs of the computer devices. This not only achieves dynamic allocation and efficient sharing of memory resources, improving the memory utilization of the entire system, but also reduces the latency of computer devices accessing memory, ensuring the consistency of shared memory among multiple computer devices, and can meet the needs of various computing scenarios with high applicability. This solves the technical problems of the existing server collaborative computing method based on RDMA technology, such as large transmission delay, inability to meet the needs of various computing scenarios, inability to ensure the consistency of shared memory among multiple computer devices, and low resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0011] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A schematic diagram of a prior art solution of an embodiment of the present application;

[0013] Figure 2A system block diagram of a shared memory resource pool provided in an embodiment of the present application;

[0014] Figure 3 A system topology diagram of a shared memory resource pool for computer devices provided in an embodiment of the present application;

[0015] Figure 4 A diagram of the entire cabinet deployment of the shared memory resource system provided in an embodiment of the present application;

[0016] Figure 5 A schematic diagram of a direct memory allocation mode provided in an embodiment of the present application;

[0017] Figure 6 Schematic diagram of the pooled memory allocation mode provided in an embodiment of the present application;

[0018] Figure 7 A schematic diagram of a shared memory allocation mode provided in an embodiment of the present application;

[0019] Figure 8 A PCIe resource allocation diagram for a computer device provided in an embodiment of the present application;

[0020] Figure 9 A block diagram of a switch node provided in an embodiment of the present application;

[0021] Figure 10 A switch board layout diagram provided in an embodiment of the present application;

[0022] Figure 11 A diagram showing the downstream port connections of a switch provided in an embodiment of the present application;

[0023] Figure 12 This is a diagram of the switch uplink port connection provided in the embodiment of the present application;

[0024] Figure 13 A block diagram of the memory resource pool provided in an embodiment of the present application;

[0025] Figure 14 A schematic diagram of the memory allocation layer provided in an embodiment of the present application;

[0026] Figure 15 A system data network topology diagram provided in an embodiment of the present application;

[0027] Figure 16 A topology diagram of the system management network provided in the embodiment of the present application;

[0028] Figure 17 A flowchart of a system memory allocation method for a shared memory resource pool provided in an embodiment of the present application;

[0029] Figure 18Memory allocation workflow diagram provided for an embodiment of the present application;

[0030] Figure 19 A flowchart of a system power-on method for a shared memory resource pool provided in an embodiment of the present application;

[0031] Figure 20 A schematic diagram of the power-on sequence of the entire cabinet provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0034] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0035] like Figure 1 As shown in the diagram of related technology (1), in which memory access is performed via RDMA, the data in the memory can bypass the CPU and be directly accessed via the RDMA network card, thereby greatly improving the data transmission rate and releasing the CPU workload. However, the following defects still exist:

[0036] (1) Although RDMA technology can increase data transmission rates without CPU involvement, the transmission delay between systems is large. Depending on the transmission protocol, the delay is generally between a few microseconds and tens of microseconds, which does not meet the requirements of computing scenarios such as fast response, real-time analysis, and distributed databases.

[0037] (2) It cannot guarantee the consistency of shared memory across multiple computer devices. When multiple processors or nodes attempt to access the same memory area simultaneously, cache inconsistencies may occur. The cache of each processor or node may store different versions of the same memory address, which can lead to data inconsistency. For example, a CPU may use RDMA to modify the value of a memory area, but other CPUs may still read the previous data in their cache. Therefore, RMDA cannot guarantee memory consistency and is not suitable for high-performance collaborative computing scenarios.

[0038] In the related technology (2), large-capacity memory expansion is mainly carried out through CXL switch (Compute Express Link switch). However, the current technology is based on the expansion of a single computer device. When allocating memory, each memory stick can only be allocated to one computer device for use, and does not support memory sharing by multiple computer devices.

[0039] Therefore, to address the aforementioned issues of large transmission delays and memory inconsistencies in RDMA technology, this application designs a system architecture for multiple computer devices to share a memory resource pool based on CXL high-speed interconnect technology, allowing multiple computer devices to access the same memory resource pool, thereby achieving dynamic allocation and efficient sharing of memory resources. This system can provide greater memory bandwidth and higher memory capacity density, and can allocate different memory capacities based on the needs of computer devices, thereby improving the memory utilization of the entire system and solving the current problem of low server memory utilization. This system can also allocate the same memory resources to different computer devices for collaborative use, thereby accelerating large-scale data processing and analysis, optimizing memory resource allocation and management, and improving data processing efficiency.

[0040] Specifically, an embodiment of the present application provides a system for a shared memory resource pool, and the system is described in detail in conjunction with the operation process of the system for the shared memory resource pool.

[0041] Figure 2 A block diagram of a system for sharing a memory resource pool provided in an embodiment of the present application.

[0042] like Figure 2 As shown, the system for sharing a memory resource pool includes: a computer device 100 , a memory resource pool 200 and a switch 300 .

[0043] Among them, the memory resource pool 200 includes multiple memory bars, the computer device 100 includes multiple, each computer device 100 includes multiple processors, the switch 300 includes multiple switching components, different processors of each computer device 100 are connected to different switching components, each switching component includes multiple uplink ports and multiple downlink ports, each uplink port of each switching component is connected to a different computer device 100, and each downlink port of each switching component is connected to a different memory bar. Multiple computer devices 100 share the memory resources of the memory resource pool 200 through the switch 300, and multiple switching components are redundant components. When any switching component fails, the computer device 100 obtains the memory resources of the memory resource pool 200 through other switching components.

[0044] It can be understood that the embodiments of the present application can be connected to the processors and memory resource pools of multiple computer devices through multiple switching components of the switch. Multiple computer devices share the memory resources of the memory resource pool through the switch to allocate different memory capacities according to the needs of the computer devices. This not only realizes the dynamic allocation and efficient sharing of memory resources and improves the memory utilization of the entire system, but also reduces the latency of computer devices accessing memory, ensures the consistency of shared memory among multiple computer devices, can meet the needs of various computing scenarios, and has high applicability.

[0045] It should be noted that the computer device in this application includes multiple processors, and the switch includes multiple switching components. This application is explained using two processors and switching components as specific embodiments, but in actual applications, multiple processors and multiple switching components can perform corresponding operations without specific limitations.

[0046] Specifically, if Figure 3 As shown, this application can use two CXL2.0 switch chips to build a system topology that supports multiple computer devices sharing a memory resource pool, including computer devices, CXL switches, and a memory resource pool. This topology provides standardized fabric management and centralized network interaction management, supports dynamic memory allocation, and enables multiple computer devices to efficiently share and manage the memory pool.

[0047] The host compute node consists of eight computers, each with CPU0 and CPU1, forming a dual-socket system. Each computer is equipped with a 100G network card that connects to a network switch for system management and inter-computer communication. The computer's baseboard management (BMC) provides out-of-band management and monitoring of the system and connects to a network switch for remote system management and maintenance. Each computer's CPU0 is interconnected to CXL switch0, and each computer's CPU1 is interconnected to CXL switch1. This topology offers the advantage of continuous memory resource availability from the remaining switch even if one switch fails, improving system reliability.

[0048] The switch consists of two CXL2.0 switch chips, a BMC, an MCU (Microcontroller Unit), and a 25G network interface card. A single CXL2.0 switch chip supports 256 GEN5 lanes, representing 16 x16 PCIe lanes (P0-P15) in the diagram. Each switch chip has eight uplink ports (P13, P12, P9, P8, P3, P2, P15, P14) and eight downlink ports (P11, P10, P7, P6, P5, P4, P1, P0). The uplink ports are configured at x16 bandwidth, while the downlink ports are configured at 2x8 bandwidth. The switch's BMC supports out-of-band management and system monitoring within the node itself. It also serves as the management center for the entire system. Monitoring information from each node is transmitted to the switch's BMC over the network for fault diagnosis, logging, and centralized maintenance management. The switch node's MCU manages the entire fabric. It receives memory request signals from each node, allocates memory, controls the switch's memory allocation routing, manages downstream devices, and monitors the switch's operating status. An external 25-bit network card can be connected to the network switch for system management and communication between computer devices.

[0049] The Memory Box is a memory resource pool that supports 64 DIMMs (Dual Inline Memory Modules) to form a memory resource pool. If 256GB DIMMs are used, the memory pool can support 16TB. The memory resource pool supports 16 2x8 interfaces that interconnect with the downstream ports of the switch. Each x8 interface can connect to two DIMMs. DIMM types can be UDIMMs (Unbuffered DIMMs), RDIMMs (Registered DIMMs), or LRDIMMs (Load-Reduced DIMMs). The Baseboard Management Controller (BMC) manages and monitors the memory box memory resource pool. The BMC's network connection can be connected to the network switch for system management.

[0050] like Figure 4 As shown in the figure, the shared memory resource system occupies a total of 23U of cabinet space. The top layer houses the data TOR (Top of Rack) and management TOR switches, each occupying 1U of space. Each computer device is 2U high, the switch is 2U high, and the memory resource pool is 2U high. 1U of cabling space is reserved for easy wiring.

[0051] The system networks of computer equipment and switches can be connected to the data TOR for unified management and data exchange. The network output from the BMC of each node can be connected to the management TOR for unified out-of-band management of the entire cabinet.

[0052] The CXL switch is placed in the center. To maximize and balance SI signals, the memory resource pool is deployed immediately below it, interconnected using 350mm cables supporting Gen5 CDFP or ASM speeds. To balance the cable lengths between each computer device and the CXL switch, computers 0-3 are deployed above it, and computers 4-7 are deployed below it. They connect to the CXL switch using a unified 900mm cable supporting Gen5 CDFP (Copper Direct Attach Form Factor Pluggable) or ASM (Advanced Signal Module). 1U of cabling space is reserved for network and power cables, facilitating overall cable management.

[0053] In an embodiment of the present application, the switch 300 is correspondingly provided with a command line interface, and the user selects the memory allocation working mode of the memory resource pool through the command line interface, wherein the memory allocation working mode includes any one of a direct memory allocation mode, a pooled memory allocation mode and a shared memory allocation mode.

[0054] It can be understood that in the embodiment of the present application, the user selects the memory allocation working mode of the memory resource pool through the command line interface. The user can switch different memory allocation modes in real time through the command line interface according to the current task requirements, thereby enhancing the system flexibility and controllability, meeting the needs of various application scenarios, and having high applicability.

[0055] It should be noted that this application supports three modes: direct memory allocation, pooled memory allocation, and shared memory allocation. Users can select the specific working mode through the CLI (Command-Line Interface) command.

[0056] In an embodiment of the present application, each switching component includes multiple direct memory allocation units. When the memory allocation working mode is the direct memory allocation mode, the switching component is configured to perform the following steps: detecting whether the downstream port of the switching component recognizes the memory stick; if the downstream port of the switching component recognizes the memory stick, using multiple direct memory allocation units to determine the memory allocation path, wherein each memory allocation path is: the direct memory allocation unit is respectively connected to a memory stick and a computer device; and a memory stick is allocated to a computer device through the memory allocation path.

[0057] It can be understood that in the embodiment of the present application, the direct memory allocation unit is respectively connected to a memory stick and a computer device, and a memory stick is allocated to a computer device through a memory allocation path. Since each memory stick is exclusively allocated to a computer device, there is no concurrent competition, so the access delay is the lowest and the bandwidth is the largest, which is suitable for high-performance computing tasks, thereby achieving low-latency, high-bandwidth, and exclusive memory access.

[0058] Specifically, if Figure 5 As shown in the figure, D2H (direct map to host) is the switch's direct memory allocation unit. After the downstream interface of the Compute Express Link Switch (CXL SW) identifies memory, the same memory can be allocated to the same compute device through the D2H functional module. CXL M0 allocates memory to compute device 7 through D2H0, and CXLM3 allocates memory to compute device 1 through D2H15. This system supports 16 D2H modules, implementing different allocation paths. Direct memory allocation mode is suitable for scenarios with fluctuating memory requirements, such as high-performance computing.

[0059] In an embodiment of the present application, each switching component includes multiple pooled memory allocation units. When the memory allocation working mode is the pooled memory allocation mode, the switching component is configured to perform the following steps: detect whether the downstream port of the switching component recognizes the memory stick; if the downstream port of the switching component recognizes the memory stick, the address of the memory stick is divided into multiple segments, and the memory allocation path is determined using multiple pooled memory allocation units. Each memory allocation path is: multiple pooled memory allocation units allocate and connect a memory stick and multiple computer devices; each segment is allocated to a computer device through the memory allocation path.

[0060] It can be understood that in the embodiment of the present application, multiple pooled memory allocation units are allocated and connected to a memory stick and multiple computer devices, and each segment is allocated to a computer device through a memory allocation path. By dividing the memory stick into multiple segments and flexibly allocating them, the waste of memory resources under traditional methods is avoided, and fine-grained memory allocation strategies are supported to meet the needs of different application scenarios and improve resource utilization.

[0061] Specifically, if Figure 6 As shown in the figure, in the pooled memory allocation mode, P2H (poolmap to host) is the pooled memory allocation unit of the switch. After the downstream interface of CXL SW recognizes the memory, it divides the memory address into three segments. Each segment can be allocated to the same computer device through the P2H function module. Figure 20 In this example, CXL M0_A and CXL M1_C are distributed to computer device 0 via P2H0 and P2H3, respectively. This system supports up to 16 P2H modules, enabling different allocation paths. Pooled memory allocation is suitable for scenarios with minimal memory demand fluctuations and sensitive resource utilization, such as edge computing.

[0062] In an embodiment of the present application, each switching component includes multiple shared memory allocation units. When the memory allocation working mode is the shared memory allocation mode, the switching component is configured to perform the following steps: detecting whether the downstream port of the switching component recognizes the memory stick; if the downstream port of the switching component recognizes the memory stick, using multiple shared memory allocation units to determine the memory allocation path, wherein each memory allocation path is: multiple shared memory allocation units allocate and connect a memory stick and multiple computer devices; and a memory stick is simultaneously allocated to multiple computer devices through the memory allocation path.

[0063] It can be understood that in the embodiment of the present application, multiple shared memory allocation units allocate and connect one memory stick and multiple computer devices, and allocate one memory stick to multiple computer devices at the same time through the memory allocation path. Multiple computer devices can access the same memory stick at the same time, thereby improving resource utilization. The CXL protocol is used to ensure data consistency when multiple computer devices access the same memory, thereby realizing memory resource sharing and improving system collaboration efficiency.

[0064] Specifically, if Figure 7 As shown in the figure, in shared memory allocation mode, L2G (local to global) is the switch's shared memory allocation unit. After the CXL SW's downstream interface identifies the memory, it can be allocated to different computers through the L2G functional module. CXL M1 is simultaneously allocated and occupied by computers 0, 1, and 7. Shared memory allocation mode is suitable for collaborative computing scenarios such as distributed databases and real-time analytics.

[0065] In an embodiment of the present application, the power-on sequence of the system includes: multiple computer devices, switches and memory resource pools are connected to the power supply; the power button of the switch is pressed, the control unit of the switch controls the switch to start power-on initialization, and the control unit sends the switch initialization completion information to the first baseboard management controller of the switch; after the first baseboard management controller recognizes the switch initialization completion information, it sends a power-on instruction to the second baseboard management controller of the memory resource pool, the second baseboard management controller of the memory resource pool controls the memory resource pool to start power-on initialization, and the second baseboard management controller sends the memory resource pool initialization completion information to the first baseboard management controller; after the first baseboard management controller recognizes the memory resource pool initialization completion information, it scans multiple memory bars in the memory resource pool and allocates memory to each upstream port according to a pre-set memory allocation mode; the first baseboard management controller sends a power-on instruction to each computer device, each computer device starts power-on initialization, and after each computer device is initialized, it obtains memory from each upstream port.

[0066] It can be understood that the embodiments of the present application can achieve orderly power-on and initialization of computer devices, switches, and memory resource pools in the system through the coordinated operation between the control unit of the switch and multiple baseboard management controllers, ensuring that the entire system can efficiently and safely complete resource configuration during the startup process, and perform dynamic memory mapping according to the preset memory allocation mode, thereby improving the stability, reliability and resource scheduling efficiency of the system.

[0067] In an embodiment of the present application, the computer device includes a third baseboard management controller and a fourth baseboard management controller, wherein the third baseboard management controller and the fourth baseboard management controller are both used for out-of-band management and status control of the computer device, and the fourth baseboard management controller and the third baseboard management controller serve as backup for each other.

[0068] It can be understood that in the embodiment of the present application, the third baseboard management controller and the fourth baseboard management controller are both responsible for out-of-band management and status control of computer equipment; the two baseboard management controllers serve as backup for each other, ensuring that when any one fails, its functions can be seamlessly taken over, ensuring the continuous operation of the system, thereby improving the reliability and availability of the system.

[0069] It should be noted that BMC allows administrators to remotely monitor, diagnose and repair system problems even when the operating system is unresponsive or the hardware fails. Specifically: Remote monitoring: Through a dedicated management interface, administrators can monitor the system health status in real time, such as temperature, voltage, fan speed, etc.; Remote control: Even if the operating system is unresponsive or the hardware fails, administrators can perform operations such as restart, shutdown, and startup through BMC; Logging: BMC will record system events and alarms to help administrators troubleshoot and analyze problems; Firmware update: Supports firmware updates through the first controller to ensure that system components are kept up to date; Virtual media: Allows administrators to mount virtual optical drives or disk drives for installing operating systems or other maintenance operations; Provides remote keyboard, video and mouse access, allowing administrators to fully control the server from a remote location.

[0070] In an embodiment of the present application, the computer device further includes a first communication component, a storage component, a power supply component, a mainboard, a heat dissipation component, and an interface component.

[0071] It can be understood that the first communication component of the computer device in the embodiment of the present application is used to realize data communication inside and outside the device, the storage component is used to store the operating system, application programs and temporary data; the power supply component provides a stable power supply for the entire device, the motherboard is used to connect and coordinate the work of all hardware components, the heat dissipation component is used to maintain the device operating within a safe temperature range, and the interface component is used to provide a human-computer interaction interface to realize connection and data exchange with external devices.

[0072] It should be noted that the first communication component includes: NIC (Network Interface Card), also known as 100G network card, CXL Retimer (Compute Express Link Retimer), OCP NIC (Open Compute Project Network Interface Card), MCIO (Multi-Channel IO) connector to achieve high-speed communication, CXL interconnection, and protocol extension. Among them, NIC is used to connect to the external network and supports Ethernet, Fibre Channel, etc. The front CXL retimer card can enhance the signal strength to ensure that the data can remain intact after long-distance transmission. It can also regenerate the clock signal to reduce jitter in signal transmission, thereby improving the stability and accuracy of transmission. Network cards typically support high-speed Ethernet (such as 25Gbps, 100Gbps or even higher), which can meet the high throughput requirements of modern data centers. By optimizing hardware design and drivers, OCP network cards can provide lower network latency, which is crucial for applications that require fast response (such as real-time data analysis). OCP network cards adopt a standardized design, which is convenient for hot-swappable operations in servers. Network cards can be replaced or upgraded without shutting down the system, improving system maintainability. The MCIO connector is a high-performance, high-bandwidth interface mainly used in servers and computing devices to achieve high-speed data transmission between the motherboard and external expansion modules. It can simultaneously support multiple PCIe channels (such as x8, x16, etc.), which enables it to provide higher total bandwidth. A signal regenerator can be integrated to enhance signal quality in long-distance transmission and reduce signal attenuation and jitter.

[0073] Storage components include NVMe (Non-Volatile Memory Express) hard drives and M.2 SSDs (M.2 Solid State Drives), which are used to achieve persistent data storage and high-speed reading and writing.

[0074] The power supply components include the PSU (Power Supply Unit) and HPCE (High Power Connector Extension) connector, which provide stable power and support redundancy. The motherboard includes the CPU, DIMMs, VR (Voltage Regulator), MCIO, BMC, CPLD (Complex Programmable Logic Device), and UPI (Ultra Path Interconnect) bus, carrying all key functions.

[0075] The heat dissipation component includes a fan module, which is used to control the device temperature and maintain stable operation. The interface components include: front and rear panel interfaces, UART (Universal Asynchronous Receiver / Transmitter) / VGA (Video Graphics Array) / BMC signal interfaces, which are used to provide human-computer interaction, peripheral access, and remote management.

[0076] Specifically, if Figure 8 As shown, the computer equipment includes a 100G network card, a front-mounted CXL retimer card, a hard drive backplane, a motherboard, a 6056 fan module, a management board, a power supply unit (PSU), and a rear-mounted PCIe (Peripheral Component Interconnect Express) module. The motherboard also includes two CPUs, 24 DIMMs, a CPU VR, a high-speed MCIO connector, a baseboard management (BMC) module, and a CPLD logic chip.

[0077] A single CPU supports at least 88 GEN5 PCIe lanes (fifth generation PCIe data lanes). All PCIe resources are connected to the MCIO connector on the motherboard. The two x16 PCIe resources on the GenZ4c+ connector are used to interconnect the CPU and the Compute Express Link Switch (CXLSW). The remaining PCIe resources are used to connect to computer I / O modules such as hard drives, PCIe network cards, and OCP network cards. CPU0 and CPU1 are interconnected via six UPI buses, each with a 24GT / s UPI rate. The south side of the CPU module is designed to dock with the hard drive backplane, using a GenZ 4C+ splint connector that supports up to x32 lanes of PCIe connectivity. A High Power Connector Extension (HPCE) power connector is also reserved for southbound power supply to the motherboard.

[0078] The BMC is used for out-of-band management and control of computer equipment and server systems. It transmits signals such as UART, VGA, and RGMII (Reduced Gigabit Media Independent Interface) to the front I / O panel. Furthermore, the BMC communicates with the CPU via ESPI (Enhanced Serial Peripheral Interface), PECI (Processor Edge Connectivity Interface), and SPI (Serial Peripheral Interface) signals for system information exchange. The CPLD controls the system's power-on logic, fan speed, and signal forwarding, exchanging data with the BMC via I2C (Inter-Integrated Circuit) and UART. This motherboard also includes a reserved BMC for interconnection with CPU1, supporting independent partitioning of CPU0 and CPU1.

[0079] CPU0's PE2 is connected to a 100G network card via a high-speed cable for network communication. PE1 is connected to an M.2 riser via a high-speed cable to store the operating system and the BMC for system VGA display. PE0 on CPU0 and CPU1 is connected to four NVMe drives for system data storage. PE2 on CPU1 is connected to an OCP network card via a cable. PE3 on CPU0 and CPU1 is connected to a CXL retimer card via a high-speed cable to CXL SW0 and CXL SW1, respectively. The remaining PCIe ports are exposed via x8 MCIO connectors.

[0080] The front panel of the computer supports one 100G network card, two CXL retimer cards, and eight NVMe hard drives. Left and right mounting brackets are used for power buttons, serial port debugging, and daily KVM (Keyboard, Video, Mouse) maintenance. The top panel houses the retimer card from CPU0, interconnected to CXL SW0. The bottom panel houses the retimer card from CPU1, interconnected to CXL SW1. The rear panel of the computer supports 1+1 redundancy for the PSU, allowing remote management of the computer via the management network port. PCIe cards can be connected to the CXL retimer card, interconnected to CXL SW.

[0081] In an embodiment of the present application, the switch includes a first controller, which is connected to a plurality of switching components respectively, and is used to control the operating status of the plurality of switches.

[0082] The first controller is an MCU (Microcontroller Unit), which is not specifically limited.

[0083] It can be understood that in the embodiment of the present application, the first controller is connected to all switching components for unified management and control of the operating status of these switching components. The controller can monitor the status of the switching components in real time, and promptly issue an alarm or switch to a backup path when an abnormality occurs in a component, thereby realizing centralized control and unified management of the entire switching system and improving system management efficiency.

[0084] It's important to note that the switching components of a switch are modular and hot-swappable, allowing individual switching devices to be replaced or upgraded as needed without replacing the entire system. A switch, which can be a CXL switch, PCIe switch, or other type of switching chip / module, is responsible for efficiently routing and sharing data between multiple computing devices.

[0085] The switch chassis supports two switch nodes and slides out forward for easy assembly and maintenance. The switch uses the CXL2.0 switch chip as the core data exchange center, primarily responsible for data exchange and serving as the heart of the entire system. A single system supports up to two switches. Each switch chip includes 16 ports, with a single full-duplex rate of up to 128 GB / s.

[0086] Specifically, if Figure 9 As shown, the first controller is an MCU, which manages the switch fabric via I2C and PCIe buses, including obtaining switch status, port types, setting speed and bandwidth, and setting memory allocation mode. The MCU directly outputs a Gen3 x8 PCIe interface to interconnect with a 25G network card for system network management.

[0087] In an embodiment of the present application, the switch further includes a first baseboard management controller and a second communication component. The first baseboard management controller is used for out-of-band management and status monitoring of the switch, and the second communication component is used for transmitting communication data of the switch.

[0088] It can be understood that the first baseboard management controller in the embodiment of the present application is used for out-of-band management and status monitoring of the switch, and can still perform management and monitoring even when the system is down or the operating system is unavailable; the second communication component is used to transmit the communication data of the switch, and is responsible for efficient data transmission within the switch and between other devices, improving data transmission efficiency, and enhancing the maintainability and reliability of the system.

[0089] It should be noted that the first baseboard management controller is BMC, and the second communication component includes: 25G network card, CXL SW0, CXL SW1, PHY (Physical Layer) and RJ45 (Registered Jack-45) interface. Among them, the 25G network card provides high-speed network communication capabilities and is connected to the MCU through the Gen3 x8 PCIe interface for system network management; CXL SW0 and CXL SW1 are connected to the MCU through the PCIe interface to realize CXL switching function, supporting high-speed data transmission and memory sharing; PHY processes the physical layer conversion of Ethernet signals, connects to the BMC through the RGMII interface, and converts the signals into MDI (Medium Dependent Interface) signals; the RJ45 interface provides a standard Ethernet physical interface for connecting external network devices to realize the BMC management network.

[0090] Specifically, if Figure 10As shown in the figure, the BMC is responsible for out-of-band management and monitoring of the switch node. It interconnects a PHY chip via RGMII, converts the signal to MDI and connects it to the RJ45 port for the BMC's management network. The MCU and BMC can be connected via the eSPI interface to transmit power-on signals, control logic signals, and other signals.

[0091] In an embodiment of the present application, the memory resource pool includes multiple memory ports, and the multiple memory ports are respectively connected to the downlink ports of the switch.

[0092] It can be understood that the embodiments of the present application are connected to the downstream ports and memory resource pool of the switching device through multiple memory ports respectively. By connecting the memory ports to the downstream ports and memory resource pool of the switching device, efficient data transmission and flexible sharing of memory resources are achieved, thereby improving memory utilization and data access efficiency, reducing redundant configuration, and reducing costs.

[0093] It should be noted that a memory resource pool is a physical entity or logical unit dedicated to storing and managing large amounts of memory resources, typically consisting of multiple memory devices. The third device body can be understood as a chassis, slot structure, or motherboard platform for mounting and integrating multiple memory devices. These memory devices can be standard DDR (Double Data Rate) memory modules, CXL memory expansion modules, or other types of high-speed memory devices. This centralized design simplifies wiring, improves heat dissipation, and facilitates unified management and maintenance. Standardized layout and wiring design helps ensure signal integrity, reduce latency variations, and improve system stability and performance consistency.

[0094] Specifically, if Figure 11 As shown in the figure, the switch board layout uses a daughter card connector and a x16 MCIO cable to connect eight SW ports, with the remaining eight ports connected internally on the PCB. Port interfaces use CDFP or ASM connectors that support PCIe Gen5 speeds. The x4 MCIO ports are used for SW management, control, and status monitoring. The power connector provides P12V and P3V3_STBY power to the switch.

[0095] In the embodiment of the present application, the switch 300 includes multiple downlink ports, wherein the multiple downlink ports of the switch are cross-interconnected with the multiple memory ports of the memory resource pool.

[0096] It can be understood that the embodiment of the present application uses cross-interconnection to enable the switch to dynamically select the optimal path to access memory resources according to actual needs, balance the length and load of each link, thereby reducing delay differences and jitter in signal transmission, supporting the access of multiple computing nodes or storage devices, improving system expansion capabilities, achieving efficient data transmission and memory resource sharing, and improving system performance.

[0097] Specifically, the port connection between the switch and the memory resource pool is as follows: Figure 11 As shown in the figure, switches A8-A15 and B8-B15 are configured in downlink mode. Because the cable lengths within each port board vary, a crossover method is used for interconnection to balance SI link loss. The cable length is uniformly 350 mm.

[0098] Switch and computer equipment port connection Figure 12 As shown in the figure, switches A0-A7 and B0-B7 are configured in uplink mode. Switches A0-A8 are connected to CPU0 of eight computers, and switches B0-B8 are connected to CPU1 of eight computers. The cables are all 900 mm long.

[0099] In an embodiment of the present application, the memory resource pool also includes a second baseboard management controller and a third communication component, wherein the second baseboard management controller is used for out-of-band management and status monitoring of the memory resource pool, and the third communication component is used to transmit communication data of the memory resource pool.

[0100] It can be understood that the embodiment of the present application can implement the out-of-band management function through the second baseboard management controller, which can perform system maintenance and troubleshooting without affecting normal business, thereby improving the availability of the system. Even in the event of system downtime or network interruption, the device can be restarted, configuration adjusted, and other operations can be performed through the out-of-band management interface to ensure that the system resumes normal operation as soon as possible. The third communication component focuses on data transmission, ensuring high-bandwidth, low-latency data flow, meeting high-performance computing, storage, and network requirements, so that the memory resource pool can flexibly respond to different types of devices and application environments, and improve the flexibility and efficiency of data transmission.

[0101] It should be noted that the third communication component includes: PCIe / CXL / Ethernet interface, PHY, and MAC (Media Access Control) controller.

[0102] Specifically, if Figure 13As shown in the figure, the MXC, the core component of the memory resource pool, is primarily used for memory expansion. Each MXC supports Gen5 x8 bandwidth and two DIMMs, allowing the entire chassis to accommodate 64 DIMMs. The BMC is responsible for out-of-band management and monitoring of the switch node. It interconnects a PHY chip via RGMII, converting the signals to MDI signals and connecting them to an RJ45 port for the BMC's management network. The BMC can manage and configure the MXC via I2C.

[0103] The system's key boards include two memory boards and a management backplane. Separate design of the memory and management boards increases modularity and significantly improves overall system maintainability, facilitating board maintenance. All key signals for management, control, and status monitoring of the memory boards are connected to the backplane's Baseboard Management (BMC) module via Slimline connectors for real-time status monitoring. The TF card provides real-time error logging. The BMC's SerDes signals are connected to the memory board's Physical Hybrid (PHY) chip via the Slimline connector. The MDI signals from the PHY are then routed to an RJ45 connector, serving as the BMC's management network port for inter-device communication.

[0104] The entire chassis of the memory resource pool can accommodate 64 DIMMs, including UDIMMs, RDIMMs, and LRDIMMs. The memory board design groups two MXCs into four identical groups, allowing for identical routing for all four groups of caches. This greatly simplifies the memory board layout and routing, improving system consistency, facilitating debugging and tuning, and enhancing system stability.

[0105] In an embodiment of the present application, a management engine is provided in the second baseboard management controller, which performs unified management of the switch and provides an interactive interface to the outside world. The management engine includes an application layer, a driver layer and a physical layer. The physical layer is managed through PCIe and I2C / UART, the driver layer implements basic configuration, port management and memory resource management, and the application layer provides CLI (Command Line Interface) and API (Application Programming Interface).

[0106] It can be understood that the embodiments of the present application can incorporate the memory resource pool and the switch connected to it into a unified management platform, thereby uniformly managing the memory resource pool and the switching equipment, and adopt a layered design to make the management function module clear and easy to expand, facilitate function upgrades, protocol adaptation and cross-platform porting, and provide a variety of interactive interfaces to meet the operating habits and system integration requirements of different users, thereby improving the system's availability and fault tolerance.

[0107] It should be noted that the physical layer implements underlying communication and connects managed devices; the driver layer implements specific control logic and supports upper-layer functions; the application layer provides human-computer interaction and system docking interfaces. The overall system management efficiency, maintainability and scalability are improved through layered architecture, multi-interface support and unified management.

[0108] Specifically, if Figure 14 As shown in the figure, in a CXL SW node, the CXL switch chip decouples resources from the memory pooling system. The management engine centrally manages the CXL switch chip and provides an external interface, enabling unified management of CXL devices in the memory resource pool, enabling the identification, management, and dynamic allocation of memory resources. The physical layer enables management via PCIe and I2C / UART. The driver layer implements basic configuration, port management, and memory resource management. The application layer provides a CLI and API for client use.

[0109] In an embodiment of the present application, it also includes: the switch communicates with the client, and the client operates and maintains multiple computer devices through the switch.

[0110] It can be understood that in the embodiment of the present application, the client operates and maintains multiple computer devices through the switch, realizes centralized management and control of all computer devices through the switch, simplifies the operation and maintenance process, utilizes the powerful port capacity and flexible topology of the switch to facilitate the addition of new computer devices, optimizes internal network traffic through high-speed switches, ensures efficient communication between computing nodes, and improves network performance.

[0111] Specifically, if Figure 15-17 As shown, each computer device is equipped with a Gen4 x16 100G network card, which is connected to a data TOR switch. The CXL SW node's MCU is connected to a Gen3 x8 25G network card. The switch supports data exchange at both 100G and 25G rates. Clients can connect to the data TOR and log in to the IP address of each node for remote operation and maintenance.

[0112] The BMC in each node interconnects with the PHY chip via the RGMII interface, converting signals into MDI signals for connection to the management TOR, which supports 1G data exchange. The BMC in the CXL SW node serves as the management center for the entire system, monitoring and receiving management data from other nodes. Clients can log in to each node's IP address for remote operation and maintenance.

[0113] In summary, this application allows each computer device to obtain memory from the memory pool, and each computer device can share a memory, so that multiple computer devices can quickly collaborate on computing, realize dynamic allocation and efficient sharing of memory resources, and are particularly suitable for application scenarios of real-time data analysis; it can provide larger memory bandwidth and higher memory capacity density, and can allocate different memory capacities based on the needs of computer devices, improve the memory utilization of the entire system, and solve the current problem of low server memory utilization; CXL-based memory expansion and sharing can achieve ns-level latency, which is lower than the RDMA method and facilitates rapid data analysis; the designed computer equipment, CXL SW switch, and memory resource pool can be mounted on a standard cabinet, facilitating daily deployment and maintenance.

[0114] According to the system for sharing a memory resource pool provided in an embodiment of the present application, the system is connected to the processors and memory resource pools of multiple computer devices through multiple switching components of a switch. Multiple computer devices share the memory resources of the memory resource pool through the switch to allocate different memory capacities according to the needs of the computer devices. This not only realizes the dynamic allocation and efficient sharing of memory resources and improves the memory utilization of the entire system, but also reduces the latency of computer devices accessing memory, ensures the consistency of shared memory of multiple computer devices, can meet the needs of various computing scenarios, and has high applicability.

[0115] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0116] An embodiment of the present application further provides a server, including the system of the shared memory resource pool of the above embodiment.

[0117] An embodiment of the present application also provides a system memory allocation method for a shared memory resource pool.

[0118] Figure 17 This is a flowchart of a system memory allocation method for a shared memory resource pool provided in an embodiment of the present application.

[0119] like Figure 17 As shown, the system memory allocation method of the shared memory resource pool is applied to the system of the shared memory resource pool. The switch is correspondingly provided with a command line interface. The user selects the memory allocation working mode of the memory resource pool through the command line interface. The memory allocation working mode includes any one of the direct memory allocation mode, the pooled memory allocation mode and the shared memory allocation mode, including:

[0120] In step S101, if the memory allocation working mode is the direct memory allocation mode, it is detected whether the downstream port of the switching component recognizes the memory stick; if the downstream port of the switching component recognizes the memory stick, a memory allocation path is determined using multiple direct memory allocation units, wherein each memory allocation path is: the direct memory allocation unit is respectively connected to a memory stick and a computer device; and a memory stick is allocated to a computer device through the memory allocation path.

[0121] It can be understood that in the embodiment of the present application, the direct memory allocation unit is respectively connected to a memory stick and a computer device, and a memory stick is allocated to a computer device through a memory allocation path. Since each memory stick is exclusively allocated to a computer device, there is no concurrent competition, so the access delay is the lowest and the bandwidth is the largest, which is suitable for high-performance computing tasks, thereby achieving low-latency, high-bandwidth, and exclusive memory access.

[0122] In step S102, if the memory allocation working mode is the pooled memory allocation mode, it is detected whether the downstream port of the switching component recognizes the memory stick. If the downstream port of the switching component recognizes the memory stick, the address of the memory stick is divided into multiple segments, and the memory allocation path is determined using multiple pooled memory allocation units. Each memory allocation path is: multiple pooled memory allocation units allocate and connect a memory stick and multiple computer devices, and each segment is allocated to a computer device through the memory allocation path.

[0123] It can be understood that in the embodiment of the present application, multiple pooled memory allocation units are allocated and connected to a memory stick and multiple computer devices, and each segment is allocated to a computer device through a memory allocation path. By dividing the memory stick into multiple segments and flexibly allocating them, the waste of memory resources under traditional methods is avoided, and fine-grained memory allocation strategies are supported to meet the needs of different application scenarios and improve resource utilization.

[0124] In step S103, if the memory allocation working mode is the shared memory allocation mode, it is detected whether the downstream port of the switching component recognizes the memory stick. If the downstream port of the switching component recognizes the memory stick, a memory allocation path is determined using multiple shared memory allocation units, wherein each memory allocation path is: multiple shared memory allocation units allocate and connect a memory stick and multiple computer devices, and a memory stick is simultaneously allocated to multiple computer devices through the memory allocation path.

[0125] It can be understood that in the embodiment of the present application, multiple shared memory allocation units allocate and connect one memory stick and multiple computer devices, and allocate one memory stick to multiple computer devices at the same time through the memory allocation path. Multiple computer devices can access the same memory stick at the same time, thereby improving resource utilization. The CXL protocol is used to ensure data consistency when multiple computer devices access the same memory, thereby realizing memory resource sharing and improving system collaboration efficiency.

[0126] Specifically, if Figure 18 As shown in the figure, the user enters a command through the command line interface to specify the memory allocation mode to be configured. After receiving the command, the switch parses and identifies the operating mode selected by the user: If the memory allocation operating mode is direct memory allocation mode, the direct memory allocation unit is enabled to allocate the same memory device exclusively to the same host through the D2H path; if the memory allocation operating mode is pooled memory allocation mode, the pooled memory allocation unit is enabled to divide the memory device into multiple segments, and each segment is allocated to the same host through the P2H path; if the memory allocation operating mode is shared memory allocation mode, the logical to shared memory allocation unit is enabled to allocate the same memory device to different hosts through the L2G path.

[0127] According to the system memory allocation method of the shared memory resource pool proposed in the embodiment of the present application, three different memory allocation working modes correspond to different application scenarios and performance requirements, respectively. By switching different types of memory allocation units in the component, an access path from the memory stick to the host is established. According to the task requirements, any one of the direct memory allocation mode, pooled memory allocation mode and shared memory allocation mode is dynamically switched to improve memory resource utilization and meet the performance, security and collaboration requirements of different applications.

[0128] An embodiment of the present application also provides a system power-on method for a shared memory resource pool.

[0129] Figure 19 This is a flowchart of a system power-on method for a shared memory resource pool provided in an embodiment of the present application.

[0130] like Figure 19 As shown, the system power-on method of the shared memory resource pool is applied to the system of the shared memory resource pool of the above embodiment, the system includes computing nodes, switches and memory resource pools, wherein the method includes:

[0131] In step S201 , multiple computer devices, switches, and a memory resource pool are connected to power sources.

[0132] It is understandable that the embodiments of the present application can control the access of multiple computer devices, switches and memory resource pools to the power supply to ensure that all nodes are in an operational state, which is a prerequisite for subsequent initialization actions.

[0133] In step S202, a power button of the switch is pressed, and the control unit of the switch controls the switch to start power-on initialization. The control unit sends a switch initialization completion message to the first baseboard management controller of the switch.

[0134] It can be understood that in the embodiment of the present application, when the user presses the power button of the switch, the control unit of the switch starts to perform power-on and initialization operations. After the initialization is completed, the control unit sends the "initialization completion information" to the first baseboard management controller of the switch. The control unit ensures that the switch completes hardware self-test, firmware loading and function initialization in a preset order during the power-on process, avoiding the BMC from misjudging or performing wrong operations when the system is not ready.

[0135] In step S203, after the first baseboard management controller recognizes the switch initialization completion information, it sends a power-on instruction to the second baseboard management controller of the memory resource pool. The second baseboard management controller of the memory resource pool controls the memory resource pool to start power-on initialization, and the second baseboard management controller sends the memory resource pool initialization completion information to the first baseboard management controller.

[0136] It can be understood that the embodiment of the present application can ensure that the switch and memory resource pool are powered on and initialized in the correct order through communication between BMC1 and BMC2, avoiding startup failure or instability caused by unprepared components, and improving the stability and reliability of the entire system.

[0137] In step S204, after the first baseboard management controller recognizes the memory resource pool initialization completion information, it scans multiple memory banks in the memory resource pool and allocates memory to each uplink port according to a preset memory allocation mode.

[0138] It can be understood that in the embodiment of the present application, the first baseboard management controller is responsible for coordinating the initialization process of the entire system. After receiving the memory resource pool initialization completion information, BMC1 starts to scan multiple physical memory bars in the memory resource pool, and then dynamically allocates memory resources to the uplink ports of each connected host according to the system's pre-set memory allocation mode, so as to automatically complete the matching and mapping of memory resources according to the preset strategy without manual intervention, and automatically complete the matching and mapping of memory resources according to the preset strategy without manual intervention, thereby improving system stability and reliability.

[0139] In step S205 , the first baseboard management controller sends a power-on instruction to each computer device, and each computer device starts power-on initialization. After the initialization is completed, each computer device obtains memory from each upstream port.

[0140] It can be understood that in the embodiment of the present application, the first baseboard management controller is responsible for coordinating the initialization process of the entire system. During the system startup phase, BMC1 sends a power-on command to each computer device, and the computing devices obtain the required memory resources from the shared memory resource pool through their respective uplink ports. The shared memory resource pool avoids the waste of resources caused by each computing device configuring memory separately, thereby improving resource utilization.

[0141] Specifically, if Figure 20 As shown in the figure, each node first connects to a 220V AC power supply from the PSU, outputs STBY (Standby) power, and the BMC completes BOO (Boot-up or Basic Operating Operation) and waits for the system power-on signal. Pressing the PWR button (Power button) on the CXL switch node initiates power-on and initialization, notifying the switch node's BMC. The switch node's BMC sends a power-on signal to the memorybox's BMC, enabling the memory pool to power on and initialize. A power-on completion signal is then sent back to the switch node's BMC over the network. The switch node's BMC then issues a power-on command to the switch chip, completes initialization, scans the memory pool devices, and allocates memory to each uplink port according to the pre-set mapping configuration. Finally, the switch node's BMC sends power-on signals to each computer device's BMC over the network. The computer device completes power-on initialization and acquires memory resources on the CXL switch port.

[0142] According to the system power-on method for a shared memory resource pool proposed in an embodiment of the present application, orderly power-on control and resource scheduling of switches, memory resource pools, and multiple computer devices are achieved through the collaborative mechanism between the first baseboard management controller and the second baseboard management controller, effectively improving the system's startup efficiency, resource utilization, and operational stability, while having good scalability and maintainability.

[0143] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0144] The above is a detailed introduction to a shared memory resource pool system provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A system for sharing a memory resource pool, characterized in that: include: A memory resource pool, wherein the memory resource pool includes a plurality of memory banks; a plurality of computer devices, each computer device including a plurality of processors; A switch, wherein the switch includes multiple switching components, different processors of each computer device are connected to different switching components, each switching component includes multiple uplink ports and multiple downlink ports, each uplink port of each switching component is connected to a different computer device, and each downlink port of each switching component is connected to a different memory bank, multiple computer devices share memory resources of the memory resource pool through the switch, multiple switching components are redundant components to each other, and when any switching component fails, the computer device obtains the memory resources of the memory resource pool through other switching components, wherein the power-on sequence of the system includes: multiple computer devices, the switch, and the memory resource pool are connected to power; pressing the power button of the switch, the control unit of the switch controls the switch to start power-on initialization, and the control unit sends the switch initialization completion information is sent to the first baseboard management controller of the switch; after the first baseboard management controller recognizes the switch initialization completion information, it sends a power-on instruction to the second baseboard management controller of the memory resource pool, the second baseboard management controller of the memory resource pool controls the memory resource pool to start power-on initialization, and the second baseboard management controller sends the memory resource pool initialization completion information to the first baseboard management controller; after the first baseboard management controller recognizes the memory resource pool initialization completion information, it scans the multiple memory bars of the memory resource pool and allocates memory to each upstream port according to a pre-set memory allocation mode; the first baseboard management controller sends a power-on instruction to each of the computer devices, each of the computer devices starts power-on initialization, and each of the computer devices obtains memory from the each upstream port after initialization is completed.

2. The system for sharing a memory resource pool according to claim 1, wherein: The switch is correspondingly provided with a command line interface, and the user selects the memory allocation working mode of the memory resource pool through the command line interface, wherein the memory allocation working mode includes any one of a direct memory allocation mode, a pooled memory allocation mode and a shared memory allocation mode.

3. The system for sharing a memory resource pool according to claim 2, wherein: Each switching component includes a plurality of direct memory allocation units. When the memory allocation working mode is the direct memory allocation mode, the switching component is configured to perform the following steps: Detecting whether a downstream port of the switch component recognizes a memory stick; If the downstream port of the switching component identifies a memory stick, a memory allocation path is determined using a plurality of the direct memory allocation units, wherein each memory allocation path is: the direct memory allocation unit is respectively connected to a memory stick and a computer device; The memory bank is allocated to a computer device through the memory allocation path.

4. The system for sharing a memory resource pool according to claim 2, wherein: Each switching component includes a plurality of pooled memory allocation units. When the memory allocation working mode is the pooled memory allocation mode, the switching component is configured to perform the following steps: Detecting whether a downstream port of the switch component recognizes a memory stick; If the downstream port of the switching component identifies a memory stick, the address of the memory stick is divided into multiple segments, and a memory allocation path is determined using multiple pooled memory allocation units, each memory allocation path being: multiple pooled memory allocation units allocate connections between one memory stick and multiple computer devices; Each of the segments is allocated to a computer device via the memory allocation path.

5. The system for sharing a memory resource pool according to claim 2, wherein: Each switching component includes a plurality of shared memory allocation units. When the memory allocation working mode is the shared memory allocation mode, the switching component is configured to perform the following steps: Detecting whether a downstream port of the switch component recognizes a memory stick; If the downstream port of the switching component identifies a memory stick, a plurality of the shared memory allocation units are used to determine a memory allocation path, wherein each memory allocation path is: a plurality of the shared memory allocation units allocate connections between a memory stick and a plurality of computer devices; The one memory bank is simultaneously allocated to a plurality of computer devices through the memory allocation path.

6. The system for sharing a memory resource pool according to claim 1, wherein: The computer device includes a third baseboard management controller and a fourth baseboard management controller, wherein the third baseboard management controller and the fourth baseboard management controller are both used for out-of-band management and status control of the computer device, and the fourth baseboard management controller and the third baseboard management controller serve as backup for each other.

7. The system for sharing a memory resource pool according to claim 6, wherein: The computer device further includes: a first communication component, a storage component, a power supply component, a mainboard, a heat dissipation component and an interface component.

8. The system for sharing a memory resource pool according to claim 1, wherein: The switch includes a first controller, which is connected to the plurality of switch components respectively, and is used to control the operating status of the plurality of switches.

9. The system for sharing a memory resource pool according to claim 8, wherein: The switch further includes a first baseboard management controller and a second communication component. The first baseboard management controller is used for out-of-band management and status monitoring of the switch, and the second communication component is used for transmitting communication data of the switch.

10. The system for sharing a memory resource pool according to claim 1, wherein: The memory resource pool includes a plurality of memory ports, and the plurality of memory ports are respectively connected to the downlink ports of the switch.

11. The system for sharing a memory resource pool according to claim 10, wherein: The memory resource pool further includes a second baseboard management controller and a third communication component, wherein the second baseboard management controller is used for out-of-band management and status monitoring of the memory resource pool, and the third communication component is used for transmitting communication data of the memory resource pool.

12. A server, characterized in that: A system comprising the shared memory resource pool according to any one of claims 1 to 11.

13. A system memory allocation method for a shared memory resource pool, characterized in that: The method is applied to the system of the shared memory resource pool according to any one of claims 1 to 11, wherein the switch is correspondingly provided with a command line interface, and a user selects a memory allocation working mode of the memory resource pool through the command line interface, wherein the memory allocation working mode includes any one of a direct memory allocation mode, a pooled memory allocation mode, and a shared memory allocation mode, including: If the memory allocation working mode is the direct memory allocation mode, detecting whether the downlink port of the switch component recognizes the memory stick; if the downlink port of the switch component recognizes the memory stick, determining a memory allocation path using multiple direct memory allocation units, wherein each memory allocation path is: the direct memory allocation unit is respectively connected to a memory stick and a computer device; and the memory stick is allocated to a computer device through the memory allocation path; If the memory allocation working mode is the pooled memory allocation mode, detecting whether the downlink port of the switching component recognizes the memory stick, if the downlink port of the switching component recognizes the memory stick, dividing the address of the memory stick into multiple segments, and using multiple pooled memory allocation units to determine a memory allocation path, each memory allocation path is: multiple pooled memory allocation units allocate and connect one memory stick and multiple computer devices, and each segment is allocated to one computer device through the memory allocation path; If the memory allocation working mode is the shared memory allocation mode, detect whether the downstream port of the switching component recognizes the memory stick. If the downstream port of the switching component recognizes the memory stick, use multiple shared memory allocation units to determine a memory allocation path, wherein each memory allocation path is: multiple shared memory allocation units allocate and connect one memory stick and multiple computer devices, and one memory stick is simultaneously allocated to multiple computer devices through the memory allocation path.

14. A system power-on method for a shared memory resource pool, characterized in that: The method is applied to the system of the shared memory resource pool according to any one of claims 1 to 11, comprising: Multiple computer devices, switches, and memory resource pools are connected to the power supply; Pressing the power button of the switch causes the control unit of the switch to control the switch to start power-on initialization, and the control unit sends switch initialization completion information to the first baseboard management controller of the switch; After the first baseboard management controller recognizes the switch initialization completion information, it sends a power-on instruction to the second baseboard management controller of the memory resource pool. The second baseboard management controller of the memory resource pool controls the memory resource pool to start power-on initialization. The second baseboard management controller sends the memory resource pool initialization completion information to the first baseboard management controller. After the first baseboard management controller recognizes the memory resource pool initialization completion information, it scans multiple memory banks in the memory resource pool and allocates memory to each uplink port according to a preset memory allocation mode; The first baseboard management controller sends a power-on instruction to each of the computer devices, and each of the computer devices starts power-on initialization. After each of the computer devices completes initialization, it obtains memory from each of the upstream ports.

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