DFT (Discrete Fourier Transform) implementation method and device under 5G (5th Generation) standard, equipment and medium
By converting the rotation factor multiplication into a random order of the number address and using a hybrid-based butterfly algorithm module, the problems of high power consumption and large hardware area in the DFT implementation method under the 5G standard are solved, and higher processing speed and lower power consumption are achieved.
Patent Information
- Application Number
- CN202510460111.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-14
- Publication Date
- 2025-08-08
AI Technical Summary
The DFT implementation method under the existing 5G standard has problems such as high power consumption, large hardware area and low processing speed.
The Chinese remainder theorem is used to convert the rotation factor multiplication into the out-of-order order of the number address, and DFT operation is performed through the hybrid base butterfly algorithm module, and the fusion operation core of the base 2/3/4/5 and the parallel read and write design of 6 memory blocks.
Reduces power consumption, reduces hardware area, and improves processing rate and data processing efficiency.
Smart Images
Figure CN120448295A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of 5G communication technology, and in particular to a method, apparatus, device, and medium for implementing discrete Fourier transform under the 5G standard. Background Art
[0002] Many modern wireless broadband transmission systems use Orthogonal Frequency Division Multiplexing (OFDM) technology, such as 4G LTE, 5G NR, digital TV broadcasting, and Wi-Fi. This is because OFDM divides the transmission bandwidth into orthogonal subcarriers, thus transforming the severe multipath interference faced by broadband transmission into a relatively flat channel on each subcarrier, and achieving high spectrum utilization through low-complexity frequency domain equalization.
[0003] Signal generation in OFDM is accomplished through an inverse Fourier transform (IFFT), which linearly combines subcarriers (complex sinusoids of different frequencies) using modulation symbols. This results in large output signal swings and an increased peak-to-average power ratio (PAPR), posing difficulties for portable or handheld uplink users. Therefore, the system undergoes pre-expansion processing before the IFFT process at the transmitter. The most typical method of expansion is the discrete Fourier transform (DFT), which is the DFT-OFDM technology.
[0004] The 5G NR protocol restricts the physical resource blocks (PRBs) allocated to DFT-OFDM waveforms. These PRBs must be powers of 2, 3, or 5, limiting the number of supported DFT points to just 67. Common DFT implementations use a hybrid approach, which involves the following steps: determining the power of 2, 3, or 5 based on the configured number of DFT points; performing radix-2, 3, or 5 operations on the data from memory; applying twiddle factors to the radix-2, 3, or 5 outputs; and outputting the data in reverse order. This approach involves redundant twiddle factor processing, which increases power consumption and requires larger memory tables. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a DFT implementation method, device, equipment and medium under the 5G standard, which can improve the processing rate, reduce the hardware area and processing power consumption.
[0006] The technical solution adopted by the present invention to solve the technical problem is to provide a DFT implementation method under the 5G standard, including the following steps:
[0007] The Chinese remainder theorem is used to convert the multiplication of twiddle factors into the random order of data access addresses;
[0008] Data is retrieved from the internal storage based on the disorder of the data retrieval addresses, and a mixed-radix butterfly algorithm module is used to perform a DFT operation on the retrieved data.
[0009] When the Chinese remainder theorem is used to convert the twiddle factor multiplication into the random order of the data access address, when N=N1N2 and N1, N2 are relatively prime, according to the Chinese remainder theorem, a unique set of coefficients {n1, k1}∈[0, N1-1], {n2, k2}∈[0, N2-1] is found so that n=mod(N1n2+N2n1), When N = N1N2 and N1 and N2 are not mutually prime, find a set of coefficients {n1, k1}∈[0, N1-1], {n2, k2}∈[0, N2-1] according to the Chinese remainder theorem such that n = N2n1+n2, k = N1k2+k1; where N is the number of configured DFT points, n is the time domain index point, k is the frequency domain index point, and mod() is the modulo operation.
[0010] The hybrid radix butterfly algorithm module adopts a fusion operation core of radix 2 / 3 / 4 / 5.
[0011] The internal storage is divided into 6 storage blocks. Each time data is fetched, data is fetched from a different storage block. The storage block index and offset address in the storage block for each fetch are expressed as: Among them, Bank is the storage block index, Address is the offset address, mod() is the modulo operation, BankCoef is the storage block coefficient, AddressCoef is the offset address coefficient, floor() is a rounding operation, GapCoef is the index point stratification coefficient, k is an index point ranging from 0 to N-1, and radix is the base number.
[0012] The technical solution adopted by the present invention to solve the technical problem is to provide a DFT implementation device under the 5G standard, including:
[0013] A conversion module, used to convert the multiplication of rotation factors into the disorder of data access addresses using the Chinese remainder theorem;
[0014] The data fetching operation module is used to fetch data from the internal storage based on the disorder of the fetching addresses, and perform DFT operation on the fetched data using the mixed-radix butterfly algorithm module.
[0015] The conversion module uses the Chinese remainder theorem to convert the twiddle factor multiplication into the random order of the data access address. When N=N1N2 and N1, N2 are relatively prime, the Chinese remainder theorem is used to find a unique set of coefficients {n1, k1}∈[0, N1-1], {n2, k2}∈[0, N2-1] such that n=mod(N1n2+N2n1). When N = N1N2 and N1 and N2 are not mutually prime, find a set of coefficients {n1, k1}∈[0, N1-1], {n2, k2}∈[0, N2-1] according to the Chinese remainder theorem such that n = N2n1+n2, k = N1k2+k1; where N is the number of configured DFT points, n is the time domain index point, k is the frequency domain index point, and mod() is the modulo operation.
[0016] The hybrid radix butterfly algorithm module adopts a fusion operation core of radix 2 / 3 / 4 / 5.
[0017] The internal storage is divided into 6 storage blocks. The data acquisition module acquires data from different storage blocks each time. The storage block index and offset address in the storage block for each acquisition are expressed as: Among them, Bank is the storage block index, Address is the offset address, mod() is the modulo operation, BankCoef is the storage block coefficient, AddressCoef is the offset address coefficient, floor() is a rounding operation, GapCoef is the index point stratification coefficient, k is an index point ranging from 0 to N-1, and radix is the base number.
[0018] The technical solution adopted by the present invention to solve its technical problem is: to provide an electronic device, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor, wherein when the processor executes the computer program, the steps of the DFT implementation method under the above-mentioned 5G standard are implemented.
[0019] The technical solution adopted by the present invention to solve its technical problem is: providing a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the DFT implementation method under the above-mentioned 5G standard are implemented.
[0020] Beneficial effects
[0021] Due to the adoption of the above-mentioned technical solution, the present invention has the following advantages and positive effects compared with the prior art: the present invention uses CRT to convert the multiplication of the rotation factors of a specific series into a random order of data access addresses, thereby reducing power consumption, adopts radix 2 / 3 / 4 / 5 shared circuits, thereby reducing logical operation units, adopts the same address for reading numbers during intermediate operations, and through the designed memory access method, multiple data points can be read within one beat, thereby achieving parallel reading and writing while reducing the overhead of internal storage resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 This is a flowchart of a DFT implementation method under the 5G standard in the first embodiment of the present invention;
[0023] Figure 2Schematic diagram of the operation core of the mixed-radix butterfly algorithm module in the first embodiment of the present invention. DETAILED DESCRIPTION
[0024] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.
[0025] The first embodiment of the present invention relates to a DFT implementation method under the 5G standard, such as Figure 1 As shown, the following steps are included:
[0026] Step 1: Use the Chinese remainder theorem to convert the twiddle factor multiplication into the random order of the data access address.
[0027] The general formula for DFT transform is:
[0028]
[0029] Where X(k) is the sequence after DFT transformation, x(n) is the input sequence, N is the number of configured DFT points, n is the time domain index point, and k is the frequency domain index point.
[0030] make Then we have:
[0031]
[0032] When N=N1N2 and N1, N2 are relatively prime, according to the Chinese Remainder Theorem (CRT), we can find a unique set of coefficients {n1, k1}∈[0,N1-1], {n2, k2}∈[0,N2-1] such that Established, among which Let mod(n,N)=<n,N> Substituting the above {n1, k1}, {n2, k2} into the DFT transform, we have:
[0033]
[0034] Simplifying, we can get:
[0035]
[0036] That is, when N1 and N2 are coprime, the N-point DFT is equivalent to N2 N1-point DFTs and N1 N2-point DFTs.
[0037] When N=N1N2 and N1, N2 are not mutually prime, we can find a unique set of coefficients {n1, k1}∈[0, N1-1], {n2, k2}∈[0, N2-1] so that n=N2n1+n2, k=N1k2+k1 holds. Substituting the above {n1, k1}, {n2, k2} into the DFT transform, we have:
[0038]
[0039] Simplifying, we can get:
[0040]
[0041] That is, when N1 and N2 are not mutually prime, the N-point DFT is equivalent to N2 N1-point DFTs, N rotation factors, and N1 N2-point DFTs.
[0042] It can be seen that when the method of this embodiment is adopted, there are no rotation factors at the boundaries of different bases, so redundant rotation factor processing can be avoided, and the storage range of the storage table can also be reduced.
[0043] Step 2: fetch data from the internal storage based on the disorder of the fetch addresses, and perform DFT operation on the fetched data using a mixed-radix butterfly algorithm module.
[0044] The hybrid basis butterfly algorithm module used in this step can be used as follows Figure 2 The fused operation core of base 2 / 3 / 4 / 5 shown can make different base operations use the same set of circuits, thereby reducing the area of the processing unit. Since the mixed-base butterfly algorithm naturally meets the same-address requirement, but the operation of step 1 will introduce disorder in the read and write data, this step adopts a new data storage method and an adapted data reading order to make the internal data read and write meet the same-address operation. In other words, this step divides the internal storage into 6 storage blocks, and each time the data is retrieved, it is retrieved from a different storage block. The storage block index and the offset address in the storage block for each data retrieval are expressed as:
[0045]
[0046] Among them, Bank is the storage block index, Address is the offset address, mod() is the modulo operation, BankCoef is the storage block coefficient, AddressCoef is the offset address coefficient, floor() is a rounding operation, GapCoef is the index point stratification coefficient, k is an index point ranging from 0 to N-1, and radix is the base number.
[0047] Through the above operations, multiple data points can be read in one beat, reducing the overhead of internal storage resources while achieving parallel reading and writing.
[0048] A second embodiment of the present invention relates to a DFT implementation device under the 5G standard, including:
[0049] A conversion module, used to convert the multiplication of rotation factors into the disorder of data access addresses using the Chinese remainder theorem;
[0050] The data fetching operation module is used to fetch data from the internal storage based on the disorder of the fetching addresses, and perform DFT operation on the fetched data using the mixed-radix butterfly algorithm module.
[0051] The conversion module uses the Chinese remainder theorem to convert the twiddle factor multiplication into the random order of the data access address. When N=N1N2 and N1, N2 are relatively prime, the Chinese remainder theorem is used to find a unique set of coefficients {n1, k1}∈[0, N1-1], {n2, k2}∈[0, N2-1] such that n=mod(N1n2+N2n1). When N = N1N2 and N1 and N2 are not mutually prime, find a set of coefficients {n1, k1}∈[0, N1-1], {n2, k2}∈[0, N2-1] according to the Chinese remainder theorem such that n = N2n1+n2, k = N1k2+k1; where N is the number of configured DFT points, n is the time domain index point, k is the frequency domain index point, and mod() is the modulo operation.
[0052] The hybrid radix butterfly algorithm module adopts a fusion operation core of radix 2 / 3 / 4 / 5.
[0053] The internal storage is divided into 6 storage blocks. The data acquisition module acquires data from different storage blocks each time. The storage block index and offset address in the storage block for each acquisition are expressed as: Among them, Bank is the storage block index, Address is the offset address, mod() is the modulo operation, BankCoef is the storage block coefficient, AddressCoef is the offset address coefficient, floor() is a rounding operation, GapCoef is the index point stratification coefficient, k is an index point ranging from 0 to N-1, and radix is the base number.
[0054] It is not difficult to find that the present invention uses CRT to convert the multiplication of the rotation factors of a specific series into a disordered order of the data access address, thereby reducing power consumption, adopting radix 2 / 3 / 4 / 5 shared circuits, thereby reducing the number of logical operation units, and using the same address for reading numbers during intermediate operations. Through the designed memory access method, multiple data points can be read within one beat, thereby achieving parallel reading and writing while reducing the overhead of internal storage resources.
[0055] A third embodiment of the present invention relates to an electronic device, comprising a memory, a processor, and a computer program stored in the memory and runnable on the processor. When the processor executes the computer program, the steps of the DFT implementation method under the 5G standard of the first embodiment are implemented.
[0056] The fourth embodiment of the present invention designs a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the DFT implementation method under the 5G standard of the first embodiment are implemented.
[0057] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) that contain computer-usable program code.
[0058] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0059] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction method, which is implemented in the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.
[0060] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1A step that specifies a function in one or more boxes.
[0061] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.
Claims
1. A DFT implementation method under the 5G standard, characterized in that: The following steps are involved: The Chinese remainder theorem is used to convert the multiplication of twiddle factors into the random order of data access addresses; Data is retrieved from the internal storage based on the disorder of the data retrieval addresses, and a mixed-radix butterfly algorithm module is used to perform a DFT operation on the retrieved data.
2. The DFT implementation method under the 5G standard according to claim 1, characterized in that When the Chinese remainder theorem is used to convert the twiddle factor multiplication into the random order of the data access address, when N=N1N2 and N1, N2 are relatively prime, according to the Chinese remainder theorem, a unique set of coefficients {n1, k1}∈[0, N1-1], {n2, k2}∈[0, N2-1] is found so that n=mod(N1n2+N2n1), When N = N1N2 and N1 and N2 are not mutually prime, find a set of coefficients {n1, k1}∈[0, N1-1], {n2, k2}∈[0, N2-1] according to the Chinese remainder theorem such that n = N2n1+n2, k = N1k2+k1; where N is the number of configured DFT points, n is the time domain index point, k is the frequency domain index point, and mod() is the modulo operation.
3. The DFT implementation method under the 5G standard according to claim 1, characterized in that The hybrid radix butterfly algorithm module adopts a fusion operation core of radix 2 / 3 / 4 / 5.
4. The DFT implementation method under the 5G standard according to claim 1, characterized in that The internal storage is divided into 6 storage blocks. Each time data is fetched, data is fetched from a different storage block. The storage block index and offset address in the storage block for each fetch are expressed as: Among them, Bank is the storage block index, Address is the offset address, mod() is the modulo operation, BankCoef is the storage block coefficient, AddressCoef is the offset address coefficient, Floor() is a rounding operation. GapCoef is the index point stratification coefficient, k is the index point ranging from 0 to N-1, and radix is the base number.
5. A DFT implementation device under the 5G standard, characterized in that: include: A conversion module, used to convert the multiplication of rotation factors into the disorder of data access addresses using the Chinese remainder theorem; The data fetching operation module is used to fetch data from the internal storage based on the disorder of the fetching addresses, and perform DFT operation on the fetched data using the mixed-radix butterfly algorithm module.
6. The 5G standard DFT implementation device according to claim 5, characterized in that: The conversion module uses the Chinese remainder theorem to convert the twiddle factor multiplication into the random order of the data access address. When N=N1N2 and N1, N2 are relatively prime, the Chinese remainder theorem is used to find a unique set of coefficients {n1, k1}∈[0, N1-1], {n2, k2}∈[0, N2-1] such that n=mod(N1n2+N2n1). When N = N1N2 and N1 and N2 are not mutually prime, find a set of coefficients {n1, k1}∈[0, N1-1], {n2, k2}∈[0, N2-1] according to the Chinese remainder theorem such that n = N2n1+n2, k = N1k2+k1; where N is the number of configured DFT points, n is the time domain index point, k is the frequency domain index point, and mod() is the modulo operation.
7. The 5G standard DFT implementation device according to claim 5, characterized in that: The hybrid radix butterfly algorithm module adopts a fusion operation core of radix 2 / 3 / 4 / 5.
8. The 5G standard DFT implementation device according to claim 5, characterized in that: The internal storage is divided into 6 storage blocks. The data acquisition module acquires data from different storage blocks each time. The storage block index and offset address in the storage block for each acquisition are expressed as: Among them, Bank is the storage block index, Address is the offset address, mod() is the modulo operation, BankCoef is the storage block coefficient, AddressCoef is the offset address coefficient, floor() is a rounding operation, GapCoef is the index point stratification coefficient, k is an index point ranging from 0 to N-1, and radix is the base number.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the DFT implementation method under the 5G standard as described in any one of claims 1-4 are implemented.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the DFT implementation method under the 5G standard as described in any one of claims 1 to 4 are implemented.