Display device

Abstract

There is provided a display device including: a pixel; a touch sensor over the pixel and including a first touch electrode and a second touch electrode; a display driver configured to drive the pixels in a first display mode in which a frame includes a first scan period or a second display mode in which another frame includes the first scan period and one or more second scan periods; and a touch sensor driver configured to provide a first driving signal to the touch sensor in a first display mode; and in a second display mode, providing a second driving signal to the touch sensor during the first scan period, and providing a third driving signal to the touch sensor during one or more second scan periods, where in the first display mode and in the second display mode, a touch reporting rate of the touch sensor driver is the same.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0019831 filed on February 8, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device. Background Art

[0004] Recently, the use of display devices has been diversified. In addition, as display devices become thinner and lighter, their scope of use is gradually expanding.

[0005] The display device may include a touch sensing device as an input device. The touch sensing device may include a touch sensor and a touch sensor driving circuit configured to drive the touch sensor and generate touch data. Summary of the Invention

[0006] One or more embodiments include a display device having improved touch sensing performance. However, such a technical problem is merely an example, and the present disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to one or more embodiments, a display device includes: pixels; a touch sensor above the pixels and including a first touch electrode and a second touch electrode; a display driver configured to drive the pixels in a first display mode or a second display mode, wherein in the first display mode, a frame includes a first scanning period, and in the second display mode, another frame includes the first scanning period and one or more second scanning periods; and a touch sensor driver configured to provide a first drive signal to the touch sensor in the first display mode; and to provide a second drive signal to the touch sensor during the first scanning period and a third drive signal to the touch sensor during the one or more second scanning periods in the second display mode, wherein the touch reporting rate of the touch sensor driver is the same in the first display mode and in the second display mode.

[0009] The display driver may be configured to provide a first synchronization signal to the touch sensor driver, the first synchronization signal having a first level voltage during a first scanning period and a second level voltage during one or more second scanning periods.

[0010] The second driving signal may have a first driving voltage, wherein the third driving signal has a second driving voltage greater than the first driving voltage.

[0011] The first driving signal may have a third driving voltage, wherein the first driving voltage is approximately 0.5 times the third driving voltage, and wherein the second driving voltage is approximately 1.5 times the third driving voltage.

[0012] In the second display mode, another frame may include one first scanning period and k second scanning periods, the first drive signal may have a third drive voltage, the first drive voltage may be approximately 1 / (k+1) times the third drive voltage, and the second drive voltage may be approximately (k+2) / (k+1) times the third drive voltage.

[0013] In the second display mode, the touch sensor driver may have a smaller number of samples during the first scanning period than during one or more second scanning periods.

[0014] The first scan period may have a first sub-period and a second sub-period, wherein the second driving signal is configured to repeat an on-voltage and an off-voltage during the first sub-period and maintain the off-voltage during the second sub-period.

[0015] The second drive signal and the third drive signal may have the same frequency.

[0016] The second drive signal may have a first frequency, wherein the third drive signal has a second frequency different from the first frequency.

[0017] The second frequency may be greater than the first frequency.

[0018] The second drive signal may have a first pulse width, wherein the third drive signal has a second pulse width different from the first pulse width.

[0019] The first pulse width may be smaller than the second pulse width.

[0020] The second drive signal and the third drive signal may have the same frequency.

[0021] The second driving signal may be a sinusoidal wave, wherein the third driving signal is a pulse wave.

[0022] According to one or more embodiments, a display device includes: pixels; a touch sensor, above the pixels, including a first touch electrode and a second touch electrode; a display driver, configured to drive the pixels in a first display mode or a second display mode, wherein in the first display mode, a frame includes a first scanning period, and in the second display mode, another frame includes the first scanning period and one or more second scanning periods; and a touch sensor driver, configured to: in the first display mode, provide a first drive signal to the touch sensor; and in the second display mode, provide a second drive signal to the touch sensor during the first scanning period, and provide a third drive signal to the touch sensor during the one or more second scanning periods, wherein the drive voltages, frequencies or waveforms of the second drive signals and the third drive signals, or the number of samples taken by the touch sensor driver during the first scanning period and during the one or more second scanning periods are different.

[0023] The display driver may be configured to provide a first synchronization signal to the touch sensor driver, the first synchronization signal having a first level voltage during a first scanning period and a second level voltage during one or more second scanning periods.

[0024] The second driving signal may have a first driving voltage, wherein the third driving signal has a second driving voltage greater than the first driving voltage.

[0025] The first scan period may have a first sub-period and a second sub-period, wherein the second driving signal is configured to repeat an on-voltage and an off-voltage during the first sub-period and maintain the off-voltage during the second sub-period.

[0026] The third drive signal and the second drive signal during the first sub-period may have the same frequency.

[0027] The second drive signal may have a first pulse width, wherein the third drive signal has a second pulse width different from the first pulse width.

[0028] The second driving signal may be a sinusoidal wave, wherein the third driving signal is a pulse wave.

[0029] These and / or other aspects will become apparent and more readily understood from the following detailed description of the embodiments, the accompanying drawings, and the claims.

[0030] These aspects may be implemented using a system, a method, a computer program, or a combination of specific systems, methods, and computer programs. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a schematic perspective view of a display device according to one or more embodiments;

[0033] Figure 2 yes Figure 1 The display device shown in Figure 1 A schematic cross-sectional view taken along line II';

[0034] Figure 3 is a schematic diagram of a display device according to one or more embodiments;

[0035] Figure 4 is a schematic diagram of a display of a display device according to one or more embodiments;

[0036] Figure 5 is a schematic equivalent circuit diagram of a pixel included in a display device according to one or more embodiments;

[0037] Figure 6 is a schematic cross-sectional view of a display device according to one or more embodiments;

[0038] Figure 7 is a schematic diagram of a touch sensor device of a display device according to one or more embodiments;

[0039] Figure 8A is a schematic plan view of a touch sensor according to one or more embodiments;

[0040] Figure 8B is a schematic cross-sectional view of a touch sensor according to one or more embodiments;

[0041] Figure 8C is a schematic plan view of a driving electrode according to one or more embodiments;

[0042] Figure 9A and Figure 9B is a conceptual diagram for explaining a display mode according to a driving frequency of a display;

[0043] Figure 10A is a view showing input / output signals of a display device in a first display mode;

[0044] Figure 10B is a view showing input / output signals of the display device in the second display mode;

[0045] Figure 11A is a view showing input / output signals of a display device in a first display mode;

[0046] Figure 11Bis a view showing input / output signals of the display device in the second display mode; and

[0047] Figures 12 to 15 is a view showing input / output signals of the display device in the second display mode. DETAILED DESCRIPTION

[0048] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for realizing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments or unnecessary processes, elements and techniques for fully understanding the various aspects of the present disclosure by those of ordinary skill in the art may be omitted. Unless otherwise stated, throughout the drawings and written description, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions may be omitted.

[0049] The described embodiments may have various modifications and may be implemented in different forms and should not be construed as limited to only the embodiments shown herein. The use of "can," "may," or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure.

[0050] In view of the entire content of the present disclosure, unless otherwise stated or implied, a person of ordinary skill in the art will understand that the present disclosure covers all modifications, equivalents and substitutions within the scope of the ideas and techniques of the present disclosure, and each of the features of the embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocking and operations are technically possible, and each embodiment may be implemented independently of each other, or may be implemented together in association.

[0051] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0052] Various embodiments are described herein with reference to cross-sectional views that are schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes of the figures due to, for example, manufacturing techniques and / or tolerances should be expected. Furthermore, the specific structural or functional descriptions disclosed herein are merely exemplary and are used for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be construed as being limited to the shapes of the elements, layers, or regions shown, but should include deviations in shapes due to, for example, manufacturing.

[0053] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0054] For ease of explanation, spatial relative terms such as "below", "below", "down", "downside", "beneath", "above", "upper side" etc. may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use or in operation. For example, if the device in the drawings is turned over, the elements described as being "below", "below" or "below" other elements or features will then be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged "on" a second part, this means that the first part is arranged on the upper or lower side of the second part, and is not limited to its upper side based on the direction of gravity.

[0055] In addition, the phrase "in a plan view" means when viewing an object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting an object portion from the side. The terms "overlap" or "overlapped" mean that a first object can be above or below a second object, or on one side of the second object, and vice versa. In addition, the term "overlap" can include stacking, facing, or facing, extending over, covering, or partially covering, or any other suitable term as will be understood and understood by those of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separated from," "separated from," or "offset from," as well as any other suitable equivalents as will be understood and understood by those of ordinary skill in the art. The terms "face" and "facing" can mean that a first object can be directly opposite or indirectly opposite to a second object. In the case where a third object is between the first and second objects, the first and second objects can be understood to be indirectly opposite to each other, but still facing each other.

[0056] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to another element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to another element, layer, region, or component, such that one or more intervening elements, layers, regions, or components may be present. Furthermore, this may collectively mean directly coupled or directly connected or indirectly coupled or indirectly connected as well as integrally coupled or integrally connected or non-integrally coupled or non-integrally connected. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or coupled to the other layer, region, and / or component, or one or more intervening layers, regions, or components may be present. The one or more intervening components may include switches, resistors, capacitors, etc. When describing embodiments, unless explicitly described as being directly connected, expressions of connection indicate electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or is directly on another component without intervening components.

[0057] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components such as "between...", "directly between...", or "adjacent to..." and "directly adjacent to..." can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0058] For the purposes of this disclosure, expressions such as "at least one of" or "any one of" or "one or more of" when preceding a list of elements modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ), or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, expressions such as "at least one of," "a plurality of," "one of," and other prepositional phrases, when preceding / following a list of elements, modify the entire list of elements and do not modify the individual elements in the list. When "C to D" is stated, it means C or greater and D or less unless otherwise specified.

[0059] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or advantage, and are used only to distinguish one element, component, component, area, region, layer, section or part from another element, component, component, area, region, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first section described below may be referred to as the second element, second component, second area, second layer or second section. The description of an element as a "first" element may not require or imply the presence of a second element or other element. The terms "first", "second", etc. may also be used herein to distinguish elements of different categories or groups. For the sake of simplicity, the terms "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0060] In the examples, the x-axis, y-axis, and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0061] The terms used herein are for the purpose of describing the embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, and the plural forms are intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises," "comprising," "have," "having," "includes," and "including," when used in this specification, specify the presence of stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0062] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously, or in a reverse order to the described order.

[0063] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms and not as terms of degree, and are intended to allow for inherent deviations in measurements or calculations that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. In view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the value and mean within an acceptable deviation range for the particular value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0064] In some embodiments, known structures and devices can be described in the accompanying drawings with respect to one or more functional blocks (e.g., block diagrams), units and / or modules to avoid unnecessary ambiguity in various embodiments. Those skilled in the art will understand that such blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connectors and other electrical circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from those of the dedicated hardware. In addition, in some embodiments, without departing from the scope of this disclosure, blocks, units and / or modules can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0066] In this specification, "ON" used in association with an element state can represent the activated state of the element, and "OFF" can represent the inactivated state of the element. "ON" used in association with a signal received by an element can represent a signal that activates the element, and "OFF" can represent a signal that disables the element. An element can be activated by a high level voltage or a low level voltage. As an example, a P-channel transistor (P-type transistor) can be activated by a low level voltage, and an N-channel transistor (N-type transistor) can be activated by a high level voltage. Therefore, it should be understood that the "ON" voltage for a P-channel transistor and an N-channel transistor is an opposite (low to high) voltage level. Hereinafter, the voltage that activates (turns on) a transistor is referred to as a gate-on voltage, and the voltage that disables (turns off) a transistor is referred to as a gate-off voltage.

[0067] Figure 1 is a schematic perspective view of a display device 1 according to one or more embodiments, Figure 2 yes Figure 1 The display device 1 is along Figure 1 Schematic cross-sectional view taken along line II'.

[0068] refer to Figure 1 , the display device 1 includes a display area DA configured to display an image and a non-display area NDA arranged outside the display area DA. The display device 1 can display an image by using light emitted from a plurality of pixels arranged in the display area DA. The non-display area NDA may be an area arranged around the display area DA, and may be an area in which no pixels are arranged. The display area DA may be completely surrounded by the non-display area NDA. Pads may be arranged in the non-display area NDA, and in the non-display area NDA, various wirings, printed circuit boards, or driver integrated circuit (IC) chips configured to transmit electrical signals to the display area DA are attached to the pads.

[0069] refer to Figure 2 , the display device 1 may include a display panel 10 and a cover window CW on the display panel 10. The display panel 10 may include a substrate 100, a display layer 200, an encapsulation layer 300, and a touch sensor layer 400.

[0070] The substrate 100 may include an insulating material such as glass, quartz, a polymer resin, or the like. The substrate 100 may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable. As an example, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may have a multilayer structure including a base layer and an inorganic layer, the base layer including a polymer resin. As an example, the substrate 100 may include two base layers and an inorganic barrier layer between the two base layers.

[0071] The display layer 200 may be located on the substrate 100. The display layer 200 may be a layer including pixels and configured to display an image. The display layer 200 may include a display element and a pixel circuit electrically connected to the display element. In addition, the display layer 200 may include a scan driver and scan lines, data lines, and power lines connected to the pixel circuit, wherein the scan driver is configured to apply scan signals to the scan lines.

[0072] The display element may include an emissive layer. The emissive layer of the display element may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, inorganic materials and quantum dots, or organic materials, inorganic materials and quantum dots. In one or more embodiments, the display element may be an organic light emitting diode.

[0073] The encapsulation layer 300 for encapsulating the display element may be located on the display layer 200. The encapsulation layer 300 may include at least one organic encapsulation layer to provide a flatter base surface for the touch sensor layer 400. Therefore, even when the touch sensor layer 400 is formed through a continuous process, the defect rate can be reduced. In one or more embodiments, the encapsulation layer 300 may include two inorganic encapsulation layers and an organic encapsulation layer between the two inorganic encapsulation layers.

[0074] The touch sensor layer 400 may be located on the encapsulation layer 300. The touch sensor layer 400 may include a touch sensor and a touch signal line. The display device 1 may be configured to determine whether a user has input a touch and the position of the touch by measuring a change in capacitance of touch electrodes forming the touch sensor.

[0075] In one or more embodiments, the touch sensor layer 400 can be formed in a continuous process with the encapsulation layer 300. As an example, the touch sensor layer 400 can be formed directly on a base surface provided by the encapsulation layer 300. In one or more other embodiments, the touch sensor layer 400 can be configured using a separate panel and attached to the encapsulation layer 300 using an adhesive or the like.

[0076] A cover window CW may be located on the display panel 10. The cover window CW may protect an upper surface of the display device 1. The cover window CW may be coupled to the display device 1 using an optically clear adhesive OCA or an optically clear resin.

[0077] In one or more embodiments, at least one functional layer may be included between the touch sensor layer 400 and the cover window CW. The functional layer may be a layer configured to perform a color filtering function, a color conversion function, a polarization function, or the like. The functional layer may be a sheet layer including a sheet, a film layer including a film, a thin film layer, a coating, a panel, a plate, or the like. A functional layer may include a single layer or may include multiple stacked thin films or coatings. As examples, the functional layer may be a color filter, an optical filter, an optical film, or the like.

[0078] Figure 3 is a schematic diagram of a display device 1 according to one or more embodiments.

[0079] refer to Figure 3 , the display device 1 may include a display panel 10 and a driving circuit portion DV configured to drive the display panel 10 .

[0080] The display panel 10 may include a display layer 200 on a substrate 100 and a touch sensor layer 400 over the display layer 200. The display layer 200 may be on the substrate 100, and the encapsulation layer 300 may be between the display layer 200 and the touch sensor layer 400.

[0081] The display layer 200 may include pixels PX and wiring and pads electrically connected to the pixels PX. The display area DA is an area in which a plurality of pixels PX are arranged. The display layer 200 may be configured to display a preset image using light emitted from the plurality of pixels PX arranged in the display area DA. The non-display area NDA is an area arranged around the display area DA (e.g., in a plan view). Various wiring and pads may be arranged in the non-display area NDA.

[0082] Each of the pixels PX may include a display element such as an organic light emitting diode and a pixel circuit configured to control the display element. The pixel circuit may include a transistor, a storage capacitor, and the like.

[0083] The pixel circuit can be electrically connected to a scan line SL extending in a first direction (x direction) and a data line DL extending in a second direction (y direction), etc. The pixel circuit can be configured to control the display element according to a data signal transmitted through the data line DL and a scan signal transmitted through the scan line SL. Each of the pixels PX can be configured to emit red light, green light, or blue light. Each of the pixels PX can be configured to emit red light, green light, blue light, or white light.

[0084] The touch sensor layer 400 may include touch sensors TS and signal lines. The touch sensing area SA is an area in which the sensing electrodes of the touch sensor TS are arranged. The touch sensor TS can be configured to determine whether a user has input a touch and the location of the touch by measuring the change in capacitance of the sensing electrodes arranged in the touch sensing area SA. The non-sensing area NSA is an area arranged around the touch sensing area SA (for example, in a plan view). The touch sensing area SA may be completely surrounded by the non-sensing area NSA. Signal lines electrically connected to the touch sensor TS may be arranged in the non-sensing area NSA.

[0085] The touch sensor TS may include drive electrodes TE (first touch electrodes), sensing electrodes RE (second touch electrodes), and a bridge pattern. The drive electrodes TE may include first body portions adjacent to each other in a first direction (x direction) and electrically connected to each other via a first bridge pattern. The sensing electrodes RE may include second body portions adjacent to each other in a second direction (y direction) and electrically connected to each other via a second bridge pattern.

[0086] The driver circuit portion DV may include a display driver DDV and a touch sensor driver TDV. In one or more embodiments, the driver circuit portion DV may include multiple integrated circuits. In one or more other embodiments, the driver circuit portion DV may include a single touch display driver integrated (TDDI) chip.

[0087] The display driver DDV may be configured to drive a plurality of pixels PX. As an example, the display driver DDV may include a gate driver, a data driver, a timing controller, and a voltage generator configured to apply an electrical signal configured to control the brightness of each of the pixels PX. In one or more embodiments, a portion of the display driver DDV may be formed on the substrate 100 together with the pixels PX and may be mounted in the non-display area NDA of the display layer 200.

[0088] The touch sensor driver TDV may be configured to drive the touch sensors TS of the touch sensor layer 400. The touch sensor driver TDV may be configured to apply a driving signal to the touch sensor TS, receive a sensing signal corresponding to the driving signal from the touch sensor TS, and convert the sensing signal into touch data TD as a digital signal (see Figure 7 ) to output it.

[0089] Figure 4 is a schematic diagram of a display (eg, display unit) DU of a display device according to one or more embodiments.

[0090] refer to Figure 4The display device may include a display DU. The display DU may include a display portion 11, a gate driver 12, a data driver 13, a timing controller 14, and a voltage generator 15. As an example, the display driver DDV may include a gate driver 12, a data driver 13, a timing controller 14, and a voltage generator 15.

[0091] The display section 11 includes pixels PX, such as a pixel PXij positioned in the i-th row and the j-th column. Figure 4 Only one pixel PXij is shown, but m×n pixels PX may be arranged, for example, in a matrix configuration. Here, i is a natural number between 1 and m, and j is a natural number between 1 and n.

[0092] exist Figure 4 In the present invention, for illustrative purposes only, the description will focus on a pixel PX using a pixel circuit including two transistors and one capacitor. However, the present disclosure is applicable not only to a pixel PX using the corresponding pixel circuit, but also to a pixel PX using another pixel circuit, for example, a pixel PX using a pixel circuit including three transistors and one capacitor, a pixel PX using a pixel circuit including seven transistors and one capacitor, etc.

[0093] Pixels PX are connected to scan lines SL_1, SL_2, ..., and SL_m, data lines DL_1, DL_2, ..., and DL_n, and power lines PL. As an example, a pixel PXij positioned in the i-th row and j-th column may be connected to scan line SL_i, data line DL_j, and power line PL.

[0094] The data lines DL_1 to DL_n may extend in the second direction (y direction) and may be connected to the pixels PX arranged in the same column. The scan lines SL_1 to SL_m may extend in the first direction (x direction) and may be connected to the pixels PX arranged in the same row.

[0095] The power lines PL may include a plurality of vertical power lines extending in the second direction (y direction), and the plurality of vertical power lines are connected to the pixels PX positioned in the same column.

[0096] The scan lines SL_1 to SL_m are configured to transmit scan signals Sn_1, Sn_2, ..., and Sn_m output from the gate driver 12 to the pixels PX in the same row. The data lines DL_1 to DL_n are configured to transmit data signals Dm_1, Dm_2, ..., and Dm_n output from the data driver 13 to the pixels PX in the same column. The pixel PXij positioned in the i-th row and j-th column is configured to receive the scan signal Sn_i and the data signal Dm_j.

[0097] The power line PL is configured to transfer the first power voltage ELVDD generated from the voltage generator 15 to the pixel PX.

[0098] Pixel PXij includes a display element and a drive transistor configured to control the amount of current flowing through the display element based on a data signal Dm_j. The data signal Dm_j is output from a data driver 13 and received by the pixel PXij via a data line DL_j. The display element may be, for example, an organic light-emitting diode. Because the display element is configured to emit light at a brightness corresponding to the amount of current received from the drive transistor, the pixel PXij can be configured to exhibit a grayscale corresponding to the data signal Dm_j. The pixel PXij may correspond to a portion of a unit pixel capable of displaying full color, such as a subpixel.

[0099] The voltage generator 15 may be configured to generate a voltage suitable for driving the pixel PXij. As an example, the voltage generator 15 may be configured to generate a first power voltage ELVDD and a second power voltage ELVSS. The level of the first power voltage ELVDD may be greater than the level of the second power voltage ELVSS.

[0100] The voltage generator 15 may be configured to generate an initialization voltage and provide it to the pixel PX. The initialization voltage may be applied to the gate of the driving transistor and / or the anode of the display element.

[0101] In addition, the voltage generator 15 can be configured to generate an on-voltage and an off-voltage for controlling the switching transistor of the pixel PXij, and provide the on-voltage and the off-voltage to the gate driver 12. When the on-voltage is applied to the gate of the switching transistor, the switching transistor can be turned on, and when the off-voltage is applied to the gate of the switching transistor, the switching transistor can be turned off. The voltage generator 15 can be configured to generate a gamma reference voltage and provide it to the data driver 13.

[0102] The timing controller 14 may be configured to control the display portion 11 by controlling the operation timing of the gate driver 12 and the data driver 13. The pixels PX of the display portion 11 may be configured to receive a new data signal Dm (see Figure 5 ) and by using the data signal Dm (see Figure 5 ) emits light with a brightness corresponding to that of the image source data RGB of one frame.

[0103] The timing controller 14 is configured to receive image source data RGB and a control signal CONT from the outside. The timing controller 14 may be configured to convert the image source data RGB into image data DATA based on characteristics of the display unit 11 and the pixels PX, etc. The timing controller 14 may be configured to provide the image data DATA to the data driver 13.

[0104] The control signal CONT may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal, a clock signal, and the like. The vertical synchronization signal Vsync may define the start of a segment in which image data DATA forming one frame is written (hereinafter referred to as one frame period). The horizontal synchronization signal Hsync may define the start of a segment in which image data DATA forming a horizontal line image displayed by one pixel row is written. The timing controller 14 may be configured to control the operation timing of the gate driver 12 and the data driver 13 using the control signal CONT. The timing controller 14 may be configured to determine the frame period by counting the data enable signal of the horizontal scanning period. The image source data RGB includes brightness information of the pixel PX. The brightness may have a set number of gray levels, for example 1024 (=2 10 )、256(=2 8 ) or 64(=2 6 ).

[0105] The timing controller 14 may be configured to generate control signals including a gate timing control signal GDC for controlling the operation timing of the gate driver 12 and a data timing control signal DDC for controlling the operation timing of the data driver 13. In one or more embodiments, the timing controller 14 may be configured to generate a synchronization signal for controlling the operation timing of the touch sensor driver TDV using the vertical synchronization signal Vsync.

[0106] The gate timing control signal GDC may include a gate start pulse, a gate shift clock, a gate output enable signal, and the like. The gate start pulse is provided to the gate driver 12, which generates the first scan signal at the start point of the scan period. The gate shift clock is a clock signal commonly input to the gate driver 12 and a clock signal for shifting the gate start pulse. The gate output enable signal is configured to control the output of the gate driver 12.

[0107] The data timing control signal DDC may include a source start pulse, a source sampling clock, a source output enable signal, and the like. The source start pulse is configured to control the data sampling start point of the data driver 13 and is provided to the data driver 13 at the start of a scan period. The source sampling clock is a clock signal configured to control the sampling operation of data within the data driver 13 based on a rising edge or a falling edge. The source output enable signal is configured to control the output of the data driver 13. Depending on the data transmission method, the source start pulse provided to the data driver 13 may be omitted.

[0108] The gate driver 12 is configured to sequentially generate scan signals Sn_1 to Sn_m in response to a gate timing control signal GDC provided from the timing controller 14 using an on-voltage or off-voltage provided from the voltage generator 15. The gate driver 12 may include a plurality of transistors and may be formed together with the pixel PX through a thin film process. As an example, the gate driver 12 may be installed in the non-display area NDA of the display panel 10 in the form of an amorphous silicon TFT gate driver circuit (ASG) or an oxide semiconductor TFT gate driver circuit (OSG).

[0109] The data driver 13 is configured to sample and latch the image data DATA provided by the timing controller 14 in response to a data timing control signal DDC provided by the timing controller 14, and convert the image data DATA into data in a parallel data system. When converting the image data DATA into data in the parallel data system, the data driver 13 converts the image data DATA into a gamma reference voltage and converts the image data DATA into an analog data signal. The data driver 13 is configured to provide data signals Dm_1 to Dm_n to the pixels PX via data lines DL_1 to DL_n. The pixels PX are configured to receive the data signals Dm_1 to Dm_n in response to scan signals Sn_1 to Sn_m.

[0110] In one or more embodiments, the display DU may support a variable refresh rate (VRR). The refresh rate is the frequency at which a data signal is actually written to the drive transistor of the pixel PX, and is also referred to as a frame scan rate or a frame reproduction rate. The refresh rate may represent the number of image frames reproduced in one second. In one or more embodiments, the refresh rate may be the output frequency of the gate driver 12 and / or the data driver 13. The frequency corresponding to the refresh rate may be the driving frequency. The display DU may be configured to adjust the output frequency of the gate driver 12 and the output frequency of the data driver 13 corresponding thereto according to the driving frequency. A display DU supporting a variable refresh rate may operate by changing the driving frequency within a range between a maximum driving frequency and a minimum driving frequency. As an example, when the refresh rate is approximately 120 Hz, a gate signal may be output to each horizontal line (row) approximately 120 times per second in synchronization with the timing of writing the data signal from the gate driver 12. The display DU may be configured to display an image by changing the driving frequency according to the refresh rate.

[0111] Figure 5 is a schematic equivalent circuit diagram of a pixel PX included in a display device according to one or more embodiments.

[0112] refer to Figure 5The pixel PX may include a pixel circuit PC and a display element connected to the pixel circuit PC, wherein the pixel circuit PC is connected to the scan line SL and the data line DL. The display element may be an organic light emitting diode OLED including a pixel electrode (anode) and an opposite electrode (cathode). The opposite electrode of the organic light emitting diode OLED may be a common electrode to which the second power voltage ELVSS is applied.

[0113] The pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The first transistor T1 may be a driving transistor in which the magnitude of its drain current is determined by its gate-source voltage, and the second transistor T2 may be a switching transistor that is turned on / off according to the gate-source voltage (substantially, the gate voltage). The first transistor T1 and the second transistor T2 may each be implemented as a thin film transistor.

[0114] The first transistor T1 may be represented by a driving transistor, and the second transistor T2 may be represented by a scanning transistor.

[0115] The storage capacitor Cst is connected between the power line PL and the gate of the first transistor T1. The storage capacitor Cst may include a second electrode connected to the power line PL and a first electrode connected to the gate of the first transistor T1. The storage capacitor Cst may be configured to store a voltage corresponding to the difference between the voltage transmitted from the second transistor T2 and the first power voltage ELVDD supplied to the power line PL.

[0116] The first transistor T1 may include a gate connected to the first electrode of the storage capacitor Cst, a first terminal connected to the power line PL, and a second terminal connected to the organic light emitting diode OLED. The first transistor T1 may be configured to control a driving current I flowing from the power line PL through the organic light emitting diode OLED according to a gate-source voltage. d The organic light emitting diode OLED can be configured to emit light with a driving current I d The corresponding preset brightness of the light.

[0117] The second transistor T2 may include a gate connected to the scan line SL, a drain connected to the data line DL, and a source connected to the gate of the first transistor T1. The second transistor T2 may be configured to transmit the data signal Dm to the gate of the first transistor T1 in response to the scan signal Sn.

[0118] Although the reference Figure 5The pixel circuit PC is described as including only p-type transistors, but the present disclosure is not limited thereto. In one or more embodiments, the pixel circuit PC may include only n-type transistors. In one or more other embodiments, the pixel circuit PC may include at least one p-type transistor and at least one n-type transistor.

[0119] The p-type transistor may be a silicon transistor. The silicon transistor may include a silicon semiconductor, and the silicon semiconductor may include amorphous silicon, polysilicon, etc. As an example, the silicon transistor may be a low temperature polysilicon (LTPS) thin film transistor.

[0120] The n-type transistor may be an oxide transistor. The oxide transistor may include an oxide semiconductor, and the oxide semiconductor is a material based on Zn oxide and may include Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In one or more embodiments, the oxide semiconductor may be an In-Ga-Zn-O (IGZO) semiconductor. In one or more embodiments, the oxide semiconductor may be an In-Sn-Ga-Zn-O (ITGZO) semiconductor.

[0121] Although the reference Figure 5 The pixel circuit PC is described as including two transistors and one storage capacitor, but the present disclosure is not limited thereto. For example, the pixel circuit PC may include three or more transistors and / or two or more capacitors. In one or more embodiments, the pixel circuit PC may include three transistors and one capacitor. In one or more other embodiments, the pixel circuit PC may include seven transistors and one capacitor.

[0122] Figure 6 is a schematic cross-sectional view of a display device according to one or more embodiments.

[0123] refer to Figure 6 , display layer 200 (see Figure 2 ) and the encapsulation layer 300 may be sequentially stacked on the substrate 100 in the display area DA of the display device. An organic light emitting diode OLED as a display element and a pixel circuit PC electrically connected to the organic light emitting diode OLED may be located in the display layer 200.

[0124] The substrate 100 may include an insulating material such as glass, quartz, polymer resin, etc. The substrate 100 may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable.

[0125] The buffer layer 201 may be located on the substrate 100, may reduce or block the penetration of foreign matter, moisture, or external air from below the substrate 100, and may provide a flat surface on the semiconductor layer Act. The buffer layer 201 may include an inorganic material, an organic material, or an organic / inorganic composite material, and may include a single layer or multiple layers including an inorganic material and / or an organic material, wherein the inorganic material includes an oxide or a nitride.

[0126] The pixel circuit PC may be located on the buffer layer 201, wherein the pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may correspond to the reference Figure 5 The first transistor T1 is described.

[0127] The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a drain electrode DE, and a source electrode SE.

[0128] The semiconductor layer Act may be located on the buffer layer 201 and may include polycrystalline silicon. In one or more other embodiments, the semiconductor layer Act may include amorphous silicon. In one or more other embodiments, the semiconductor layer Act may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer Act may include a channel region, a source region, and a drain region, the source region and the drain region being doped with impurities. The source region and the drain region may be located on two opposite sides of the channel region, respectively.

[0129] The first gate insulating layer 203 may be positioned to cover the semiconductor layer Act. The first gate insulating layer 203 may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO x ). Zinc oxide (ZnO x ) may be ZnO and / or ZnO 2 . The first gate insulating layer 203 may include a single layer or multiple layers including an inorganic insulating material.

[0130] The gate electrode GE is positioned on the first gate insulating layer 203 to overlap the semiconductor layer Act. The gate electrode GE may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers. As an example, the gate electrode GE may include a single molybdenum layer.

[0131] The second gate insulating layer 204 may be provided to cover the gate electrode GE. The second gate insulating layer 204 may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO x ). Zinc oxide (ZnO x ) may be ZnO and / or ZnO 2 . The second gate insulating layer 204 may include a single layer or multiple layers including an inorganic insulating material.

[0132] The second electrode CE2 of the storage capacitor Cst may be located on the second gate insulating layer 204. The second electrode CE2 may overlap the gate electrode GE. The gate electrode GE and the second electrode CE2 may overlap with each other with the second gate insulating layer 204 therebetween to form the storage capacitor Cst. That is, the gate electrode GE may function as the first electrode CE1 of the storage capacitor Cst.

[0133] The second electrode CE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may include a single layer or a multilayer including the above materials.

[0134] The interlayer insulating layer 205 may be positioned to cover the second electrode CE2. The interlayer insulating layer 205 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO x ). Zinc oxide (ZnO x ) may be ZnO and / or ZnO 2 . The interlayer insulating layer 205 may include a single layer or multiple layers including an inorganic insulating material.

[0135] The source electrode SE and the drain electrode DE may be located on the interlayer insulating layer 205. The source electrode SE and the drain electrode DE may each include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may include a single layer or multiple layers including the above materials. As an example, the source electrode SE and the drain electrode DE may have a multilayer structure of Ti / Al / Ti. In one or more embodiments, the source electrode SE or the drain electrode DE may be omitted. As an example, adjacent thin film transistors TFT may be configured to share a source region or a drain region of the semiconductor layer Act. The source region or the drain region may serve as the source electrode SE or the drain electrode DE.

[0136] The planarization insulating layer 207 may be positioned to cover the source electrode SE and the drain electrode DE. The planarization insulating layer 207 may provide a flat base surface for the pixel electrode 210 located thereon.

[0137] The planarization insulating layer 207 may include an organic material or an inorganic material and include a single-layer structure or a multi-layer structure. The planarization insulating layer 207 may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol-based group, an acrylic acid-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer or a vinyl alcohol-based polymer. The planarization insulating layer 207 may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO x ). Zinc oxide (ZnO x ) may be ZnO and / or ZnO 2 . While the planarization insulating layer 207 is being formed, chemical mechanical polishing may be performed on the upper surface of the layer in order to provide a flat upper surface after the layer is formed.

[0138] The pixel electrode 210 may be located on the planarization insulating layer 207. The planarization insulating layer 207 may have a through hole exposing one of the source electrode SE and the drain electrode DE of the thin film transistor TFT. The pixel electrode 210 may be electrically connected to the thin film transistor TFT by contacting the source electrode SE or the drain electrode DE through the through hole.

[0139] The pixel electrode 210 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). The pixel electrode 210 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. As an example, the pixel electrode 210 may have a structure including a layer above / below the reflective layer, the layer including ITO, IZO, ZnO or In2O3. As an example, the pixel electrode 210 may have a stacked structure of ITO / Ag / ITO.

[0140] The pixel defining layer 209 may cover the edge of the pixel electrode 210 on the planarization insulating layer 207 and may have or define a pixel opening OP that exposes a central portion of the pixel electrode 210. The emission area EA of the organic light emitting diode OLED, that is, the size and shape of the pixel is defined by the pixel opening OP.

[0141] The pixel defining layer 209 can reduce or prevent the possibility of arcing, etc., occurring at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the opposing electrode 230 above the pixel electrode 210. The pixel defining layer 209 may include an organic insulating material such as polyamide, acrylic resin, benzocyclobutene, or hexamethyldisiloxane (HMDSO), and may be formed by spin coating, etc.

[0142] The pixel defining layer 209 may be formed in black. The pixel defining layer 209 may include a light-blocking material and may be set to black. The light-blocking material may include carbon black, carbon nanotubes, a resin or paste including a black dye, metal (e.g., nickel (Ni), aluminum (Al), molybdenum (Mo)) particles or alloys thereof, metal oxide (e.g., chromium oxide) particles, or metal nitride (e.g., chromium nitride) particles. When the pixel defining layer 209 includes a light-blocking material, external reflections caused by the metal structure located below the pixel defining layer 209 may be reduced.

[0143] The intermediate layer 220 may be positioned between the pixel electrode 210 and the opposite electrode 230. The intermediate layer 220 may include a first functional layer 221, an emission layer 222, and a second functional layer 223.

[0144] Emission layer 222 is located in pixel opening OP of pixel defining layer 209, wherein emission layer 222 is formed to correspond to pixel electrode 210. Emission layer 222 may include a polymer material or a low molecular weight material and may be configured to emit red, green, blue, or white light.

[0145] The first and second functional layers 221 and 223 may be respectively located below and / or above the emission layer 222. In one or more embodiments, unlike the emission layer 222 patterned for each pixel, the first and second functional layers 221 and 223 may be completely integrated in the display area DA.

[0146] The first functional layer 221 may include a single layer or multiple layers. For example, if the first functional layer 221 includes a polymer material, the first functional layer 221 may include a hole transport layer having a single layer structure and may include poly(ethylenedihydroxythiophene) (PEDOT) or polyaniline (PANI). If the first functional layer 221 includes a low molecular weight material, the first functional layer 221 may include a hole injection layer and a hole transport layer.

[0147] The second functional layer 223 may be omitted. As an example, in the case where the first functional layer 221 and the emissive layer 222 include polymer materials, it may be appropriate to form the second functional layer 223. The second functional layer 223 may include a single layer or multiple layers. The second functional layer 223 may include an electron transport layer and / or an electron injection layer. In one or more embodiments, at least one of the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer may be omitted.

[0148] The opposing electrode 230 may include a conductive material having a relatively low work function. As an example, the opposing electrode 230 may include a (semi) transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the opposing electrode 230 may further include a layer on the (semi) transparent layer comprising ITO, IZO, ZnO, or In2O3. In one or more embodiments, the opposing electrode 230 may include silver (Ag) and magnesium (Mg).

[0149] The stack structure of the pixel electrode 210 , the intermediate layer 220 , and the opposite electrode 230 stacked in sequence may form an organic light emitting diode OLED.

[0150] In one or more embodiments, a capping layer may be located on the organic light emitting diode (OLED). The capping layer may be configured to improve the light emission efficiency of the organic light emitting diode (OLED) based on constructive interference. The capping layer may be an organic capping layer comprising an organic material, an inorganic capping layer comprising an inorganic material, or a composite capping layer comprising an organic material and an inorganic material.

[0151] The encapsulation layer 300 may be located on the organic light-emitting diode (OLED). In one or more embodiments, the encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. As an example, the encapsulation layer 300 may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 therebetween.

[0152] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each include at least one inorganic insulating material. Inorganic insulating materials include aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO), silicon oxide (SiO x ), silicon nitride (SiN x ) or / and silicon oxynitride (SiON). The first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may each be formed by chemical vapor deposition.

[0153] The organic encapsulating layer 320 may further include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane (HMDSO), acrylic resin, or a combination thereof.

[0154] The encapsulation layer 300 may completely cover the display area DA, extend toward the non-display area NDA, and may be arranged to cover at least a portion of the non-display area NDA.

[0155] As described above, the encapsulation layer 300 may include the organic encapsulation layer 320 to provide a more flat base surface. Therefore, even when the touch sensor layer 400 (see FIG. 1 ) is formed by a continuous process, Figure 2 ) components, the defect rate can also be reduced.

[0156] Figure 7 is a schematic diagram of a touch sensor device (eg, a touch sensor unit) of a display apparatus according to one or more embodiments.

[0157] refer to Figure 7 , the display device may include a touch sensor device TU. The touch sensor device TU may include a touch sensor TS and a touch sensor driver TDV.

[0158] The touch sensor TS may include drive electrodes TE and sensing electrodes RE. The drive electrodes TE may include first main body portions that are adjacent to each other in a first direction (x direction) and electrically connected to each other through a first bridge pattern. The sensing electrodes RE may include second main body portions that are adjacent to each other in a second direction (y direction) and electrically connected to each other through a second bridge pattern. The drive electrodes TE extending in the first direction (x direction) and the sensing electrodes RE extending in the second direction (y direction) may cross each other. For ease of understanding, although Figure 7 Four driving electrodes TE and five sensing electrodes RE are shown, but the number of driving electrodes TE and the number of sensing electrodes RE may be variously changed.

[0159] The touch sensor driver TDV may include a signal input part (eg, a signal input unit) 23 and a signal sensor 25. The signal input part 23 may be configured to generate a driving signal Tx synchronized with an active frame synchronization signal AFsync.

[0160] The active frame synchronization signal AFsync is a signal synchronized with the vertical synchronization signal Vsync and may be a signal indicating a time period during which an address scan operation and a self-scan operation of the display DU are performed. In one or more embodiments, the signal input unit 23 may be configured to receive the active frame synchronization signal AFsync from the timing controller 14. In one or more other embodiments, the signal input unit 23 may be configured to receive the active frame synchronization signal AFsync from an application processor. The signal input unit 23 may be configured to generate a drive signal Tx based on the active frame synchronization signal AFsync and apply the drive signal Tx to each of the drive electrodes TE via the first touch signal line TSL1.

[0161] In one or more embodiments, the signal input unit 23 may operate using code division multiplexing. As an example, the signal input unit 23 may be configured to concurrently or substantially simultaneously apply the drive signal Tx to multiple channels electrically connected to the drive electrodes TE. In this case, at least some of the drive signals Tx may have different frequencies or waveforms. In one or more embodiments, the signal input unit 23 may be configured to operate using time division driving. As an example, the signal input unit 23 may be configured to sequentially apply the drive signal Tx to the drive electrodes TE.

[0162] The sensing electrode RE can be configured to transmit a sensing signal Rx to the signal sensor 25 via the second touch signal line TSL2, wherein the sensing signal Rx corresponds to the drive signal Tx applied to the drive electrode TE. When a touch event occurs in a corresponding area of the touch sensor TS, the self-capacitance of the drive electrode TE and / or the sensing electrode RE arranged in the relevant area and the mutual capacitance between the drive electrode TE and the sensing electrode RE may change. The sensing signal Rx may change due to the change in capacitance. The signal sensor 25 can be configured to receive a sensing signal Rx from each of the sensing electrodes RE via each of the second touch signal lines TSL2, and convert the sensing signal Rx into a digital signal to obtain touch data TD including information on whether a touch input has been made and the touch position.

[0163] The signal sensor 25 may include an analog front end configured to receive the sensing signal as an analog signal, an analog-to-digital converter configured to convert the received sensing signal Rx into a digital signal, and a processor configured to process the digital signal and generate touch data TD.

[0164] In one or more embodiments, the touch sensor device TU may support a preset touch report rate. The touch report rate is the frequency of a series of operations (such as applying a drive signal Tx to the drive electrode TE of the touch sensor TS, receiving a sense signal Rx from the sense electrode RE, and transmitting touch data TD generated by processing the received sense signal Rx to an external host system). The touch report rate may represent the number of touch scanning operations performed per second.

[0165] In one or more embodiments, the touch reporting rate of the touch sensor device TU can be the same as the maximum refresh rate of the display DU. As an example, if the maximum refresh rate of the display DU is approximately 120 Hz, the touch reporting rate of the touch sensor device TU can be approximately 120 Hz. Even if the display DU adjusts its refresh rate based on the display mode, the touch reporting rate of the touch sensor device TU can remain at approximately 120 Hz. Therefore, even when the display mode of the display DU changes, the touch input accuracy and sensitivity can be maintained.

[0166] Figure 8A is a schematic plan view of a touch sensor TS according to one or more embodiments, Figure 8B is a schematic cross-sectional view of a touch sensor TS according to one or more embodiments, and Figure 8C is a schematic plan view of a driving electrode TE according to one or more embodiments.

[0167] Figure 8A yes Figure 7 An enlarged schematic diagram of region II of the touch sensor shown in FIG. Figure 8A The touch sensor TS may include a drive electrode TE and a sensing electrode RE. The drive electrode TE may include first body portions BE1 adjacent to each other in a first direction (x direction) and a first bridge pattern BP1 electrically connecting the first body portions BE1. The sensing electrode RE may include second body portions BE2 adjacent to each other in a second direction (y direction) and a second bridge pattern BP2 electrically connecting the second body portions BE2.

[0168] In one or more embodiments, the first body portion BE1, the second body portion BE2, and the second bridge pattern BP2 may be located on the same layer, and the first bridge pattern BP1 may be located on a different layer from the first body portion BE1, the second body portion BE2, and the second bridge pattern BP2. As an example, the first bridge pattern BP1 may be located below the second bridge pattern BP2. In one or more embodiments, the second body portion BE2 and the second bridge pattern BP2 may be integrally formed. The first bridge pattern BP1 and the second bridge pattern BP2 may intersect in different directions and may partially overlap in plan view.

[0169] Figure 8B Schematically shows Figure 8A The touch sensor TS shown in FIG. Figure 8A The cross section is taken along line III-III'. Figure 8B The touch sensor layer 400 may be located on the encapsulation layer 300 . The touch sensor layer 400 may include a first insulating layer 401 , a first conductive layer MTL1 , a second insulating layer 403 , a second conductive layer MTL2 , and a third insulating layer 405 .

[0170] The first insulating layer 401 may be located on the encapsulation layer 300, and the first conductive layer MTL1 may be located on the first insulating layer 401. The first insulating layer 401 may cover the encapsulation layer 300 and may be configured to reduce or prevent damage to the encapsulation layer 300. In one or more embodiments, the first insulating layer 401 may be omitted.

[0171] The first conductive layer MTL1 may be located on the first insulating layer 401. The first conductive layer MTL1 may include a first bridge pattern BP1.

[0172] The second insulating layer 403 may be located on the first conductive layer MTL1, and the second conductive layer MTL2 may be located on the second insulating layer 403. The second conductive layer MTL2 may include a first body portion BE1 of the driving electrode TE and a second bridge pattern BP2.

[0173] The first conductive layer MTL1 and the second conductive layer MTL2 may each have a single-layer structure or a multi-layer structure. The single-layer conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include at least one of molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), and alloys thereof. The transparent conductive layer may include a transparent conductive oxide such as ITO, IZO, ZnO, or ITZO. In addition, the transparent conductive layer may include a conductive polymer such as poly-3,4-ethylenedioxythiophene (PEDOT), metal nanowires, graphene, etc.

[0174] In one or more embodiments, the conductive layer of the multilayer structure may include multiple metal layers. As an example, the conductive layer of the multilayer structure may have a three-layer structure of Ti / Al / Ti. The conductive layer of the multilayer structure may include at least one transparent conductive layer.

[0175] The third insulating layer 405 may be located on the second conductive layer MTL2. The first insulating layer 401, the second insulating layer 403, and / or the third insulating layer 405 may include an inorganic insulating material or an organic insulating material and may have a single-layer structure or a multi-layer structure.

[0176] Each of the first body portions BE1 may be electrically connected to the first bridge pattern BP1 through a contact hole CNT passing through the second insulating layer 403. The second bridge pattern BP2 may be located above the first bridge pattern BP1, and the second insulating layer 403 may be located between the first and second bridge patterns BP1 and BP2, thereby forming a capacitor.

[0177] Despite Figure 8A and Figure 8B , the sensing electrode RE including the second body portion BE2 and the second bridge pattern BP2 is shown as being integrally provided, but the present disclosure is not limited thereto. As an example, the driving electrode TE including the first body portion BE1 and the first bridge pattern BP1 may be integrally provided. In this case, the first body portion BE1, the second body portion BE2, and the first bridge pattern BP1 may be located on the second conductive layer MTL2, and the second bridge pattern BP2 may be located on a different layer from the second body portion BE2 (e.g., the first conductive layer MTL1).

[0178] Figure 8C yes Figure 8A FIG. 1 is an enlarged schematic diagram of the region IV of the driving electrode TE shown in FIG. Figure 8C The drive electrode TE may have a mesh (or grid, grid) structure. As an example, the first body portion BE1 and the first bridge pattern BP1 of the drive electrode TE may have a mesh structure. The mesh structure may include first and second conductive lines that intersect each other, wherein the first conductive lines extend in a fourth direction DR4, and the second conductive lines extend in a fifth direction DR5 that intersects the fourth direction DR4. The fourth direction DR4 and the fifth direction DR5 may be directions that intersect the first direction (x direction) and the second direction (y direction), respectively. The first and second conductive lines may define a plurality of electrode openings EOP.

[0179] In one or more embodiments, one electrode opening EOP may overlap with one pixel PX. As an example, the pixel PX may include a first pixel PX1 configured to emit light of a first color, a second pixel PX2 configured to emit light of a second color, and a third pixel PX3 configured to emit light of a third color. In a plan view, the first pixel PX1, the second pixel PX2, or the third pixel PX3 may be located inside the corresponding electrode opening EOP. In one or more other embodiments, one electrode opening EOP may overlap with a unit pixel group including a plurality of pixels PX.

[0180] and Figure 8C Similar to the driving electrodes TE shown in FIG, the sensing electrodes RE may have a mesh structure. Light emitted by the pixels PX located under the touch sensor layer 400 may pass through the driving electrodes TE and the sensing electrodes RE through the electrode openings EOP.

[0181] Figure 9A and Figure 9B 1 is a conceptual diagram for explaining a display mode according to the driving frequency of the display DU.

[0182] refer to Figure 9A and Figure 9B According to one or more embodiments, the display DU may support a variable refresh rate. The display driver DDV of the display DU supporting the variable refresh rate may operate by changing the driving frequency within a range between a maximum driving frequency and a minimum driving frequency.

[0183] According to the driving frequency, one frame 1F may include the first scanning period AS or the first scanning period AS and one or more second scanning periods SS. Figure 9A As shown in FIG, in the first display mode DM1 in which the display driver DDV operates at a driving frequency of N Hz, one frame 1F may include one first scanning period AS.

[0184] like Figure 9B As shown in FIG. 4 , in the second display mode DM2 in which the display driver DDV operates at a driving frequency of N / 2 Hz, one frame 1F may include one first scanning period AS and one second scanning period SS.

[0185] The display driver DDV may include two or more display modes. As an example, the display driver DDV may also include a display mode in which one frame 1F includes one first scanning period AS and two or more second scanning periods SS. When the driving frequency is low, one frame 1F may be extended.

[0186] The first scanning period AS may be defined as an address scanning period, in which a data signal is written into the pixel PX by turning on a write transistor within the pixel PX in response to a gate signal, and the pixel PX emits light at a brightness corresponding to the written data signal. The operation in which the data signal is written from the data line DL into the pixel PX may be referred to as a data programming operation.

[0187] The second scanning period SS can be defined as a self-scanning period, in which a data signal is not written to the pixel PX by turning off the gate signal of the write transistor of the pixel PX. During the second scanning period SS, the data signal written and stored during the first scanning period AS can be retained in the pixel PX, and the pixel PX can emit light at a brightness corresponding to the written data signal. When the number of second scanning periods SS included in one frame 1F increases, power consumption can be reduced.

[0188] In one or more embodiments, the length of the first scanning period AS and the length of the second scanning period SS may be the same or substantially the same. As an example, when the maximum driving frequency is approximately 120 Hz, each of the first scanning period AS and the second scanning period SS may be approximately 8.3 ms. In the first display mode DM1, one frame 1F may be approximately 8.3 ms, and in the second display mode DM2, one frame 1F may be approximately 16.6 ms. When the lengths of the first scanning period AS and the second scanning period SS are the same, changes in image quality due to changes in the refresh rate can be reduced.

[0189] Figure 10A is a view showing input / output signals of a display device in a first display mode, and Figure 10B is a view showing input / output signals of the display device in the second display mode.

[0190] refer to Figure 10A When the display driver DDV operates in the first display mode DM1, each frame 1F may include one first scanning period AS. As described above, the vertical synchronization signal Vsync is a signal that defines the start of one frame 1F and may be received from an external host, etc. One frame period and the first scanning period AS may start based on a falling edge of the vertical synchronization signal Vsync.

[0191] When the display driver DDV is driven in the first display mode DM1, the first scan period AS may overlap with one touch scan period TSP. During one touch scan period TSP, the touch sensor driver TDV may perform one touch scan operation, i.e., apply a drive signal Tx to the drive electrode TE of the touch sensor TS, receive a sensing signal Rx from the sensing electrode RE, and transmit touch data TD generated by processing the received sensing signal Rx to an external host system, etc. The touch report rate of the touch sensor driver TDV may be the same as the refresh rate of the display DU. In other words, when the display driver DDV operates at a drive frequency of approximately N Hz in the first display mode DM1, the touch report rate of the touch sensor driver TDV may be approximately N Hz.

[0192] refer to Figure 10B , when the display driver DDV operates in the second display mode DM2, each frame 1F may include a first scanning period AS and a second scanning period SS. In the case where the display driver DDV operates at a driving frequency of approximately N Hz in the first display mode DM1, the display driver DDV may operate at a driving frequency of approximately N / 2 Hz in the second display mode DM2. Because the vertical synchronization signal Vsync is a signal that defines the start of one frame 1F, the frequency of the vertical synchronization signal Vsync may be approximately N / 2 Hz. In one or more embodiments, the frequency of the vertical synchronization signal Vsync in the first display mode DM1 may be approximately 120 Hz, and the frequency of the vertical synchronization signal Vsync in the second display mode DM2 may be approximately 60 Hz. One frame period and the first scanning period AS may start based on the falling edge of the vertical synchronization signal Vsync.

[0193] The timing controller 14 or a separate application processor may be configured to generate an active frame synchronization signal AFsync and transmit it to the touch sensor driver TDV. The active frame synchronization signal AFsync may be a signal having a first level voltage (e.g., an on-voltage) during the first scanning period AS and a second level voltage (e.g., an off-voltage) different from the first level voltage during the second scanning period SS. Figure 10B , the active frame synchronization signal AFsync is shown to have a high-level voltage during the first scanning period AS and a low-level voltage during the second scanning period SS, but in one or more other embodiments, the active frame synchronization signal AFsync may have a low-level voltage during the first scanning period AS and may have a high-level voltage during the second scanning period SS.

[0194] In one or more embodiments, the active frame synchronization signal AFsync may have a first voltage level during the first scan period AS of the second display mode DM2. In this case, the touch sensor driver TDV may distinguish the display mode of the display driver DDV based on whether the first voltage level of the active frame synchronization signal AFsync is applied. In one or more other embodiments, an application processor, etc. may be configured to transmit a separate signal for distinguishing the display mode of the display driver DDV to the touch sensor driver TDV.

[0195] When the display driver DDV operates in the second display mode DM2, the touch sensor driver TDV can be configured to perform one touch scan operation during each of the first touch scan period TSP1 and the second touch scan period TSP2. The first scan period AS can overlap with the first touch scan period TSP1, and the second scan period SS can overlap with the second touch scan period TSP2. In other words, the touch sensor driver TDV can be configured to perform two scan operations per frame 1F. Therefore, even when the display driver DDV operates at a driving frequency of approximately N / 2 Hz, the touch report rate of the touch sensor driver TDV can be maintained at approximately N Hz.

[0196] Because a data programming operation, in which data signals are written to pixels PX, is performed during the first scanning period AS, relatively high noise may occur. Because the touch sensor layer 400 is located on the display layer 200, the touch sensor TS may be affected by display noise caused by the pixels PX. For example, even if there is no touch event during the first scanning period AS, the capacitance value of the touch sensor TS may remain high due to the display node. In contrast, during the second scanning period SS, in which the data programming operation is not performed, display noise may be reduced.

[0197] In the first display mode DM1 including only the first scanning period AS, the capacitance value of the touch sensor TS remains relatively constant, but in the second display mode DM2 including the first scanning period AS and the second scanning period SS, the difference between the maximum value and the minimum value of the capacitance of the touch sensor TS may increase. Therefore, in the second display mode DM2, touch jitter may increase and the signal-to-noise ratio (SNR) of the touch sensor device TU may decrease.

[0198] Therefore, when the display driver DDV operates in the first display mode DM1, the touch sensor driver TDV can be configured to provide a first drive signal to the touch sensor TS. When the display driver DDV operates in the second display mode DM2, the touch sensor driver TDV can be configured to provide a second drive signal during the first touch scan period TSP1 and provide a third drive signal to the touch sensor TS during the second touch scan period TSP2. In this case, the second drive signal and the third drive signal can be signals having different frequencies, waveforms, numbers of pulses, etc.

[0199] Figure 11A is a view showing input / output signals of a display device in a first display mode, and Figure 11B is a view showing input / output signals of the display device in the second display mode.

[0200] refer to Figure 11A In the first display mode DM1, each frame 1F may include only one first scanning period AS. The first scanning period AS may overlap with the touch scanning period TSP.

[0201] During the touch scan period TSP, the touch sensor driver TDV may be configured to apply a first driving signal Tx1 to the driving electrodes TE of the touch sensor TS. In one or more embodiments, the first driving signal Tx1 may have a first driving voltage V1 that is a difference between a high level voltage and a low level voltage.

[0202] refer to Figure 11B In the second display mode DM2, each frame 1F may include a first scanning period AS and a second scanning period SS. The active frame synchronization signal AFsync may have a first level voltage during the first scanning period AS and a second level voltage during the second scanning period SS. The first scanning period AS may overlap with the first touch scanning period TSP1, and the second scanning period SS may overlap with the second touch scanning period TSP2.

[0203] The touch sensor driver TDV may be configured to apply the second drive signal Tx2 to the drive electrode TE of the touch sensor TS during the first touch scan period TSP1, and to apply the third drive signal Tx3 to the drive electrode TE of the touch sensor TS using the active frame synchronization signal AFsync during the second touch scan period TSP2. In other words, when the display driver DDV operates in the second display mode DM2, the touch sensor driver TDV may be configured to provide the second drive signal Tx2 to the touch sensor TS during the first scan period AS, and to provide the third drive signal Tx3 to the touch sensor TS during the second scan period SS.

[0204] The second driving signal Tx2 may have a second driving voltage V2, and the third driving signal Tx3 may have a third driving voltage V3. In this case, the second driving voltage V2 may be lower than the third driving voltage V3.

[0205] In one or more embodiments, the second drive voltage V2 of the second drive signal Tx2 may be approximately 0.5 times the first drive voltage V1 of the first drive signal Tx1, and the third drive voltage V3 of the third drive signal Tx3 may be approximately 1.5 times the first drive voltage V1. In this case, the amplitudes of the second drive voltage V2 and the third drive voltage V3 may be adjusted according to display noise. As an example, if the capacitance value of the touch sensor TS increases significantly due to display noise during the first scanning period AS, the second drive voltage V2 of the second drive signal Tx2 may be less than approximately 0.5 times the first drive voltage V1.

[0206] In one or more other embodiments, the display driver DDV may operate in a third display mode, and each frame 1F may include one first scan period AS and k second scan periods SS, where k is a positive integer. The first scan period AS may overlap with the first touch scan period TSP1, and each of the second scan periods SS may overlap with the second touch scan period TSP2. When the display driver DDV operates in the third display mode, the touch sensor driver TDV may be configured to provide a second drive signal Tx2 to the touch sensor TS during the first scan period AS and to provide a third drive signal Tx3 to the touch sensor TS during each second scan period SS. The second drive signal Tx2 may have a second drive voltage V2, and the third drive signal Tx3 may have a third drive voltage V3.

[0207] In this case, the second driving voltage V2 of the second driving signal Tx2 may be approximately 1 / (k+1) times the first driving voltage V1 of the first driving signal Tx1, and the third driving voltage V3 of the third driving signal Tx3 may be approximately (k+2) / (k+1) times the first driving voltage V1. The amplitudes of the second driving voltage V2 and the third driving voltage V3 may be adjusted according to display noise.

[0208] By making the second driving voltage V2 of the second driving signal Tx2 and the third driving voltage V3 of the third driving signal Tx3 different, touch jitter caused by display noise in the second display mode DM2 can be reduced and the SNR of the touch sensor device TU can be improved or optimized.

[0209] Figures 12 to 15 is a view showing input / output signals of the display device in the second display mode.

[0210] refer to Figure 12 When the display driver DDV operates in the second display mode DM2, each frame 1F may include a first scanning period AS and a second scanning period SS. The active frame synchronization signal AFsync may have a first level voltage during the first scanning period AS and a second level voltage during the second scanning period SS.

[0211] The first scan period AS may overlap with the first touch scan period TSP1, and the second scan period SS may overlap with the second touch scan period TSP2. The first touch scan period TSP1 may include a first sub-period SP1 and a second sub-period SP2.

[0212] The touch sensor driver TDV can be configured to apply a second drive signal Tx2 to the drive electrode TE of the touch sensor TS during the first scan period AS (or the first touch scan period TSP1), and apply a third drive signal Tx3 to the drive electrode TE of the touch sensor TS using the active frame synchronization signal AFsync during the second scan period SS (or the second touch scan period TSP2).

[0213] The touch sensor driver TDV may perform sampling with a first sampling number during the first scanning period AS, and may perform sampling with a second sampling number greater than the first sampling number during the second scanning period SS. Because the touch sensor driver TDV performs sampling based on the cycle of the drive signal, the first sampling number may be proportional to the number of pulses (or on-voltage signals) of the second drive signal Tx2 during the first scanning period AS, and the second sampling number may be proportional to the number of pulses (or on-voltage signals) of the third drive signal Tx3 during the second scanning period SS.

[0214] In one or more embodiments, the second drive signal Tx2 may repeat the on-voltage and off-voltage with a first period t1 during the first sub-period SP1, and may maintain the off-voltage during the second sub-period SP2. Here, the first period t1 represents a drive signal period in which the waveform of the drive signal repeats. In one or more other embodiments, the touch sensor driver TDV may be configured to output the second drive signal Tx2 only during the first sub-period SP1 and not output the second drive signal Tx2 during the second sub-period SP2.

[0215] That is, the touch sensor driver TDV can be configured to perform sampling only during the first sub-period SP1 of the first scanning period AS and not perform sampling during the second sub-period SP2. Conversely, the touch sensor driver TDV can be configured to perform sampling during the entire section of the second scanning period SS by outputting the third drive signal Tx3 that repeats the on-voltage and off-voltage during the second scanning period SS. The third drive signal Tx3 has the same frequency as the second drive signal Tx2 during the first sub-period SP1.

[0216] In one or more embodiments, the period of the second drive signal Tx2 and the period of the third drive signal Tx3 may be the same. As an example, when the period of the second drive signal Tx2 is the first period t1, the period of the third drive signal Tx3 may be equal to the first period t1.

[0217] By reducing the number of samples during the first scanning period AS where display noise may have a large influence, touch jitter caused by display noise in the second display mode DM2 may be reduced, and the SNR of the touch sensor device TU may be improved or optimized.

[0218] refer to Figure 13 , when the display driver DDV operates in the second display mode DM2, the touch sensor driver TDV can be configured to apply a second drive signal Tx2 to the drive electrode TE of the touch sensor TS during the first scanning period AS, and apply a third drive signal Tx3 having a frequency different from the frequency of the second drive signal Tx2 to the drive electrode TE of the touch sensor TS using the active frame synchronization signal AFsync during the second scanning period SS.

[0219] The second drive signal Tx2 may have a first period t1 in which the on-voltage and the off-voltage are repeated, and the third drive signal Tx3 may have a second period t2 different from the first period t1. In other words, the second drive signal Tx2 may have a first frequency 1 / t1, and the third drive signal Tx3 may have a second frequency 1 / t2 different from the first frequency. Here, the first frequency and the second frequency are drive signal frequencies or sampling frequencies and may range from several hundred Hz to several hundred kHz. The first frequency may be a frequency that is advantageous in terms of avoiding display noise, etc., and the second frequency may be a frequency that is advantageous in terms of improving touch sensitivity.

[0220] In one or more embodiments, the second frequency may be greater than the first frequency. In this case, the first period t1 of the second drive signal Tx2 may be greater than the second period t2 of the third drive signal Tx3. Therefore, even if the first scanning period AS does not include the second sub-period SP2 in which the second drive signal Tx2 is maintained at the cut-off voltage, the number of sampling operations performed during the first scanning period AS may be less than the number of sampling operations performed during the second scanning period SS.

[0221] refer to Figure 14 , when the display driver DDV operates in the second display mode DM2, the touch sensor driver TDV can be configured to apply the second drive signal Tx2 to the drive electrode TE of the touch sensor TS during the first scanning period AS, and apply the third drive signal Tx3 to the drive electrode TE of the touch sensor TS using the active frame synchronization signal AFsync during the second scanning period SS.

[0222] The second drive signal Tx2 may have a first pulse width w1, and the third drive signal Tx3 may have a second pulse width w2 different from the first pulse width w1. Here, the pulse width represents the time interval from approximately 50% of the rise time of the pulse to approximately 50% of the fall time of the pulse. The first pulse width w1 may have a value suitable for avoiding display noise. The second pulse width w2 may be different from the first pulse width w1 and may have a value for improving the touch sensitivity of the touch sensor device TU. As an example, the first pulse width w1 may be smaller than the second pulse width w2.

[0223] In one or more embodiments, because the pulse width of the second drive signal Tx2 is different from the pulse width of the third drive signal Tx3, the second drive signal Tx2 may have a first period t1, and the third drive signal Tx3 may have a second period t2 different from the first period t1. In other words, the second drive signal Tx2 may have a first frequency 1 / t1, and the third drive signal Tx3 may have a second frequency 1 / t2 different from the first frequency.

[0224] In one or more other embodiments, by adjusting the duty cycle of the second drive signal Tx2 and the third drive signal Tx3, the second drive signal Tx2 and the third drive signal Tx3 can have the same period. In other words, the second drive signal Tx2 and the third drive signal Tx3 can have different pulse widths but the same frequency. Here, the duty cycle of the drive signal represents the ratio of the pulse width to the period.

[0225] refer to Figure 15, when the display driver DDV operates in the second display mode DM2, the touch sensor driver TDV can be configured to apply the second drive signal Tx2 to the drive electrode TE of the touch sensor TS during the first scanning period AS, and apply the third drive signal Tx3 to the drive electrode TE of the touch sensor TS using the active frame synchronization signal AFsync during the second scanning period SS.

[0226] The second drive signal Tx2 can be a sinusoidal wave, and the third drive signal Tx3 can be a pulse wave or a square wave. Here, the sinusoidal wave can be a sine wave or a cosine wave. Because the noise of the sinusoidal wave can be appropriately removed, when the influence of the display noise is large, the SNR of the touch sensor device TU can be improved by applying the second drive signal Tx2 as a sinusoidal wave during the first scanning period AS. Conversely, because the pulse wave has high touch sensitivity, the touch sensitivity of the touch sensor device TU can be improved by applying the third drive signal Tx3 as a pulse wave during the second scanning period SS. In addition, because the sinusoidal wave has low power consumption compared to the pulse wave, the overall power consumption of the display device 1 can be reduced.

[0227] For ease of understanding, although Figures 11B to 15 The second drive signal Tx2 and the third drive signal Tx3 are shown in the case where they are different in terms of their drive voltage, period (or frequency), pulse width, waveform (sine wave, pulse wave) and / or the number of pulses, but the present disclosure is not limited thereto. The present disclosure includes various combinations of the above embodiments. The second drive signal Tx2 and the third drive signal Tx3 may be different in terms of at least one of their drive voltage, period, pulse width, waveform and the number of pulses depending on the operating environment such as display noise and the drive mode.

[0228] According to one or more embodiments, the touch report rate of the touch sensor device can be kept constant even when the refresh rate of the display changes. Therefore, even when the display is driven at a low frequency, the touch sensitivity of the touch sensor device can be reduced or prevented from decreasing.

[0229] According to one or more embodiments, the touch sensor driver is configured to output a noise-robust drive signal during an address scan operation section and output a drive signal with high touch sensitivity during a self-scan operation section, thereby improving the SNR of the touch sensor device and reducing or preventing a decrease in touch sensitivity.

[0230] According to one or more embodiments, a display device having a reduced jitter phenomenon caused by display noise and having improved touch sensing performance can be implemented. However, the scope of the present disclosure is not limited to the above.

[0231] It should be understood that the embodiments described herein should be considered to be descriptive only and not for the purpose of limitation. The description of aspects within each embodiment should generally be considered to be applicable to other similar aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims (and their functional equivalents should be included therein).

Claims

1. A display device, comprising: Pixels; a touch sensor over the pixel and including a first touch electrode and a second touch electrode; a display driver configured to drive the pixels in a first display mode or a second display mode, wherein in the first display mode, a frame includes a first scanning period, and in the second display mode, another frame includes the first scanning period and one or more second scanning periods; as well as Touch sensor driver, configured as: In the first display mode, providing a first driving signal to the touch sensor; as well as In the second display mode, a second driving signal is provided to the touch sensor during the first scanning period, and a third driving signal is provided to the touch sensor during the one or more second scanning periods, Wherein, in the first display mode and in the second display mode, the touch report rate of the touch sensor driver is the same.

2. The display device according to claim 1, wherein The display driver is configured to provide a first synchronization signal to the touch sensor driver, the first synchronization signal having a first level voltage during the first scanning period and having a second level voltage during the one or more second scanning periods.

3. The display device according to claim 1, in, The second driving signal has a first driving voltage, and The third driving signal has a second driving voltage greater than the first driving voltage.

4. The display device according to claim 3, in, The first driving signal has a third driving voltage, wherein the first driving voltage is 0.5 times the third driving voltage, and The second driving voltage is 1.5 times the third driving voltage.

5. The display device according to claim 3, wherein In the second display mode, the other frame includes one first scanning period and k second scanning periods, the first drive signal has a third drive voltage, the first drive voltage is 1 / (k+1) times the third drive voltage, and the second drive voltage is (k+2) / (k+1) times the third drive voltage, where k is a positive integer. The display device according to claim 1 , wherein: In the second display mode, the touch sensor driver has a smaller number of samples during the first scanning period than a number of samples during the one or more second scanning periods.

7. The display device according to claim 6, in, The first scanning period has a first sub-period and a second sub-period, and The second driving signal is configured to repeat the on-voltage and the off-voltage during the first sub-period, and maintain the off-voltage during the second sub-period.

8. The display device according to claim 7, wherein The second driving signal and the third driving signal have the same frequency.

9. The display device according to claim 1, in, The second drive signal has a first frequency, and The third driving signal has a second frequency different from the first frequency.

10. The display device according to claim 9, wherein The second frequency is greater than the first frequency.

11. The display device according to claim 1, in, The second driving signal has a first pulse width, and The third driving signal has a second pulse width different from the first pulse width.

12. The display device according to claim 11, wherein The first pulse width is smaller than the second pulse width.

13. The display device according to claim 11, wherein The second driving signal and the third driving signal have the same frequency.

14. The display device according to claim 1, in, The second driving signal is a sinusoidal wave, and Wherein, the third driving signal is a pulse wave.

15. A display device comprising: Pixels; a touch sensor, above the pixel, comprising a first touch electrode and a second touch electrode; a display driver configured to drive the pixels in a first display mode or a second display mode, wherein in the first display mode, a frame includes a first scanning period, and in the second display mode, another frame includes the first scanning period and one or more second scanning periods; as well as Touch sensor driver, configured as: In the first display mode, providing a first driving signal to the touch sensor; as well as In the second display mode, a second drive signal is provided to the touch sensor during the first scanning cycle, and a third drive signal is provided to the touch sensor during the one or more second scanning cycles, and the driving voltage, frequency or waveform of the second drive signal and the third drive signal or the number of samplings of the touch sensor driver during the first scanning cycle and the number of samplings during the one or more second scanning cycles are different.

16. The display device according to claim 15, wherein The display driver is configured to provide a first synchronization signal to the touch sensor driver, the first synchronization signal having a first level voltage during the first scanning period and a second level voltage during the one or more second scanning periods.

17. The display device according to claim 15, in, The second driving signal has a first driving voltage, and The third driving signal has a second driving voltage greater than the first driving voltage.

18. The display device according to claim 15, in, The first scanning period has a first sub-period and a second sub-period, and The second driving signal is configured to repeat a turn-on voltage and a turn-off voltage during the first sub-period, and maintain the turn-off voltage during the second sub-period.

19. The display device according to claim 18, wherein The third drive signal has the same frequency as the second drive signal during the first sub-period.

20. The display device according to claim 15, in, The second driving signal has a first pulse width, and The third driving signal has a second pulse width different from the first pulse width.

21. The display device according to claim 15, in, The second driving signal is a sinusoidal wave, and Wherein, the third driving signal is a pulse wave.

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