Display device

Abstract

A display device includes a plurality of data lines and a plurality of pixels. Each of the plurality of pixels includes a light emitting element, a first transistor, a second transistor for receiving a first scan signal, and a third transistor. The plurality of data lines include a plurality of first groups of data lines and a plurality of second groups of data lines. The plurality of pixels includes a plurality of first group pixels connected to the plurality of first group data lines and a plurality of second group pixels connected to the plurality of second group data lines. A first scan signal and a first clock signal are applied to different ones of the third transistors.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0018655 filed on February 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device with reduced power consumption, and more particularly, to a display device including a plurality of pixel groups connected to a shared scan line and receiving different clock signals. Background Art

[0004] Many electronic devices include display panels for displaying images. These electronic devices may include televisions, mobile phones, tablets, computers, navigation and game consoles.

[0005] The display device may be an organic light-emitting display device. An organic light-emitting display device may include a light-emitting element. The light-emitting element can generate light through the recombination of electrons and holes. Organic light-emitting displays generally have a fast response speed and low power consumption. Summary of the Invention

[0006] Embodiments of the present disclosure provide a display device with reduced power consumption.

[0007] An embodiment of the present disclosure provides a display device including a plurality of pixel groups connected to a shared scan line and receiving different clock signals.

[0008] According to an embodiment, a display device may include: a plurality of data lines and a plurality of pixels, wherein each of the plurality of pixels includes: a light-emitting element; a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node electrically connected to a first power line, and a second electrode connected to a third node electrically connected to the light-emitting element; a second transistor electrically connected to a first scan line and connected between a data line among the plurality of data lines and the first electrode of the first transistor; and first-third transistors and second-third transistors connected between the first node and the third node, wherein the plurality of data lines include: a plurality of first-group data lines; and a plurality of second-group data lines. The plurality of pixels include: a plurality of first-group pixels connected to the plurality of first-group data lines; and a plurality of second-group pixels connected to the plurality of second-group data lines, wherein the first scan line is electrically connected to one of the first-third transistor and the second-third transistor in each of the plurality of first-group pixels and the plurality of second-group pixels.

[0009] The first-third transistor and the second-third transistor may be connected in series between the first node and the third node, a first clock signal may be applied to the remaining one of the first-third transistor and the second-third transistor in each pixel of the plurality of first-group pixels, and a second clock signal different from the first clock signal may be applied to the remaining one of the first-third transistor and the second-third transistor in each pixel of the plurality of second-group pixels.

[0010] An active period of the first clock signal may be in a state not to overlap with an active period of the second clock signal.

[0011] The frame period may include a first subframe period and a second subframe period after the first subframe period, wherein during the first subframe period, the first clock signal has an activation level and the second clock signal has a deactivation level, and during the second subframe period, the second clock signal has an activation level and the first clock signal has a deactivation level.

[0012] According to an embodiment, a display device may include a plurality of data lines and a plurality of pixels. Each of the plurality of pixels may include: a light-emitting element; a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node electrically connected to a first power line, and a second electrode connected to a third node electrically connected to the light-emitting element; a second transistor configured to receive a first scan signal and connected between a data line in the plurality of data lines and the first electrode of the first transistor; and a plurality of third transistors connected between the first node and the third node. The plurality of data lines may include a plurality of first-group data lines and a plurality of second-group data lines. The plurality of pixels may include: a plurality of first-group pixels connected to the plurality of first-group data lines; and a plurality of second-group pixels connected to the plurality of second-group data lines. A first scan signal and a first clock signal may be applied to different transistors among the plurality of third transistors in each of the plurality of first-group pixels. A first scan signal and a second clock signal different from the first clock signal may be applied to different transistors among the plurality of third transistors in each of the plurality of second-group pixels.

[0013] An active period of the first clock signal may be in a state not to overlap with an active period of the second clock signal.

[0014] The frame period may include a first subframe period and a second subframe period following the first subframe period, and during the first subframe period, the first clock signal may have an activation level and the second clock signal may have a deactivation level. During the second subframe period, the second clock signal may have an activation level and the first clock signal may have a deactivation level.

[0015] The display device may further include: a demultiplexer connected to multiple data lines, the demultiplexer may include: multiple first control transistors respectively connected to multiple first groups of data lines to receive first control signals; and multiple second control transistors respectively connected to multiple second groups of data lines to receive second control signals.

[0016] During the first subframe period, the first control signal may alternately have an activation level and a deactivation level, and the second control signal may have a deactivation level, and during the second subframe period, the first control signal may have a deactivation level and the second control signal may alternately have an activation level and a deactivation level.

[0017] The plurality of third transistors may be formed as a first double transistor.

[0018] Each of the multiple pixels may further include: multiple fourth transistors connected between the first node and an initialization voltage line for applying an initialization voltage, the second scan signal and the first clock signal may be applied to different transistors among the multiple fourth transistors in each pixel of the multiple first groups of pixels, and the second scan signal and the second clock signal may be applied to different transistors among the multiple fourth transistors in each pixel of the multiple second groups of pixels.

[0019] Each of the multiple pixels may further include: multiple fifth transistors connected between the initialization voltage line and the light-emitting element, a third scan signal different from the second scan signal and the first clock signal may be applied to different transistors among the multiple fifth transistors in each pixel of the multiple first group pixels, and the third scan signal and the second clock signal may be applied to different transistors among the multiple fifth transistors in each pixel of the multiple second group pixels.

[0020] The plurality of fourth transistors may be formed as a second double transistor, and the plurality of fifth transistors may be formed as a third double transistor.

[0021] The display device may further include: a driving circuit configured to output a first scanning signal. The driving circuit may include: a plurality of scanning stages, including a plurality of first scanning stages and a plurality of second scanning stages. Each of the plurality of scanning stages may include: a first input node and a second input node, and a first scanning clock signal may be applied to the first input node of each of the plurality of first scanning stages, and a second scanning clock signal different from the first scanning clock signal may be applied to the second input node of each of the plurality of first scanning stages. A second scanning clock signal may be applied to the first input node of each of the plurality of second scanning stages, and the first scanning clock signal may be applied to the second input node of each of the plurality of second scanning stages.

[0022] The display device may further include a driving circuit configured to output a first scanning signal, wherein the driving circuit may include a plurality of scanning stages including a plurality of first scanning stages, a plurality of second scanning stages, a plurality of third scanning stages, and a plurality of fourth scanning stages. Each of the plurality of scanning stages may include: a first input node and a second input node, wherein a first scan clock signal may be applied to the first input node of each of the plurality of first scanning stages, and a second scan clock signal different from the first scan clock signal may be applied to the second input node of each of the plurality of first scanning stages, a second scan clock signal may be applied to the first input node of each of the plurality of second scanning stages, and a third scan clock signal different from the first scan clock signal and the second scan clock signal may be applied to the second input node of each of the plurality of second scanning stages, a third scan clock signal may be applied to the first input node of each of the plurality of third scanning stages, and a fourth scan clock signal different from the first scan clock signal, the second scan clock signal and the third scan clock signal may be applied to the second input node of each of the plurality of third scanning stages, and a fourth scan clock signal may be applied to the first input node of each of the plurality of fourth scanning stages, and the first scan clock signal may be applied to the second input node of each of the plurality of fourth scanning stages.

[0023] According to an embodiment, a display device may include: a plurality of pixels, including a plurality of first groups of pixels and a plurality of second groups of pixels. Each of the plurality of pixels may include: a light-emitting element; a first transistor connected between a first power supply line for applying a first power supply voltage and the light-emitting element, and including a gate electrode connected to a first node; a second transistor connected between the first transistor and a data line for applying a data signal, and including a gate electrode for receiving a first scan signal; and a plurality of third transistors connected between the first transistor and the first node. A first scan signal and a first clock signal may be applied to different transistors among the plurality of third transistors in each pixel of the plurality of first groups of pixels, and a first scan signal and a second clock signal different from the first clock signal may be applied to different transistors among the plurality of third transistors in each pixel of the plurality of second groups of pixels.

[0024] Each of the plurality of pixels may further include: a plurality of fourth transistors connected between the first node and an initialization voltage line for applying an initialization voltage; and a plurality of fifth transistors connected between the initialization voltage line and the light emitting element.

[0025] A second scan signal different from the first scan signal and the first clock signal may be applied to a different transistor among the plurality of fourth transistors in each pixel in the plurality of first group pixels. A second scan signal and a second clock signal may be applied to a different transistor among the plurality of fourth transistors in each pixel in the plurality of second group pixels.

[0026] A third scan signal different from the second scan signal and the first clock signal may be applied to a different transistor among the plurality of fifth transistors in each pixel in the plurality of first group pixels. The third scan signal and the second clock signal may be applied to a different transistor among the plurality of fifth transistors in each pixel in the plurality of second group pixels.

[0027] The third transistor may be formed as a first double transistor, the fourth transistor may be formed as a second double transistor, and the fifth transistor may be formed as a third double transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0029] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0030] Figure 2 is a perspective view of a display device according to an embodiment of the present disclosure.

[0031] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0032] Figure 4 is a conceptual diagram illustrating a portion of a display device according to an embodiment of the present disclosure.

[0033] Figure 5A and Figure 5B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0034] Figure 6 is a conceptual diagram illustrating a portion of a display device according to an embodiment of the present disclosure.

[0035] Figure 7A and Figure 7B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0036] Figure 8A is an equivalent circuit diagram of one first group of pixels among a plurality of first group of pixels according to an embodiment of the present disclosure.

[0037] Figure 8Bis an equivalent circuit diagram of one second group pixel among a plurality of second group pixels according to an embodiment of the present disclosure.

[0038] Figure 9 is a timing diagram illustrating the operation of the display device according to an embodiment of the present disclosure.

[0039] Figure 10A is an equivalent circuit diagram of one first group of pixels among a plurality of first group of pixels according to an embodiment of the present disclosure.

[0040] Figure 10B is an equivalent circuit diagram of one second group pixel among a plurality of second group pixels according to an embodiment of the present disclosure.

[0041] Figure 11A is an equivalent circuit diagram of one first group of pixels among a plurality of first group of pixels according to an embodiment of the present disclosure.

[0042] Figure 11B is an equivalent circuit diagram of one second group pixel among a plurality of second group pixels according to an embodiment of the present disclosure.

[0043] Figure 12A is an equivalent circuit diagram of one first group of pixels among a plurality of first group of pixels according to an embodiment of the present disclosure.

[0044] Figure 12B is an equivalent circuit diagram of one second group pixel among a plurality of second group pixels according to an embodiment of the present disclosure.

[0045] Figure 13A is an equivalent circuit diagram of one first group of pixels among a plurality of first group of pixels according to an embodiment of the present disclosure.

[0046] Figure 13B is an equivalent circuit diagram of one second group pixel among a plurality of second group pixels according to an embodiment of the present disclosure.

[0047] Figure 14A is an equivalent circuit diagram of one first group of pixels among a plurality of first group of pixels according to an embodiment of the present disclosure.

[0048] Figure 14B is an equivalent circuit diagram of one second group pixel among a plurality of second group pixels according to an embodiment of the present disclosure.

[0049] Figure 15A is an equivalent circuit diagram of one first group of pixels among a plurality of first group of pixels according to an embodiment of the present disclosure.

[0050] Figure 15B is an equivalent circuit diagram of one second group of pixels among a plurality of second group of pixels according to an embodiment of the present disclosure.

[0051] Figure 16A is an equivalent circuit diagram of one first group of pixels among a plurality of first group of pixels according to an embodiment of the present disclosure.

[0052] Figure 16B is an equivalent circuit diagram of one second group of pixels among a plurality of second group of pixels according to an embodiment of the present disclosure.

[0053] Figure 17A is a block diagram illustrating a first driving circuit according to an embodiment of the present disclosure.

[0054] Figure 17B is a block diagram illustrating a first driving circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] In the specification, the expression that a first component (or region, layer, part, portion, etc.) is “on,” “connected to,” or “coupled to” a second component may mean that the first component may be directly on, directly connected to, or directly coupled to the second component, or may mean that a third component is interposed between the first and second components. The expression that a first component is “directly disposed on,” “directly connected to,” or “directly coupled to” a second component may mean that no third component is interposed between the first and second components.

[0056] The same reference numerals will be assigned to the same components. In addition, in the drawings, the thickness, proportions, and sizes of the components may be exaggerated to effectively describe the technical features. The term "and / or" may include any and all combinations of one or more of the associated components.

[0057] Although the terms "first," "second," etc. may be used to describe various components, these components should not be construed as being limited by these terms. Terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope and spirit of the present disclosure. Unless the context clearly indicates otherwise, the singular is intended to include the plural.

[0058] In addition, the terms "below", "at the lower part", "above", and "upper" are used to describe the relationship between the components illustrated in the drawings. The terms are relative and are described with reference to the directions indicated in the drawings.

[0059] It will be further understood that the terms “include” or “comprises” or “has” and variations thereof specify the presence of stated features, quantities, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts and / or combinations thereof.

[0060] Unless otherwise defined, all terms (including technical and scientific terms) used in the specification have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms defined in dictionaries and commonly used should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0061] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0062] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0063] refer to Figure 1 The display device DD may be a device activated in response to an electrical signal. The display device DD may include an active area 1000A and a peripheral area 1000NA. The display device DD may display an image in the active area 1000A. The active area 1000A may include a surface defined by a first direction DR1 and a second direction DR2. The peripheral area 1000NA may be disposed adjacent to the active area 1000A. The peripheral area 1000NA may surround the active area 1000A. According to an embodiment of the present disclosure, the peripheral area 1000NA may be omitted.

[0064] The thickness direction of the display device DD may be parallel to a third direction DR3 crossing the first direction DR1 and the second direction DR2. Accordingly, the front surface (or top surface) and the rear surface (or bottom surface) of the member of the display device DD may be defined in the third direction DR3.

[0065] According to an embodiment of the present disclosure, the display device DD may be an emissive display. However, the present disclosure is not limited thereto. For example, the display device DD may be an organic light-emitting display device, a quantum dot light-emitting display device, a micro light-emitting diode (LED) display device, or a nano-LED display device. The light-emitting layer of the organic light-emitting display device may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display device may include quantum dots or quantum rods. The light-emitting layer of the micro-LED display device may include micro-LEDs. The light-emitting layer of the nano-LED display device may include nano-LEDs.

[0066] Figure 1 A display device DD serving as a portable terminal is illustrated. Figure 1The display device DD may be a straight-type device having a substantially rectangular parallelepiped shape. The portable terminal may include a tablet computer, a personal computer (PC), a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a game console, or a watch-type electronic device. However, the present disclosure is not limited thereto. In addition to large electronic devices such as televisions or outdoor billboards, the present disclosure may be used for small and medium-sized electronic devices such as personal computers, notebook computers, kiosks, car navigation units, or cameras. These display devices are examples, and the display device may be applied to various other applications without departing from the scope of the present disclosure.

[0067] Figure 2 is a perspective view of a display device according to an embodiment of the present disclosure.

[0068] refer to Figure 2 The display device DD-1 may include a folding area FA and a non-folding area. The non-folding area may include a first non-folding area NFA1 and a second non-folding area NFA2. The folding area FA may be located between the first non-folding area NFA1 and the second non-folding area NFA2.

[0069] like Figure 2 As shown in FIG, the folding area FA can be folded about a folding axis FX. The folding axis FX can be parallel to the second direction DR2. When the display device DD-1 is folded, the folding area FA can have a specific curvature and a specific radius of curvature. When the display device DD-1 is in a closed state, the first non-folding area NFA1 and the second non-folding area NFA2 can face each other so that the display surface is not exposed to the outside. For example, in the closed state, the display device DD-1 can be folded about the folding axis FX, and the opposing edges of the first non-folding area NFA1 and the second non-folding area NFA2 can be close together.

[0070] According to an embodiment of the present disclosure, the display device DD-1 can be in an open state, such that the display surface is exposed to the outside. For example, in the open state, the opposing edges of the first non-folding area NFA1 and the second non-folding area NFA2 can be spaced apart from each other. According to an embodiment of the present disclosure, the display device DD-1 can be in a closed state or an open state. However, the present disclosure is not limited thereto.

[0071] although Figure 2 The folding axis FX is shown to be defined in the display device DD-1, but the present disclosure is not limited thereto. For example, the display device DD-1 may include a plurality of folding axes defined therein and may be in an unfolded state to a closed state or an open state.

[0072] although Figure 1 and Figure 2A bar-type display device DD and a foldable-type display device DD-1 are illustrated, but the present disclosure is not limited thereto. For example, the following description will be applied to various electronic devices such as a curved electronic device, a rollable electronic device, or a slidable electronic device.

[0073] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0074] refer to Figure 3 , the display device DD may include a driving controller TC, a data driving circuit DDC, a demultiplexer DM, a first driving circuit SDC1 , a second driving circuit SDC2 , and pixels PXij disposed in the active area 1000A.

[0075] The display device DD may include a plurality of scan lines. For example, the display device DD may include first scan lines GWL1 to GWLn, second scan lines GIL1 to GILn, and third scan lines GBL1 to GBLn. The display device DD may include emission control lines EML1 to EMLn and data lines DL1 to DLm. In this case, n and m are integers greater than 1.

[0076] The data lines DL1 to DLm may be connected to the demultiplexer DM. The data lines DL1 to DLm may be connected between the demultiplexer DM and the active area 1000A. The data lines DL1 to DLm may be arranged in a first direction DR1, and each of the data lines DL1 to DLm may extend in a second direction DR2.

[0077] The first scan lines GWL1 to GWLn may be connected to the first drive circuit SDC1. The first scan lines GWL1 to GWLn may be connected between the first drive circuit SDC1 and the active area 1000A. The first scan lines GWL1 to GWLn may be arranged in the second direction DR2, and each of the first scan lines GWL1 to GWLn may extend in the first direction DR1.

[0078] The second scan lines GIL1 to GILn may be connected to the first drive circuit SDC1. The second scan lines GIL1 to GILn may be connected between the first drive circuit SDC1 and the active area 1000A. The second scan lines GIL1 to GILn may be arranged in the second direction DR2, and each of the second scan lines GIL1 to GILn may extend in the first direction DR1.

[0079] The third scan lines GBL1 to GBLn may be connected to the first drive circuit SDC1. The third scan lines GBL1 to GBLn may be connected between the first drive circuit SDC1 and the active area 1000A. The third scan lines GBL1 to GBLn may be arranged in the second direction DR2, and each of the third scan lines GBL1 to GBLn may extend in the first direction DR1.

[0080] The emission control lines EML1 to EMLn may be connected to the second drive circuit SDC2. The emission control lines EML1 to EMLn may be connected between the second drive circuit SDC2 and the active area 1000A. The emission control lines EML1 to EMLn may be arranged in the second direction DR2, and each of the emission control lines EML1 to EMLn may extend in the first direction DR1.

[0081] The display device DD may include a plurality of pixels connected to first scan lines GWL1 to GWLn, second scan lines GIL1 to GILn, third scan lines GBL1 to GBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm. As a representative example, Figure 3 The pixel PXij is shown. The pixel PXij can be electrically connected to the first scan line GWLi among the first scan lines GWL1 to GWLn and the data line DLj among the data lines DL1 to DLm, where i is an integer greater than 1 and less than or equal to n, and j is an integer greater than 1 and less than or equal to m. Although Figure 3 The first scan line GWLi among the first scan lines GWL1 to GWLn is shown to be connected to the pixel PXij, but the present disclosure is not limited thereto. For example, an additional scan line may be connected to the pixel PXij. The lines connected to the pixel PXij will be described herein.

[0082] The driver controller TC can receive input image signals RGB and a control signal CTRL. The driver controller TC can generate an image data signal DATA. The image data signal DATA can be formed by converting the data format of the image signal RGB to match the interface specification of the data driver circuit DDC. Furthermore, the driver controller TC can generate a first control signal DCS for controlling the data driver circuit DDC, a second control signal SCS for controlling the first driver circuit SDC1, and a third control signal ECS for controlling the second driver circuit SDC2.

[0083] According to an embodiment of the present disclosure, the display device DD may further include channel lines CL1 to CLx. The channel lines CL1 to CLx may be connected between the data driving circuit DDC and the demultiplexer DM. The channel lines CL1 to CLx may be selectively electrically connected to the data lines DL1 to DLm through the demultiplexer DM. The number of channel lines CL1 to CLx may be less than the number of data lines DL1 to DLm. More generally, x is an integer greater than 1 and less than m. Although the demultiplexer DM is included in the display device DD as an example, the present disclosure is not limited thereto. For example, the demultiplexer DM may be included in the data driving circuit DDC, implemented in the form of a separate integrated circuit, or integrated into a printed circuit board on which the data driving circuit DDC is mounted.

[0084] According to an embodiment of the present disclosure, due to the demultiplexer DM, the number of channels of data output from the data driver circuit DDC can be less than the number of data lines DL1 to DLm. The number of channels can correspond to the number of channel lines CL1 to CLx. In this case, the number of integrated circuit (IC) chips including the data driver circuit DDC included in the display device DD can be reduced as the number of channels decreases. In addition, as the number of channels of a single IC chip including the data driver circuit DDC decreases, the cost of the IC chip can be reduced.

[0085] The data drive circuit DDC may receive a first control signal DCS and an image data signal DATA from a drive controller TC. The data drive circuit DDC may convert the image data signal DATA into a data signal and output the data signal to the channel lines CL1 to CLx. The data signal may be an analog voltage corresponding to the grayscale value of the image data signal DATA. The demultiplexer DM may electrically connect some of the data lines DL1 to DLm to the channel lines CL1 to CLx, and the data signal may be output to some of the data lines DL1 to DLm.

[0086] The first drive circuit SDC1 may be connected to the first scan lines GWL1 to GWLn, the second scan lines GIL1 to GILn, and the third scan lines GBL1 to GBLn. The second drive circuit SDC2 may be connected to the emission control lines EML1 to EMLn. The first drive circuit SDC1 and the second drive circuit SDC2 may receive first and second control signals SCS and ECS, respectively, from a drive controller TC and may apply scan signals to the first scan lines GWL1 to GWLn, the second scan lines GIL1 to GILn, the third scan lines GBL1 to GBLn, and the emission control lines EML1 to EMLn based on the first and second control signals SCS and ECS.

[0087] The scan signal can be set to a voltage for turning on the transistor receiving the scan signal. For example, the scan signal applied to the P-type transistor can be set to a logic low level, and the scan signal applied to the N-type transistor can be set to a logic high level. Hereinafter, the meaning of "applying a scan signal" or "activating a scan signal" can be understood as applying a scan signal at a logic level for turning on the transistor controlled by the scan signal.

[0088] According to an embodiment of the present disclosure, the first driver circuit SDC1 and the second driver circuit SDC2 may be spaced apart from each other, and the active area 1000A may be interposed between the first driver circuit SDC1 and the second driver circuit SDC2. However, the present disclosure is not limited thereto. For example, the first driver circuit SDC1 and the second driver circuit SDC2 may be disposed on the same side of the active area 1000A, or at least a portion of the first driver circuit SDC1 and the second driver circuit SDC2 may be disposed within the active area 1000A.

[0089] Figure 4 is a conceptual diagram illustrating a portion of a display device according to an embodiment of the present disclosure. Figure 5A and Figure 5B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0090] refer to Figure 4 , four first scan lines GWL1, GWL2, GWL3, and GWL4, eight data lines DL, and 32 pixels PX11 to PX18, PX21 to PX28, PX31 to PX38, and PX41 to PX48 are illustrated. However, this is provided for illustrative purposes only, and the display device according to an embodiment of the present disclosure is not limited thereto.

[0091] The plurality of pixels PX11 to PX18, PX21 to PX28, PX31 to PX38 and PX41 to PX48 may include first pixels PX11, PX12, PX13, PX14, PX15, PX16, PX17, PX18, second pixels PX21, PX22, PX23, PX24, PX25, PX26, PX27, PX28, third pixels PX31, PX32, PX33, PX34, PX35, PX36, PX37 and PX38 and fourth pixels PX41, PX42, PX43, PX44, PX45, PX46, PX47 and PX48.

[0092] Each of the first pixels PX11 to PX18 may include a first emission region for outputting light having a first color. Each of the second pixels PX21 to PX28 may include a second emission region for outputting light having a second color different from the first color. Each of the third pixels PX31 to PX38 may include a third emission region for outputting light having a third color different from the first and second colors. Each of the fourth pixels PX41 to PX48 may include a fourth emission region for outputting light having a second color. The first color may be red, the second color may be green, and the third color may be blue. The second pixels PX21 to PX28 and the fourth pixels PX41 to PX48 may output light having the second color.

[0093] like Figure 4 As shown in FIG, dot hatching or comb-shaped hatching is illustrated in the first to fourth emission areas, respectively. The shapes of the second emission areas of the second pixels PX21 to PX28 and the shapes of the fourth emission areas of the fourth pixels PX41 to PX48 may be symmetrical to each other.

[0094] According to an embodiment of the present disclosure, the first emission region and the third emission region may be arranged alternately and repeatedly in the first direction DR1 and the second direction DR2. The second emission region and the fourth emission region may be arranged alternately and repeatedly in the first direction DR1 and the second direction DR2. For example, the second emission region may be provided within an area defined by two first emission regions and two third emission regions adjacent to each other.

[0095] Each of the plurality of pixels PX11 to PX18, PX21 to PX28, PX31 to PX38, and PX41 to PX48 may be electrically connected to a first scan line among the first scan lines GWL1, GWL2, GWL3, and GWL4 and a data line among the data lines DL. For example, the pixel PX11 may be connected to the scan line GWL1 and to the data line DL1-1.

[0096] The data lines DL may include a first group of data lines DLG1 and a second group of data lines DLG2. For example, when a data signal is applied to the first group of data lines DLG1, the data signal may not be applied to the second group of data lines DLG2. Alternatively, when a data signal is applied to the second group of data lines DLG2, the data signal may not be applied to the first group of data lines DLG1.

[0097] The diagram shows four first group data lines DL1-1, DL1-2, DL1-3, and DL1-4 included in the first group data lines DLG1 and four second group data lines DL2-1, DL2-2, DL2-3, and DL2-4 included in the second group data lines DLG2. The first group data lines DL1-1, DL1-2, DL1-3, and DL1-4 and the second group data lines DL2-1, DL2-2, DL2-3, and DL2-4 may be arranged alternately and repeatedly.

[0098] The first and second data lines DL1-1, DL1-2, DL1-3, DL1-4, DL2-1, DL2-2, DL2-3, and DL2-4 may be connected to a demultiplexer DM. The demultiplexer DM may include a plurality of first control transistors CTR1 connected corresponding to the first data lines DL1-1, DL1-2, DL1-3, and DL1-4, and a plurality of second control transistors CTR2 connected corresponding to the second data lines DL2-1, DL2-2, DL2-3, and DL2-4. For example, the demultiplexer DM may include a plurality of first control transistors CTR1 connected one-to-one with the first data lines DL1-1, DL1-2, DL1-3, and DL1-4, and a plurality of second control transistors CTR2 connected one-to-one with the second data lines DL2-1, DL2-2, DL2-3, and DL2-4.

[0099] The first control transistor CTR1 may be configured to be switched by a first control signal CLA (see FIG. 1 ) applied through a first control line CTL1. Figure 9 ) is controlled, and the second control transistor CTR2 may be configured to be controlled by a second control signal CLB (see Figure 9 )control.

[0100] The first pixel PX11, the second pixel PX21, the third pixel PX31, the fourth pixel PX41, the first pixel PX12, the second pixel PX22, the third pixel PX32, and the fourth pixel PX42 may be arranged in a first pixel row. The third pixel PX33, the fourth pixel PX43, the first pixel PX13, the second pixel PX23, the third pixel PX34, the fourth pixel PX44, the first pixel PX14, and the second pixel PX24 may be arranged in a second pixel row. The first pixel PX15, the second pixel PX25, the third pixel PX35, the fourth pixel PX45, the first pixel PX16, the second pixel PX26, the third pixel PX36, and the fourth pixel PX46 may be arranged in a third pixel row. The third pixel PX37, the fourth pixel PX47, the first pixel PX17, the second pixel PX27, the third pixel PX38, the fourth pixel PX48, the first pixel PX18, and the second pixel PX28 may be arranged in a fourth pixel row. The first to fourth pixel rows may extend in the first direction DR1 and may be sequentially arranged in the second direction DR2.

[0101] Pixels PX11, PX21, PX31, PX41, PX12, PX22, PX32, and PX42 arranged in the first pixel row can be connected to the 1-1 scan line GWL1. Pixels PX33, PX43, PX13, PX23, PX34, PX44, PX14, and PX24 arranged in the second pixel row can be connected to the 1-2 scan line GWL2. Pixels PX15, PX25, PX35, PX45, PX16, PX26, PX36, and PX46 arranged in the third pixel row can be connected to the 1-3 scan line GWL3. Pixels PX37, PX47, PX17, PX27, PX38, PX48, PX18, and PX28 arranged in the fourth pixel row can be connected to the 1-4 scan line GWL4. The 1-1 scan line GWL1 , the 1-2 scan line GWL2 , the 1-3 scan line GWL3 , and the 1-4 scan line GWL4 may extend in the first direction DR1 and may be sequentially arranged in the second direction DR2 .

[0102] According to an embodiment of the present disclosure, a plurality of pixels PX11 to PX18, PX21 to PX28, PX31 to PX38, and PX41 to PX48 may be divided into a plurality of first group pixels PX11 to PX18 and PX31 to PX38 connected to a first group of data lines DL1-1, DL1-2, DL1-3, and DL1-4, and a plurality of second group pixels PX21 to PX28 and PX41 to PX48 connected to a second group of data lines DL2-1, DL2-2, DL2-3, and DL2-4. The plurality of first group pixels PX11 to PX18 and PX31 to PX38 may be referred to as pixels arranged in odd-numbered columns, and the plurality of second group pixels PX21 to PX28 and PX41 to PX48 may be referred to as pixels arranged in even-numbered columns.

[0103] According to an embodiment of the present disclosure, the first group of pixels PX11 to PX18 and PX31 to PX38 may include first pixels PX11 to PX18 and third pixels PX31 to PX38. The second group of pixels PX21 to PX28 and PX41 to PX48 may include second pixels PX21 to PX28 and fourth pixels PX41 to PX48.

[0104] The first group of data lines DL1-1, DL1-2, DL1-3, and DL1-4 may be connected to the first pixels PX11 to PX18 and the third pixels PX31 to PX38, and the second group of data lines DL2-1, DL2-2, DL2-3, and DL2-4 may be connected to the second pixels PX21 to PX28 and the fourth pixels PX41 to PX48. For example, the first pixels PX11 and PX15 and the third pixels PX33 and PX37 may be connected to the first group of data lines DL1-1, and the second pixels PX21 and PX25 and the fourth pixels PX43 and PX47 may be connected to the second group of data lines DL2-1.

[0105] refer to Figures 4 to 5B , the display device DD can be used in a frame period FP (see Figure 9 ) is operated in units of . The data corresponding to the complete image can be processed in the frame period FP (see Figure 9 ) is applied to the pixel. Accordingly, the first to fourth pixels PX11 to PX18, PX21 to PX28, PX31 to PX38, and PX41 to PX48 may emit light during one frame period FP. For example, all of the first to fourth pixels PX11 to PX18, PX21 to PX28, PX31 to PX38, and PX41 to PX48 may emit light during one frame period FP. Frame period FP (see Figure 9 ) may include a first subframe period HFR1 and a second subframe period HFR2 subsequent to the first subframe period HFR1.

[0106] refer to Figure 4 and Figure 5A During the first subframe period HFR1, the first to fourth channel lines CL1, CL2, CL3, and CL4 may respond to the first control signal CLA (see Figure 9 ) and respectively transmit the first color data signal RD, the third color data signal BD, the first color data signal RD and the third color data signal BD to the first group of data lines DL1-1, DL1-2, DL1-3 and DL1-4.

[0107] For example, during the first subframe period HFR1, the first channel line CL1 and the third channel line CL3 may alternately output the first color data signal RD and the third color data signal BD, respectively, and the second channel line CL2 and the fourth channel line CL4 may alternately output the third color data signal BD and the first color data signal RD. In other words, during the first subframe period HFR1, the display device DD (see Figure 3 ) can display a first sub-image having a first color (eg, red) and a third color (eg, blue). For example, the first sub-image can have a magenta color.

[0108] refer to Figure 4 and Figure 5B During the second subframe period HFR2, each of the first to fourth channel lines CL1, CL2, CL3, and CL4 may respond to the second control signal CLB (see Figure 9 ) and transmit the second color data signal GD to the second group of data lines DL2-1, DL2-2, DL2-3, and DL2-4, respectively. For example, during the second subframe period HFR2, each of the first to fourth channel lines CL1, CL2, CL3, and CL4 can output the second color data signal GD. In other words, during the second subframe period HFR2, the display device DD can display a second sub-image having a second color (e.g., green).

[0109] The types of color data signals output during the subframe period according to the embodiment of the present disclosure can be reduced. The types of color data signals may include a data signal corresponding to red, a data signal corresponding to green, and a data signal corresponding to blue. Accordingly, the charge / discharge operation according to the change in the type of the color data signal can be reduced or eliminated, and the data driving circuit DDC (see Figure 3 For example, with respect to the change in the type of the color data signal, a change from a red data signal to a green data signal or a change from a red data signal to a blue data signal may be performed.

[0110] Figure 6is a conceptual diagram illustrating a portion of a display device according to an embodiment of the present disclosure, and Figure 7A and Figure 7B 1 is a diagram illustrating the operation of the display device according to an embodiment of the present disclosure. Figure 6 In the following description, the same reference numerals are assigned to reference Figure 4 The components described above are described, and their repeated descriptions may be omitted.

[0111] refer to Figure 6 The first group of data lines DL1-1a, DL1-2a, DL1-3a and DL1-4a may include the 1-1 group of data lines DL1-1a connected to the first pixels PX11 and PX15, the 1-2 group of data lines DL1-2a and DL1-4a connected to the second pixels PX21, PX24, PX25 and PX28 and the fourth pixels PX42, PX43, PX46 and PX47, and the 1-3 group of data lines DL1-3a connected to the third pixels PX32, PX34, PX36 and PX38.

[0112] The second group of data lines DL2-1a, DL2-2a, DL2-3a and DL2-4a may include the 2-1 group of data lines DL2-1a connected to the third pixels PX31, PX33, PX35 and PX37, the 2-2 group of data lines DL2-2a and DL2-4a connected to the second pixels PX22, PX23, PX26 and PX27 and the fourth pixels PX41, PX44, PX45 and PX48, and the 2-3 group of data lines DL2-3a connected to the first pixels PX12, PX13, PX16 and PX17.

[0113] The 1-1 group of data lines DL1-1a, the 2-1 group of data lines DL2-1a, the 1-2 group of data lines DL1-2a, the 2-2 group of data lines DL2-2a, the 2-3 group of data lines DL2-3a, the 1-3 group of data lines DL1-3a, the 2-2 group of data lines DL2-4a and the 1-2 group of data lines DL1-4a can extend in the second direction DR2 and can be arranged sequentially in the first direction DR1.

[0114] refer to Figure 6 and Figure 7A During the first subframe period HFR1a, the first to fourth channel lines CL1, CL2, CL3, and CL4 may respond to the first control signal CLA (see Figure 9) and is electrically connected to the first group of data lines DL1-1a, DL1-2a, DL1-3a, and DL1-4a. The first color data signal RD can be sequentially output through the first channel line CL1, the second color data signal GD can be sequentially output through each of the second channel line CL2 and the fourth channel line CL4, and the third color data signal BD can be sequentially output through the third channel line CL3. In other words, during the first subframe period HFR1a, the display device DD (see Figure 3 ) can display a first sub-image having a first color (e.g., red), a second color (e.g., green), and a third color (e.g., blue).

[0115] refer to Figure 6 and Figure 7B During the second subframe period HFR2a, the first to fourth channel lines CL1, CL2, CL3, and CL4 may respond to the second control signal CLB (see Figure 9 ) and electrically connected to the second group of data lines DL2-1a, DL2-2a, DL2-3a and DL2-4a. The third color data signal BD can be sequentially output through the first channel line CL1, the second color data signal GD can be sequentially output through each of the second channel line CL2 and the fourth channel line CL4, and the first color data signal RD can be sequentially output through the third channel line CL3. In other words, during the second subframe period HFR2a, the display device DD (see Figure 3 ) can display a second sub-image having a first color (e.g., red), a second color (e.g., green), and a third color (e.g., blue).

[0116] According to an embodiment of the present disclosure, for each of the first subframe period HFR1a and the second subframe period HFR2a, the data signal applied to the pixel emitting light having the same color can be applied to the channel line. Therefore, the charging / discharging operation caused by the change in the type of the color data signal can be omitted, and the data driving circuit DDC (see Figure 3 ) power consumption.

[0117] In addition, according to an embodiment of the present disclosure, for each of the first subframe period HFR1a and the second subframe period HFR2a, a sub-image having a first color (e.g., red), a second color (e.g., green), and a third color (e.g., blue) can be displayed. Accordingly, the probability of a color breakup phenomenon in which a color difference between the first subframe period HFR1a and the second subframe period HFR2a can be perceived can be reduced or eliminated.

[0118] Figure 8A is an equivalent circuit diagram of one first group of pixels among a plurality of first group of pixels according to an embodiment of the present disclosure.

[0119] A plurality of pixels PXij (see Figure 3 ) can each have a 7T1C structure. Figure 3 ) may include a plurality of first groups of pixels PX11 to PX18 and PX31 to PX38 (see Figure 4 ) and a plurality of second groups of pixels PX21 to PX28 and PX41 to PX48 (see Figure 4 ).

[0120] Figure 8A A plurality of first groups of pixels PX11 to PX18 and PX31 to PX38 are shown (see Figure 4 ) in the first group of pixels GP1.

[0121] refer to Figure 3 and Figure 8A , the first group of pixels GP1 may include a light emitting element ED, first to seventh transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 , and a capacitor Cst.

[0122] The light-emitting element ED may be a light-emitting diode. According to an embodiment of the present disclosure, the light-emitting element ED may be an organic light-emitting diode including an organic emission layer, but the present disclosure is not particularly limited thereto. The first group of pixels GP1 may control the amount of current flowing through the light-emitting element ED in response to the data signal DT. The light-emitting element ED may emit light having a specific brightness in response to the amount of current supplied from the pixel circuit (e.g., the first group of pixels GP1).

[0123] Each of the first to seventh transistors T1 to T7 may be a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, this is provided for illustrative purposes only, and the semiconductor layer according to an embodiment of the present disclosure is not limited thereto. For example, the semiconductor layer may include an oxide semiconductor or crystalline silicon. However, the present disclosure is provided for illustrative purposes only, and the first to seventh transistors T1 to T7 according to an embodiment of the present disclosure may be N-type transistors. According to an embodiment, at least one of the first to seventh transistors T1 to T7 may be a P-type transistor, and the remaining transistors among the first to seventh transistors T1 to T7 may be N-type transistors.

[0124] The first transistor T1 may control the brightness of the light emitting element ED and may be configured to include a semiconductor layer including polysilicon having high reliability, thereby realizing a high-resolution display device.

[0125] Each of the first scan lines GWL1 to GWLn can transmit a first scan signal GW. Each of the second scan lines GIL1 to GILn can transmit a second scan signal GI. Each of the third scan lines GBL1 to GBLn can transmit a third scan signal GB. Each of the emission control lines EML1 to EMLn can transmit an emission control signal EM. Each of the data lines DL1 to DLm can transmit a data signal DT. The data signal DT can have the same characteristics as the image signal RGB (see Figure 3 ) corresponding to the voltage level.

[0126] The first power line VL1 may provide a first power voltage ELVDD to the first group of pixels GP1. The second power line VL2 may provide a second power voltage ELVSS to the first group of pixels GP1. The initialization voltage line VL3 may provide an initialization voltage Vint to the first group of pixels GP1.

[0127] The first transistor T1 may be connected between a first power line VL1 for receiving a first power voltage ELVDD and the light-emitting element ED. The first transistor T1 may include a first electrode connected to the first power line VL1 via a fifth transistor T5, a second electrode connected to the first electrode (or referred to as an anode electrode) of the light-emitting element ED via a sixth transistor T6, and a gate electrode connected to an end of the capacitor Cst. The gate electrode of the first transistor T1 may be connected to a first node N1, the first electrode of the first transistor T1 may be connected to a second node N2, and the second electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 may receive a data signal DT via a data line DL in response to a switching operation of the second transistor T2 and may apply a driving current to the light-emitting element ED. The first transistor T1 may be referred to as a driving transistor.

[0128] The second transistor T2 may be connected between the data line DL and the first electrode of the first transistor T1. The second transistor T2 may include a first electrode connected to the data line DL, a second electrode connected to the second node N2, and a gate electrode for receiving the first scan signal GW. The second transistor T2 may be turned on according to the first scan signal GW to transmit the data signal DT that may be received through the data line DL to the first electrode of the first transistor T1.

[0129] The transistors T3-1 and T3-2 may be connected between the first node N1 and the third node N3. The third transistors T3-1 and T3-2 may include a 3-1st transistor (or a first-third transistor) T3-1 and a 3-2nd transistor (or a second-third transistor) T3-2. The 3-1st transistor T3-1 and the 3-2nd transistor T3-2 may be connected in series.

[0130] According to the present disclosure, the third transistors T3-1 and T3-2 can be configured as a dual transistor. When the dual transistors are turned off, leakage current can be reduced or eliminated. Accordingly, the display quality of the display device DD can be improved.

[0131] The 3-1th transistor T3 - 1 may include a first electrode connected to the first node N1 , a second electrode serially connected to the 3-2nd transistor T3 - 2 , and a gate electrode for receiving the first clock signal GCLA.

[0132] The 3-2 th transistor T3 - 2 may include a first electrode connected in series to the 3-1 th transistor T3 - 1 , a second electrode connected to the third node N3 , and a gate electrode for receiving the first scan signal GW.

[0133] In other words, the first scan signal GW may be applied to one of the third transistors T3-1 and T3-2 of the first group of pixels GP1, and the first clock signal GCLA may be applied to the remaining one of the third transistors T3-1 and T3-2. For example, the first scan signal GW may be applied to the 3-2 transistor T3-2, and the first clock signal GCLA may be applied to the 3-1 transistor T3-1.

[0134] The transistors T3 - 1 and T3 - 2 may be turned on in response to the first scan signal GW and the first clock signal GCLA to connect the gate electrode of the first transistor T1 to the second electrode of the first transistor T1 so that the first transistor T1 may be diode-connected.

[0135] The transistors T4-1 and T4-2 may be connected between the first node N1 and the initialization voltage line VL3 for receiving the initialization voltage Vint. The fourth transistors T4-1 and T4-2 may include a 4-1st transistor T4-1 and a 4-2nd transistor T4-2. The 4-1st transistor T4-1 and the 4-2nd transistor T4-2 may be connected in series.

[0136] According to the present disclosure, the fourth transistors T4-1 and T4-2 can be configured as a dual transistor. When the dual transistors are turned off, leakage current can be reduced or eliminated. Accordingly, the display quality of the display device DD can be improved.

[0137] The 4-1th transistor T4 - 1 may include a first electrode connected to the initialization voltage line VL3 , a second electrode serially connected to the 4-2nd transistor T4 - 2 , and a gate electrode for receiving the first clock signal GCLA.

[0138] The 4-2 transistor T4-2 may include a first electrode connected in series to the 4-1 transistor T4-1, a second electrode connected to the first node N1, and a gate electrode for receiving the second scan signal GI. However, this is provided for illustrative purposes only. For example, according to an embodiment of the present disclosure, the first scan signal GW may be applied to the gate electrode of the 4-2 transistor T4-2 instead of the second scan signal GI. For example, when the n-th first scan signal GWn is applied to the gate electrode of the second transistor T2, the n-1-th first scan signal GWn-1 may be applied to the gate electrode of the 4-2 transistor T4-2.

[0139] In other words, the second scan signal GI may be applied to one of the fourth transistors T4-1 and T4-2 of the first group of pixels GP1, and the first clock signal GCLA may be applied to the remaining one of the fourth transistors T4-1 and T4-2. For example, the second scan signal GI may be applied to the 4-2 transistor T4-2, and the first clock signal GCLA may be applied to the 4-1 transistor T4-1.

[0140] The fourth transistors T4 - 1 and T4 - 2 may be turned on in response to the second scan signal GI and the first clock signal GCLA to transmit the initialization voltage Vint to the first node N1 so that the potential of the gate electrode of the first transistor T1 may be initialized.

[0141] The fifth transistor T5 may include a first electrode connected to the first power line VL1, a second electrode connected to the second node N2, and a gate electrode for receiving the emission control signal EM. The sixth transistor T6 may include a first electrode connected to the third node N3, a second electrode connected to the first electrode of the light emitting element ED, and a gate electrode for receiving the emission control signal EM.

[0142] The fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously in response to the emission control signal EM. The first power supply voltage ELVDD applied by the turned-on fifth transistor T5 can be compensated by the diode-connected first transistor T1, and the first power supply voltage ELVDD can be transmitted to the light emitting element ED through the sixth transistor T6.

[0143] The transistors T7-1 and T7-2 may be connected between the initialization voltage line VL3 and the light emitting element ED. The seventh transistors T7-1 and T7-2 may include a 7-1st transistor T7-1 and a 7-2nd transistor T7-2. The 7-1st transistor T7-1 and the 7-2nd transistor T7-2 may be connected in series.

[0144] According to the present disclosure, the seventh transistors T7-1 and T7-2 can be configured as a dual transistor. When the dual transistors are turned off, leakage current can be reduced or eliminated. Accordingly, the display quality of the display device DD can be improved.

[0145] The 7-1th transistor T7-1 may include a first electrode connected to the initialization voltage line VL3, a second electrode serially connected to the 7-2nd transistor T7-2, and a gate electrode for receiving the first clock signal GCLA.

[0146] The 7-2 transistor T7-2 may include a first electrode connected in series to the 7-1 transistor T7-1, a second electrode connected to the light-emitting element ED, and a gate electrode for receiving the third scan signal GB. However, this is provided for illustrative purposes only. For example, according to an embodiment of the present disclosure, the first scan signal GW may be applied to the gate electrode of the 7-2 transistor T7-2 instead of the third scan signal GB.

[0147] In other words, the third scan signal GB may be applied to one of the seventh transistors T7-1 and T7-2 of the first group of pixels GP1, and the first clock signal GCLA may be applied to the remaining one of the seventh transistors T7-1 and T7-2. For example, the third scan signal GB may be applied to the 7-2 transistor T7-2, and the first clock signal GCLA may be applied to the 7-1 transistor T7-1.

[0148] The transistors T7 - 1 and T7 - 2 may be turned on in response to the third scan signal GB and the first clock signal GCLA to transmit the initialization voltage Vint to the first electrode of the light emitting element ED, thereby initializing the potential of the anode electrode of the light emitting element ED.

[0149] A first end of the capacitor Cst may be connected to the first node N1, and a second end of the capacitor Cst may be connected to the first power line VL1. A second electrode (also referred to as a cathode electrode) of the light emitting element ED may be connected to the second power line VL2. The second power supply voltage ELVSS may have a voltage level lower than that of the first power supply voltage ELVDD.

[0150] Figure 8B is an equivalent circuit diagram of one of the second group pixels of the plurality of second group pixels according to an embodiment of the present disclosure. Figure 8B In the following description, the same reference numerals will be assigned to reference numerals. Figure 8A The components described above are described, and their repeated descriptions may be omitted.

[0151] Figure 8B A plurality of second groups of pixels PX21 to PX28 and PX41 to PX48 are shown (see Figure 4 ) in a second group of pixels GP2.

[0152] refer to Figure 3 and Figure 8B , the 3-1st transistor T3-1 may include a first electrode connected to the first node N1, a second electrode connected in series to the 3-2nd transistor T3-2, and a gate electrode for receiving the second clock signal GCLB. The second clock signal GCLB may be different from the first clock signal GCLA (see Figure 8A ).

[0153] The 3-2 th transistor T3 - 2 may include a first electrode connected in series to the 3-1 th transistor T3 - 1 , a second electrode connected to the third node N3 , and a gate electrode for receiving the first scan signal GW.

[0154] In other words, the first scan signal GW may be applied to one of the third transistors T3-1 and T3-2 of the second group of pixels GP2, and the second clock signal GCLB may be applied to the remaining one of the third transistors T3-1 and T3-2. For example, the first scan signal GW may be applied to the 3-2 transistor T3-2, and the second clock signal GCLB may be applied to the 3-1 transistor T3-1.

[0155] The 4-1th transistor T4 - 1 may include a first electrode connected to the initialization voltage line VL3 , a second electrode serially connected to the 4-2nd transistor T4 - 2 , and a gate electrode for receiving the second clock signal GCLB.

[0156] The 4-2 th transistor T4 - 2 may include a first electrode connected in series to the 4-1 th transistor T4 - 1 , a second electrode connected to the first node N1 , and a gate electrode for receiving the second scan signal GI.

[0157] In other words, the second scan signal GI may be applied to one of the fourth transistors T4-1 and T4-2 of the second group of pixels GP2, and the second clock signal GCLB may be applied to the remaining one of the fourth transistors T4-1 and T4-2. For example, the second scan signal GI may be applied to the 4-2 transistor T4-2, and the second clock signal GCLB may be applied to the 4-1 transistor T4-1.

[0158] The 7-1th transistor T7-1 may include a first electrode connected to the initialization voltage line VL3, a second electrode serially connected to the 7-2nd transistor T7-2, and a gate electrode for receiving the second clock signal GCLB.

[0159] The 7-2 th transistor T7 - 2 may include a first electrode connected in series to the 7-1 th transistor T7 - 1 , a second electrode connected to the light emitting element ED, and a gate electrode for receiving the third scan signal GB.

[0160] In other words, the third scan signal GB may be applied to one of the seventh transistors T7-1 and T7-2 of the second group of pixels GP2, and the second clock signal GCLB may be applied to the remaining one of the seventh transistors T7-1 and T7-2. For example, the third scan signal GB may be applied to the 7-2 transistor T7-2, and the second clock signal GCLB may be applied to the 7-1 transistor T7-1.

[0161] In other words, the second group of pixels GP2 may receive the second clock signal GCLB instead of the first clock signal GCLA applied in the first group of pixels GP1. The first clock signal GCLA and the second clock signal GCLB will be described herein.

[0162] Figure 9 is a timing diagram illustrating the operation of the display device according to an embodiment of the present disclosure.

[0163] refer to Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 8A 、 Figure 8B and Figure 9 During the first subframe period HFR1, the first control signal CLA may be alternately and repeatedly applied with an activation level and a deactivation level, and the second control signal CLB may have a deactivation level. Referring to the first control signal CLA and the second control signal CLB, the activation level may be a low level, and the deactivation level may be a high level.

[0164] During the first subframe period HFR1, the first clock signal GCLA may have an activation level, and the second clock signal GCLB may have a deactivation level. For example, in the first subframe period HFR1, in response to activation of the first control signal CLA in the first subframe period HFR1, the first clock signal GCLA may be transitioned to an activation level, and the second clock signal GCLB may be transitioned to a deactivation level. In the first subframe period HFR1, throughout multiple clock cycles of the first control signal CLA, the first clock signal GCLA may be maintained at an activation level, and the second clock signal GCLB may be maintained at a deactivation level. With reference to the first clock signal GCLA and the second clock signal GCLB, the activation level may be a low level, and the deactivation level may be a high level.

[0165] During the first subframe period HFR1, one of the third transistors T3-1 and T3-2, one of the fourth transistors T4-1 and T4-2, and one of the seventh transistors T7-1 and T7-2 of the first group of pixels GP1 may be turned on in response to the first clock signal GCLA. For example, the 3-1st transistor T3-1, the 4-1st transistor T4-1, and the 7-1st transistor T7-1 may be turned on in response to the first clock signal GCLA. During the first subframe period HFR1, the first group of pixels GP1 may emit light from the light-emitting element ED in response to the first scan signal GW.

[0166] During the first subframe period HFR1, in the second group of pixels GP2, one of the third transistors T3-1 and T3-2, one of the fourth transistors T4-1 and T4-2, and one of the seventh transistors T7-1 and T7-2 may be turned off in response to the second clock signal GCLB. For example, the 3-1st transistor T3-1, the 4-1st transistor T4-1, and the 7-1st transistor T7-1 may be turned off in response to the second clock signal GCLB. During the first subframe period HFR1, the second group of pixels GP2 may not emit light from the light emitting element ED.

[0167] During the first subframe period HFR1, the plurality of first scan lines GWL1, GWL2, GWL3, and GWL4 may be sequentially activated. For example, the first scan signals GW1, GW2, GW3, GW4 to GWn-1 and GWn applied to the first scan lines GWL1 to GWLn may sequentially have an activation level (e.g., a low level).

[0168] During the first subframe period HFR1 , the data signal DT may be applied to a first group of pixels GP1 connected to the first group of data lines DL1 - 1 , DL1 - 2 , DL1 - 3 , and DL1 - 4 among the first to fourth pixels PX11 to PX18 , PX21 to PX28 , PX31 to PX38 , and PX41 to PX48 .

[0169] During the second subframe period HFR2 , the first control signal CLA may have a deactivation level, and the second control signal CLB may be alternately and repeatedly applied with an activation level and a deactivation level.

[0170] During the second subframe period HFR2, the second clock signal GCLB may have an activation level, and the first clock signal GCLA may have a deactivation level. The activation period of the first clock signal GCLA may not overlap with the activation period of the second clock signal GCLB. That is, the activation period of the first clock signal GCLA may be in a state that does not overlap with the activation period of the second clock signal GCLB. For example, in the second subframe period HFR2, in response to the activation of the second control signal CLB, the first clock signal GCLA may be changed to a deactivation level, and the second clock signal GCLB may be changed to an activation level. In the second subframe period HFR2, throughout multiple clock cycles of the second control signal CLB, the first clock signal GCLA may be maintained at the deactivation level, and the second clock signal GCLB may be maintained at the activation level.

[0171] During the second subframe period HFR2, in the first group of pixels GP1, one of the third transistors T3-1 and T3-2, one of the fourth transistors T4-1 and T4-2, and one of the seventh transistors T7-1 and T7-2 may be turned off in response to the first clock signal GCLA. For example, the 3-1st transistor T3-1, the 4-1st transistor T4-1, and the 7-1st transistor T7-1 may be turned off in response to the first clock signal GCLA. During the second subframe period HFR2, the first group of pixels GP1 may not emit light from the light emitting element ED.

[0172] During the second subframe period HFR2, in the second group of pixels GP2, one of the third transistors T3-1 and T3-2, one of the fourth transistors T4-1 and T4-2, and one of the seventh transistors T7-1 and T7-2 may be turned on in response to the second clock signal GCLB. For example, the 3-1st transistor T3-1, the 4-1st transistor T4-1, and the 7-1st transistor T7-1 may be turned on in response to the second clock signal GCLB. During the second subframe period HFR2, the second group of pixels GP2 may emit light from the light-emitting element ED in response to the first scan signal GW.

[0173] During the second subframe period HFR2, the first scan lines GWL1, GWL2, GWL3, and GWL4 may be sequentially activated. For example, the first scan signals GW1, GW2, GW3, GW4 to GWn-1 and GWn applied to the first scan lines GWL1 to GWLn may sequentially have activation levels.

[0174] During the second subframe period HFR2, the data signal DT may be applied to the second group of pixels PX21 to PX28 and PX41 to PX48 connected to the second group of data lines DL2-1, DL2-2, DL2-3 and DL2-4 among the first to fourth pixels PX11 to PX18, PX21 to PX28, PX31 to PX38 and PX41 to PX48.

[0175] According to the present disclosure, the first group of pixels GP1 and the second group of pixels GP2 can be connected to the same first scan line GWLi (see Figure 3 ). In some embodiments, the pixel area can be reduced compared to the case where the first group of pixels GP1 and the second group of pixels GP2 are connected to different scan lines. In some embodiments, the number of pixels arranged in the same area can be increased. Accordingly, the display device DD (see Figure 1 ) can be achieved with high resolution.

[0176] In a comparative embodiment, when the first group of pixels GP1 and the second group of pixels GP2 are connected to different first scan lines, a plurality of first drive circuits SDC1 may be provided to output first scan signals GW to drive the first group of pixels GP1 and the second group of pixels GP2, respectively. According to an embodiment of the present disclosure, the first drive circuit SDC1 may be used to provide the first scan signal GW. The first group of pixels GP1 and the second group of pixels GP2 may be driven separately by the first clock signal GCLA and the second clock signal GCLB. Accordingly, a plurality of first drive circuits SDC1 may be provided in the peripheral area 1000NA (see Figure 1 ) with a reduced area display device DD (see Figure 1 ).

[0177] In addition, according to an embodiment of the present disclosure, the first scanning signal GW can be provided by using the first driving circuit SDC1. In this case, the amount of power consumed in the first driving circuit SDC1 can be reduced compared to the amount of power consumed when the first scanning signal GW is applied separately to the first group of pixels GP1 and the second group of pixels GP2 to drive the first group of pixels GP1 and the second group of pixels GP2. Accordingly, the display device DD (see Figure 1 ) power consumption.

[0178] Figure 10A is an equivalent circuit diagram of a first group of pixels according to an embodiment of the present disclosure. Figure 10B is an equivalent circuit diagram of the second group of pixels according to an embodiment of the present disclosure. Figure 10A and Figure 10B In the following description, the same reference numerals will be assigned to reference numerals. Figure 8A and Figure 8B The components described above are described, and their repeated descriptions may be omitted.

[0179] refer to Figure 10A and Figure 10B The first and second pixel groups GP1a and GP2a may include first to seventh transistors T1, T2, T3-1, T3-2, T4-1a, T4-2a, T5, T6, T7-1, and T7-2, a capacitor Cst, and a light emitting element ED.

[0180] The 4-1th transistor T4-1a may include a first electrode connected to the initialization voltage line VL3, a second electrode serially connected to the 4-2nd transistor T4-2a, and a gate electrode for receiving the second scan signal GI.

[0181] The 4-2 th transistor T4 - 2 a may include a first electrode connected in series to the 4-1 th transistor T4 - 1 a , a second electrode connected to the first node N1 , and a gate electrode.

[0182] The first clock signal GCLA may be applied to the gate electrode of the 4-2 th transistor T4 - 2 a of the first group pixel GP1 a , and the second clock signal GCLB may be applied to the gate electrode of the 4-2 th transistor T4 - 2 a of the second group pixel GP2 a .

[0183] Figure 11A is an equivalent circuit diagram of a first group of pixels according to an embodiment of the present disclosure. Figure 11B is an equivalent circuit diagram of the second group of pixels according to an embodiment of the present disclosure. Figure 11A and Figure 11B In the following description, the same reference numerals are assigned to reference Figure 8A and Figure 8B The components described above are described, and their repeated descriptions may be omitted.

[0184] refer to Figure 11A and Figure 11B The first and second pixel groups GP1b and GP2b may include first to seventh transistors T1, T2, T3-1b, T3-2b, T4-1, T4-2, T5, T6, T7-1, and T7-2, a capacitor Cst, and a light emitting element ED.

[0185] The 3-1th transistor T3 - 1b may include a first electrode connected to the first node N1, a second electrode serially connected to the 3-2nd transistor T3 - 2b, and a gate electrode for receiving the first scan signal GW.

[0186] The 3-2 th transistor T3 - 2 b may include a first electrode connected in series to the 3-1 th transistor T3 - 1 b , a second electrode connected to the third node N3 , and a gate electrode.

[0187] The first clock signal GCLA may be applied to the gate electrode of the 3-2 th transistor T3 - 2 b of the first group pixel GP1 a , and the second clock signal GCLB may be applied to the gate electrode of the 3-2 th transistor T3 - 2 b of the second group pixel GP2 a .

[0188] Figure 12A is an equivalent circuit diagram of a first group of pixels according to an embodiment of the present disclosure. Figure 12B is an equivalent circuit diagram of the second group of pixels according to an embodiment of the present disclosure. Figure 12A and Figure 12B In the following description, the same reference numerals will be assigned to reference numerals. Figure 8A and Figure 8B The components described above are described, and their repeated descriptions may be omitted.

[0189] refer to Figure 12A and Figure 12B The first and second pixel groups GP1c and GP2c may include first to seventh transistors T1, T2, T3-1c, T3-2c, T4-1c, T4-2c, T5, T6, T7-1, and T7-2, a capacitor Cst, and a light emitting element ED.

[0190] The 3-1th transistor T3 - 1c may include a first electrode connected to the first node N1, a second electrode serially connected to the 3-2nd transistor T3 - 2c, and a gate electrode for receiving the first scan signal GW.

[0191] The 3-2 th transistor T3 - 2 c may include a first electrode connected in series to the 3-1 th transistor T3 - 1 c , a second electrode connected to the third node N3 , and a gate electrode.

[0192] The first clock signal GCLA may be applied to the gate electrode of the 3-2 th transistor T3 - 2 c of the first group pixel GP1 c , and the second clock signal GCLB may be applied to the gate electrode of the 3-2 th transistor T3 - 2 c of the second group pixel GP2 c .

[0193] The 4-1th transistor T4 - 1c may include a first electrode connected to the initialization voltage line VL3 , a second electrode serially connected to the 4-2nd transistor T4 - 2c , and a gate electrode for receiving the second scan signal GI.

[0194] The 4-2nd transistor T4-2c may include a first electrode connected in series to the 4-1st transistor T4-1c, a second electrode connected to the first node N1, and a gate electrode.

[0195] The first clock signal GCLA may be applied to the gate electrode of the 4-2 th transistor T4 - 2 c of the first group pixel GP1 c , and the second clock signal GCLB may be applied to the gate electrode of the 4-2 th transistor T4 - 2 c of the second group pixel GP2 c .

[0196] Figure 13A is an equivalent circuit diagram of a first group of pixels according to an embodiment of the present disclosure. Figure 13B is an equivalent circuit diagram of the second group of pixels according to an embodiment of the present disclosure. Figure 13A and Figure 13B In the following description, the same reference numerals will be assigned to reference numerals. Figure 8A and Figure 8B The components described above are described, and their repeated descriptions may be omitted.

[0197] refer to Figure 13A and Figure 13B The first and second pixel groups GP1d and GP2d may include first to seventh transistors T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6, T7-1d, and T7-2d, a capacitor Cst, and a light emitting element ED.

[0198] The 7-1th transistor T7-1d may include a first electrode connected to the initialization voltage line VL3, a second electrode serially connected to the 7-2nd transistor T7-2d, and a gate electrode for receiving the third scan signal GB.

[0199] The 7-2nd transistor T7-2d may include a first electrode connected in series to the 7-1st transistor T7-1d, a second electrode connected to the light emitting element ED, and a gate electrode.

[0200] The first clock signal GCLA may be applied to the gate electrode of the 7-2 nd transistor T7 - 2 d of the first group pixel GP1 d, and the second clock signal GCLB may be applied to the gate electrode of the 7-2 nd transistor T7 - 2 d of the second group pixel GP2 d.

[0201] Figure 14A is an equivalent circuit diagram of a first group of pixels according to an embodiment of the present disclosure. Figure 14B is an equivalent circuit diagram of the second group of pixels according to an embodiment of the present disclosure. Figure 14A and Figure 14B In the following description, the same reference numerals are assigned to reference Figure 8A and Figure 8B The components described above are described, and their repeated descriptions may be omitted.

[0202] refer to Figure 14A and Figure 14BThe first and second pixel groups GP1e and GP2e may include first to seventh transistors T1, T2, T3-1, T3-2, T4-1e, T4-2e, T5, T6, T7-1e, and T7-2e, a capacitor Cst, and a light emitting element ED.

[0203] The 4-1th transistor T4 - 1e may include a first electrode connected to the initialization voltage line VL3 , a second electrode serially connected to the 4-2nd transistor T4 - 2e , and a gate electrode for receiving the second scan signal GI.

[0204] The 4-2nd transistor T4-2e may include a first electrode connected in series to the 4-1st transistor T4-1e, a second electrode connected to the first node N1, and a gate electrode.

[0205] The first clock signal GCLA may be applied to the gate electrode of the 4-2 nd transistor T4 - 2 e of the first group pixel GP1 e, and the second clock signal GCLB may be applied to the gate electrode of the 4-2 nd transistor T4 - 2 e of the second group pixel GP2 e.

[0206] The 7-1st transistor T7-1e may include a first electrode connected to the initialization voltage line VL3, a second electrode serially connected to the 7-2nd transistor T7-2e, and a gate electrode for receiving the third scan signal GB.

[0207] The 7-2nd transistor T7-2e may include a first electrode connected in series to the 7-1st transistor T7-1e, a second electrode connected to the light emitting element ED, and a gate electrode.

[0208] The first clock signal GCLA may be applied to the gate electrode of the 7-2 th transistor T7 - 2 e of the first group pixel GP1 e, and the second clock signal GCLB may be applied to the gate electrode of the 7-2 th transistor T7 - 2 e of the second group pixel GP2 e.

[0209] Figure 15A is an equivalent circuit diagram of a first group of pixels according to an embodiment of the present disclosure. Figure 15B is an equivalent circuit diagram of the second group of pixels according to an embodiment of the present disclosure. Figure 15A and Figure 15B In the following description, the same reference numerals are assigned to reference Figure 8A and Figure 8B The components described above are described, and their repeated descriptions may be omitted.

[0210] refer to Figure 15A and Figure 15BThe first and second pixel groups GP1f and GP2f may include first to seventh transistors T1, T2, T3-1f, T3-2f, T4-1, T4-2, T5, T6, T7-1f, T7-2f, a capacitor Cst, and a light emitting element ED.

[0211] The 3-1st transistor T3 - 1f may include a first electrode connected to the first node N1, a second electrode serially connected to the 3-2nd transistor T3 - 2f, and a gate electrode for receiving the first scan signal GW.

[0212] The 3-2nd transistor T3-2f may include a first electrode connected in series to the 3-1st transistor T3-1f, a second electrode connected to the third node N3, and a gate electrode.

[0213] The first clock signal GCLA may be applied to the gate electrode of the 3-2 th transistor T3 - 2 f of the first group pixel GP1 f , and the second clock signal GCLB may be applied to the gate electrode of the 3-2 th transistor T3 - 2 f of the second group pixel GP2 f .

[0214] The 7-1st transistor T7-1f may include a first electrode connected to the initialization voltage line VL3, a second electrode serially connected to the 7-2nd transistor T7-2f, and a gate electrode for receiving the third scan signal GB.

[0215] The 7-2nd transistor T7-2f may include a first electrode connected in series to the 7-1st transistor T7-1f, a second electrode connected to the light emitting element ED, and a gate electrode.

[0216] The first clock signal GCLA may be applied to the gate electrode of the 7-2 th transistor T7 - 2 f of the first group pixel GP1 f, and the second clock signal GCLB may be applied to the gate electrode of the 7-2 th transistor T7 - 2 f of the second group pixel GP2 f.

[0217] Figure 16A is an equivalent circuit diagram of a first group of pixels according to an embodiment of the present disclosure. Figure 16B is an equivalent circuit diagram of the second group of pixels according to an embodiment of the present disclosure. Figure 16A and Figure 16B In the following description, the same reference numerals are assigned to reference Figure 8A and Figure 8B The components described above are described, and their repeated descriptions may be omitted.

[0218] refer to Figure 16A and Figure 16BThe first and second pixel groups GP1g and GP2g may include first to seventh transistors T1, T2, T3-1g, T3-2g, T4-1g, T4-2g, T5, T6, T7-1g, T7-2g, a capacitor Cst, and a light emitting element ED.

[0219] The 3-1th transistor T3-1g may include a first electrode connected to the first node N1, a second electrode serially connected to the 3-2nd transistor T3-2g, and a gate electrode for receiving the first scan signal GW.

[0220] The 3-2 th transistor T3 - 2 g may include a first electrode connected in series to the 3-1 th transistor T3 - 1 g , a second electrode connected to the third node N3 , and a gate electrode.

[0221] The first clock signal GCLA may be applied to the gate electrode of the 3-2 nd transistor T3 - 2 g of the first group pixel GP1 g, and the second clock signal GCLB may be applied to the gate electrode of the 3-2 nd transistor T3 - 2 g of the second group pixel GP2 g.

[0222] The 4-1th transistor T4-1g may include a first electrode connected to the initialization voltage line VL3, a second electrode serially connected to the 4-2nd transistor T4-2g, and a gate electrode for receiving the second scan signal GI.

[0223] The 4-2nd transistor T4-2g may include a first electrode connected in series to the 4-1st transistor T4-1g, a second electrode connected to the first node N1, and a gate electrode.

[0224] The first clock signal GCLA may be applied to the gate electrode of the 4-2 nd transistor T4 - 2 g of the first group pixel GP1 g, and the second clock signal GCLB may be applied to the gate electrode of the 4-2 nd transistor T4 - 2 g of the second group pixel GP2 g.

[0225] The 7-1st transistor T7-1g may include a first electrode connected to the initialization voltage line VL3, a second electrode serially connected to the 7-2nd transistor T7-2g, and a gate electrode for receiving the third scan signal GB.

[0226] The 7-2nd transistor T7-2g may include a first electrode connected in series to the 7-1st transistor T7-1g, a second electrode connected to the light emitting element ED, and a gate electrode.

[0227] The first clock signal GCLA may be applied to the gate electrode of the 7-2 th transistor T7 - 2 g of the first group pixel GP1 g, and the second clock signal GCLB may be applied to the gate electrode of the 7-2 th transistor T7 - 2 g of the second group pixel GP2 g.

[0228] Figure 17A is a block diagram illustrating a first driving circuit according to an embodiment of the present disclosure.

[0229] refer to Figure 3 and Figure 17A The first drive circuit SDC1 may include a plurality of scanning stages ST1, ST2, ST3, and ST4. Each of the plurality of scanning stages ST1 to ST4 may include a first input node and a second input node for receiving different scan clock signals. Each of the plurality of scanning stages ST1 to ST4 may receive a first scan clock signal CLK1, a second scan clock signal CLK2, and a carry signal. The first drive circuit SDC1 may output first scan signals GW1, GW2, GW3, and GW4.

[0230] The plurality of scanning stages ST1 to ST4 may include a first scanning stage ST1, a second scanning stage ST2, a third scanning stage ST3, and a fourth scanning stage ST4. The plurality of scanning stages ST1 to ST4 may be arranged in sequence. Figure 17A Four scanning stages are illustrated in FIG, but the number of scanning stages according to an embodiment of the present disclosure is not limited thereto.

[0231] Depending on the scan clock signal applied to the input node, the plurality of scan stages ST1 to ST4 may belong to different groups of scan stages. For example, the first scan stage ST1 and the third scan stage ST3, which receive the first scan clock signal CLK1 at the first input node and the second scan clock signal CLK2 at the second input node, may belong to the plurality of first scan stages. The second scan stage ST2 and the fourth scan stage ST4, which receive the first scan clock signal CLK1 at the second input node and the second scan clock signal CLK2 at the first input node, may belong to the plurality of second scan stages.

[0232] The plurality of scan stages ST1 to ST4 may be connected to correspond to the plurality of first scan lines GWL1 , GWL2 , GWL3 , and GWL4 , respectively.

[0233] The first scanning stage ST1 among the plurality of scanning stages ST1 to ST4 may receive a start signal FLM which may serve as a carry signal of the first scanning stage ST1. The first scanning stage ST1 may receive a start signal FLM from the driving controller TC (see Figure 3 )Receive the start signal FLM.

[0234] Each of the remaining scanning stages ST2, ST3, and ST4 among the plurality of scanning stages ST1 to ST4 can receive a scanning signal among the first scanning signals GW1, GW2, GW3, and GW4 output from the previous scanning stage and serving as a carry signal. For example, the second scanning stage ST2 can receive the first scanning signal GW1 output from the first scanning stage ST1, and the first scanning signal GW1 can serve as a carry signal for the second scanning stage ST2. The third scanning stage ST3 can receive the first scanning signal GW2 output from the second scanning stage ST2, and the first scanning signal GW2 can serve as a carry signal for the third scanning stage ST3. The fourth scanning stage ST4 can receive the first scanning signal GW3 output from the third scanning stage ST3, and the first scanning signal GW3 can serve as a carry signal for the fourth scanning stage ST4.

[0235] The phase of the first scan clock signal CLK1 and the second scan clock signal CLK2 may be shifted in sequence. The first scan clock signal CLK1 may have a first voltage and a second voltage that repeat at a specific period. The first voltage may have a voltage level higher than that of the second voltage. The first voltage may be referred to as a high level. The second voltage may be referred to as a low level.

[0236] Figure 17B is a block diagram illustrating a first driving circuit according to an embodiment of the present disclosure.

[0237] refer to Figure 3 and Figure 17B The first drive circuit SDC1a may include a plurality of scanning stages ST1-1, ST2-1, ST3-1, ST4-1, ST5-1, ST6-1, ST7-1, ST8-1, and ST9-1. Each of the plurality of scanning stages ST1-1 to ST9-1 may include a first input node and a second input node for receiving different scan clock signals.

[0238] For example, the plurality of scanning stages ST1-1 to ST9-1 may sequentially receive a combination of two clock signals from among the first scanning clock signal CLK1-1, the second scanning clock signal CLK2-1, the third scanning clock signal CLK3-1, and the fourth scanning clock signal CLK4-1. The plurality of scanning stages ST1-1 to ST9-1 may respectively output scanning signals GW1a, GW2a, GW3a, GW4a, GW5a, GW6a, GW7a, GW8a, and GW9a.

[0239] The plurality of scanning stages ST1-1 to ST9-1 may include a first scanning stage ST1-1, a second scanning stage ST2-1, a third scanning stage ST3-1, a fourth scanning stage ST4-1, a fifth scanning stage ST5-1, a sixth scanning stage ST6-1, a seventh scanning stage ST7-1, an eighth scanning stage ST8-1, and a ninth scanning stage ST9-1. The plurality of scanning stages ST1-1 to ST9-1 may be arranged sequentially. Figure 17B Nine scanning stages are illustrated in FIG, but the number of scanning stages according to an embodiment of the present disclosure is not limited thereto.

[0240] According to the scan clock signal applied to the first input node and the second input node, a plurality of scan stages ST1-1 to ST9-1 can belong to different groups of scan stages. For example, the first scan stage ST1-1, the fifth scan stage ST5-1, and the ninth scan stage ST9-1 that receive the first scan clock signal CLK1-1 at the first input node and the second scan clock signal CLK2-1 at the second input node can belong to multiple first scan stages. The second scan stage ST2-1 and the sixth scan stage ST6-1 that receive the second scan clock signal CLK2-1 at the first input node and the third scan clock signal CLK3-1 at the second input node can belong to multiple second scan stages. The third scan stage ST3-1 and the seventh scan stage ST7-1 that receive the third scan clock signal CLK3-1 at the first input node and the fourth scan clock signal CLK4-1 at the second input node can belong to multiple third scan stages. The fourth scan stage ST4-1 and the eighth scan stage ST8-1 that receive the fourth scan clock signal CLK4-1 at the first input node and the first scan clock signal CLK1-1 at the second input node can belong to multiple fourth scan stages.

[0241] Among the plurality of scanning stages ST1-1 to ST9-1, the first scanning stage ST1-1 may receive a start signal FLM which may serve as a carry signal of the first scanning stage ST1-1. The first scanning stage ST1-1 may receive a start signal FLM from the driving controller TC (see Figure 3 )Receive the start signal FLM.

[0242] The phases of the first scanning clock signal CLK1-1, the second scanning clock signal CLK2-1, the third scanning clock signal CLK3-1, and the fourth scanning clock signal CLK4-1 may be sequentially shifted. In the first scanning clock signal CLK1-1, the second scanning clock signal CLK2-1, the third scanning clock signal CLK3-1, and the fourth scanning clock signal CLK4-1, the first voltage and the second voltage may be repeated at a specific cycle.

[0243] According to the present disclosure, when four clock signals such as a first scan clock signal CLK1-1, a second scan clock signal CLK2-1, a third scan clock signal CLK3-1, and a fourth scan clock signal CLK4-1 are used, the capacitance of each of the first scan clock signal CLK1-1, the second scan clock signal CLK2-1, the third scan clock signal CLK3-1, and the fourth scan clock signal CLK4-1 can be reduced by half, and the period can be doubled compared to when two clock signals are used. Since each of the capacitance and the frequency can be reduced by half, the power consumption can be reduced to one-quarter (i.e., 1 / 4). Accordingly, a display device DD with reduced power consumption can be provided (see Figure 1 ).

[0244] As described above, the first group of pixels and the second group of pixels can be connected to the same first scan line. Compared to the case where the first group of pixels and the second group of pixels can be connected to different scan lines, the pixel area can be reduced. A first drive circuit can be used to apply a first scan signal to the first group of pixels and the second group of pixels. The first group of pixels and the second group of pixels can be driven separately in response to a first clock signal and a second clock signal. The area of the non-display area can be reduced. In addition, the first drive circuit can be used to apply the first scan signal. In this case, compared to the case of driving multiple first drive circuits, the power consumption in the first drive circuit can be reduced. Accordingly, the display device can have reduced power consumption.

[0245] Although the embodiments of the present disclosure have been described for illustrative purposes, it will be understood by those skilled in the art that various modifications and substitutions are possible without departing from the scope and spirit of the present disclosure as disclosed in the claims. Accordingly, the technical scope of the present disclosure is not limited to the detailed description of this specification, but should be defined by the claims.

[0246] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the claims.

Claims

1. A display device, comprising: Multiple data lines and multiple pixels, Each of the plurality of pixels includes: Light-emitting element; a first transistor including a gate electrode connected to the first node, a first electrode connected to a second node electrically connected to the first power line, and a second electrode connected to a third node electrically connected to the light emitting element; a second transistor electrically connected to the first scan line and connected between a data line among the plurality of data lines and the first electrode of the first transistor; and A first-third transistor and a second-third transistor are connected between the first node and the third node, Wherein, the plurality of data lines include: a first plurality of data lines; and Multiple second set of data lines, Wherein, the plurality of pixels include: a first plurality of pixels connected to the first plurality of data lines; and a plurality of second group pixels connected to the plurality of second group data lines, The first scan line is electrically connected to one of the first-third transistors and the second-third transistors in each pixel of the plurality of first group pixels and the plurality of second group pixels.

2. The display device according to claim 1, wherein The first-third transistors and the second-third transistors are connected in series between the first node and the third node, A first clock signal is applied to the remaining one of the first-third transistors and the second-third transistors in each pixel of the plurality of first group pixels, and A second clock signal different from the first clock signal is applied to the remaining one of the first-third transistors and the second-third transistors in each pixel of the plurality of second group pixels.

3. The display device according to claim 2, wherein: An active period of the first clock signal is in a state of not overlapping with an active period of the second clock signal.

4. The display device according to claim 2, wherein The frame period includes: a first subframe period and a second subframe period following the first subframe period, wherein, during the first subframe period, the first clock signal has an activation level and the second clock signal has a deactivation level, and During the second subframe period, the second clock signal has the activation level and the first clock signal has the deactivation level.

5. A display device comprising: Multiple data lines and multiple pixels, Each of the plurality of pixels includes: Light-emitting element; a first transistor including a gate electrode connected to the first node, a first electrode connected to a second node electrically connected to the first power line, and a second electrode connected to a third node electrically connected to the light emitting element; a second transistor configured to receive a first scan signal and connected between a data line among the plurality of data lines and the first electrode of the first transistor; and a plurality of third transistors connected between the first node and the third node, Wherein, the plurality of data lines include: a first plurality of data lines; and Multiple second set of data lines, Wherein, the plurality of pixels include: a first plurality of pixels connected to the first plurality of data lines; and a plurality of second group pixels connected to the plurality of second group data lines, wherein the first scan signal and the first clock signal are applied to different transistors among the plurality of third transistors in each pixel of the plurality of first group pixels, and The first scan signal and a second clock signal different from the first clock signal are applied to different transistors of the plurality of third transistors in each pixel of the plurality of second group pixels. The display device according to claim 5 , wherein: An active period of the first clock signal is in a state of not overlapping with an active period of the second clock signal.

7. The display device according to claim 5, wherein The frame period includes: a first subframe period and a second subframe period following the first subframe period, wherein, during the first subframe period, the first clock signal has an activation level and the second clock signal has a deactivation level, and During the second subframe period, the second clock signal has the activation level and the first clock signal has the deactivation level.

8. The display device according to claim 7, further comprising: a demultiplexer connected to the plurality of data lines, Wherein, the demultiplexer comprises: a plurality of first control transistors respectively connected to the plurality of first data lines to receive first control signals; and A plurality of second control transistors are respectively connected to the plurality of second data lines to receive second control signals.

9. The display device according to claim 8, wherein During the first subframe period, the first control signal alternately has the activation level and the deactivation level, and the second control signal has the deactivation level, and During the second subframe period, the first control signal has the deactivation level, and the second control signal alternately has the activation level and the deactivation level.

10. The display device according to claim 5, wherein The plurality of third transistors are formed as a first double transistor.

11. The display device according to claim 5, wherein Each pixel of the plurality of pixels further comprises: a plurality of fourth transistors connected between the first node and an initialization voltage line for applying an initialization voltage, wherein the second scan signal and the first clock signal are applied to different transistors among the plurality of fourth transistors in each pixel of the plurality of first group pixels, and The second scan signal and the second clock signal are applied to different ones of the plurality of fourth transistors in each pixel of the plurality of second group pixels.

12. The display device according to claim 11, wherein Each pixel of the plurality of pixels further comprises: a plurality of fifth transistors connected between the initialization voltage line and the light emitting element; wherein a third scan signal different from the second scan signal and the first clock signal are applied to different transistors among the plurality of fifth transistors in each pixel of the plurality of first group pixels, and The third scan signal and the second clock signal are applied to different transistors of the plurality of fifth transistors in each pixel of the plurality of second group pixels.

13. The display device according to claim 12, wherein: The plurality of fourth transistors are formed as a second double transistor, and the plurality of fifth transistors are formed as a third double transistor.

14. The display device according to any one of claims 5 to 13, further comprising: a driving circuit configured to output the first scanning signal, Wherein, the driving circuit includes: a plurality of scanning stages, including a plurality of first scanning stages and a plurality of second scanning stages, Each of the plurality of scanning stages includes: The first input node and the second input node, wherein a first scan clock signal is applied to the first input node of each of the plurality of first scan stages, and a second scan clock signal different from the first scan clock signal is applied to the second input node of each of the plurality of first scan stages, The second scan clock signal is applied to the first input node of each of the plurality of second scan stages, and The first scan clock signal is applied to the second input node of each of the plurality of second scan stages.

15. The display device according to any one of claims 5 to 13, further comprising: a driving circuit configured to output the first scanning signal, Wherein, the driving circuit includes: a plurality of scanning stages, including a plurality of first scanning stages, a plurality of second scanning stages, a plurality of third scanning stages, and a plurality of fourth scanning stages, Each of the plurality of scanning stages includes: The first input node and the second input node, wherein a first scan clock signal is applied to the first input node of each of the plurality of first scan stages, and a second scan clock signal different from the first scan clock signal is applied to the second input node of each of the plurality of first scan stages, The second scan clock signal is applied to the first input node of each of the plurality of second scan stages, and a third scan clock signal different from the first scan clock signal and the second scan clock signal is applied to the second input node of each of the plurality of second scan stages, the third scan clock signal is applied to the first input node of each of the plurality of third scan stages, and a fourth scan clock signal different from the first scan clock signal, the second scan clock signal, and the third scan clock signal is applied to the second input node of each of the plurality of third scan stages, and The fourth scan clock signal is applied to the first input node of each of the plurality of fourth scan stages, and the first scan clock signal is applied to the second input node of each of the plurality of fourth scan stages.

16. A display device comprising: a plurality of pixels, including a plurality of first group pixels and a plurality of second group pixels, Each of the plurality of pixels includes: Light-emitting element; a first transistor connected between a first power supply line for applying a first power supply voltage and the light emitting element and including a gate electrode connected to a first node; a second transistor connected between the first transistor and a data line for applying a data signal and including a gate electrode for receiving a first scan signal; and a plurality of third transistors connected between the first transistor and the first node, wherein the first scan signal and the first clock signal are applied to different transistors among the plurality of third transistors in each pixel of the plurality of first group pixels, and The first scan signal and a second clock signal different from the first clock signal are applied to different transistors of the plurality of third transistors in each pixel of the plurality of second group pixels.

17. The display device according to claim 16, wherein: Each pixel of the plurality of pixels further comprises: a plurality of fourth transistors connected between the first node and an initialization voltage line for applying an initialization voltage; and A plurality of fifth transistors are connected between the initialization voltage line and the light emitting element.

18. The display device according to claim 17, wherein: A second scan signal different from the first scan signal and the first clock signal are applied to different transistors of the plurality of fourth transistors in each pixel of the plurality of first group pixels, and The second scan signal and the second clock signal are applied to different ones of the plurality of fourth transistors in each pixel of the plurality of second group pixels.

19. The display device according to claim 18, wherein A third scan signal different from the second scan signal and the first clock signal are applied to different transistors of the plurality of fifth transistors in each pixel of the plurality of first group pixels, and The third scan signal and the second clock signal are applied to different transistors of the plurality of fifth transistors in each pixel of the plurality of second group pixels.

20. The display device according to claim 19, wherein The plurality of third transistors are formed as a first double transistor, the plurality of fourth transistors are formed as a second double transistor, and the plurality of fifth transistors are formed as a third double transistor.

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