Display device

Abstract

A display device includes pixels each including: a first transistor including a gate connected to a first node, a source connected to a second node, and a drain connected to a third node; a second transistor including a gate configured to receive a first gate signal, a source configured to receive a data voltage, and a drain connected to a fourth node; a third transistor including a gate configured to receive a second gate signal, a source connected to the third node, and a drain connected to the first node; a storage capacitor including a first terminal connected to the first node and a second terminal connected to the fourth node; and a light emitting element including a first terminal connected to the fifth node and a second terminal configured to receive a second power supply voltage. At least two of the pixels share at least two transistors.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display device including pixels supporting a variable refresh rate and high-speed driving. Background Art

[0002] The display device may include a plurality of pixels. Each of the pixels may include a plurality of transistors including a driving transistor, a light-emitting element, and at least one capacitor. The driving transistor may generate a driving current, and the light-emitting element may emit light having a brightness corresponding to the driving current.

[0003] In order to improve the driving efficiency of the display device and minimize the power consumption of the display device, some methods may use variable refresh rate (VRR) driving that changes the driving frequency (or refresh rate) of the display device. Further, in order to drive the display device at high speed, some methods may use separate compensation driving (SCD) that separates the threshold voltage compensation period and the data writing period of the driving transistor.

[0004] However, when VRR driving and SCD are adopted, problems such as flickering and uneven image quality may occur, and some methods for compensating for such problems may increase the number of transistors included in a pixel and the number of voltages supplied to the pixel. Summary of the Invention

[0005] The embodiment provides a display device in which the number of transistors included in a pixel is reduced.

[0006] In a display device including a plurality of pixels according to an embodiment, each of the plurality of pixels may include: a first transistor including a gate connected to a first node, a source connected to a second node, and a drain connected to a third node; a second transistor including a gate configured to receive a first gate signal, a source configured to receive a data voltage, and a drain connected to a fourth node; a third transistor including a gate configured to receive a second gate signal, a source connected to the third node, and a drain connected to the first node; a storage capacitor including a first terminal connected to the first node and a second terminal connected to the fourth node; and a light emitting element including a first terminal connected to a fifth node and a second terminal configured to receive a second power supply voltage. At least two of the plurality of pixels may share the at least two transistors connected to the second node.

[0007] In an embodiment, the plurality of pixels may include a first pixel and a second pixel disposed in the same pixel row and adjacent to each other, and the first pixel and the second pixel may share at least two transistors.

[0008] In an embodiment, the first pixel may be one of a red pixel, a green pixel, and a blue pixel, and the second pixel may be another one of the red pixel, the green pixel, and the blue pixel.

[0009] In an embodiment, the plurality of pixels may include a first pixel, a second pixel, and a third pixel disposed in the same pixel row and adjacent to each other, and the first pixel, the second pixel, and the third pixel may share at least two transistors.

[0010] In an embodiment, the first pixel may be one of a red pixel, a green pixel, and a blue pixel, the second pixel may be another one of the red pixel, the green pixel, and the blue pixel, and the third pixel may be the remaining one of the red pixel, the green pixel, and the blue pixel.

[0011] In an embodiment, the at least two transistors may include: an eighth transistor including a gate configured to receive a first transmission signal, a source configured to receive a first power supply voltage, and a drain connected to the second node; and a ninth transistor including a gate configured to receive a fourth gate signal, a source configured to receive a bias voltage, and a drain connected to the second node.

[0012] In an embodiment, the at least two transistors may further include a tenth transistor including a gate configured to receive the second gate signal, a source configured to receive the first power supply voltage, and a drain connected to the second node.

[0013] In an embodiment, each of the plurality of pixels may further include: a fifth transistor including a gate configured to receive a second gate signal, a source configured to receive a reference voltage, and a drain connected to a fourth node; a sixth transistor including a gate configured to receive a first emission signal, a source connected to the third node, and a drain connected to a fifth node; and a seventh transistor including a gate configured to receive a fourth gate signal, a source configured to receive a second initialization voltage, and a drain connected to the fifth node.

[0014] In an embodiment, each of the plurality of pixels may further include: a sixth transistor including a gate configured to receive a second emission signal, a source connected to the third node, and a drain connected to the fifth node; and a seventh transistor including a gate configured to receive a fourth gate signal, a source configured to receive a second initialization voltage, and a drain connected to the fifth node.

[0015] In an embodiment, each of the plurality of pixels may further include a fifth transistor including a gate configured to receive the second gate signal, a source configured to receive a reference voltage, and a drain connected to the fourth node.

[0016] In an embodiment, each of the plurality of pixels may further include a fifth transistor including a gate configured to receive the second gate signal, a source connected to the second node, and a drain connected to the fourth node.

[0017] In an embodiment, each of the plurality of pixels may further include: a fourth transistor comprising a gate configured to receive a third gate signal, a source configured to receive a first initialization voltage, and a drain connected to the first node; and a holding capacitor comprising a first terminal connected to the fourth node and a second terminal configured to receive a first power supply voltage.

[0018] In a display device including a plurality of pixels according to an embodiment, each of the plurality of pixels may include: a first transistor including a gate connected to a first node, a source connected to a second node, and a drain connected to a third node; a second transistor including a gate configured to receive a first gate signal, a source configured to receive a data voltage, and a drain connected to a fourth node; a third transistor including a gate configured to receive a second gate signal, a source connected to the third node, and a drain connected to the first node; a storage capacitor including a first terminal connected to the first node and a second terminal connected to the fourth node; and a light emitting element including a first terminal connected to a fifth node and a second terminal configured to receive a second power supply voltage. At least two of the plurality of pixels may share a ninth transistor including a gate configured to receive a fourth gate signal, a source configured to receive a bias voltage, and a drain connected to the second node.

[0019] In an embodiment, at least two pixels may further share a tenth transistor including a gate configured to receive the second gate signal, a source configured to receive the first power supply voltage, and a drain connected to the second node.

[0020] In a display device including a first pixel region, a second pixel region, and a third pixel region according to an embodiment, each of the first pixel region, the second pixel region, and the third pixel region may include: an active layer disposed on a substrate and including a first source region, a first drain region, a second source region, a second drain region, a third source region, and a third drain region; a first conductive layer disposed on the active layer and including a first gate electrode defining a first transistor together with the first source region and the first drain region, a second gate electrode defining a second transistor together with the second source region and the second drain region, and a third gate electrode defining a third transistor together with the third source region and the third drain region; a second conductive layer disposed on the first conductive layer and including a first capacitor electrode overlapping with the first gate electrode; a third conductive layer disposed on the second conductive layer and including a second capacitor electrode overlapping with the first capacitor electrode; and a fourth conductive layer disposed on the third conductive layer. The first pixel region and the second pixel region may share the first source region. The first source region of the third pixel region may be connected to the first source region shared by the first and second pixel regions via a bridge disposed on a layer different from the active layer.

[0021] In an embodiment, the first pixel region, the second pixel region, and the third pixel region may be disposed in the same pixel row, and the second pixel region may be adjacent to the first pixel region and the third pixel region.

[0022] In an embodiment, the shape of the first pixel region and the shape of the second pixel region may be symmetrical to each other about an imaginary line extending in the pixel column direction between the first pixel region and the second pixel region.

[0023] In an embodiment, the first pixel region and the third pixel region may have the same shape.

[0024] In an embodiment, the fourth conductive layer may include a bridge.

[0025] In an embodiment, the fourth conductive layer may further include a first gate line connected to the second gate electrode and a second gate line connected to the third gate electrode.

[0026] In an embodiment, the first source region shared by the first pixel region and the second pixel region may include a first protrusion extending in the pixel row direction, and the first end portion of the bridge may be connected to the first protrusion.

[0027] In an embodiment, the first source region of the third pixel region may include a second protrusion extending in the pixel row direction, and the second end portion of the bridge may be connected to the second protrusion.

[0028] In an embodiment, the active layer of each of the first pixel region and the second pixel region may further include an eighth source region, an eighth drain region, a ninth source region, a ninth drain region, a tenth source region and a tenth drain region, and the first pixel region and the second pixel region may share the eighth source region, the eighth drain region, the tenth source region and the tenth drain region.

[0029] In an embodiment, the first conductive layer of each of the first pixel region and the second pixel region may further include: an eighth gate electrode, which together with the eighth source region and the eighth drain region defines an eighth transistor; a ninth gate electrode, which together with the ninth source region and the ninth drain region defines a ninth transistor; and a tenth gate electrode, which together with the tenth source region and the tenth drain region defines a tenth transistor.

[0030] In an embodiment, each of the first pixel region, the second pixel region, and the third pixel region may further include: a fifth conductive layer disposed on the fourth conductive layer and including a data line electrically connected to the second source region and a power line electrically connected to the second capacitor electrode.

[0031] In the display device according to the embodiment, at least two pixels can share at least two transistors connected to the source (or second node) of the first transistor, so that the number of transistors included in the pixel can be reduced. Accordingly, the resolution of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0033] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0034] Figure 2 is used to describe Figure 1 A view of a variable refresh rate driver of a display device.

[0035] Figure 3 The diagram is included in Figure 1 1 is a circuit diagram of an example of a first pixel and a second pixel in a display device.

[0036] Figures 4 and 5 is used to describe Figure 3 A timing diagram of operations of the first pixel and the second pixel.

[0037] Figure 6 The diagram is included in Figure 1 1 is a circuit diagram of an example of first to third pixels in a display device.

[0038] Figures 7 to 15 The diagram shows the settings Figure 6 Layout diagram of first pixel region to third pixel region of first pixel to third pixel.

[0039] Figure 16 It is along Figure 7 A cross-sectional view taken along line AA'.

[0040] Figure 17 The diagram is included in Figure 1 1 is a circuit diagram of an example of a first pixel and a second pixel in a display device.

[0041] Figures 18 and 19 is used to describe Figure 17 A timing diagram of operations of the first pixel and the second pixel.

[0042] Figure 20 The diagram is included in Figure 1 1 is a circuit diagram of an example of first to third pixels in a display device.

[0043] Figure 21 The diagram is included in Figure 1 1 is a circuit diagram of an example of a first pixel and a second pixel in a display device.

[0044] Figure 22 The diagram is included in Figure 1 1 is a circuit diagram of an example of first to third pixels in a display device.

[0045] Figure 23 is a block diagram illustrating an electronic device according to an embodiment. DETAILED DESCRIPTION

[0046] Hereinafter, a display device according to an embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals will be used for the same elements in the drawings.

[0047] Embodiments supported by the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings in which one or more example embodiments are illustrated. However, aspects supported by the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example aspects of the invention to those skilled in the art.

[0048] Terms such as first and second, etc., can be used to describe various components, but components should not be limited by the terms. The terms used in this article can distinguish one component from other components. For example, without departing from the scope of this disclosure, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component. Unless otherwise specified, terms in the singular may include plural forms.

[0049] The terms used in this article are used to describe the purpose of specific embodiments and are not intended to limit. As used in this article, "one", "the (described)" and "at least one" do not represent the limitation of quantity, and unless the context clearly indicates otherwise, it is intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "element" and "at least one element" have the same meaning. "At least one" should not be interpreted as limiting "one". "Or" means "and / or". As used in this article, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that when used in this specification, the term "includes" or "comprising" and variations thereof specify the presence of stated features, regions, entireties, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or their groups.

[0050] As used herein, the terms "about" or "approximately" are inclusive of the stated value and include an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of a particular quantity. For example, the term "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0051] As used herein, the term "substantially" means approximately or practically. The term "substantially equal" means approximately or practically equal. The term "substantially the same" means approximately or practically the same. The term "substantially the same" means approximately or practically the same. The term "substantially perpendicular" means approximately or practically perpendicular.

[0052] For ease of description, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that, in addition to the orientation depicted in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" can include both the orientation above and below. The device can be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0053] The embodiments are described herein with reference to cross-sectional illustrations which are schematic illustrations of example embodiments. Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as illustrated herein, but rather are intended to include deviations in shapes resulting, for example, from manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, illustrated sharp corners may be rounded. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and, unless expressly defined as such herein, will not be interpreted in an idealized or overly formal sense.

[0055] It should be understood that the various embodiments of the present disclosure and the terms used therein are not intended to limit the technical features set forth in this article to specific embodiments, and include various variations, equivalents or substitutes of the corresponding embodiments. With regard to the description of the accompanying drawings, similar figure numerals may be used to refer to similar or related elements. It should be understood that unless the relevant context clearly indicates otherwise, the singular form of the noun corresponding to the item may include one or more things. As used in this article, each of the phrases such as "A or B", "at least one of A and B", "A, B or C", and "at least one of A, B and C" may include any one or all possible combinations of the items listed together in the corresponding one of these phrases.

[0056] It should be understood that if an element (e.g., a first element) is referred to as being "coupled" or "connected" with another element (e.g., a second element) or "coupled to" or "connected to" another element (e.g., a second element) with or without the term "operably" or "communicatively", this means that the element can be coupled to the other element directly (e.g., wired), wirelessly, or via a third element.

[0057] Figure 1 is a block diagram illustrating a display apparatus 100 according to an embodiment.

[0058] refer to Figure 1 , the display device 100 may include a display panel 110 , a gate driver 120 , an emission driver 130 , a data driver 140 , and a controller 150 .

[0059] The display panel 110 may include a plurality of pixels. At least two pixels among the plurality of pixels may share at least two transistors connected to the source of the first transistor (e.g., the driving transistor). Accordingly, the number of transistors included in the pixel can be reduced, and the resolution of the display device 100 can be improved.

[0060] The plurality of pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be arranged in the same pixel row, and two or more of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be adjacent to each other. For example, the second pixel PX2 may be adjacent to the first pixel PX1 and the third pixel PX3. For example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be arranged in a first direction (or pixel row direction) DR1, and two or more of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be adjacent to each other in the first direction DR1. In some aspects, the first pixel PX1 may be adjacent to another third pixel PX3 (not shown) (for example, in the negative first direction DR1), and the third pixel PX3 may be adjacent to another first pixel PX1 (not shown) (for example, in the positive first direction DR1). Although not illustrated, the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 may be adjacent to another pixel (eg, another first pixel PX1 , second pixel PX2 , or third pixel PX3 ) in the second direction DR2 .

[0061] In an embodiment, the first pixel PX1 and the second pixel PX2 may share at least two transistors connected to the source of the first transistor. Accordingly, the number of transistors included in the first pixel PX1 and the second pixel PX2 may be reduced by at least two, and the resolution of the display device 100 may be improved.

[0062] In an embodiment, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may share at least two transistors connected to the source of the first transistor. Accordingly, the number of transistors included in the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be reduced by at least four, and the resolution of the display device 100 may be improved.

[0063] The gate driver 120 may provide a gate signal GS to the display panel 110. The gate driver 120 may generate the gate signal GS based on the gate control signal GCS. In an embodiment, the gate control signal GCS may include a gate start signal or a gate clock signal, etc.

[0064] The emission driver 130 may provide an emission signal EM to the display panel 110. The emission driver 130 may generate the emission signal EM based on the emission control signal ECS. In an embodiment, the emission control signal ECS may include an emission start signal or an emission clock signal, etc.

[0065] The data driver 140 may provide a data voltage VDAT to the display panel 110. The data driver 140 may generate the data voltage VDAT based on the second image data IMD2 and the data control signal DCS. In an embodiment, the second image data IMD2 may include grayscale values corresponding to pixels, and the data control signal DCS may include a load signal or a data clock signal, etc.

[0066] The controller 150 may control the driving (or operation) of the gate driver 120, the driving (or operation) of the emission driver 130, and the driving (or operation) of the data driver 140. The controller 150 may provide a gate control signal GCS to the gate driver 120, an emission control signal ECS to the emission driver 130, and second image data IMD2 and a data control signal DCS to the data driver 140. The controller 150 may generate the gate control signal GCS, the emission control signal ECS, the second image data IMD2, and the data control signal DCS based on the first image data IMD1 and the control signal CNT. In embodiments, the first image data IMD1 may include grayscale values corresponding to pixels, and the control signal CNT may include a horizontal start signal, a vertical start signal, a main clock signal, or the like.

[0067] Figure 2 is used to describe Figure 1 FIG. 1 is a view of a variable refresh rate (VRR) driven display device 100 .

[0068] refer to Figure 1 and Figure 2 , a frame period of the display device 100 may include an address scanning period AS and at least one self-scanning period SS. The address scanning period AS may be defined as a period in which a data voltage VDAT is applied to the display panel 110. In the address scanning period AS, the display device 100 may display an image based on the data voltage VDAT applied in the address scanning period AS. The self-scanning period SS may be defined as a period in which the data voltage VDAT is not applied to the display panel 110. In the self-scanning period SS, the display device 100 may display an image based on the data voltage VDAT applied in the address scanning period AS.

[0069] The display device 100 can change the driving frequency (or refresh rate) of the display device 100 by adjusting the number of self-scan periods SS included in the frame period. The driving frequency of the display device 100 can increase as the number of self-scan periods SS included in the frame period decreases, and the driving frequency of the display device 100 can decrease as the number of self-scan periods SS included in the frame period increases.

[0070] In an embodiment, Figure 2 As illustrated in FIG, when the first frame period FR1 includes one self-scan period SS, the second frame period FR2 includes two self-scan periods SS, and the third frame period FR3 includes three self-scan periods SS, the driving frequency of the second frame period FR2 may be lower than the driving frequency of the first frame period FR1, and the driving frequency of the third frame period FR3 may be lower than the driving frequency of the second frame period FR2. For example, the driving frequency of the first frame period FR1 may be approximately 120 Hz, the driving frequency of the second frame period FR2 may be approximately 80 Hz, and the driving frequency of the third frame period FR3 may be approximately 60 Hz.

[0071] Figure 3 The diagram is included in Figure 1 1 is a circuit diagram of an example of a first pixel PX1 and a second pixel PX2 in the display device 100.

[0072] refer to Figure 1 and Figure 3 Each of the first pixel PX1 and the second pixel PX2 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, a hold capacitor CHD, and a light emitting element EL. The first pixel PX1 and the second pixel PX2 may share three transistors. For example, the first pixel PX1 and the second pixel PX2 may share an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The gate signal GS may include a first gate signal GW, a second gate signal GC, a third gate signal GI, and a fourth gate signal GB.

[0073] In an embodiment, the first pixel PX1 may be one of a red pixel, a green pixel, and a blue pixel, and the second pixel PX2 may be another of the red pixel, the green pixel, and the blue pixel. For example, the first pixel PX1 may be a red pixel, and the second pixel PX2 may be a green pixel.

[0074] The first transistor T1 may include a gate connected to the first node N1, a source connected to the second node N2, and a drain connected to the third node N3. The first transistor T1 may generate a driving current corresponding to a voltage difference between the first node N1 and the second node N2.

[0075] The second transistor T2 may include a gate receiving the first gate signal GW, a source receiving the data voltage VDAT, and a drain connected to the fourth node N4. The second transistor T2 may transmit the data voltage VDAT to the fourth node N4 in response to the first gate signal GW.

[0076] The third transistor T3 may include a gate receiving the second gate signal GC, a source connected to the third node N3, and a drain connected to the first node N1. The third transistor T3 may connect the third node N3 and the first node N1 in response to the second gate signal GC.

[0077] The fourth transistor T4 may include a gate receiving the third gate signal GI, a source receiving the first initialization voltage VINT, and a drain connected to the first node N1. The fourth transistor T4 may transmit the first initialization voltage VINT to the first node N1 in response to the third gate signal GI.

[0078] The fifth transistor T5 may include a gate receiving the second gate signal GC, a source receiving the reference voltage VREF, and a drain connected to the fourth node N4. The fifth transistor T5 may transmit the reference voltage VREF to the fourth node N4 in response to the second gate signal GC. In an embodiment, the fifth transistor T5 may receive the first power supply voltage ELVDD instead of the reference voltage VREF.

[0079] The sixth transistor T6 may include a gate receiving the emission signal EM, a source connected to the third node N3, and a drain connected to the fifth node N5. The sixth transistor T6 may connect the third node N3 and the fifth node N5 in response to the emission signal EM.

[0080] The seventh transistor T7 may include a gate receiving the fourth gate signal GB, a source receiving the second initialization voltage VAINT, and a drain connected to the fifth node N5. The seventh transistor T7 may transmit the second initialization voltage VAINT to the fifth node N5 in response to the fourth gate signal GB.

[0081] The eighth transistor T8 may include a gate receiving the emission signal EM, a source receiving the first power voltage ELVDD, and a drain connected to the second node N2. The eighth transistor T8 may transmit the first power voltage ELVDD to the second node N2 in response to the emission signal EM.

[0082] The ninth transistor T9 may include a gate receiving the fourth gate signal GB, a source receiving the bias voltage VBIAS, and a drain connected to the second node N2. The ninth transistor T9 may transmit the bias voltage VBIAS to the second node N2 in response to the fourth gate signal GB.

[0083] The tenth transistor T10 may include a gate receiving the second gate signal GC, a source receiving the first power voltage ELVDD, and a drain connected to the second node N2. The tenth transistor T10 may transmit the first power voltage ELVDD to the second node N2 in response to the second gate signal GC.

[0084] In an embodiment, each of the first to tenth transistors T1 to T10 may be a P-type transistor (e.g., a PMOS transistor). However, the embodiments of the present disclosure are not limited thereto, and in another embodiment, at least one of the first to tenth transistors T1 to T10 may be an N-type transistor (e.g., an NMOS transistor).

[0085] The storage capacitor CST may include a first terminal connected to the first node N1 and a second terminal connected to the fourth node N4. The storage capacitor CST may store a voltage corresponding to a voltage difference between the first node N1 and the fourth node N4.

[0086] The hold capacitor CHD may include a first terminal connected to the fourth node N4 and a second terminal receiving the first power voltage ELVDD. The hold capacitor CHD may store the voltage of the fourth node N4.

[0087] The light emitting element EL may include a first terminal connected to the fifth node N5 and a second terminal receiving the second power supply voltage ELVSS. The light emitting element EL may emit light having brightness corresponding to the driving current generated in the first transistor T1.

[0088] In the embodiment, the light emitting element EL may be an organic light emitting diode. However, the embodiment of the present disclosure is not limited thereto, and in another embodiment, the light emitting element EL may be any one of an inorganic light emitting diode, a micro light emitting diode, and a quantum dot light emitting diode.

[0089] In reference Figure 3 In the described embodiment, the first pixel PX1 and the second pixel PX2 can share three transistors T8, T9, and T10 connected to the second node N2 (or the source of the first transistor T1). Accordingly, the sharing of the three transistors T8, T9, and T10 can reduce the number of transistors included in the first pixel PX1 and the second pixel PX2 by three, and can improve the resolution of the display device 100.

[0090] Figures 4 and 5 is used to describe Figure 3 FIG. 1 is a timing diagram of operations of the first pixel PX1 and the second pixel PX2 .

[0091] refer to Figure 3 、 Figure 4 and Figure 5 The address scanning period AS may include a first initialization period PI1, a first compensation period PC1, a second initialization period PI2, a second compensation period PC2, a write period PW, a first bypass period PB1, and a first emission period PE1, and the self-scan period SS may include a second bypass period PB2 and a second emission period PE2. The emission signal EM may have a turn-on voltage level (e.g., a logic low level) in the first emission period PE1 and the second emission period PE2, and may have a turn-off voltage level (e.g., a logic high level) in periods other than the first emission period PE1 and the second emission period PE2.

[0092] The third gate signal GI may have a turn-on voltage level during the first initialization period PI1 and the second initialization period PI2. The third gate signal GI may have a turn-off voltage level during periods other than the first initialization period PI1 and the second initialization period PI2. The second gate signal GC may have a turn-on voltage level during the first compensation period PC1 and the second compensation period PC2. The second gate signal GC may have a turn-off voltage level during periods other than the first compensation period PC1 and the second compensation period PC2.

[0093] The first gate signal GW may have a turn-on voltage level during the write period PW. The first gate signal GW may have a turn-off voltage level during a period other than the write period PW. The fourth gate signal GB may have a turn-on voltage level during the first bypass period PB1 and the second bypass period PB2. The fourth gate signal GB may have a turn-off voltage level during a period other than the first bypass period PB1 and the second bypass period PB2.

[0094] The fourth transistor T4 may be turned on in response to the third gate signal GI having a turn-on voltage level during the first initialization period PI1 and may transmit the first initialization voltage VINT to the first node N1. Accordingly, the gate of the first transistor T1 may be initialized to the first initialization voltage VINT. During the first initialization period PI1, the fourth node N4 may be charged with the data voltage of the previous frame period.

[0095] The third transistor T3, the fifth transistor T5, and the tenth transistor T10 can be turned on in response to the second gate signal GC having a turn-on voltage level during the first compensation period PC1. A voltage ELVDD-Vth obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the first power supply voltage ELVDD can be transmitted to the first node N1, and a reference voltage VREF can be transmitted to the fourth node N4. The voltage of the fourth node N4 can be changed from the data voltage of the previous frame period to the reference voltage VREF, and due to the coupling effect of the storage capacitor CST, the voltage change of the fourth node N4 can affect the voltage of the first node N1. During the first compensation period PC1, the first node N1 can be charged with a voltage of ELVDD-Vth+α (α is a coupling voltage caused by the voltage change of the fourth node N4).

[0096] The fourth transistor T4 may be turned on in response to the third gate signal GI having the turn-on voltage level in the second initialization period PI2 and may transmit the first initialization voltage VINT to the first node N1. Accordingly, the gate of the first transistor T1 may be reinitialized to the first initialization voltage VINT.

[0097] The third transistor T3, the fifth transistor T5, and the tenth transistor T10 may be turned on in response to the second gate signal GC having a turn-on voltage level during the second compensation period PC2. A voltage ELVDD-Vth obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the first power supply voltage ELVDD may be transmitted to the first node N1, and a reference voltage VREF may be transmitted to the fourth node N4. The voltage VREF of the fourth node N4 may not change, and a voltage change of the fourth node N4 may not affect the voltage of the first node N1. During the second compensation period PC2, the first node N1 may be charged with a voltage of ELVDD-Vth. Accordingly, the gate of the first transistor T1 may be charged with a voltage ELVDD-Vth in which the threshold voltage (Vth) of the first transistor T1 is compensated.

[0098] The second transistor T2 may be turned on in response to the first gate signal GW having a turn-on voltage level during the write period PW and may transmit the data voltage VDAT to the fourth node N4. The voltage of the fourth node N4 may change from the reference voltage VREF to the data voltage VDAT, and due to the coupling effect of the storage capacitor CST, the voltage change VDAT-VREF of the fourth node N4 may be transmitted to the first node N1. During the write period PW, the first node N1 may be charged with a voltage of ELVDD-Vth+VDAT-VREF.

[0099] The seventh transistor T7 and the ninth transistor T9 can be turned on in response to the fourth gate signal GB having a turn-on voltage level during the first bypass period PB1, and the seventh transistor T7 can transmit the second initialization voltage VAINT to the first terminal of the light emitting element EL and the ninth transistor T9 can transmit the bias voltage VBIAS to the source of the first transistor T1. Accordingly, the first terminal of the light emitting element EL can be initialized to the second initialization voltage VAINT, and the first transistor T1 can be biased to be turned on by the bias voltage VBIAS.

[0100] The sixth and eighth transistors T6 and T8 may be turned on in response to the emission signal EM having the turn-on voltage level in the first emission period PE1 , and the first transistor T1 may generate the driving current (I) calculated by Equation 1.

[0101] [Equation 1]

[0102] I∝(Vsg-Vth) 2

[0103] In Equation 1, Vsg may be the source-gate voltage of the first transistor T1. The source-gate voltage Vsg of the first transistor T1 may be a value obtained by subtracting the voltage ELVDD-Vth+VDAT-VREF of the first node N1 from the voltage ELVDD of the second node N2. Accordingly, the driving current (I) may be calculated by Equation 2.

[0104] [Equation 2]

[0105] I∝(VREF-VDAT) 2

[0106] In the first emission period PE1, a driving current (I) may flow through the light emitting element EL, and the light emitting element EL may emit light having brightness corresponding to the data voltage VDAT.

[0107] The seventh transistor T7 and the ninth transistor T9 may be turned on in response to the fourth gate signal GB having a turn-on voltage level during the second bypass period PB2, and the seventh transistor T7 may transmit the second initialization voltage VAINT to the first terminal of the light emitting element EL and the ninth transistor T9 may transmit the bias voltage VBIAS to the source of the first transistor T1. Accordingly, the first terminal of the light emitting element EL may be initialized to the second initialization voltage VAINT, and the first transistor T1 may be biased to be turned on by the bias voltage VBIAS.

[0108] The sixth transistor T6 and the eighth transistor T8 may be turned on in response to the emission signal EM having the turn-on voltage level in the second emission period PE2, and the first transistor T1 may generate the driving current (I) calculated by Equation 1 and Equation 2. In the second emission period PE2, the driving current (I) may flow through the light emitting element EL, and the light emitting element EL may emit light having a luminance corresponding to the data voltage VDAT.

[0109] Figure 6 The diagram is included in Figure 1 1 is a circuit diagram of an example of a first pixel PX1, a second pixel PX2, and a third pixel PX3 in the display device 100.

[0110] Will omit reference Figure 3 The components of the first pixel PX1 and the second pixel PX2 are substantially the same or similar to those described above. Figure 6 Description of components of the first pixel PX1, the second pixel PX2, and the third pixel PX3 are described.

[0111] refer to Figure 1 and Figure 6 Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, a hold capacitor CHD, and a light emitting element EL. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may share three transistors. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may share an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.

[0112] Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be a red pixel, a green pixel, or a blue pixel. In an embodiment, the first pixel PX1 may be one of the red pixel, the green pixel, and the blue pixel, the second pixel PX2 may be the other of the red pixel, the green pixel, and the blue pixel, and the third pixel PX3 may be the remaining one of the red pixel, the green pixel, and the blue pixel. For example, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel.

[0113] In reference Figure 6In the described embodiment, the first pixel PX1, the second pixel PX2, and the third pixel PX3 can share three transistors T8, T9, and T10 connected to the second node N2 (or the source of the first transistor T1). Accordingly, the number of transistors included in the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be reduced to six, and the resolution of the display device 100 can be improved.

[0114] Figures 7 to 15 The diagram shows the settings Figure 6 Layout diagram of a first pixel area PXA1, a second pixel area PXA2, and a third pixel area PXA3 of a first pixel PX1, a second pixel PX2, and a third pixel PX3. Figure 16 It is along Figure 7 A cross-sectional view taken along line AA'.

[0115] refer to Figures 6 to 16 The first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may be arranged in the same pixel row and may be adjacent to each other. Each of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may include an active layer ACT, a first conductive layer GAT1, a second conductive layer GAT2, a third conductive layer GAT3, a fourth conductive layer SD1, and a fifth conductive layer SD2.

[0116] In an embodiment, the substrate SUB may include glass, plastic, quartz, metal, or the like.

[0117] The buffer layer BUF may be disposed on the substrate SUB. In an embodiment, the buffer layer BUF may include an inorganic insulating material.

[0118] The active layer ACT may be disposed on the buffer layer BUF. In an embodiment, the active layer ACT may include polysilicon. However, the embodiments of the present disclosure are not limited thereto, and the active layer ACT may include any one of amorphous silicon and an oxide semiconductor.

[0119] The active layer ACT of each of the first pixel area PXA1, the second pixel area PXA2 and the third pixel area PXA3 may include a first source area SA1, a first drain area DA1, a second source area SA2, a second drain area DA2, a third source area SA3, a third drain area DA3, a fourth source area SA4, a fourth drain area DA4, a fifth source area SA5, a fifth drain area DA5, a sixth source area SA6, a sixth drain area DA6, a seventh source area SA7 and a seventh drain area DA7. The first source area SA1 and the first drain area DA1 may respectively correspond to the source and drain of the first transistor T1, the second source area SA2 and the second drain area DA2 may respectively correspond to the source and drain of the second transistor T2, the third source area SA3 and the third drain area DA3 may respectively correspond to the source and drain of the third transistor T3, the fourth source area SA4 and the fourth drain area DA4 may respectively correspond to the source and drain of the fourth transistor T4, the fifth source area SA5 and the fifth drain area DA5 may respectively correspond to the source and drain of the fifth transistor T5, the sixth source area SA6 and the sixth drain area DA6 may respectively correspond to the source and drain of the sixth transistor T6, and the seventh source area SA7 and the seventh drain area DA7 may respectively correspond to the source and drain of the seventh transistor T7.

[0120] The first pixel region PXA1 and the second pixel region PXA2 may share the first source region SA1. In other words, the first source region SA1 of the first pixel region PXA1 and the first source region SA1 of the second pixel region PXA2 may be integrally formed.

[0121] The first source area SA1 of the third pixel area PXA3 may be connected to the first source area SA1 shared by the first pixel area PXA1 and the second pixel area PXA2 via a bridge BRG provided at a layer different from the active layer ACT. Accordingly, the first source area SA1 of the first pixel area PXA1, the first source area SA1 of the second pixel area PXA2, and the first source area SA1 of the third pixel area PXA3 may be electrically connected.

[0122] In an embodiment, the first source region SA1 shared by the first and second pixel regions PXA1 and PXA2 may include a first protrusion PP1 extending in the first direction DR1. In an embodiment, the first source region SA1 of the third pixel region PXA3 may include a second protrusion PP2 extending in the first direction DR1.

[0123] The active layer ACT of each of the first pixel area PXA1 and the second pixel area PXA2 may include an eighth source area SA8, an eighth drain area DA8, a ninth source area SA9, a ninth drain area DA9, a tenth source area SA10, and a tenth drain area DA10. The eighth source area SA8 and the eighth drain area DA8 may respectively correspond to the source and drain of the eighth transistor T8, the ninth source area SA9 and the ninth drain area DA9 may respectively correspond to the source and drain of the ninth transistor T9, and the tenth source area SA10 and the tenth drain area DA10 may respectively correspond to the source and drain of the tenth transistor T10.

[0124] In an embodiment, the first pixel region PXA1 and the second pixel region PXA2 may share the eighth source region SA8, the eighth drain region DA8, the tenth source region SA10, and the tenth drain region DA10. In other words, the eighth source region SA8 of the first pixel region PXA1 and the eighth source region SA8 of the second pixel region PXA2 may be formed integrally, the eighth drain region DA8 of the first pixel region PXA1 and the eighth drain region DA8 of the second pixel region PXA2 may be formed integrally, the tenth source region SA10 of the first pixel region PXA1 and the tenth source region SA10 of the second pixel region PXA2 may be formed integrally, and the tenth drain region DA10 of the first pixel region PXA1 and the tenth drain region DA10 of the second pixel region PXA2 may be formed integrally.

[0125] The first insulating layer INS1 may be disposed on the active layer ACT. In an embodiment, the first insulating layer INS1 may include an inorganic insulating material.

[0126] The first conductive layer GAT1 may be disposed on the first insulating layer INS1. In an embodiment, the first conductive layer GAT1 may include metal. The first conductive layer GAT1 may include a first gate electrode GE1, a second gate electrode GE2, a third gate electrode GE3, a fourth gate electrode GE4, a fifth gate electrode GE5, a sixth gate electrode GE6, a fourth gate line GBL, an eighth gate electrode GE8, and a tenth gate electrode GE10. The fourth gate line GBL may include a seventh gate electrode GE7 and a ninth gate electrode GE9. The first gate electrode GE1 may correspond to the gate of the first transistor T1 and the first terminal of the storage capacitor CST, the second gate electrode GE2 may correspond to the gate of the second transistor T2, the third gate electrode GE3 may correspond to the gate of the third transistor T3, the fourth gate electrode GE4 may correspond to the gate of the fourth transistor T4, the fifth gate electrode GE5 may correspond to the gate of the fifth transistor T5, the sixth gate electrode GE6 may correspond to the gate of the sixth transistor T6, the seventh gate electrode GE7 may correspond to the gate of the seventh transistor T7, the eighth gate electrode GE8 may correspond to the gate of the eighth transistor T8, the ninth gate electrode GE9 may correspond to the gate of the ninth transistor T9, and the tenth gate electrode GE10 may correspond to the gate of the tenth transistor T10.

[0127] In the plan view, the first gate electrode GE1 can be located between the first source region SA1 and the first drain region DA1, the second gate electrode GE2 can be located between the second source region SA2 and the second drain region DA2, the third gate electrode GE3 can be located between the third source region SA3 and the third drain region DA3, the fourth gate electrode GE4 can be located between the fourth source region SA4 and the fourth drain region DA4, the fifth gate electrode GE5 can be located between the fifth source region SA5 and the fifth drain region DA5, the sixth gate electrode GE6 can be located between the sixth source region SA6 and the sixth drain region DA6, the seventh gate electrode GE7 can be located between the seventh source region SA7 and the seventh drain region DA7, the eighth gate electrode GE8 can be located between the eighth source region SA8 and the eighth drain region DA8, the ninth gate electrode GE9 can be located between the ninth source region SA9 and the ninth drain region DA9, and the tenth gate electrode GE10 can be located between the tenth source region SA10 and the tenth drain region DA10.

[0128] The fourth gate line GBL may extend in the first direction DR1 and may transmit a fourth gate signal GBL.

[0129] The second insulating layer INS2 may be disposed on the first conductive layer GAT1. In an embodiment, the second insulating layer INS2 may include an inorganic insulating material.

[0130] The second conductive layer GAT2 may be disposed on the second insulating layer INS2. In an embodiment, the second conductive layer GAT2 may include a metal. The second conductive layer GAT2 may include a first capacitor electrode CE1, a first initialization line INTL, and a first bias line BIASL1.

[0131] The first capacitor electrode CE1 may overlap the first gate electrode GE1. The first capacitor electrode CE1 may correspond to the second terminal of the storage capacitor CST and the first terminal of the hold capacitor CHD.

[0132] The first initialization line INTL may extend in the first direction DR1. The first initialization line INTL may transmit a first initialization voltage VINT. The first bias line BIASL1 may extend in the first direction DR1. The first bias line BIASL1 may transmit a bias voltage VBIAS.

[0133] The third insulating layer INS3 may be disposed on the second conductive layer GAT2. In an embodiment, the third insulating layer INS3 may include an inorganic insulating material.

[0134] The third conductive layer GAT3 may be disposed on the third insulating layer INS3. In an embodiment, the third conductive layer GAT3 may include a metal. The third conductive layer GAT3 may include a second capacitor electrode CE2 and a repair line RPL.

[0135] The second capacitor electrode CE2 may overlap the first capacitor electrode CE1. The second capacitor electrode CE2 may correspond to a second terminal of the holding capacitor CHD. The second capacitor electrode CE2 may extend in the first direction DR1.

[0136] The repair line RPL may extend in the first direction DR1.

[0137] The fourth insulating layer INS4 may be disposed on the third conductive layer GAT3. In embodiments, the fourth insulating layer INS4 may include an inorganic insulating material and / or an organic insulating material.

[0138] The fourth conductive layer SD1 may be disposed on the fourth insulating layer INS4. In an embodiment, the fourth conductive layer SD1 may include metal. The fourth conductive layer SD1 may include a second bias line BIASL2, a third gate line GIL, a first gate line GWL, a first initialization connection pattern ICP1, a data connection pattern DCP, a second gate line GCL, a first power connection pattern PCP1, a first node connection pattern NCP1, a fourth node connection pattern NCP4, a second power connection pattern PCP2, an emission line EML, a 5-1st node connection pattern NCP5-1, a third power connection pattern PCP3, a 2-1st initialization line AINTL1, a 2-2nd initialization line AINTL2, and a bridge BRG.

[0139] The second bias line BIASL2 may extend in the first direction DR1. The second bias line BIASL2 may transmit the bias voltage VBIAS. The second bias line BIASL2 may be connected to the ninth source region SA9 and the first bias line BIASL1 through the first contact hole CNT1.

[0140] The third gate line GIL may extend in the first direction DR1, transmit the third gate signal GI, and be connected to the fourth gate electrode GE4 through the first contact hole CNT1.

[0141] The first gate line GWL may extend in the first direction DR1 , transmit the first gate signal GW, and be connected to the second gate electrode GE2 through the first contact hole CNT1 .

[0142] The first initialization connection pattern ICP1 may be connected to the fourth source region SA4 and the first initialization line INTL through the first contact hole CNT1. The data connection pattern DCP may be connected to the second source region SA2 through the first contact hole CNT1.

[0143] The second gate line GCL may extend in the first direction DR1 , transmit a second gate signal GC, and be connected to the third, fifth, and tenth gate electrodes GE3 , GE5 , and GE10 through the first contact hole CNT1 .

[0144] The first power connection pattern PCP1 can be connected to the fifth source region SA5 and the tenth source region SA10 through the first contact hole CNT1. The first node connection pattern NCP1 can be connected to the third drain region DA3, the fourth drain region DA4, and the first gate electrode GE1 through the first contact hole CNT1. In this case, the first power supply voltage ELVDD instead of the reference voltage VREF can be transmitted to the fifth source region SA5. In other words, the source of the fifth transistor T5 can receive the first power supply voltage ELVDD instead of the reference voltage VREF.

[0145] The fourth node connection pattern NCP4 may be connected to the second drain area DA2, the fifth drain area DA5, and the first capacitor electrode CE1 through the first contact hole CNT1. The second power connection pattern PCP2 may be connected to the second capacitor electrode CE2 through the first contact hole CNT1.

[0146] The emission line EML may extend in the first direction DR1 , transmit an emission signal EM, and be connected to the sixth gate electrode GE6 and the eighth gate electrode GE8 through the first contact hole CNT1 .

[0147] The 5-1st node connection pattern NCP5-1 may be connected to the sixth drain region DA6 and the seventh drain region DA7 through the first contact hole CNT1. The third power connection pattern PCP3 may be connected to the eighth source region SA8 through the first contact hole CNT1.

[0148] The 2-1st initialization line AINTL1 may extend in the first direction DR1, transmit the second initialization voltage VAINT for the second pixel PX2, and be connected to the seventh source region SA7 of the second pixel area PXA2 through the first contact hole CNT1.

[0149] The 2-2 initialization line AINTL2 may extend in the first direction DR1. The 2-2 initialization line AINTL2 may transmit the second initialization voltage VAINT for the first pixel PX1 and the third pixel PX3. The 2-2 initialization line AINTL2 may be connected to the seventh source region SA7 of the first pixel region PXA1 and the seventh source region SA7 of the third pixel region PXA3 through the first contact hole CNT1.

[0150] The bridge BRG may be connected to the first protrusion PP1 and the second protrusion PP2 through the first contact hole CNT1. Specifically, the first end of the bridge BRG (also referred to herein as the first end portion) may be connected to the first protrusion PP1 through the first contact hole CNT1, and the second end of the bridge BRG (also referred to herein as the second end portion) may be connected to the second protrusion PP2 through the first contact hole CNT1.

[0151] The fifth insulating layer INS5 may be disposed on the fourth conductive layer SD1. In embodiments, the fifth insulating layer INS5 may include an inorganic insulating material and / or an organic insulating material.

[0152] The fifth conductive layer SD2 may be disposed on the fifth insulating layer INS5. In an embodiment, the fifth conductive layer SD2 may include metal. The fifth conductive layer SD2 may include a data line DL, a power line PL, and a 5-2 th node connection pattern NCP5-2.

[0153] The data line DL may extend in the second direction (or pixel column direction) DR2. The data line DL may transmit a data voltage VDAT. The data line DL may be connected to the data connection pattern DCP through the second contact hole CNT2.

[0154] The power line PL may extend in the second direction DR2 . The power line PL may transmit the first power voltage ELVDD . The power line PL may be connected to the first power connection pattern PCP1 , the second power connection pattern PCP2 , and the third power connection pattern PCP3 through the second contact hole CNT2 .

[0155] The 5-2 th node connection pattern NCP5 - 2 may be connected to the 5-1 th node connection pattern NCP5 - 1 through the second contact hole CNT2 .

[0156] The sixth insulating layer INS6 may be disposed on the fifth conductive layer SD2. In embodiments, the sixth insulating layer INS6 may include an inorganic insulating material and / or an organic insulating material.

[0157] The first electrode layer PXL may be disposed on the sixth insulating layer INS6. In an embodiment, the first electrode layer PXL may include a metal and / or a transparent conductive oxide. The first electrode layer PXL may correspond to a first terminal of the light emitting element EL.

[0158] The pixel defining layer PDL may be disposed on the sixth insulating layer INS6 and may cover the periphery (or edge) of the first electrode layer PXL. In embodiments, the pixel defining layer PDL may include an inorganic insulating material and / or an organic insulating material.

[0159] The light emitting layer EMTL may be disposed at the center of the first electrode layer PXL that is not covered by the pixel defining layer PDL. In an embodiment, the light emitting layer EMTL may include an organic light emitting material.

[0160] The second electrode layer CML may be disposed on the light emitting layer EMTL and the pixel defining layer PDL. In an embodiment, the second electrode layer CML may include metal and / or transparent conductive oxide. The second electrode layer CML may correspond to the second terminal of the light emitting element EL.

[0161] The shapes of the first pixel area PXA1 and the second pixel area PXA2 may be symmetrical to each other about an imaginary line IML extending in the second direction DR2 between the first pixel area PXA1 and the second pixel area PXA2 . Specifically, the shape of the active layer ACT of the first pixel area PXA1 and the shape of the active layer ACT of the second pixel area PXA2 can be symmetrical to each other about the imaginary line IML, the shape of the first conductive layer GAT1 of the first pixel area PXA1 and the shape of the first conductive layer GAT1 of the second pixel area PXA2 can be symmetrical to each other about the imaginary line IML, the shape of the second conductive layer GAT2 of the first pixel area PXA1 and the shape of the second conductive layer GAT2 of the second pixel area PXA2 can be symmetrical to each other about the imaginary line IML, the shape of the third conductive layer GAT3 of the first pixel area PXA1 and the shape of the third conductive layer GAT3 of the second pixel area PXA2 can be symmetrical to each other about the imaginary line IML, the shape of the fourth conductive layer SD1 of the first pixel area PXA1 and the shape of the fourth conductive layer SD1 of the second pixel area PXA2 can be symmetrical to each other about the imaginary line IML, and the shape of the fifth conductive layer SD2 of the first pixel area PXA1 and the shape of the fifth conductive layer SD2 of the second pixel area PXA2 can be symmetrical to each other about the imaginary line IML.

[0162] The first pixel area PXA1 and the third pixel area PXA3 may have substantially the same shape. Specifically, the active layer ACT of the first pixel area PXA1 and the active layer ACT of the third pixel area PXA3 may have substantially the same shape, the first conductive layer GAT1 of the first pixel area PXA1 and the first conductive layer GAT1 of the third pixel area PXA3 may have substantially the same shape, the second conductive layer GAT2 of the first pixel area PXA1 and the second conductive layer GAT2 of the third pixel area PXA3 may have substantially the same shape, the third conductive layer GAT3 of the first pixel area PXA1 and the third conductive layer GAT3 of the third pixel area PXA3 may have substantially the same shape, the fourth conductive layer SD1 of the first pixel area PXA1 and the fourth conductive layer SD1 of the third pixel area PXA3 may have substantially the same shape, and the fifth conductive layer SD2 of the first pixel area PXA1 and the fifth conductive layer SD2 of the third pixel area PXA3 may have substantially the same shape.

[0163] Figure 17 The diagram is included in Figure 1 1 is a circuit diagram of an example of a first pixel PX1 and a second pixel PX2 in the display device 100.

[0164] Will omit reference Figure 3 The components of the first pixel PX1 and the second pixel PX2 are substantially the same or similar to those described above. Figure 17 Description of components of the first pixel PX1 and the second pixel PX2 are described.

[0165] refer to Figure 1 and Figure 17 Each of the first pixel PX1 and the second pixel PX2 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, a hold capacitor CHD, and a light-emitting element EL. The first pixel PX1 and the second pixel PX2 may share two transistors. The first pixel PX1 and the second pixel PX2 may share an eighth transistor T8 and a ninth transistor T9. The emission signal EM may include a first emission signal EM1 and a second emission signal EM2.

[0166] The sixth transistor T6 may include a gate receiving the second emission signal EM2, a source connected to the third node N3, and a drain connected to the fifth node N5. The sixth transistor T6 may connect the third node N3 and the fifth node N5 in response to the second emission signal EM2.

[0167] The eighth transistor T8 may include a gate receiving the first emission signal EM1, a source receiving the first power voltage ELVDD, and a drain connected to the second node N2. The eighth transistor T8 may transmit the first power voltage ELVDD to the second node N2 in response to the first emission signal EM1.

[0168] In reference Figure 17 In the embodiment described, the first pixel PX1 and the second pixel PX2 can share two transistors T8 and T9 connected to the second node N2 (or the source of the first transistor T1). Accordingly, the number of transistors included in the first pixel PX1 and the second pixel PX2 can be reduced by two, and the resolution of the display device 100 can be improved.

[0169] Figures 18 and 19 is used to describe Figure 17 FIG. 1 is a timing diagram of operations of the first pixel PX1 and the second pixel PX2 .

[0170] Will omit reference Figure 4 and Figure 5The description of the operation period of the first pixel PX1 and the second pixel PX2 is substantially the same or similar to that of the reference numerals 1 and 2. Figure 18 and Figure 19 A description of a period of operation of the first pixel PX1 and the second pixel PX2 is described.

[0171] refer to Figure 17 、 Figure 18 and Figure 19 The first emission signal EM1 may have an on-voltage level in the first and second initialization periods PI1 and PI2, the first and second compensation periods PC1 and PC2, and the first and second emission periods PE1 and PE2, and the first emission signal EM1 may have an off-voltage level in the write period PW and the first and second bypass periods PB1 and PB2. The second emission signal EM2 may have an on-voltage level in the first and second emission periods PE1 and PE2. The second emission signal EM2 may have an off-voltage level in periods other than the first and second emission periods PE1 and PE2.

[0172] The third transistor T3, the fifth transistor T5, and the eighth transistor T8 can be turned on in response to the second gate signal GC having a turn-on voltage level and the first emission signal EM1 during the first compensation period PC1. A voltage ELVDD-Vth obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the first power voltage ELVDD can be transmitted to the first node N1, and a reference voltage VREF can be transmitted to the fourth node N4. The voltage of the fourth node N4 can be changed from the data voltage of the previous frame period to the reference voltage VREF, and due to the coupling effect of the storage capacitor CST, the voltage change of the fourth node N4 can affect the voltage of the first node N1. During the first compensation period PC1, the first node N1 can be charged with a voltage of ELVDD-Vth+α (α is a coupling voltage caused by the voltage change of the fourth node N4).

[0173] The third transistor T3, the fifth transistor T5, and the eighth transistor T8 may be turned on in response to the second gate signal GC having a turn-on voltage level and the first emission signal EM1 during the second compensation period PC2. A voltage ELVDD-Vth obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the first power supply voltage ELVDD may be transmitted to the first node N1, and a reference voltage VREF may be transmitted to the fourth node N4. The voltage VREF of the fourth node N4 may not change, and a voltage change of the fourth node N4 may not affect the voltage of the first node N1. During the second compensation period PC2, the first node N1 may be charged with a voltage of ELVDD-Vth. Accordingly, the gate of the first transistor T1 may be charged with a voltage ELVDD-Vth in which the threshold voltage (Vth) of the first transistor T1 is compensated.

[0174] The sixth transistor T6 and the eighth transistor T8 may be turned on in response to the first emission signal EM1 and the second emission signal EM2 having the turn-on voltage level in the first emission period PE1, and the first transistor T1 may generate a driving current (I) calculated by Equation 1 and Equation 2. In the first emission period PE1, the driving current (I) may flow through the light emitting element EL, and the light emitting element EL may emit light having a luminance corresponding to the data voltage VDAT.

[0175] The sixth transistor T6 and the eighth transistor T8 may be turned on in response to the first emission signal EM1 and the second emission signal EM2 having the turn-on voltage level in the second emission period PE2, and the first transistor T1 may generate a driving current (I) calculated by Equation 1 and Equation 2. In the second emission period PE2, the driving current (I) may flow through the light emitting element EL, and the light emitting element EL may emit light having a luminance corresponding to the data voltage VDAT.

[0176] Figure 20 The diagram is included in Figure 1 1 is a circuit diagram of an example of a first pixel PX1, a second pixel PX2, and a third pixel PX3 in the display device 100.

[0177] Will omit reference Figure 17 The components of the first pixel PX1 and the second pixel PX2 are substantially the same or similar to those described above. Figure 20 Description of components of the first to third pixels PX1, PX2, and PX3 are described.

[0178] refer to Figure 1 and Figure 20Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, a hold capacitor CHD, and a light emitting element EL. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may share two transistors. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may share an eighth transistor T8 and a ninth transistor T9.

[0179] In reference Figure 20 In the described embodiment, the first pixel PX1, the second pixel PX2, and the third pixel PX3 can share two transistors T8 and T9 connected to the second node N2 (or the source of the first transistor T1). Accordingly, the number of transistors included in the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be reduced by four, and the resolution of the display device 100 can be improved.

[0180] Figure 21 The diagram is included in Figure 1 1 is a circuit diagram of an example of a first pixel PX1 and a second pixel PX2 in the display device 100.

[0181] Will omit reference Figure 3 and Figure 17 The components of the first pixel PX1 and the second pixel PX2 are substantially the same or similar to those described above. Figure 21 Description of components of the first pixel PX1 and the second pixel PX2 are described.

[0182] refer to Figure 1 and Figure 21 Each of the first pixel PX1 and the second pixel PX2 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, a hold capacitor CHD, and a light emitting element EL. The first pixel PX1 and the second pixel PX2 may share two transistors. The first pixel PX1 and the second pixel PX2 may share an eighth transistor T8 and a ninth transistor T9.

[0183] The fifth transistor T5 may include a gate receiving the second gate signal GC, a source connected to the second node N2, and a drain connected to the fourth node N4. The fifth transistor T5 may connect the second node N2 and the fourth node N4 in response to the second gate signal GC.

[0184] In reference Figure 21In the embodiment described, the first pixel PX1 and the second pixel PX2 can share two transistors T8 and T9 connected to the second node N2 (or the source of the first transistor T1). Accordingly, the number of transistors included in the first pixel PX1 and the second pixel PX2 can be reduced by two, and the resolution of the display device 100 can be improved.

[0185] Figure 22 The diagram is included in Figure 1 1 is a circuit diagram of an example of a first pixel PX1, a second pixel PX2, and a third pixel PX3 in the display device 100.

[0186] Will omit reference Figure 21 The components of the first pixel PX1 and the second pixel PX2 are substantially the same or similar to those described above. Figure 22 Description of components of the first pixel PX1, the second pixel PX2, and the third pixel PX3 are described.

[0187] refer to Figure 1 and Figure 22 Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, a hold capacitor CHD, and a light emitting element EL. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may share two transistors. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may share an eighth transistor T8 and a ninth transistor T9.

[0188] In reference Figure 22 In the described embodiment, the first pixel PX1, the second pixel PX2, and the third pixel PX3 can share two transistors T8 and T9 connected to the second node N2 (or the source of the first transistor T1). Accordingly, the number of transistors included in the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be reduced by four, and the resolution of the display device 100 can be improved.

[0189] Figure 23 is a block diagram illustrating an electronic device 1000 according to an embodiment.

[0190] refer to Figure 23 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The electronic device 1000 may further include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. or communicating with other systems.

[0191] The processor 1010 may perform a specific calculation or task. Depending on the embodiment, the processor 1010 may be a microprocessor or a central processing unit (CPU). The processor 1010 may be connected to other components via an address bus, a control bus, and a data bus. Depending on the embodiment, the processor 1010 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. In an embodiment, the processor 1010 may process the first image data ( Figure 1 IMD1) and control signal ( Figure 1 CNT) is provided to the display device 1060.

[0192] The memory device 1020 may store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include: a non-volatile memory device such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano-floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM); and / or a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a mobile DRAM.

[0193] The storage device 1030 may include a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The I / O device 1040 may include: an input device such as a keyboard, a keypad, a touch pad, a touch screen, or a mouse; and an output device such as a speaker or a printer. The power supply 1050 may supply power required for the operation of the electronic device 1000. The display device 1060 may be connected to other components through a bus or other communication links. The display device 1060 may correspond to Figure 1 display device 100.

[0194] At least two pixels among the plurality of pixels included in the display device 1060 may share at least two transistors connected to the source (or second node) of the first transistor, so that the number of transistors included in the pixel can be reduced. Accordingly, the resolution of the display device 1060 can be improved.

[0195] The display device according to the embodiment may be applied to a display device included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a smart watch, a PMP, a PDA, an MP3 player, or the like.

[0196] Although the display device according to the embodiment has been described with reference to the accompanying drawings, the illustrated embodiment is an example and can be modified and changed by those having ordinary skill in the relevant art without departing from the technical spirit described in the claims.

Claims

1. A display device comprising a plurality of pixels, each of the plurality of pixels comprising: a first transistor including a gate connected to the first node, a source connected to the second node, and a drain connected to a third node; a second transistor including a gate configured to receive the first gate signal, a source configured to receive the data voltage, and a drain connected to the fourth node; a third transistor comprising a gate configured to receive a second gate signal, a source connected to the third node, and a drain connected to the first node; a storage capacitor comprising a first terminal connected to the first node and a second terminal connected to the fourth node; as well as a light emitting element including a first terminal connected to the fifth node and a second terminal configured to receive a second power supply voltage, At least two pixels among the plurality of pixels share at least two transistors connected to the second node.

2. The display device according to claim 1, wherein The plurality of pixels include a first pixel and a second pixel that are disposed in the same pixel row and are adjacent to each other, and The first pixel and the second pixel share the at least two transistors.

3. The display device according to claim 2, wherein: The first pixel is one of a red pixel, a green pixel, and a blue pixel, and The second pixel is another one of the red pixel, the green pixel and the blue pixel.

4. The display device according to claim 1, wherein The plurality of pixels include a first pixel, a second pixel, and a third pixel that are arranged in the same pixel row and are adjacent to each other, and The first pixel, the second pixel and the third pixel share the at least two transistors.

5. The display device according to claim 4, wherein The first pixel is one of a red pixel, a green pixel, and a blue pixel, wherein the second pixel is another one of the red pixel, the green pixel, and the blue pixel, and The third pixel is the remaining one of the red pixel, the green pixel and the blue pixel.

6. The display device according to any one of claims 1 to 5, wherein: The at least two transistors include: an eighth transistor including a gate configured to receive the first transmission signal, a source configured to receive the first power supply voltage, and a drain connected to the second node; and The ninth transistor includes a gate configured to receive a fourth gate signal, a source configured to receive a bias voltage, and a drain connected to the second node.

7. The display device according to claim 6, wherein: The at least two transistors further include: A tenth transistor includes a gate configured to receive the second gate signal, a source configured to receive the first power supply voltage, and a drain connected to the second node.

8. The display device according to claim 7, wherein: Each pixel of the plurality of pixels further comprises: a fifth transistor comprising a gate configured to receive the second gate signal, a source configured to receive a reference voltage, and a drain connected to the fourth node; a sixth transistor including a gate configured to receive the first emission signal, a source connected to the third node, and a drain connected to the fifth node; and The seventh transistor includes a gate configured to receive the fourth gate signal, a source configured to receive the second initialization voltage, and a drain connected to the fifth node.

9. The display device according to claim 6, wherein: Each pixel of the plurality of pixels further comprises: a sixth transistor including a gate configured to receive a second transmit signal, a source connected to the third node, and a drain connected to the fifth node; and The seventh transistor includes a gate configured to receive the fourth gate signal, a source configured to receive the second initialization voltage, and a drain connected to the fifth node.

10. The display device according to claim 9, wherein Each pixel of the plurality of pixels further comprises: The fifth transistor includes a gate configured to receive the second gate signal, a source configured to receive a reference voltage, and a drain connected to the fourth node.

11. The display device according to claim 9, wherein Each pixel of the plurality of pixels further comprises: A fifth transistor includes a gate configured to receive the second gate signal, a source connected to the second node, and a drain connected to the fourth node.

12. The display device according to claim 1, wherein Each pixel of the plurality of pixels further comprises: a fourth transistor including a gate configured to receive a third gate signal, a source configured to receive a first initialization voltage, and a drain connected to the first node; and A holding capacitor includes a first terminal connected to the fourth node and a second terminal configured to receive a first power supply voltage.

13. A display device comprising a plurality of pixels, each of the plurality of pixels comprising: a first transistor including a gate connected to the first node, a source connected to the second node, and a drain connected to a third node; a second transistor including a gate configured to receive the first gate signal, a source configured to receive the data voltage, and a drain connected to the fourth node; a third transistor comprising a gate configured to receive a second gate signal, a source connected to the third node, and a drain connected to the first node; a storage capacitor comprising a first terminal connected to the first node and a second terminal connected to the fourth node; as well as a light emitting element including a first terminal connected to the fifth node and a second terminal configured to receive a second power supply voltage, At least two pixels among the plurality of pixels share a ninth transistor, and the ninth transistor includes a gate configured to receive a fourth gate signal, a source configured to receive a bias voltage, and a drain connected to the second node.

14. The display device according to claim 13, wherein: The at least two pixels further share a tenth transistor including a gate configured to receive the second gate signal, a source configured to receive a first power supply voltage, and a drain connected to the second node.

15. A display device comprising a first pixel region, a second pixel region, and a third pixel region, wherein each of the first pixel region, the second pixel region, and the third pixel region comprises: an active layer disposed on the substrate and comprising a first source region, a first drain region, a second source region, a second drain region, a third source region, and a third drain region; a first conductive layer disposed on the active layer and comprising a first gate electrode defining a first transistor together with the first source region and the first drain region, a second gate electrode defining a second transistor together with the second source region and the second drain region, and a third gate electrode defining a third transistor together with the third source region and the third drain region; a second conductive layer disposed on the first conductive layer and including a first capacitor electrode overlapping the first gate electrode; a third conductive layer disposed on the second conductive layer and comprising a second capacitor electrode overlapping the first capacitor electrode; as well as a fourth conductive layer, disposed on the third conductive layer, wherein the first pixel region and the second pixel region share the first source region, and The first source region of the third pixel region is connected to the first source region shared by the first pixel region and the second pixel region through a bridge provided at a layer different from the active layer.

16. The display device according to claim 15, wherein The first pixel region, the second pixel region, and the third pixel region are arranged in a same pixel row, and the second pixel region is adjacent to the first pixel region and the third pixel region.

17. The display device according to claim 16, wherein: The shape of the first pixel region and the shape of the second pixel region are symmetrical to each other about an imaginary line extending in a pixel column direction between the first pixel region and the second pixel region.

18. The display device according to claim 17, wherein: The first pixel region and the third pixel region have the same shape.

19. The display device according to claim 15, wherein: The fourth conductive layer includes the bridge.

20. The display device according to claim 19, wherein The fourth conductive layer further includes a first gate line connected to the second gate electrode and a second gate line connected to the third gate electrode.

21. The display device according to claim 15, wherein The first source region shared by the first pixel region and the second pixel region includes a first protrusion extending in a pixel row direction, and Wherein, the first end portion of the bridge is connected to the first protrusion.

22. The display device according to claim 21, wherein The first source region of the third pixel region includes a second protrusion extending in the pixel row direction, and Wherein, the second end of the bridge is connected to the second protrusion.

23. The display device according to claim 15, wherein The active layer of each of the first pixel region and the second pixel region further includes an eighth source region, an eighth drain region, a ninth source region, a ninth drain region, a tenth source region, and a tenth drain region, and The first pixel region and the second pixel region share the eighth source region, the eighth drain region, the tenth source region, and the tenth drain region.

24. The display device according to claim 23, wherein The first conductive layer of each of the first pixel region and the second pixel region further includes: an eighth gate electrode, defining an eighth transistor together with the eighth source region and the eighth drain region; a ninth gate electrode, defining a ninth transistor together with the ninth source region and the ninth drain region; and A tenth gate electrode, together with the tenth source region and the tenth drain region, defines a tenth transistor.

25. The display device according to any one of claims 15 to 24, wherein: Each of the first pixel region, the second pixel region, and the third pixel region further includes: The fifth conductive layer is disposed on the fourth conductive layer and includes a data line electrically connected to the second source region and a power line electrically connected to the second capacitor electrode.

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