Display panel and display device including the same

Abstract

Disclosed are a display panel and a display device including the same. Each sub-pixel in the display panel includes a pixel circuit and a pixel control circuit configured to disable the pixel circuit in response to a voltage from a data line connected to the pixel circuit.

Description

Technical Field

[0001] The present disclosure relates to a display panel and a display device including the same. Background Art

[0002] Various flat panel display devices, such as liquid crystal displays and electroluminescent displays, are known. Electroluminescent displays use light-emitting elements arranged in individual pixels to emit light without a backlight, thereby displaying input images. Depending on the material of the light-emitting layer, the light-emitting elements of electroluminescent displays can be categorized as organic or inorganic.

[0003] Recently, display devices using light-emitting diodes (LEDs), which are inorganic light-emitting elements, as the light-emitting elements of pixels have attracted attention as next-generation display devices. Because LEDs are made of inorganic materials, they do not require a separate encapsulation layer to protect the organic material from moisture, and they have excellent reliability and long life compared to organic light-emitting diodes (OLEDs). In addition, LEDs have a fast lighting speed, excellent luminous efficiency, and impact resistance.

[0004] In the case of micro-LEDs, defective sub-pixels may occur due to defects in the transfer process of micro-LEDs. In the case of micro-LEDs, the micro-LED chips on the wafer can be transferred to a substrate on which pixel circuits are formed using a donor substrate without the need for an LED binning process. Contact failures may occur between the micro-LEDs transferred to the pixel circuit substrate, or the pixel circuits may be defective. In the repair process before product shipment, defective pixels can be turned into dark spots by laser cutting. However, adding a repair process may result in reduced panel productivity and increased manufacturing costs. Summary of the Invention

[0005] The present disclosure is intended to address the above-mentioned needs and / or problems.

[0006] The present disclosure provides a display panel capable of turning a sub-pixel into a dark spot without a separate repair process and a display device including the same.

[0007] Problems to be solved by the present disclosure are not limited to those described above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] A display panel according to one embodiment of the present disclosure includes: a plurality of data lines; a plurality of gate lines intersecting the data lines; a plurality of power lines; and a plurality of sub-pixels. Each sub-pixel includes: a pixel circuit; and a pixel control circuit configured to disable the pixel circuit based on a voltage from a data line connected to the pixel circuit.

[0009] Each subpixel may include a first-color subpixel including a first-first subpixel and a first-second subpixel; a second-color subpixel including a second-first subpixel and a second-second subpixel; and a third-color subpixel including a third-first subpixel and a third-second subpixel. Each of the first-first subpixel, the first-second subpixel, the second-first subpixel, the second-second subpixel, the third-first subpixel, and the third-second subpixel may include a pixel circuit and a pixel control circuit.

[0010] The pixel circuit of the first-first subpixel may include: a first light-emitting element; a first driving transistor including a first electrode connected to a first power line to which a pixel power voltage is applied, a gate electrode connected to a first-first node, and a second electrode connected to a first-second node; a first-first switching transistor configured to electrically connect the first data line to the first-first node in response to a strobe signal; a first-second switching transistor configured to supply a reference voltage to the first-second node in response to the strobe signal; and a first-first capacitor connected between the first-first node and the first-second node. The first light-emitting element may include an anode electrode connected to the first-second node and a cathode electrode connected to a second power line to which a ground voltage is applied. The pixel circuit of the first-second subpixel may include: a second light-emitting element; a second driving transistor including a first electrode connected to the first power line, a gate electrode connected to the second-first node, and a second electrode connected to the second-second node; a second-first switching transistor configured to electrically connect the second data line to the second-first node in response to a strobe signal; a second-second switching transistor configured to supply a reference voltage to the second-second node in response to the strobe signal; and a second-first capacitor connected between the second-first node and the second-second node. The second light-emitting element may include an anode electrode connected to the second-second node and a cathode electrode connected to the second power line.

[0011] When a pixel driving voltage is applied to the first data line, the first light-emitting element may emit light. When a pixel driving voltage is applied to the second data line, the second light-emitting element may emit light. When a neutral voltage higher than the maximum voltage of the pixel driving voltage is applied to the first data line, the pixel control circuit of the first-first sub-pixel may electrically connect the first-first node to the second power line. When a neutral voltage is applied to the second data line, the pixel control circuit of the first-second sub-pixel may electrically connect the second-first node to the second power line.

[0012] The display panel may further include a neutral reference voltage line to which a neutral reference voltage is applied. The pixel control circuit of the first-first subpixel may include: first-third switching transistors including a first electrode connected to the first data line, a gate electrode to which a selection signal is applied, and a second electrode connected to the first-third node; first-fourth switching transistors including a first electrode connected to the first-first node, a first gate electrode to which the neutral reference voltage is applied, a second gate electrode connected to the first-third node, and a second electrode connected to the second power line; and first-second capacitors connected between the first-third node and the second power line.

[0013] The pixel control circuit of the first-second sub-pixel may include: a second-third switching transistor, which includes a first electrode connected to the second data line, a gate electrode to which a selection signal is applied, and a second electrode connected to the second-third node; a second-fourth switching transistor, which includes a first electrode connected to the second-first node, a first gate electrode to which a neutral reference voltage is applied, a second gate electrode connected to the second-third node, and a second electrode connected to the second power line; and a second-second capacitor, which is connected between the second-third node and the second power line.

[0014] When a pixel driving voltage is applied to the first data line, the first light-emitting element may emit light. When a pixel driving voltage is applied to the second data line, the second light-emitting element may emit light. When a neutral voltage higher than the maximum voltage of the pixel driving voltage is applied to the first data line, the pixel control circuit of the first-first sub-pixel may electrically connect the cathode electrode of the first light-emitting element to the first power line. When a neutral voltage is applied to the second data line, the pixel control circuit of the first-second sub-pixel may electrically connect the cathode electrode of the second light-emitting element to the first power line.

[0015] The pixel circuit of the first-first subpixel may include: a first light-emitting element; a first driving transistor including a first electrode connected to a first power supply line to which a pixel power supply voltage is applied, a gate electrode connected to a first-first node, and a second electrode connected to a first-second node; a first-first switching transistor configured to electrically connect the first data line to the first-first node in response to a strobe signal; a first-second switching transistor configured to supply a reference voltage to the first-second node in response to the strobe signal; and a first-first capacitor connected between the first-first node and the first-second node. The first light-emitting element may include an anode electrode connected to the first-second node and a cathode electrode connected to the first-fourth node. The pixel circuit of the first-second subpixel may include: a second light-emitting element; a second driving transistor including a first electrode connected to the first power line, a gate electrode connected to the second-first node, and a second electrode connected to the second-second node; a second-first switching transistor configured to electrically connect the second data line to the second-first node in response to a strobe signal; a second-second switching transistor configured to supply a reference voltage to the second-second node in response to the strobe signal; and a second-first capacitor connected between the second-first node and the second-second node. The second light-emitting element may include an anode electrode connected to the second-second node and a cathode electrode connected to the second-fourth node.

[0016] The pixel control circuit of the first-first sub-pixel may include: first-third switching transistors, which include a first electrode connected to the first data line, a gate electrode to which a selection signal is applied, and a second electrode connected to the first-third node; first-fourth switching transistors, which include a first electrode connected to the cathode electrode of the first light-emitting element, a first gate electrode to which a first neutral reference voltage is applied, a second gate electrode connected to the first-third node, and a second electrode connected to the first power line; first-fifth switching transistors, which include a first electrode connected to the first-fourth node, a first gate electrode connected to the first-third node, a second gate electrode to which a second neutral reference voltage is applied, and a second electrode connected to the second power line to which a ground voltage is applied; and first-second capacitors, which are connected between the first-third node and the first-fourth node. The pixel control circuit of the first-second sub-pixel may include: a second-third switching transistor, which includes a first electrode connected to the second data line, a gate electrode to which a selection signal is applied, and a second electrode connected to the second-third node; a second-fourth switching transistor, which includes a first electrode connected to the cathode electrode of the second light-emitting element, a first gate electrode to which a first neutral reference voltage is applied, a second gate electrode connected to the second-third node, and a second electrode connected to the first power line; a second-fifth switching transistor, which includes a first electrode connected to the second-fourth node, a first gate electrode connected to the second-third node, a second gate electrode to which a second neutral reference voltage is applied, and a second electrode connected to the second power line; and a second-second capacitor, which is connected between the second-third node and the second-fourth node.

[0017] The first neutral reference voltage may be a negative voltage, and the second neutral reference voltage may be a positive voltage. Each of the first to third switching transistors, the first to fourth switching transistors, the second to third switching transistors, and the second to fourth switching transistors may be an n-channel transistor. Each of the first to fifth switching transistors and the second to fifth switching transistors may be a p-channel transistor.

[0018] The first-first subpixel may further include a first sensing circuit connected to a sensing line to which a reference voltage is applied and configured to sense an electrical characteristic of the first drive transistor. The first-second subpixel may further include a second sensing circuit connected to the sensing line and configured to sense an electrical characteristic of the second drive transistor.

[0019] A display device according to one embodiment of the present disclosure includes: a display panel having a plurality of data lines, a plurality of gate lines intersecting the data lines, a plurality of power lines, and a plurality of sub-pixels arranged therein; a data driver configured to output a pixel driving voltage for driving the sub-pixels and a neutral voltage for disabling the sub-pixels to the data lines; and a gate driver configured to supply a gate signal to the gate lines. Each sub-pixel may include a pixel circuit; and a pixel control circuit configured to disable the pixel circuit in response to the neutral voltage.

[0020] Each subpixel may include: a first color subpixel including a first-first subpixel connected to a first data line and a first-second subpixel connected to a second data line; a second color subpixel including a second-first subpixel connected to a third data line and a second-second subpixel connected to a fourth data line; and a third color subpixel including a third-first subpixel connected to a fifth data line and a third-second subpixel connected to a sixth data line. Each of the first-first subpixel, the first-second subpixel, the second-first subpixel, the second-second subpixel, the third-first subpixel, and the third-second subpixel may include a pixel circuit and a pixel control circuit.

[0021] The first-first sub-pixel may include: a first light-emitting element; and a first driving transistor configured to drive the first light-emitting element. The first-second sub-pixel may include: a second light-emitting element; and a second driving transistor configured to drive the second light-emitting element. When a pixel driving voltage is applied to the first data line, the first light-emitting element may emit light. When a pixel driving voltage is applied to the second data line, the second light-emitting element may emit light. When a neutral voltage higher than a maximum voltage of the pixel driving voltage is applied to the first data line, the pixel control circuit of the first-first sub-pixel may disable the pixel circuit of the first-first sub-pixel. When a neutral voltage is applied to the second data line, the pixel control circuit of the first-second sub-pixel may disable the pixel circuit of the first-second sub-pixel.

[0022] When a neutral voltage is applied to the first data line, the pixel control circuit of the first-first subpixel may supply a ground voltage to the gate electrode of the first driving transistor. When a neutral voltage is applied to the second data line, the pixel control circuit of the first-second subpixel may supply a ground voltage to the gate electrode of the second driving transistor.

[0023] When a neutral voltage is applied to the first data line, the pixel control circuit of the first-first subpixel may supply a pixel power supply voltage to the cathode electrode of the first light-emitting element. When a neutral voltage is applied to the second data line, the pixel control circuit of the first-second subpixel may supply a pixel power supply voltage to the cathode electrode of the second light-emitting element.

[0024] A display device may include: a sensing circuit connected to a drive transistor provided in each subpixel and configured to sense an electrical characteristic of the drive transistor of each subpixel; and a memory configured to store sensing data obtained from the sensing circuit. In response to the sensing data having an overflow value or an underflow value outside a normal driving range of the subpixel, neutral data is stored in the memory.

[0025] According to an embodiment of the present disclosure, a light-emitting element can be driven with high efficiency and high brightness to improve lifespan and achieve low-power driving, and multiple sub-pixels of the same color within a pixel can be arranged to effectively respond to improvements in defects in the light-emitting element or pixel circuit, thereby improving process optimization and yield of the display panel.

[0026] According to an embodiment of the present disclosure, when a defective subpixel identified in an inspection process and a progressive defect in which a normal subpixel is converted into a defective subpixel due to stress accumulation within a driving history are sensed, the defective subpixel can become a dark spot without a separate repair process.

[0027] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be apparently understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0029] Figure 1 is a block diagram illustrating a display device according to one embodiment of the present disclosure;

[0030] Figure 2 is a diagram showing a timing of entering a sensing mode in a driving sequence of a display device;

[0031] Figure 3 is a circuit diagram illustrating a sub-pixel according to one embodiment of the present disclosure;

[0032] Figure 4 is a diagram showing an example of a path to which a neutral reference voltage is applied;

[0033] Figure 5 is a diagram showing a sub-pixel configuration of one pixel according to one embodiment of the present disclosure;

[0034] Figure 6A and Figure 6B is shown in sensing mode Figure 5 A diagram illustrating an example of a sensing operation of a pixel;

[0035] Figure 7is a diagram illustrating an example of a method of sensing a sub-pixel to be dimmed according to one embodiment of the present disclosure;

[0036] Figure 8 is a circuit diagram illustrating a first-first sub-pixel and a first-second sub-pixel according to one embodiment of the present disclosure;

[0037] Figure 9 It shows Figure 8 A graph showing operating characteristics of the first-fourth switching transistor M14 and the second-fourth switching transistor M24;

[0038] Figure 10 is a diagram showing the voltage of the main node and the current of the light emitting element, which shows the operation of the sub-pixel to be dimmed;

[0039] Figure 11 is a diagram showing the voltage of the main node and the current of the light emitting element, which shows the operation of a normal sub-pixel;

[0040] Figure 12 is a circuit diagram illustrating a sub-pixel according to another embodiment of the present disclosure;

[0041] Figure 13 is a circuit diagram illustrating a first-first sub-pixel and a first-second sub-pixel according to another embodiment of the present disclosure; and

[0042] Figure 14 It shows Figure 13 A diagram showing the operating characteristics of a switching transistor in a pixel control circuit. DETAILED DESCRIPTION

[0043] The advantages and features of the present disclosure and their implementation methods will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, the present embodiments will make the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0044] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, similar reference numerals generally represent similar elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0045] Terms such as “including,” “comprising,” and “having” used herein are generally intended to allow the addition of other components unless these terms are used with the term “only.” Any reference to the singular may include the plural unless expressly stated otherwise.

[0046] Even if not explicitly stated, components are interpreted as including ordinary margins of error.

[0047] When describing the position or interconnection relationship between two components, such as "on", "above", "below", "beside", "connected or coupled to", "crossing", "intersecting", etc., unless "immediately" or "directly" is used, one or more other components may be interposed between them.

[0048] When describing a temporal precedent relationship, such as "after," "subsequently," "next," "before," etc., unless "immediately" or "directly" is used, it may not be continuous based on time.

[0049] Terms such as “first” and “second” may be used to distinguish components from each other, but the function or structure of the components is not limited by ordinal numbers preceding the components or names of the components.

[0050] The following embodiments may be partially or completely joined or combined with each other, and may be linked and operated in various ways technically. These embodiments may be implemented independently of each other or in association with each other.

[0051] A pixel circuit of a display device may include a plurality of transistors, which may be implemented as an oxide thin film transistor (TFT) including an oxide semiconductor, a low-temperature polysilicon TFT (LTPS TFT) including low-temperature polysilicon, or the like.

[0052] A transistor is a three-electrode component consisting of a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current flow direction from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, the present disclosure is not limited to the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0053] The gate signal swings between a gate-on voltage and a gate-off voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be a gate high voltage (VGH), and the gate-off voltage can be a gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage can be a gate low voltage (VGL), and the gate-off voltage can be a gate high voltage (VGH).

[0054] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 is a block diagram illustrating a display device according to one embodiment of the present disclosure.

[0056] Reference Figure 1 , a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driving circuit.

[0057] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be used in a transparent display device, where an image is displayed on a screen and a real object is visible outside the display panel. The display panel 100 can be made into a flexible display panel. In addition, the display panel 100 can be made of a stretchable panel that can be stretched.

[0058] The display panel 100 may be a panel having a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, a plurality of sensing lines 104, and pixels arranged in a matrix form. The display panel 100 may also include a power supply line connected to the pixels in common. The power supply line may be connected to the pixel circuit in common and supply the voltage required to drive the pixel 101 to the pixel 101. The power supply line may be implemented as a long lead along the X-axis direction or the Y-axis direction, or as a meshed lead electrically connected to the lead in the X-axis direction and the lead in the Y-axis direction.

[0059] The data lines 102 are arranged in the form of long leads along the Y-axis direction of the display panel 100 and are electrically connected to data channel terminals of the data driver 110. The sensing lines 104 are arranged on the display panel in parallel with the data lines 102 and can be connected to the sensing channel terminals of the sub-pixels and the data driver 110. The gate lines 103 are arranged in the form of long leads along the X-axis direction of the display panel 100 to cross the data lines 102 and are electrically connected to output terminals of the gate driver 120.

[0060] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color realization. Each pixel can also include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light-emitting element. Each pixel circuit can be connected to a data line, a gate line, a power line, a sense line, and a neutral reference voltage line.

[0061] The pixel array includes a plurality of pixel rows L1(1) to L1(N). N is a natural number greater than or equal to 2. Each of the pixel rows L1(1) to L1(N) includes a row of pixels arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel row can share a gate line 103. Sub-pixels arranged in the column direction (Y-axis direction) along the data line direction can share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of pixel rows L1(1) to L1(N).

[0062] The power supply 140 regulates the level of the DC voltage Vin input from the host system 200 to output the first voltage V1 required to drive the pixel array and display panel driving circuit of the display panel 100. The power supply 140 may include a DC-DC converter (DC-DC converter). The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 outputs a constant voltage (or DC voltage) using the DC-DC converter, such as a gamma reference voltage, a gate high voltage, a gate low voltage, a pixel power supply voltage, a pixel ground voltage (hereinafter referred to as "ground voltage"), a reference voltage, or a neutral reference voltage. The gamma reference voltage is supplied to the data driver 110. The dynamic range of the data voltage output from the data driver 110 is determined by the voltage range of the gamma reference voltage. The voltage level of the data voltage is selected by the grayscale value of the pixel data. The dynamic range of the data voltage has a voltage range between a maximum voltage and a minimum voltage of the data voltage. The output voltage range of the data driver 110 may have a voltage range greater than the dynamic range of the data voltage.

[0063] The gate high voltage and the gate low voltage are supplied to the level shifter 150 and the gate driver 120. Constant voltages such as a pixel power voltage, a ground voltage, a reference voltage, and a neutral reference voltage are supplied to the pixels 101 through power lines commonly connected thereto.

[0064] The display panel driving circuit writes pixel data of an input image into pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110, a gate driver 120, and a sensing part 160.

[0065] The display device includes a sensing circuit that provides digital data corresponding to a sensing voltage obtained from a subpixel (hereinafter referred to as “sensing data”) to a timing controller 130 using a data driver 110 , a gate driver 120 , and a sensing line 104 connected to the subpixel.

[0066] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver may be integrated into one driving IC (Integrated Circuit).

[0067] The data driver 110 outputs a pixel driving voltage for driving a sub-pixel and a neutral voltage for disabling a sub-pixel to the data line. The pixel driving voltage may include a data voltage corresponding to pixel data of an input image. The neutral voltage is different from the pixel driving voltage.

[0068] The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage to the data line 102. The data voltage corresponding to the pixel data may be a pixel driving voltage. The data driver 110 may convert neutral data into a neutral voltage and output it to the data line 102 connected to the sub-pixel to be dimmed.

[0069] The data driver 110 includes a data channel electrically connected to the data line 102 and outputting a data voltage Vdata, and a sensing channel electrically connected to the sensing line 104 and receiving a sensing voltage.

[0070] The data channels of the data driver 110 use a digital-to-analog converter (hereinafter referred to as a "DAC") to convert pixel data DATA' of the input image into gamma compensation voltages and output the data voltages for the pixel data. The gamma reference voltage is divided into gamma compensation voltages for each grayscale by a voltage divider circuit. The gamma compensation voltages for each grayscale are supplied to the DACs in the data driver 110. The data voltages are output from each channel of the data driver 110 via an output buffer.

[0071] The sensing channel of the data driver 110 includes an analog-to-digital converter (ADC). The sensing channel converts a sensing voltage received through the sensing line 104 into digital data using the ADC and outputs sensing data Dsen. The sensing data Dsen is transmitted to the timing controller 130.

[0072] The gate driver 120 may be disposed in the non-display area NA on at least one of the right and left sides outside the display area AA of the display panel 100 , or at least a portion thereof may be disposed within the display area AA.

[0073] The gate driver 120 may be provided in the non-display areas NA on both sides of the display panel 100 with the display area AA of the display panel interposed therebetween, and may supply gate pulses from both sides of the gate line 103 in a dual-feed method. In another embodiment, the gate driver 120 may be provided on at least one side of the left and right non-display areas BZ of the display panel 100 to supply gate signals to the gate line 103 in a single-feed method. The gate driver 120 sequentially outputs pulses of the gate signal to the gate line 103 under the control of the timing controller 130. The gate driver 120 may shift the pulses of the gate signal using a shift register to sequentially supply them to the gate line 103.

[0074] The timing controller 130 receives digital video data of an input image and timing signals synchronized with the digital video data from the host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The vertical and horizontal periods can be identified by counting the data enable signal DE, so the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a period of one horizontal period (1H).

[0075] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200. The timing controller 130 synchronizes the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0076] The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 150. The level shifter 150 gates the voltage of the signal received from the timing controller 130 to a swing width between a gate high voltage and a gate low voltage, and outputs a start pulse and a shift clock. The start pulse and shift clock of the gate timing signal are input to the gate driver 120.

[0077] The display panel drive circuit, under the control of the timing controller 130, scans the pixels in the display mode to write pixel data of the input image into the pixels 101. In the display mode, the input image is reproduced on the display area AA. The sensing circuit can sense each sub-pixel in the display area AA in the sensing mode, thereby sensing the electrical characteristics (e.g., threshold voltage) of the drive transistors in all sub-pixels in real time and sensing the sub-pixels to be dimmed.

[0078] The display device may enter the sensing mode in at least one of the following sequences: a power-on sequence (ON RF) in which power starts to be applied to the display device, a vertical blanking time VB within a display time, and a power-off sequence (OFF RS) in which a power-off switch of the display device is turned on. Figure 2 As shown. The vertical blanking time VB is a blanking period within a frame period, except for the effective period AT during which the pixel data of the input image is written into the pixel. During the vertical blanking time VB, pixel data is not input to the data driver 110, and the pixel data is not written into the sub-pixel. In the display mode, during the effective period AT of each frame period, the pixel data DATA' is input to the data driver 110, and the data voltage output from the data driver 110 charges the sub-pixel, so that the pixel data is written into the sub-pixel.

[0079] In the power-off sequence (OFF RS), the display panel driving circuit may continue driving for a predetermined period of time after the user turns on the power-off switch to sense the threshold voltage of the driving transistor in each sub-pixel, and then stop driving when the DC input voltage (Vin) applied to the power supply 140 from the host system 200 is cut off. In the sensing mode, the sensing data Dsen output from the sensing channel of the data driver 110 electrically connected to the sensing line 104 is transmitted to the timing controller 130.

[0080] Compensation values for compensating the initial electrical characteristics of the drive transistors in each subpixel may be pre-stored in a lookup table memory accessible to the timing controller 130. The compensation values stored in the lookup table memory may be stored for each subpixel. In sensing mode, the timing controller 130 may update the compensation values for each subpixel in the lookup table memory based on the sensing data Dsen (i.e., sensing values) received from the sensing channels of the data driver 110. The lookup table memory may be, but is not limited to, a NAND flash memory or an electrically erasable programmable ROM (EEPROM).

[0081] When sensing data Dsen is input, the LUT can output the compensation value stored at the address pointed to by the sensing data Dsen. The timing controller 130 can update the threshold voltage of each subpixel by writing sensing data Dsen received from the ADC in sensing mode into the LUT.

[0082] The timing controller 130 modulates the pixel data by adding or multiplying the pixel data of the input image with a compensation value used to compensate for deviations or variations in the electrical characteristics of the driving transistors of each sub-pixel. The compensation value can be obtained for each sub-pixel as a sensed value sensed for each sub-pixel or as a result of an operation that reflects preset parameters in the sensed value. The pixel data DATA' modulated by the timing controller 130 can be sent to the data driver 110 for writing to the sub-pixels in the display mode.

[0083] In the display mode, pixel data DATA' modulated by the timing controller 130 is transmitted to the data driver 110 for writing into the subpixels. The data driver 110 converts the pixel data DATA' received from the timing controller 130 into a data voltage Vdata and outputs the converted data voltage Vdata.

[0084] When the sensing data Dsen (i.e., sensing value) sensed in each sub-pixel is an overflow value or an underflow value outside the normal operating range of the sub-pixel, the timing controller 130 determines that the sub-pixel from which the sensing value is obtained is a defective sub-pixel, and stores neutral data for turning the sub-pixel into a dark spot in the lookup table memory. As a result of counting the pixel data of the input image, the timing controller 130 uses the neutral data to modulate (or replace) the pixel data to be written to the sub-pixel to be darkened (or defective sub-pixel) and sends it to the data driver 110. The data driver 110 can convert the neutral data into a neutral voltage and output the neutral voltage. The sub-pixel to be darkened to which the neutral voltage is applied does not emit light because no current is generated from the driving transistor. Therefore, according to the present disclosure, the defective sub-pixel that appears due to stress accumulation can automatically become a dark spot without the need for a separate repair process. The neutral voltage can be interpreted as a neutral data voltage or a darkening voltage.

[0085] After the product of the display panel 100 is shipped, the display panel can be handed over to an assembly plant. In the assembly plant, a host system is connected to the display panel drive circuit of the display panel 100, and the display panel is completed as a user-usable product. After the product of the display panel 100 is shipped, the electrical characteristics (e.g., threshold voltage) of the drive transistor DR can be sensed in each sub-pixel. In the display device, the stress of the drive transistor DR in the display mode accumulates in each sub-pixel, thereby changing the electrical characteristics (e.g., threshold voltage) of the drive transistor DR. The sensing circuit can sense the electrical characteristics of the drive transistor DR in the sensing mode, and the timing controller 130 can modulate the pixel data using a compensation value selected based on the sensed value to compensate for the change in the electrical characteristics of the drive transistor DR, thereby preventing image quality degradation and extending the life of the display device.

[0086] When a user uses the display panel 100 after it has been shipped, the timing controller 130 can change the sub-pixels to be dimmed into dark spots by sending updated neutral data in the lookup table to the data driver 110 based on the sensing values of the respective sub-pixels obtained in the sensing mode. Therefore, while the user is using the display device, defective sub-pixels caused by stress accumulation can be automatically changed into dark spots without requiring any repair process.

[0087] Figure 3 is a circuit diagram illustrating a sub-pixel according to one embodiment of the present disclosure.

[0088] Reference Figure 3 , a sub-pixel may include a pixel circuit PXL, a sensing circuit SC and a pixel control circuit 30.

[0089] The pixel circuit PXL drives the light emitting element LD according to pixel data of an input image. The pixel circuit PXL may include a light emitting element LD, a driving transistor DR, a capacitor Cst, a first switching transistor M1, and a second switching transistor M2.

[0090] The sensing circuit SC may include an ADC, a third switching transistor M3, and a fourth switching transistor M4. The drive transistor DR and the switching transistors M1 to M4 may be implemented as, but not limited to, n-channel transistors. The ADC and the switching transistors M3 and M4 of the sensing circuit may be provided in a sensing channel of the data driver 110.

[0091] The pixel circuit PXL is connected to a first power line PL1 to which a pixel power supply voltage EVDD is applied, a second power line PL2 to which a ground voltage EVSS is applied, and a sensing line SL to which a reference voltage Vref is applied. The pixel power supply voltage EVDD can be set to, but is not limited to, a voltage at which the drive transistor DR operates in its saturation region (e.g., 20V). The pixel power supply voltage EVDD is a voltage higher than the maximum voltage of the data voltage Vdata. The ground voltage EVSS and the reference voltage Vref are voltages lower than the pixel power supply voltage EVDD and lower than the minimum voltage of the data voltage Vdata. The ground voltage EVSS can be 0V, and the reference voltage Vref can be, but is not limited to, 1V to 2V.

[0092] The pixel circuit PXL is connected to a data line DL to which a data voltage Vdata is applied, a gate line GL to which a gate signal SCAN is applied, and a sensing line SL. The pulse of the gate signal SCAN swings between a gate high voltage (hereinafter referred to as a "gate-on voltage") and a gate low voltage (hereinafter referred to as a "gate-off voltage").

[0093] The drive transistor DR drives the light-emitting element LD by supplying a current to the light-emitting element LD according to its gate-source voltage Vgs. The voltage between the first node DTG and the second node DTS is the gate-source voltage of the drive transistor DR. The drive transistor DR includes a first electrode connected to a first power line PL1 to which a pixel power supply voltage EVDD is applied, a gate electrode connected to the first node DTG, and a second electrode connected to a second node DTS. A capacitor Cst is connected between the first node DTG and the second node DTS.

[0094] The light-emitting element LD may include an anode electrode, a cathode electrode, and a light-emitting layer. The anode electrode of the light-emitting element LD may be connected to a second node DTS. The cathode electrode of the light-emitting element LD may be connected to a second power line PL2 to which a ground voltage EVSS is applied. The light-emitting element LD may be, but is not limited to, a light-emitting element such as an OLED, a mini-LED, a micro-LED, or the like. The mini-LED or micro-LED may have a vertical structure in which electrodes are arranged at the top and bottom of a semiconductor chip in which the light-emitting element LD is integrated. The semiconductor chip in which the light-emitting element LD is integrated may be implemented in a lateral structure or a flip-chip structure. The light-emitting element LD and the drive transistor DR may be connected in series between the pixel power supply voltage EVDD and the ground voltage EVSS.

[0095] The first switching transistor M1 is connected between the data line DL and the first node DTG and is turned on in response to a gate-on voltage of a selection signal SCAN. When the first switching transistor M1 is turned on, the data line DL is electrically connected to the first node DTG. The first switching transistor M1 includes a first electrode connected to the data line DL, a gate electrode connected to the gate line GL to which the selection signal SCAN is applied, and a second electrode connected to the first node DTG.

[0096] The second switching transistor M2 is connected between the second node DTS and the sensing line SL and is turned on in response to the gate-on voltage of the selection signal SCAN. When the second switching transistor M2 is turned on, the second node DTS is electrically connected to the sensing line SL. The second switching transistor M2 includes a first electrode connected to the second node DTS, a gate electrode connected to the gate line GL to which the selection signal SCAN is applied, and a second electrode connected to the sensing line SL. A capacitor Cs storing a sensing voltage Vsen may be connected to the sensing line SL. The capacitor Cs may be formed as a parasitic capacitor connected to the sensing line SL or as a separate capacitor connected to the sensing line SL.

[0097] The third switching transistor M3 is connected between the sensing line SL and a third power line PL3 to which a reference voltage Vref is applied, and may be turned on in a sensing mode under the control of the timing controller 130. When the third switching transistor M3 is turned on, the reference voltage Vref may be applied to the sensing line SL to initialize the sensing line SL to the reference voltage Vref.

[0098] The fourth switching transistor M4 may be connected between the sensing line SL and the ADC and may be turned on in a sensing mode under the control of the timing controller 130. When the fourth switching transistor M4 is turned on, a voltage Vsen sensed from the second node DTS of the pixel circuit is input to the ADC through the sensing line SL and the fourth switching transistor M4.

[0099] The ADC converts the sensing voltage Vsen into digital data and outputs the sensing data Dsen. In addition, a sample-and-hold circuit, an amplifier, an integrator, etc. may be added between the fourth switching transistor M4 and the ADC.

[0100] The pixel control circuit 30 can selectively disable the pixel circuit PXL according to the voltage level of the data voltage, allowing subpixels to be darkened. For example, in subpixels to be darkened that are found to be defective during the inspection process before product shipment, or in subpixels to be darkened that are detected as defective by the sensing circuit SC after product shipment, the pixel control circuit 30 can be turned on, thereby controlling the drive transistor DR to be in an off state. On the other hand, in normal subpixels, the pixel control circuit 30 is disabled, without affecting the driving of the normal subpixels. The pixel control circuit 30 can be interpreted as a neutral circuit or a dimming circuit.

[0101] The pixel control circuit 30 receives a strobe signal SCAN, a neutral reference voltage Vnr, and a ground voltage EVSS, and is connected to the data line DL. When a neutral voltage is applied to the data line DL, the pixel control circuit 30 turns on to turn the drive transistor DR off. Consequently, the sub-pixel in which the pixel control circuit 30 turns on becomes a dark pixel because the light-emitting element LD does not emit light.

[0102] The neutral reference voltage Vnr may be set as a reference voltage for distinguishing between the on / off states of the pixel control circuit 30 in the normal sub-pixel and the sub-pixel to be dimmed. The neutral reference voltage Vnr may be commonly applied to all sub-pixels through a neutral reference voltage line RL connected to the sub-pixels, but is not limited thereto.

[0103] Figure 4 is a diagram showing an example of a path to which a neutral reference voltage is applied.

[0104] Reference Figure 4 , the display device may include a control board CPCB, a source board SPCB, and a chip on film COF electrically connected to the display panel 100. A source driver IC (DIC) integrated with a circuit of the data driver 110 may be mounted on a flexible film of the COF.

[0105] The control board CPCB may include a timing controller 130, a power supply 140, and the like. The control board CPCB may be electrically connected to the source board SPCB via a flexible circuit and connector, such as a flexible flat cable (FFC) and a flexible printed circuit board (FPCB). The level shifter 150 may be mounted on the control board CPCB or the source board SPCB.

[0106] The circuit of the data driver 110 is integrated into the source driver IC (DIC). A COF may be connected between the source plate SPCB and the display panel 100 to electrically connect the source plate SPCB to the display panel 100 and supply the data voltage output from the source driver IC (DIC) to the data lines on the display panel 100.

[0107] A neutral reference voltage Vnr output from a power supply 140 is supplied to the display panel 100 via a source plate SPCB and a dummy channel line of the COF. The display panel 100 includes a neutral reference voltage line RL that supplies the neutral reference voltage Vnr to the subpixels SP_R, SP_G, and SP_B. The neutral reference voltage line RL may be connected to a wiring disposed in a non-display area NA of the display panel 100 and connected to the subpixels SP_R, SP_G, and SP_B of the display area AA by branching from the wiring to respective pixel rows.

[0108] Figure 5 is a diagram illustrating a sub-pixel configuration of one pixel according to one embodiment of the present disclosure.

[0109] Reference Figure 5 Each pixel 101 may include at least a first color sub-pixel SP_R, a second color sub-pixel SP_G, and a third color sub-pixel SP_B. The first color may be red, the second color may be green, and the third color may be blue, but is not limited thereto.

[0110] The first color subpixel SP_R may include a first-first subpixel R1 and a first-second subpixel R2. The second color subpixel SP_G may include a second-first subpixel G1 and a second-second subpixel G2. The third color subpixel SP_B may include a third-first subpixel B1 and a third-second subpixel B2. Thus, each subpixel includes a primary subpixel and a secondary subpixel. The subpixels R1 to B2 may be commonly connected to a gate line GL and a neutral reference voltage line RL to share the gate line GL and the neutral reference voltage line RL.

[0111] Subpixels R1 to B2 can be connected to different data lines DL1 to DL6 to supply independent data voltages Vdata1 to Vdata6, respectively. The first-first subpixel R1 and the first-second subpixel R2 can be commonly connected to the first sensing line SL1 to share the first sensing line SL1. The second-first subpixel G1 and the second-second subpixel G2 can be commonly connected to the second sensing line SL2 to share the second sensing line SL2. The third-first subpixel B1 and the third-second subpixel B2 can be commonly connected to the third sensing line SL3 to share the third sensing line SL3.

[0112] Figure 6A and Figure 6B is shown in sensing mode Figure 5 A diagram showing an example of a sensing operation of a pixel is shown.

[0113] In the sensing mode, adjacent sub-pixels of the same color sharing a sensing line may be alternately sensed.

[0114] During the first sensing period, as Figure 6A As shown, a pulse of the strobe signal SCAN is applied to subpixels R1 to B2, and data voltages Vdata1, Vdata3, and Vdata5 for sensing are applied to the first-first subpixel R1, the second-first subpixel G1, and the third-first subpixel B1 in synchronization therewith. At this time, a black grayscale voltage is applied to the first-second subpixel R2, the second-second subpixel G2, and the third-second subpixel B2 via data lines DL2, DL4, and DL6. During the first sensing period, data voltages Vdata1, Vdata3, and Vdata5 for sensing are applied to the first node DTG of the first-first subpixel R1, the second-first subpixel G1, and the third-first subpixel B1. As a result, the drive transistor DR is turned on, causing the voltage of the second node DTS to rise. Therefore, the threshold voltage Vth of the drive transistor DR can be sensed. The sensing voltage is input to the ADC via the sensing line SL. During the first sensing period, the black gray voltage is applied to the first nodes DTG of the first-second subpixel R2, the second-second subpixel G2, and the third-second subpixel B2, and thus the driving transistors DR of these subpixels R2, G2, and B2 are in an off state.

[0115] During the second sensing period, as Figure 6B As shown, a pulse of the strobe signal SCAN is applied to subpixels R1 to B2, and data voltages Vdata2, Vdata4, and Vdata6 for sensing are applied to the first-second subpixel R2, the second-second subpixel G2, and the third-second subpixel B2 in synchronization therewith. At this time, a black grayscale voltage can be applied to the first-first subpixel R1, the second-first subpixel G1, and the third-first subpixel B1 via data lines DL1, DL3, and DL5. During the second sensing period, data voltages Vdata2, Vdata4, and Vdata6 for sensing are applied to the first node DTG of the first-second subpixel R2, the second-second subpixel G2, and the third-second subpixel B2. As a result, the drive transistor DR is turned on, causing the voltage of the second node DTS to rise. Therefore, the threshold voltage of the drive transistor DR can be sensed. The sensing voltage is input to the ADC via the sensing line SL. During the second sensing period, the black gray voltage is applied to the first nodes DTG of the first-first subpixel R1, the second-first subpixel G1, and the third-first subpixel B1, and thus the driving transistors DR of these subpixels R1, G1, and B1 are in an off state.

[0116] Figure 7 1 is a diagram illustrating an example of a method of sensing a sub-pixel to be dimmed according to an embodiment of the present disclosure. The sub-pixel to be dimmed may be sensed in real time (eg, in a power-off sequence (OFF RS)) in a sensing mode, but is not limited thereto.

[0117] Reference Figure 7 , the sensing circuit SC senses each sub-pixel in the sensing mode ( S1 ).

[0118] The timing controller 130 receives the sensing data Dsen for each subpixel from the ADC of the sensing circuit SC and transfers it to a lookup table memory. The lookup table memory can update the compensation value for each subpixel in the sensing mode. When the sensing data Dsen overflows or underflows outside the normal driving range of the subpixel, the timing controller 130 can determine that the subpixel is a subpixel to be dimmed and record the compensation data for the subpixel to be dimmed as neutral data in the lookup table memory, so that the compensation value for the subpixel to be dimmed is updated (S2 and S3). In other words, the subpixel is to be dimmed in response to the sensing data Dsen that is less than or greater than the sensing value within the predetermined range of the subpixel.

[0119] The timing controller 130 modulates or replaces pixel data to be written to the subpixel to be darkened from the pixel data of the input image with neutral data and transmits it to the data driver 110. As a result, a neutral voltage is applied to the subpixel to be darkened and the subpixel to be darkened does not emit light.

[0120] Figure 8 is a circuit diagram showing a first-first sub-pixel and a first-second sub-pixel according to one embodiment of the present disclosure. Hereinafter, the embodiment will be described under the assumption that the first-first sub-pixel R1 is a sub-pixel to be dimmed and the first-second sub-pixel R2 is a normal sub-pixel. Figure 8 The pixel circuit shown can be omitted Figure 3 The above description in the description is redundant. Figure 8 In the example, the sensing circuit is omitted.

[0121] Reference Figure 8 Each of the first-first sub-pixel R1 and the first-second sub-pixel R2 includes a pixel circuit PXL and a pixel control circuit 30 .

[0122] The pixel circuit PXL of the 1st-first subpixel R1 may include a first light emitting element LD1 , a first driving transistor DR1 , a 1st-first capacitor Cst1 , a 1st-first switching transistor M11 , and a 1st-second switching transistor M12 .

[0123] The first driving transistor DR1 includes a first electrode connected to a first power line PL1 to which a pixel power voltage EVDD is applied, a gate electrode connected to a first-first node DTG1, and a second electrode connected to a first-second node DTS1. A first-first capacitor Cst1 is connected between the first-first node DTG1 and the first-second node DTS1.

[0124] The first light emitting element LD1 includes an anode electrode connected to the first-second node DTS1 and a cathode electrode connected to the second power line PL2 to which the ground voltage EVSS is applied.

[0125] When the first-first switching transistor M11 is turned on, the first data line DL1 is electrically connected to the first-first node DTG1. The first-first switching transistor M11 includes a first electrode connected to the first data line DL1, a gate electrode connected to the gate line GL to which the gate signal SCAN is applied, and a second electrode connected to the first-first node DTG1.

[0126] When the first-second switching transistor M12 is turned on, the first-second node DTS1 is electrically connected to the sensing line SL. The first-second switching transistor M12 includes a first electrode connected to the first-second node DTS1, a gate electrode to which a gate signal SCAN is applied, and a second electrode connected to the sensing line SL.

[0127] The pixel control circuit 30 of the first-first sub-pixel R1 may include first-third switching transistors M13 , first-fourth switching transistors M14 , and first-second capacitors C12 .

[0128] The first-third switching transistor M13 is connected between the first data line DL1 and the first-third node n13 and is turned on in response to a gate-on voltage of a strobe signal SCAN. When the first-third switching transistor M13 is turned on, the first data line DL1 is electrically connected to the first-third node n13. The first-third switching transistor M13 includes a first electrode connected to the first data line DL1, a gate electrode to which the strobe signal SCAN is applied, and a second electrode connected to the first-third node n13.

[0129] The first-fourth switching transistors M14 are connected between the first-first node DTG1 and the second power line PL2 to which the ground voltage EVSS is applied. They can be turned on and off based on the voltage of the first-third node n13 applied to the second gate electrode of the first-fourth switching transistors M14. The first-fourth switching transistors M14 can be turned on when a neutral voltage is applied to the first-third node n13 and turned off when a data voltage of pixel data is applied to the first-third node n13. The neutral voltage can be set to a voltage higher than the maximum voltage of the data voltage of the pixel data. In other words, the neutral voltage is set to a voltage greater than the maximum possible voltage of the data voltage range of the pixel data. When the first-fourth switching transistors M14 are turned on, the first-first node DTG1 can be electrically connected to the second power line PL2. The first-fourth switching transistors M14 include a first electrode connected to the first-first node DTG1, a first gate electrode to which the neutral reference voltage Vnr is applied, a second gate electrode connected to the first-third node n13, and a second electrode connected to the second power line PL2. The second gate electrode can be interpreted as a back gate electrode, a back bias electrode, or the like. The first-second capacitor C12 is connected between the first-third node n13 and the second power line PL2 to maintain the voltage of the first-third node n13 during one frame period.

[0130] The pixel circuit PXL of the first-second subpixel R2 may include a second light emitting element LD2 , a second driving transistor DR2 , a second-first capacitor Cst2 , a second-first switching transistor M21 , and a second-second switching transistor M22 .

[0131] The second drive transistor DR2 includes a first electrode connected to the first power line PL1, a gate electrode connected to the second-first node DTG2, and a second electrode connected to the second-second node DTS2. The second-first capacitor Cst2 is connected between the second-first node DTG2 and the second-second node DTS2. The second light-emitting element LD2 includes an anode electrode connected to the second-second node DTS2 and a cathode electrode connected to the second power line PL2.

[0132] The second-first switching transistor M21 includes a first electrode connected to the second data line DL2, a gate electrode to which the strobe signal SCAN is applied, and a second electrode connected to the second-first node DTG2. The second-second switching transistor M22 includes a first electrode connected to the second-second node DTS2, a gate electrode to which the strobe signal SCAN is applied, and a second electrode connected to the sensing line SL.

[0133] The pixel control circuit 30 of the first-second sub-pixel R2 may include second-third switching transistors M23 , second-fourth switching transistors M24 , and second-second capacitors C22 .

[0134] The second-third switching transistor M23 is connected between the second data line DL2 and the second-third node n23 and is turned on in response to the gate-on voltage of the strobe signal SCAN. When the second-third switching transistor M23 is turned on, the second data line DL2 is electrically connected to the second-third node n23. The second-third switching transistor M23 includes a first electrode connected to the second data line DL2, a gate electrode to which the strobe signal SCAN is applied, and a second electrode connected to the second-third node n23.

[0135] The second-fourth switching transistor M24 can be connected between the second-first node DTG2 and the second power line PL2 and can be turned on / off according to the voltage of the second-third node n23. The second-fourth switching transistor M24 can be turned on when a neutral voltage is applied to the second-third node n23 and turned off when a data voltage of pixel data is applied to the second-third node n23. The second-fourth switching transistor M24 includes a first electrode connected to the second-first node DTG2, a first gate electrode to which a neutral reference voltage Vnr is applied, a second gate electrode connected to the second-third node n23, and a second electrode connected to the second power line PL2. The second-second capacitor C22 is connected between the second-third node n23 and the second power line PL2 to maintain the voltage of the second-third node n23 during a frame period.

[0136] Figure 9 It shows Figure 8 FIG. 1 is a diagram showing the operating characteristics of the first to fourth switching transistors M14 and the second to fourth switching transistors M24. Figure 9 In , the x-axis is the gate voltage applied to the first gate electrodes of the first to fourth switching transistors M14 and the second to fourth switching transistors M24, and the y-axis is the current flowing through the channels of the first to fourth switching transistors M14 and the second to fourth switching transistors M24. Figure 9 , the curves are operating voltage and current characteristics that vary with the reverse bias voltage applied to the first to fourth switching transistors M14 and the second to fourth switching transistors M24.

[0137] Reference Figure 9 The data voltage for reproducing the pixel data of the input image from the pixel may be a voltage within a dynamic range of 0V to 8V, but is not limited thereto. The neutral voltage may be set to a voltage higher than the maximum voltage of the data voltage of the pixel data, for example, but not limited to, 11V. The data voltage of the pixel data and the neutral voltage may be applied to the first-third node n13 and the second-third node n23 as reverse bias voltages applied to the second gate electrodes of the first-fourth switching transistors M14 and the second-fourth switching transistors M24.

[0138] The threshold voltages of the first to fourth switching transistors M14 and the second to fourth switching transistors M24 may be shifted according to the reverse bias voltage applied to their second gate electrodes. Figure 9 As shown, when the data voltage of the pixel data is 8 V, the threshold voltages of the first to fourth switching transistors M14 and the second to fourth switching transistors M24 may be lower than the threshold voltages of the first to fourth switching transistors M14 and the second to fourth switching transistors M24 when the data voltage of the pixel data is 0 V. The neutral reference voltage Vnr may be set to (but not limited to) a constant voltage (e.g., -5 V), which allows the first to fourth switching transistors M14 and the second to fourth switching transistors M24 to be non-conductive when the data voltage of the pixel data is 0 V to 8 V, and allows the first to fourth switching transistors M14 and the second to fourth switching transistors M24 to be conductive when the data voltage of the pixel data is 0 V to 8 V.

[0139] When the neutral voltage is 11V, the threshold voltages of the first to fourth switching transistors M14 and the second to fourth switching transistors M24 decrease, allowing the first to fourth switching transistors M14 and the second to fourth switching transistors M24 to turn on. When the first to fourth switching transistors M14 and the second to fourth switching transistors M24 turn on, the gate voltage of the drive transistors DR1 and DR2 is discharged to the second power line PL2, and thus the drive transistors DR1 and DR2 are turned off. Therefore, since the drive transistors DR1 and DR2 are respectively turned off, the sub-pixels applied with the neutral voltage may become dark because no current flows to the light-emitting elements LD1 and LD2.

[0140] Of the first-first subpixel R1 and the first-second subpixel R2 of the red subpixel SP_R, the first-first subpixel R1 may be the subpixel that is dimmed, while the first-second subpixel R2 may be a normal subpixel. In this case, a neutral voltage is applied to the first data line DL1, and a data voltage corresponding to pixel data is applied to the second data line DL2. As a result, the first-first subpixel R1 may become a dark spot, while the first-second subpixel may emit light at a target brightness corresponding to the grayscale value of the pixel data.

[0141] Figure 10 is a diagram showing the voltage of the main node and the current of the light emitting element, which shows the operation of the sub-pixel to be dimmed. Figure 10 In FIG, “ILD1” represents the current of the first light emitting element.

[0142] Reference Figure 10When the first data voltage Vdata1 applied to the first data line DL1 is at a neutral voltage of 11V, the first-third switching transistors M13 and the first-fourth switching transistors M14 of the pixel control circuit 30 are turned on. The first-third switching transistors M13 can be turned on for one horizontal period in response to the gate-on voltage VGH of the strobe signal SCAN, allowing the neutral voltage to be transmitted to the first-third node n13. The first-fourth switching transistors M14 can be turned on by shifting their threshold voltages to a voltage below 0V due to the neutral voltage, and can remain on for one frame period using the voltage charged in the first-second capacitor C12. At this time, the first-first node DTG1 is connected to the second power supply line PL2, to which the ground voltage EVSS is applied, via the first-fourth switching transistors M14. When the pixel control circuit 30 is driven by the neutral voltage, the first drive transistor DR1 remains in an off state, so no current flows to the first light-emitting element LD1. As a result, the first subpixel R1 becomes a dark dot.

[0143] In the first-first subpixel R1 that becomes a dark spot, after the pulse of the selection signal SCAN is inverted to the gate-off voltage VGL, the voltage charged in the first-first capacitor Cst1 may be 0V, and the voltages of the first-first node DTG1 and the first-second node DTS1 may be 0V.

[0144] Figure 11 is a graph showing the voltage of the main node and the current of the light emitting element, which shows the operation of a normal sub-pixel.

[0145] Reference Figure 11 When the second data voltage Vdata2 applied to the second data line DL2 is the data voltage of pixel data 0V to 8V, the second to fourth switching transistors M24 of the pixel control circuit 30 are maintained in the off state. The second to third switching transistors M23 can be turned on for one horizontal period in response to the gate-on voltage VGH of the strobe signal SCAN, while the second to fourth switching transistors M24 are in the off state because their threshold voltages are not shifted to a voltage below 0V. Therefore, the pixel control circuit 30 of the first to second sub-pixels R2 does not affect the normal operation of the pixel circuit PXL of the first to second sub-pixels R2.

[0146] In the first-second subpixel R2, to which the data voltage of the pixel data is applied, when the data voltage of the pixel data is applied to the second-first node DTG2, the second drive transistor DR2 may be turned on to generate a current ILD2 according to its gate-source voltage. The second light-emitting element LD2 may emit light due to the current ILD2 from the second drive transistor DR2. After the pulse of the strobe signal SCAN is inverted to the gate-off voltage VGL, the voltages of the second-first node DRG2 and the second-second node DRS2 may increase according to the data voltage charged in the second-first capacitor Cst2, and the current of the second light-emitting element LD2 may increase.

[0147] Figure 12 is a circuit diagram showing a sub-pixel according to another embodiment of the present disclosure. In this embodiment, Figure 3 Substantially identical components in the illustrated sub-pixels will be denoted by the same reference numerals, and detailed description will be omitted.

[0148] Reference Figure 12 , a sub-pixel may include a pixel circuit PXL, a sensing circuit SC and a pixel control circuit 50.

[0149] The pixel control circuit 50 can selectively disable the pixel circuit PXL according to the voltage level of the data voltage, allowing subpixels to be darkened. For example, in a subpixel to be darkened that was found to be defective during a pre-shipment inspection process, or in a subpixel to be darkened that was detected by the sensing circuit SC after product shipment, the pixel control circuit 50 can be turned on, thereby controlling the drive transistor DR to be in an off state. On the other hand, disabling the pixel control circuit 50 in a normal subpixel does not affect the driving of the normal subpixel.

[0150] The pixel control circuit 50 receives a strobe signal SCAN, a first neutral reference voltage Vnr1, a second neutral reference voltage Vnr2, and a pixel power supply voltage EVDD, and is connected to the data line DL. When a neutral voltage is applied to the data line DL, the pixel control circuit 50 turns on to apply the pixel power supply voltage EVDD to the cathode electrode of the light-emitting element LD. In this case, the cathode voltage of the light-emitting element LD rises to the pixel power supply voltage EVDD, which applies a reverse bias to the light-emitting element LD, resulting in no current flowing into the light-emitting element LD. As a result, the sub-pixel driven by the pixel control circuit 50 may become dark.

[0151] Figure 13 is a circuit diagram showing an example of a first-first sub-pixel and a first-second sub-pixel according to another embodiment of the present disclosure. Figure 12 The sub-pixels shown are substantially the same components and redundant descriptions will be omitted. Figure 13 In the example, the sensing circuit is omitted.

[0152] Reference Figure 13 Each of the first-first sub-pixel R1 and the first-second sub-pixel R2 includes a pixel circuit PXL and a pixel control circuit 50 .

[0153] The first light emitting element LD1 includes an anode electrode connected to the first-second node DTS1 and a cathode electrode connected to the first-fourth node n14. The second light emitting element LD2 includes an anode electrode connected to the second-second node DTS2 and a cathode electrode connected to the second-fourth node n24.

[0154] The pixel control circuit 50 of the first-first subpixel R1 may include first-third switching transistors M33, first-fourth switching transistors M34, first-fifth switching transistors M35, and first-second capacitors C12. The first-third switching transistors M33 and the first-fourth switching transistors M34 may be implemented as n-channel transistors, and the first-fifth switching transistors M35 may be implemented as p-channel transistors, but are not limited thereto.

[0155] When the first-third switching transistor M33 is turned on, the first data line DL1 is electrically connected to the first-third node n13. The first-third switching transistor M33 includes a first electrode connected to the first data line DL1, a gate electrode to which a gate signal SCAN is applied, and a second electrode connected to the first-third node n13.

[0156] The first-fourth switching transistor M34 is connected between the first-fourth node n14 and the first power line PL1, to which the pixel power supply voltage EVDD is applied, and can be turned on and off according to the voltage of the first-third node n13. The first-fourth switching transistor M34 can be turned on when a neutral voltage is applied to the first-third node n13 and turned off when a data voltage of pixel data is applied to the first-third node n13. The neutral voltage can be set to a voltage higher than the maximum voltage of the data voltage of pixel data. When the first-fourth switching transistor M34 is turned on, the cathode electrode of the first light-emitting element LD1 is electrically connected to the first power line PL1 through the first-fourth switching transistor M34. The first-fourth switching transistor M34 includes a first electrode connected to the first-fourth node n14, a first gate electrode to which the first neutral reference voltage Vnr1 is applied, a second gate electrode connected to the first-third node n13, and a second electrode connected to the first power line PL1. The first-second capacitor C12 is connected between the first-third node n13 and the first-fourth node n14.

[0157] The first-fifth switching transistor M35 can be connected between the first-fourth node n14 and the second power line PL2 and can be turned on / off depending on the voltage of the first-third node n13. The first-fifth switching transistor M35 can be turned off when a neutral voltage is applied to the first-third node n13 and turned on when a data voltage of pixel data is applied to the first-third node n13. When the first-fifth switching transistor M35 is turned on, the cathode electrode of the first light-emitting element LD1 can be electrically connected to the second power line PL2 via the first-fifth switching transistor M35. When the first-fifth switching transistor M35 is turned off, the cathode electrode of the first light-emitting element LD1 can be electrically connected to the first power line PL1 via the first-fourth switching transistor M34. The first-fifth switching transistor M35 includes a first electrode connected to the first-fourth node n14, a first gate electrode connected to the first-third node n13, a second gate electrode to which the second neutral reference voltage Vnr2 is applied, and a second electrode connected to the second power line PL2.

[0158] The pixel control circuit 50 of the first-second sub-pixel R2 may include second-third switching transistors M43, second-fourth switching transistors M44, second-fifth switching transistors M45, and second-second capacitors C22. The second-third switching transistors M43 and the second-fourth switching transistors M44 may be implemented as n-channel transistors, and the second-fifth switching transistors M45 may be implemented as p-channel transistors, but are not limited thereto.

[0159] The second-third switching transistor M43 includes a first electrode connected to the second data line DL2, a gate electrode to which the strobe signal SCAN is applied, and a second electrode connected to the second-third node n23. The second-fourth switching transistor M44 includes a first electrode connected to the second-fourth node n24, a first gate electrode to which the first neutral reference voltage Vnr1 is applied, a second gate electrode connected to the second-third node n23, and a second electrode connected to the first power line PL1. The second-second capacitor C22 is connected between the second-third node n23 and the second-fourth node n24.

[0160] The second-fifth switching transistor M45 includes a first electrode connected to the second-fourth node n24, a first gate electrode connected to the second-third node n23, a second gate electrode to which the second neutral reference voltage Vnr2 is applied, and a second electrode connected to the second power line PL2.

[0161] The first neutral reference voltage Vnr1 can be set to (but not limited to) a negative constant voltage (e.g., -5V), which allows the first to fourth switching transistors M34 and the second to fourth switching transistors M44 to maintain a cut-off state at a data voltage of 0V to 8V of pixel data applied to a normal sub-pixel, and allows the first to fourth switching transistors M34 and the second to fourth switching transistors M44 to be turned on at a neutral voltage of 11V applied to the sub-pixel to be dimmed.

[0162] The second neutral reference voltage Vnr2 can be set to (but not limited to) a positive constant voltage (for example, a voltage equal to or greater than 11V), which allows the first to fifth switching transistors M35 and the second to fifth switching transistors M45 to maintain a turned-on state at a data voltage of 0V to 8V of pixel data applied to a normal sub-pixel, and allows the first to fifth switching transistors M35 and the second to fifth switching transistors M45 to be turned off at a neutral voltage of 11V applied to the sub-pixel to be dimmed.

[0163] When the neutral voltage is applied to the first data line DL1, the first to third switching transistors M33 are turned on in response to the gate-on voltage VGH of the selection signal SCAN synchronized with the neutral voltage. Figure 14 As shown by the dashed lines, the first to fourth switching transistors M34 may be turned on because their threshold voltages decrease in response to the neutral voltage applied to the first to third node n13, and the first to fifth switching transistors M35 may be turned off. The first to fifth switching transistors M35 may be turned off because their threshold voltages decrease when a neutral voltage is applied. In this case, the cathode voltage of light-emitting element LD1 rises to the pixel power supply voltage EVDD, resulting in no current flowing into light-emitting element LD1. As a result, the first subpixel R1 may become a dark spot.

[0164] When the data voltage of the pixel data is applied to the second data line DL2, the second-third switching transistors M43 are turned on in response to the gate-on voltage VGH of the selection signal SCAN synchronized with the data voltage of the pixel data, while the second-fourth switching transistors M44 are kept off and the second-fifth switching transistors M45 are kept on. Therefore, the pixel control circuit 50 of the first-second sub-pixel R2 does not affect the driving of the pixel circuit PXL of the first-second sub-pixel R2, and thus, current can flow to the second light-emitting element LD2.

[0165] Figure 14 It shows Figure 13 FIG2 is a diagram showing the operating characteristics of the switching transistor in the pixel control circuit. Figure 14In FIG, the x-axis is the voltage applied to the first gate electrodes of the switching transistors M34, M35, M44, and M45, and the y-axis is the current flowing through the channels of the switching transistors M34, M35, M44, and M45. "Vdata" represents the reverse bias voltage applied to the second gate electrodes of the switching transistors M34, M35, M44, and M45.

[0166] Reference Figure 14 The threshold voltages of the first to fourth switching transistors M34 and the second to fourth switching transistors M44 may be shifted according to the reverse bias voltage applied to their second gate electrodes. For example, the neutral reference voltage Vnr1 applied as the reverse bias voltage may be set to, but not limited to, a constant voltage (e.g., -5V). This allows the first to fourth switching transistors M34 and the second to fourth switching transistors M34 to be non-conductive at a data voltage of 0V to 8V of the pixel data, and allows the first to fourth switching transistors M34 and the second to fourth switching transistors M34 to be conductive at a neutral voltage higher than the data voltage of the pixel data.

[0167] When the neutral voltage is applied to the second gate electrodes of the first-fourth switching transistors M34 and the second-fourth switching transistors M44, the threshold voltages of the first-fourth switching transistors M34 and the second-fourth switching transistors M44 are lowered to allow the first-fourth switching transistors M34 and the second-fourth switching transistors M44 to be turned on.

[0168] The threshold voltages of the first-fifth switching transistors M35 and the second-fifth switching transistors M45 can shift depending on the reverse bias voltage applied to their second gate electrodes. For example, the threshold voltages of the first-fifth switching transistors M35 and the second-fifth switching transistors M45 can be increased by the second neutral reference voltage Vnr2 applied as the reverse bias voltage. When a data voltage of 0V to 8V of pixel data is applied to their first gate electrodes, the first-fifth switching transistors M35 and the second-fifth switching transistors M45, whose threshold voltages are increased by the second neutral reference voltage Vnr2, remain in an on state. On the other hand, when a neutral voltage higher than the data voltage of the pixel data is applied to the first gate electrodes of the first-fifth switching transistors M35 and the second-fifth switching transistors M45, the threshold voltages of the first-fifth switching transistors M35 and the second-fifth switching transistors M45 can be decreased, thereby turning off the first-fifth switching transistors M35 and the second-fifth switching transistors M45.

[0169] According to one or more embodiments of the present disclosure, the display device can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic organizers, electronic books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation, vehicle navigation, in-vehicle display devices, in-vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, camcorders, and home appliances, etc. In addition, the display device according to one or more embodiments of the present disclosure can be applied to organic light-emitting devices or inorganic light-emitting devices.

[0170] The above-mentioned objects to be achieved by the present disclosure, means for achieving these objects, and effects of the present disclosure do not indicate essential features of the claims, and therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0171] Although the embodiments of the present disclosure are described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concepts of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concepts of the present disclosure. The scope of the technical concepts of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and do not limit the present disclosure.

[0172] CROSS-REFERENCE TO RELATED APPLICATIONS

[0173] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0018907, filed on February 7, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display panel, comprising: Multiple data lines; a plurality of gate lines, wherein the plurality of gate lines intersect the plurality of data lines; Multiple power cords; as well as a plurality of pixels, each of the plurality of pixels comprising a plurality of sub-pixels, Each of the plurality of sub-pixels comprises: a pixel circuit including a light-emitting element; and A pixel control circuit is connected to the pixel circuit, the pixel control circuit being configured to disable the pixel circuit according to a voltage from a data line connected to the pixel circuit among the plurality of data lines.

2. The display panel according to claim 1, wherein The plurality of sub-pixels included in each of the plurality of pixels include: sub-pixels of a first color, comprising a main first sub-pixel and an auxiliary first sub-pixel; sub-pixels of a second color, comprising a main second sub-pixel and an auxiliary second sub-pixel; and a sub-pixel of a third color, comprising a main third sub-pixel and an auxiliary third sub-pixel, Each of the main first sub-pixel, the auxiliary first sub-pixel, the main second sub-pixel, the auxiliary second sub-pixel, the main third sub-pixel and the auxiliary third sub-pixel includes a corresponding pixel circuit and a corresponding pixel control circuit.

3. The display panel according to claim 2, wherein: The pixel circuit of the main first sub-pixel includes: a first light-emitting element; a first driving transistor including a first electrode connected to a first power line of the plurality of power lines to which a pixel power voltage is applied, a gate electrode connected to a first node of the main first subpixel, and a second electrode connected to a second node of the main first subpixel; a first switching transistor of the main first sub-pixel, the first switching transistor being configured to electrically connect a first data line of the plurality of data lines to the first node of the main first sub-pixel in response to a gate signal; a second switching transistor of the main first sub-pixel, the second switching transistor configured to supply a reference voltage to the second node of the main first sub-pixel in response to the gate signal; and a first capacitor of the main first subpixel, the first capacitor being connected to the first node and the second node of the main first subpixel, The first light emitting element includes an anode electrode connected to the second node of the main first sub-pixel and a cathode electrode connected to a second power line applied with a ground voltage among the plurality of power lines. Wherein, the pixel circuit of the auxiliary first sub-pixel includes: a second light-emitting element; a second driving transistor including a first electrode connected to the first power line, a gate electrode connected to the first node of the auxiliary first subpixel, and a second electrode connected to the second node of the auxiliary first subpixel; a first switching transistor of the auxiliary first subpixel, the first switching transistor being configured to electrically connect a second data line of the plurality of data lines to the first node of the auxiliary first subpixel in response to the gate signal; a second switching transistor of the auxiliary first subpixel, the second switching transistor configured to supply the reference voltage to the second node of the auxiliary first subpixel in response to the gate signal; and a first capacitor of the auxiliary first subpixel, the first capacitor being connected to the first node and the second node of the auxiliary first subpixel, and The second light emitting element includes an anode electrode connected to the second node of the auxiliary first sub-pixel and a cathode electrode connected to the second power line.

4. The display panel according to claim 3, wherein: The first light emitting element emits light in response to a pixel driving voltage being applied to the first data line, and the second light emitting element emits light in response to the pixel driving voltage being applied to the second data line, The pixel control circuit of the primary first subpixel is configured to disable the pixel circuit of the primary first subpixel by electrically connecting the first node of the primary first subpixel to the second power line in response to a neutral voltage greater than a maximum possible voltage of the pixel driving voltage being applied to the first data line, and The pixel control circuit of the auxiliary first subpixel is configured to disable the pixel circuit of the auxiliary first subpixel by electrically connecting the first node of the auxiliary first subpixel to the second power line in response to the neutral voltage being applied to the second data line.

5. The display panel according to claim 3, further comprising: a neutral reference voltage line to which a neutral reference voltage is applied, Wherein, the pixel control circuit of the main first sub-pixel includes: a third switching transistor of the main first sub-pixel, the third switching transistor comprising a first electrode connected to the first data line, a gate electrode to which the gate signal is applied, and a second electrode connected to a third node of the main first sub-pixel; a fourth switching transistor of the main first subpixel, the fourth switching transistor including a first electrode connected to the first node of the main first subpixel, a first gate electrode connected to the neutral reference voltage line to which the neutral reference voltage is applied, a second gate electrode connected to the third node of the main first subpixel, and a second electrode connected to the second power line; and a second capacitor of the main first sub-pixel, the second capacitor being connected to the third node of the main first sub-pixel and the second power supply line, and Wherein, the pixel control circuit of the auxiliary first sub-pixel includes: a third switching transistor of the auxiliary first sub-pixel, the third switching transistor comprising a first electrode connected to the second data line, a gate electrode to which the gate signal is applied, and a second electrode connected to a third node of the auxiliary first sub-pixel; a fourth switching transistor of the auxiliary first subpixel, the fourth switching transistor including a first electrode connected to the first node of the auxiliary first subpixel, a first gate electrode connected to the neutral reference voltage line to which the neutral reference voltage is applied, a second gate electrode connected to the third node of the auxiliary first subpixel, and a second electrode connected to the second power line; and The second capacitor of the auxiliary first subpixel is connected to the third node of the auxiliary first subpixel and the second power line. The display panel according to claim 3 , wherein: The first light emitting element emits light in response to a pixel driving voltage being applied to the first data line, and the second light emitting element emits light in response to the pixel driving voltage being applied to the second data line, The pixel control circuit of the main first subpixel is configured to disable the pixel circuit of the main first subpixel by electrically connecting the cathode electrode of the first light emitting element to the first power line in response to a neutral voltage greater than a maximum possible voltage of the pixel driving voltage being applied to the first data line, and The pixel control circuit of the auxiliary first subpixel is configured to disable the pixel circuit of the auxiliary first subpixel by electrically connecting the cathode electrode of the second light emitting element to the first power line in response to the neutral voltage being applied to the second data line.

7. The display panel according to claim 3, wherein: The pixel control circuit of the main first sub-pixel includes: a third switching transistor of the main first sub-pixel, the third switching transistor comprising a first electrode connected to the first data line, a gate electrode to which the gate signal is applied, and a second electrode connected to a third node of the main first sub-pixel; a fourth switching transistor of the main first subpixel, the fourth switching transistor including a first electrode connected to the cathode electrode of the first light-emitting element, a first gate electrode to which a first neutral reference voltage is applied, a second gate electrode connected to the third node of the main first subpixel, and a second electrode connected to the first power line; a fifth switching transistor of the main first subpixel, the fifth switching transistor including a first electrode connected to the fourth node of the main first subpixel, a first gate electrode connected to the third node of the main first subpixel, a second gate electrode to which a second neutral reference voltage is applied, and a second electrode connected to a second power line of the plurality of power lines to which a ground voltage is applied; and a second capacitor of the main first subpixel, the second capacitor being connected to the third node and the fourth node of the main first subpixel, and Wherein, the pixel control circuit of the auxiliary first sub-pixel includes: a third switching transistor of the auxiliary first sub-pixel, the third switching transistor comprising a first electrode connected to the second data line, a gate electrode to which the gate signal is applied, and a second electrode connected to a third node of the auxiliary first sub-pixel; a fourth switching transistor of the auxiliary first subpixel, the fourth switching transistor comprising a first electrode connected to the cathode electrode of the second light-emitting element, a first gate electrode to which the first neutral reference voltage is applied, a second gate electrode connected to the third node of the auxiliary first subpixel, and a second electrode connected to the first power line; a fifth switching transistor of the auxiliary first subpixel, the fifth switching transistor including a first electrode connected to the fourth node of the auxiliary first subpixel, a first gate electrode connected to the third node of the auxiliary first subpixel, a second gate electrode to which the second neutral reference voltage is applied, and a second electrode connected to the second power line; and A second capacitor of the auxiliary first subpixel is connected to the third node and the fourth node of the auxiliary first subpixel.

8. The display panel according to claim 7, wherein: The first neutral reference voltage is a negative voltage, and the second neutral reference voltage is a positive voltage greater than the negative voltage, Each of the third and fourth switching transistors of the main first sub-pixel and the third and fourth switching transistors of the auxiliary first sub-pixel is an n-channel transistor, and Each of the fifth switching transistor of the main first subpixel and the fifth switching transistor of the auxiliary first subpixel is a p-channel transistor.

9. The display panel according to claim 3, wherein: The main first sub-pixel further includes a first sensing circuit connected to a sensing line to which the reference voltage is applied, the first sensing circuit being configured to sense an electrical characteristic of the first driving transistor, and The auxiliary first sub-pixel further includes a second sensing circuit connected to the sensing line, and the second sensing circuit is configured to sense an electrical characteristic of the second driving transistor.

10. A display device, comprising: A display panel comprising a plurality of data lines, a plurality of gate lines crossing the plurality of data lines, a plurality of power supply lines, and a plurality of pixels, each pixel comprising a plurality of sub-pixels; a data driver configured to output at least one of a pixel driving voltage and a neutral voltage to the plurality of data lines, the pixel driving voltage being used to drive the plurality of pixels to display an image, the neutral voltage being used to disable at least one of the plurality of sub-pixels; a gate driver configured to supply a gate signal to the plurality of gate lines, Each of the plurality of sub-pixels comprises: a pixel circuit connected to a corresponding data line among the plurality of data lines, the pixel circuit including a light emitting element; and A pixel control circuit is connected to the pixel circuit, the pixel control circuit being configured to disable the pixel circuit in response to the corresponding data line outputting the neutral voltage. The display device according to claim 10 , wherein: The plurality of sub-pixels included in each of the plurality of pixels include: sub-pixels of a first color, comprising a main first sub-pixel connected to a first data line and an auxiliary first sub-pixel connected to a second data line; sub-pixels of a second color, which include a main second sub-pixel connected to a third data line and an auxiliary second sub-pixel connected to a fourth data line; and a sub-pixel of a third color, which includes a main third sub-pixel connected to the fifth data line and an auxiliary third sub-pixel connected to the sixth data line, and Each of the main first sub-pixel, the auxiliary first sub-pixel, the main second sub-pixel, the auxiliary second sub-pixel, the main third sub-pixel and the auxiliary third sub-pixel includes a corresponding pixel circuit and a corresponding pixel control circuit.

12. The display device according to claim 11, wherein The main first sub-pixel includes: a first light-emitting element; and a first driving transistor configured to drive the first light emitting element; The auxiliary first sub-pixel includes: a second light-emitting element; and a second driving transistor configured to drive the second light emitting element, wherein the first light emitting element emits light in response to the pixel driving voltage being applied to the first data line, and the second light emitting element emits light in response to the pixel driving voltage being applied to the second data line, The pixel control circuit of the main first subpixel is configured to disable the pixel circuit of the main first subpixel in response to the neutral voltage being applied to the first data line, which is greater than the maximum possible voltage of the pixel driving voltage, and The pixel control circuit of the auxiliary first subpixel is configured to disable the pixel circuit of the auxiliary first subpixel in response to the neutral voltage being applied to the second data line.

13. The display device according to claim 12, wherein: The pixel control circuit of the main first sub-pixel is configured to disable the pixel circuit of the main first sub-pixel by supplying a ground voltage to the gate electrode of the first driving transistor in response to the neutral voltage being applied to the first data line, and the pixel control circuit of the auxiliary first sub-pixel is configured to disable the pixel circuit of the auxiliary first sub-pixel by supplying the ground voltage to the gate electrode of the second driving transistor in response to the neutral voltage being applied to the second data line.

14. The display device according to claim 12, wherein: The pixel control circuit of the main first sub-pixel is configured to disable the pixel circuit of the main first sub-pixel by supplying a pixel power supply voltage to the cathode electrode of the first light-emitting element in response to the neutral voltage being applied to the first data line, and the pixel control circuit of the auxiliary first sub-pixel is configured to disable the pixel circuit of the auxiliary first sub-pixel by supplying the pixel power supply voltage to the cathode electrode of the second light-emitting element in response to the neutral voltage being applied to the second data line.

15. The display device according to claim 10, further comprising: a sensing circuit connected to a driving transistor provided in each of the plurality of sub-pixels and configured to sense an electrical characteristic of the driving transistor of each of the plurality of sub-pixels; as well as a memory configured to store sensing data obtained from the sensing circuit, In response to the sensing data being greater than an overflow value of a normal driving range of the sub-pixel and / or less than an underflow value of the normal driving range of the sub-pixel, neutral data is stored in the memory.

16. A display device, comprising: A display panel comprising a plurality of data lines, a plurality of gate lines crossing the plurality of data lines, a plurality of power supply lines, and a plurality of pixels, each pixel comprising a plurality of sub-pixels; a data driver configured to output at least one of a pixel driving voltage and a neutral voltage to the plurality of data lines, the pixel driving voltage being used to drive the plurality of pixels to display an image, the neutral voltage being used to disable at least one of the plurality of sub-pixels; a gate driver configured to supply a gate signal to the plurality of gate lines, The sub-pixels in the plurality of sub-pixels include: a pixel circuit connected to a corresponding data line among the plurality of data lines, the pixel circuit including a driving transistor and a light emitting element connected to the driving transistor; and A pixel control circuit is connected to the pixel circuit, the pixel control circuit being configured to disable one of the driving transistor or the light emitting element in response to the corresponding data line outputting the neutral voltage.

17. The display device according to claim 16, wherein: The light emitting element emits light in response to the pixel driving voltage being applied to the corresponding data line.

18. The display device according to claim 16, wherein: The neutral voltage is greater than a maximum possible voltage of the pixel driving voltage.

19. The display device according to claim 16, wherein: The pixel control circuit is configured to disable the drive transistor by supplying a ground voltage to a gate electrode of the drive transistor in response to the neutral voltage being applied to the corresponding data line.

20. The display device according to claim 16, wherein The pixel control circuit is configured to disable the light emitting element by supplying a pixel power supply voltage supplied to the driving transistor to a cathode electrode of the light emitting element in response to the neutral voltage being applied to the corresponding data line.

21. The display device according to claim 16, wherein The plurality of sub-pixels included in each of the plurality of pixels include: sub-pixels of a first color, comprising a main first sub-pixel connected to a first data line among the plurality of data lines and an auxiliary first sub-pixel connected to a second data line among the plurality of data lines; sub-pixels of a second color, comprising a main second sub-pixel connected to a third data line among the plurality of data lines and an auxiliary second sub-pixel connected to a fourth data line among the plurality of data lines; and The sub-pixels of a third color include a main third sub-pixel connected to a fifth data line among the plurality of data lines and an auxiliary third sub-pixel connected to a sixth data line among the plurality of data lines.

Images