Display driver integrated circuit and display device

Abstract

The invention relates to a display driver integrated circuit and a display device. The display driver integrated circuit includes a first memory, a compensator, a sampler, and a data processor. The first memory stores accumulated stress data. The compensator generates output data for image display by compensating the input image data based on the accumulated stress data. The sampler selects slice data. The data processor: generates current slice accumulation data of the current slice accumulation data set by adding the selected slice data and previous slice accumulation data of the previous slice accumulation data set; selecting the maximum value as the current maximum value; determining whether the current slice accumulation data is abnormal based on comparing a previous maximum value of the previous slice accumulation data set with the current maximum value; and selectively updating a previous slice accumulation data set by selectively storing the current slice accumulation data set in the first memory based on the determination.

Description

Technical Field

[0001] Embodiments generally relate to semiconductor integrated circuits, and more particularly, to a display driver integrated circuit for driving a display panel and a display device including the display driver integrated circuit. Background Art

[0002] With the development of information technology, display devices have become important for providing information to users. Various display devices such as liquid crystal displays ("LCDs"), plasma displays, and electroluminescent displays have gained popularity. Among these display devices, electroluminescent displays use light-emitting diodes ("LEDs") or organic light-emitting diodes ("OLEDs") that emit light through the recombination of electrons and holes and have a fast response speed and reduced power consumption.

[0003] Electroluminescent displays offer advantages such as fast response and low power consumption. Typical OLED display devices use a drive transistor in a corresponding pixel to supply current corresponding to a data signal, generating light through the OLED in the corresponding pixel. Thus, an electroluminescent display device uses current to display an image. However, the drive transistor and OLED degrade over time, and various technologies have been developed to mitigate this degradation. Summary of the Invention

[0004] Some embodiments provide a display driver integrated circuit capable of ensuring the integrity of accumulated stress data while performing image sticking compensation.

[0005] Some embodiments provide a display device including a display driver integrated circuit capable of ensuring integrity of accumulated stress data while performing image sticking compensation.

[0006] In an embodiment of the present disclosure, a display driver integrated circuit is used to drive a display panel including a plurality of pixels, and the display driver integrated circuit includes a first memory, a compensator, a sampler, and a data processor. The first memory stores accumulated stress data for compensating for degradation of the plurality of pixels. The compensator generates output data for image display by compensating input image data based on the accumulated stress data. The sampler selects slice data from each of a plurality of frames of input image data in slice units based on a clock signal. The data processor generates current slice accumulated data of a current slice accumulated data set associated with a selected frame by adding the selected slice data to previous slice accumulated data of a previous slice accumulated data set associated with a frame selected from the plurality of frames; selects a maximum value as a current maximum value from degradation values of pixels included in the current slice accumulated data; determines whether the current slice accumulated data is abnormal based on comparing the previous maximum value of the previous slice accumulated data set with the current maximum value; and selectively updates the previous slice accumulated data set by selectively storing the current slice accumulated data set in the first memory based on the determination of whether the current slice accumulated data is abnormal.

[0007] In an embodiment, the slice unit includes at least one pixel row from among a plurality of pixels or at least one pixel column from among a plurality of pixels.

[0008] In an embodiment, the data processor includes an accumulator, a maximum value generator, a maximum value checker, a checksum generator, and an interrupt signal generator. The accumulator generates current slice cumulative data by adding selected slice data to previous slice cumulative data. The maximum value generator selects a maximum value from the degradation values of the pixels included in the current slice cumulative data as the current maximum value. The maximum value checker generates a difference between the current maximum value and the previous maximum value, compares the difference with a reference value, and generates a check signal indicating whether the current slice cumulative data is abnormal based on the comparison of the difference with the reference value. The checksum generator generates a current checksum of the current slice cumulative data set by performing a cyclic redundancy check ("CRC") operation on the degradation values of the pixels included in the current slice cumulative data. The interrupt signal generator generates an interrupt signal that is activated when the current maximum value is abnormal based on the check signal.

[0009] In an embodiment, the maximum value checker outputs a check signal having a first logic level in response to the difference being equal to or less than a reference value. The checksum generator performs a CRC operation in response to the check signal having the first logic level.

[0010] In an embodiment, the maximum value checker outputs a check signal having a second logic level different from the first logic level in response to the difference being greater than the reference value. The checksum generator suspends the CRC operation in response to the check signal having the second logic level.

[0011] In an embodiment, the maximum value checker includes a difference value generator and a comparator. The difference value generator generates a difference value by subtracting the previous maximum value from the current maximum value. The comparator generates a check signal by comparing the difference value with a reference value, and determines the logic level of the check signal based on the result of the comparison between the difference value and the reference value.

[0012] In one embodiment, the display driver integrated circuit further includes a second memory. When the display driver integrated circuit is powered on, accumulated stress data is loaded from a third memory external to the display driver integrated circuit and stored in the first memory. The sampler provides a target address associated with selected slice data to the first memory, and the first memory provides a previously sliced accumulated data set to the second memory in response to the target address.

[0013] In an embodiment, the second memory provides the data processor with a previous slice cumulative data set, and the second memory provides the first memory with a current slice cumulative data set provided to the data processor.

[0014] In an embodiment, the data processor provides the second memory with an interrupt signal indicating whether the current maximum value is abnormal, and the second memory suspends (ie, stops) operation in response to the interrupt signal indicating that the current maximum value is abnormal.

[0015] In an embodiment, the display driver integrated circuit further includes an error detector. The error detector determines whether the accumulated stress data loaded from the third memory is abnormal based on a maximum value and a checksum among the accumulated stress data loaded from the third memory, and provides an interrupt signal to the second memory indicating whether the accumulated stress data is abnormal.

[0016] In an embodiment, the second memory suspends operation in response to an interrupt signal indicating that the current maximum value is abnormal.

[0017] In an embodiment, the display driver integrated circuit further includes a memory interface that provides the first memory with the accumulated stress data loaded from the third memory and performs a backup operation of storing the accumulated stress data stored in the first memory in the third memory at predetermined intervals.

[0018] In an embodiment, the first memory is a non-volatile memory device, and each of the second memory and the third memory is a volatile memory device.

[0019] In one embodiment, the display driver integrated circuit further includes a second memory, encoding / decoding logic, and decoding logic. The encoding / decoding logic encodes the current slice cumulative data set provided by the data processor and provides the encoded current slice cumulative data set to the second memory; and decodes the encoded previous slice cumulative data set provided by the first memory and provides the previous slice cumulative data set to the second memory. The decoding logic decodes the encoded cumulative stress data and provides the cumulative stress data to the compensator.

[0020] In one embodiment, when the display driver integrated circuit is powered on, the encoded cumulative stress data is loaded from a third memory disposed external to the display driver integrated circuit and stored in the first memory. The sampler provides a target address associated with the selected slice data to the first memory, and the first memory provides the encoded previous slice cumulative data set to the encoding / decoding logic in response to the target address.

[0021] In an embodiment, the data processor provides the second memory with an interrupt signal indicating whether the current maximum value is abnormal, and the second memory suspends operation in response to the interrupt signal indicating that the current maximum value is abnormal.

[0022] In an embodiment of the present disclosure, a display device includes a display panel including a plurality of pixels and a display driver integrated circuit that drives the display panel. The display driver integrated circuit includes a first memory, a compensator, a sampler, and a data processor. The first memory stores accumulated stress data for compensating for degradation of the plurality of pixels. The compensator generates output data for image display by compensating input image data based on the accumulated stress data. The sampler selects slice data from each of a plurality of frames of the input image data in slice units based on a clock signal. The data processor generates current slice accumulated data of a current slice accumulated data set associated with a selected frame by adding the selected slice data to previous slice accumulated data of a previous slice accumulated data set associated with a frame selected from the plurality of frames; selects a maximum value as a current maximum value from degradation values of pixels included in the current slice accumulated data; determines whether the current slice accumulated data is abnormal based on comparing the previous maximum value of the previous slice accumulated data set with the current maximum value; and selectively updates the previous slice accumulated data set by selectively storing the current slice accumulated data set in the first memory based on the determination of whether the current slice accumulated data is abnormal.

[0023] In an embodiment, the slice unit includes at least one pixel row from among a plurality of pixels or at least one pixel column from among a plurality of pixels.

[0024] In an embodiment, a data processor includes an accumulator, a maximum value generator, a maximum value checker, a checksum generator, and an interrupt signal generator. The accumulator generates current slice cumulative data by adding selected slice data to previous slice cumulative data. The maximum value generator selects the maximum value from the degradation values of the pixels included in the current slice cumulative data as the current maximum value. The maximum value checker generates the difference between the current maximum value and the previous maximum value, compares the difference with a reference value, and generates a check signal indicating whether the current slice cumulative data is abnormal based on the comparison of the difference with the reference value. The checksum generator generates a current checksum of the current slice cumulative data set by performing a CRC operation on the degradation values of the pixels included in the current slice cumulative data. The interrupt signal generator generates an interrupt signal based on the check signal that is activated when the current maximum value is abnormal.

[0025] In an embodiment, the display driver integrated circuit further includes a second memory, an error detector, and encoding / decoding logic, the encoding / decoding logic providing an encoded current slice cumulative data set to the second memory by encoding the current slice cumulative data set provided from the data processor, and the encoding / decoding logic providing a previous slice cumulative data set to the second memory by decoding the encoded previous slice cumulative data set provided from the first memory.

[0026] The sampler provides a target address associated with the selected slice data to the first memory. The first memory provides an encoded previous slice cumulative data set to the encoding / decoding logic in response to the target address. The second memory provides the previous slice cumulative data set to the data processor, and the second memory provides the current slice cumulative data set provided to the first memory. The data processor provides a first interrupt signal to the second memory indicating whether the current maximum value is abnormal, and the second memory suspends operation in response to the first interrupt signal indicating the current maximum value is abnormal. The error detector determines whether the accumulated stress data loaded from the third memory is abnormal based on the maximum value and the checksum in the accumulated stress data loaded from the third memory, and the error detector provides a second interrupt signal to the second memory indicating whether the accumulated stress data is abnormal. When the display driver integrated circuit is powered on, the accumulated stress data is loaded from the third memory provided outside the display driver integrated circuit and stored in the first memory.

[0027] Therefore, when a defect occurs in the encoded accumulated stress data stored in the first memory, the display driver integrated circuit verifies the integrity of the accumulated stress data based on a change in the maximum value of the slice data, and can suspend updating the slice accumulated data in the first memory or suspend a backup operation of storing the accumulated stress data in the third memory. The accumulated stress data is then loaded from the third memory, and the display driver integrated circuit can perform accumulation and compensation operations based on the normal slice accumulated data. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Exemplary, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a block diagram illustrating an embodiment of an organic light emitting diode ("OLED") display device including a display driver integrated circuit.

[0030] Figure 2 yes Figure 1 A plan view of an embodiment of an OLED display device.

[0031] Figure 3 Show Figure 1 The connection of pixels in an OLED display device.

[0032] Figure 4 It shows Figure 3 A circuit diagram of an embodiment of a pixel.

[0033] Figure 5 It shows Figure 1 A block diagram of an embodiment of a compensation circuit in a display driver integrated circuit is provided.

[0034] Figure 6 Show Figure 5 An embodiment of the previous slice accumulated dataset and the current slice accumulated dataset in.

[0035] Figure 7 Show Figure 6 An embodiment in which a sampler selects slice data from a plurality of frames.

[0036] Figure 8 Show Figure 6 An embodiment in which a sampler selects slice data from a plurality of frames.

[0037] Figure 9 Show Figure 5 A compensation circuit in a first memory embodiment.

[0038] Figure 10 It shows Figure 5A block diagram of an embodiment of a compensation circuit in a data processor.

[0039] Figure 11 It shows Figure 10 Block diagram of an embodiment of a maximum value checker in .

[0040] Figure 12 An embodiment of slicing an accumulated data set is shown.

[0041] Figure 13 It shows Figure 1 A block diagram of an embodiment of a compensation circuit in a display driver integrated circuit is provided.

[0042] Figure 14 is a flowchart illustrating an embodiment of a method of driving a display device.

[0043] Figure 15 is a block diagram illustrating an embodiment of a display system.

[0044] Figure 16 is a block diagram illustrating an embodiment of an electronic device including an OLED display device.

[0045] Figure 17 It shows Figure 16 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0046] Embodiments are described more fully hereinafter with reference to the accompanying drawings.The same or similar reference numerals refer to the same or similar elements throughout.

[0047] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be present between the element and the other element. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements.

[0048] It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings herein, the "first element," "first component," "first region," "first layer," or "first part" discussed below may be named "second element," "second component," "second region," "second layer," or "second part."

[0049] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "one (kind / one)" and "the" are intended to include plural forms, including "at least one (kind / one)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more relevant listed items. It will also be understood that when used in this specification, the term "comprises and / or comprising" or "includes and / or including" indicates the presence of stated features, regions, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or groups thereof.

[0050] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to encompass different orientations of a device in addition to the orientation depicted in the accompanying drawings. For example, if the device in a drawing is turned over, an element described as being "below" the other elements will subsequently be oriented as being "above" the other elements. Thus, depending on the specific orientation of the drawing, the exemplary term "lower" can encompass both "lower" and "above" orientations. Similarly, if the device in a drawing is turned over, an element described as being "below" or "beneath" the other elements will subsequently be oriented as being "above" the other elements. Thus, the exemplary terms "below" or "below" can encompass both "above" and "below" orientations.

[0051] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, a term such as "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0052] As used herein, the terms "compensator," "sampler," "processor," "accumulator," "maximum value generator," "maximum value checker," "checksum generator," "interrupt signal generator," "difference value generator," "comparator," "error detector," "memory interface," or "logic" are intended to refer to a hardware component, such as a circuit, that performs a predetermined function. For example, the hardware component may include a field programmable gate array ("FPGA") or an application specific integrated circuit ("ASIC").

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0054] Figure 1 is a block diagram illustrating an embodiment of an OLED display device including a display driver integrated circuit.

[0055] Reference Figure 1 , the display device 100 may include a display driver integrated circuit 105 , a display panel 110 , and a power supply 180 .

[0056] The display driver integrated circuit 105 may include a timing controller 130, a data driver 150, a scan driver 160, and an emission driver 170, and the timing controller 130 may include a compensation circuit 300. The timing controller 130 may be connected to a nonvolatile memory device 200 provided outside the display driver integrated circuit 105.

[0057] The timing controller 130 , the data driver 150 , the scan driver 160 , and the emission driver 170 may be coupled to the display panel 110 through a chip on flexible printed circuit (“COF”), a chip on glass (“COG”), a flexible printed circuit (“FPC”), or the like.

[0058] The display panel 110 may be coupled to the scan driver 160 of the display driver integrated circuit 105 via a plurality of scan line sets SLS1-SLSn (n is an integer greater than three), may be coupled to the data driver 150 of the display driver integrated circuit 105 via a plurality of data lines DL1-DLm (m is an integer greater than three), and may be coupled to the emission driver 170 of the display driver integrated circuit 105 via a plurality of emission control lines EL1-ELn. The display panel 110 may include a plurality of pixels PX, and each pixel PX is provided at an intersection of each of the scan line sets SLS1-SLSn, each of the data lines DL1-DLm, and each of the emission control lines EL1-ELn.

[0059] The plurality of pixels PX may be grouped into a plurality of blocks BLK, and each of the plurality of blocks BLK may include at least one pixel row or at least one pixel column.

[0060] The power supply 180 may provide a higher power voltage ELVDD, a lower power voltage ELVSS, and an initialization voltage VINT to the display panel 110. The power supply 180 may provide a first voltage VGL and a second voltage VGH to the emission driver 170 and the scan driver 160.

[0061] The scan driver 160 can apply a plurality of scan signals to each of the pixels PX via the scan line sets SLS1-SLSn based on the second drive control signal SCTL. The scan driver 160 can activate at least two of the plurality of scan signals during a non-emission interval in which the pixels PX do not emit light, such that the scan signals partially overlap during two consecutive horizontal periods. The horizontal period can correspond to a period in which the data driver 150 supplies a data voltage to a pixel row. The horizontal period can also correspond to a period of a horizontal synchronization signal used in the timing controller 130.

[0062] The data driver 150 may apply a data voltage to each of the pixels PX through the plurality of data lines DL1 -DLm based on a first driving control signal DCTL.

[0063] The emission driver 170 may apply an emission control signal to each of the pixels PX through the plurality of emission control lines EL1-ELn based on the third driving control signal ECTL. The brightness of the display panel 110 may be adjusted based on the emission control signal.

[0064] The power supply 180 can provide a relatively high power voltage ELVDD, a lower power voltage ELVSS, and an initialization voltage VINT to the display panel 110 in response to the power control signal PCTL, and can provide a first voltage VGL and a second voltage VGH to the emission driver 170 and the scan driver 160 in response to the power control signal PCTL.

[0065] The timing controller 130 may receive input image data IMG, a control signal CTL, and a clock signal CLK, and may generate a first drive control signal DCTL, a second drive control signal SCTL, and a third drive control signal ECTL, as well as a power control signal PCTL based on the control signal CTL. The timing controller 130 may provide the first drive control signal DCTL to the data driver 150, the second drive control signal SCTL to the scan driver 160, the third drive control signal ECTL to the emission driver 170, and the power control signal PCTL to the power supply 180.

[0066] The compensation circuit 300 may store accumulated stress data ASD loaded from the nonvolatile memory device 200 when the display driver integrated circuit 105 is powered on, may generate output data DTA by compensating input image data IMG based on the accumulated stress data ASD, and may provide the output data DTA to the data driver 150 .

[0067] Due to the degradation (i.e., deterioration) of multiple pixels PX, a phenomenon called image sticking occurs, where the primary image is permanently formed on the screen, leading to a fatal problem in image quality. Technologies for compensating for the degradation of multiple pixels PX can be roughly divided into two approaches. One is to detect and compensate for the amount of degradation by using a separate circuit to sense the electrical characteristics of multiple pixels PX, and the other is to predict the amount of degradation (e.g., the amount of use) using an input image and then predict and compensate for the total amount of degradation by accumulating the degradation. The first approach (e.g., the sensing approach) may have the disadvantage of requiring a separate circuit for sensing the electrical characteristics and requiring a separate sensing operation. The second approach (e.g., the accumulation compensation approach) can be widely used in mobile devices because it does not require a separate sensing circuit and a separate sensing operation, and compensation is performed in real time without requiring additional operations. In embodiments, the compensation circuit 300 included in the display driver integrated circuit 105 of the display device 100 can be implemented based on the second approach (e.g., the accumulation compensation approach).

[0068] The compensation circuit 300 may: select slice data in slice units from each of a plurality of frames of the input image data IMG based on a clock signal CLK; generate current slice accumulation data of a current slice accumulation data set associated with the selected frame by adding the selected slice data and previous slice accumulation data of a previous slice accumulation data set associated with the frame selected from the plurality of frames; select a maximum value as a current maximum value from among degradation values of pixels included in the current slice accumulation data; determine whether the current slice accumulation data is abnormal based on comparing the previous maximum value of the previous slice accumulation data set with the current maximum value; selectively update the previous slice accumulation data set by selectively storing the current slice accumulation data set in a first memory based on the determination; and may perform a backup operation of storing the accumulated stress data ASD in the non-volatile memory device 200.

[0069] The nonvolatile memory device 200 may also be referred to as a third memory 200 .

[0070] In some embodiments, at least some of the multiple elements included in the display driver integrated circuit 105 may be provided (e.g., directly provided (e.g., mounted)) on the display panel 110, or may be connected to the display panel 110 in a tape carrier package ("TCP") type. In alternative embodiments, at least some of the multiple elements included in the display driver integrated circuit 105 may be integrated into the display panel 110. In some embodiments, the elements included in the display driver integrated circuit 105 may be implemented using separate circuits / modules / chips. In other embodiments, based on their functions, some of the multiple elements included in the display driver integrated circuit 105 may be combined into one circuit / module / chip, or may be further separated into multiple circuits / modules / chips.

[0071] Figure 2 yes Figure 1 A plan view of an embodiment of an OLED display device.

[0072] Reference Figure 2 , the display device 100 may include a substrate 10. The substrate 10 may include a display area DA and a peripheral area PA outside the display area DA.

[0073] A plurality of pixels PX may be arranged in the display area DA of the substrate 10. Various wirings for transmitting electrical signals to be applied to the display driver integrated circuit 105 and the display area DA may be in the peripheral area PA of the substrate 10. When the area occupied by the display driver integrated circuit 105 in the display area DA is reduced, unused space in the substrate 10 may be reduced.

[0074] Figure 3 Show Figure 1 The connection of pixels in an OLED display device.

[0075] Figure 4 It shows Figure 3 A circuit diagram of an embodiment of a pixel.

[0076] exist Figure 3 and Figure 4 In the embodiment, the pixel PX is coupled to a first scan line set SLS1, a first data line DL1 and a first emission control line EL1.

[0077] Reference Figure 3 and Figure 4 , the first scan line set SLS1 includes a first scan line SL11, a second scan line SL21 and a third scan line SL31.

[0078] The pixel PX may include a pixel circuit 112 and an organic light emitting diode ("OLED") 113. The pixel circuit 112 may include a switching transistor T1, a driving transistor T2, a compensation transistor T3, a first initialization transistor T4, a second initialization transistor T7, a first emission transistor T5, a second emission transistor T6, and a storage capacitor CST.

[0079] The switching transistor T1 may include a P-channel metal oxide semiconductor ("PMOS") transistor having a first electrode coupled to the data line DL1 to receive the data voltage SDT, a gate electrode coupled to the second scan line SL21 to receive the second scan signal GW1, and a second electrode coupled to the first node N11. The driving transistor T2 may include a PMOS transistor having a first electrode coupled to the first node N11, a gate electrode coupled to the second node N12, and a second electrode coupled to the third node N13.

[0080] The compensation transistor T3 may include a PMOS transistor having a gate electrode coupled to the second scan line SL21 to receive the second scan signal GW1, a first electrode coupled to the second node N12, and a second electrode coupled to the third node N13. The first initialization transistor T4 may include a PMOS transistor having a gate electrode coupled to the first scan line SL11 to receive the first scan signal GI1, a first electrode coupled to the second node N12, and a second electrode receiving the initialization voltage VINT.

[0081] The first emission transistor T5 may include a PMOS transistor having a first electrode coupled to a relatively high power supply voltage ELVDD, a second electrode coupled to a first node N11, and a gate electrode coupled to a first emission control line EL1 to receive a first emission control signal EC1. The second emission transistor T6 may include a PMOS transistor having a first electrode coupled to a third node N13, a second electrode coupled to a fourth node N14, and a gate electrode coupled to the first emission control line EL1 to receive the first emission control signal EC1.

[0082] The second initialization transistor T7 may include a PMOS transistor having a gate electrode coupled to the third scan line SL31 to receive the third scan signal GB1 , a first electrode receiving the initialization voltage VINT, and a second electrode coupled to the fourth node N14 .

[0083] The storage capacitor CST may have a first terminal coupled to the relatively high power voltage ELVDD and a second terminal coupled to the second node N12. The OLED 113 may have an anode coupled to the fourth node N14 and a cathode coupled to the relatively low power voltage ELVSS.

[0084] The switching transistor T1 transfers the data voltage SDT to the storage capacitor CST in response to the second scan signal GW1 , and the OLED 113 may emit light in response to the data voltage SDT stored in the storage capacitor CST to display an image.

[0085] The emission transistors T5 and T6 are turned on or off in response to the first emission control signal EC1 to supply current to the OLED 113 or intercept current from the OLED 113. When current is intercepted from the OLED 113, the OLED 113 does not emit light. Therefore, the emission transistors T5 and T6 are turned on or off in response to the first emission control signal EC1 to adjust the brightness of the display panel 110.

[0086] The compensation transistor T3 can connect the second node N12 and the third node N13 in response to the second scan signal GW1. That is, when an image is displayed by diode-connecting the gate electrode and the second electrode of the driving transistor T2, the compensation transistor T3 can compensate for the variation in the threshold voltage of each driving transistor of each pixel PX.

[0087] The first initialization transistor T4 may transmit a first initialization voltage VINT to the second node N12 in response to the first scan signal GI1. The first initialization transistor T4 may initialize the data voltage transmitted to the driving transistor T2 during the previous frame by transmitting the initialization voltage VINT to the gate electrode of the driving transistor T2.

[0088] The second initialization transistor T7 may transmit the initialization voltage VINT to the fourth node N14 in response to the third scan signal GB1 to discharge the parasitic capacitance between the second emission transistor T6 and the OLED 113 .

[0089] Figure 5 It shows Figure 1 A block diagram of an embodiment of a compensation circuit in a display driver integrated circuit is provided, and Figure 6 Show Figure 5 An embodiment of the previous slice accumulated dataset and the current slice accumulated dataset in.

[0090] Reference Figure 6The previous slice accumulation dataset SLADS_P may include the previous slice accumulation data SLAD_P, the previous maximum value MAX_P, and the previous checksum CS_P. The previous slice accumulation data SLAD_P may include degradation values of pixels included in the selected slice data. The previous maximum value MAX_P may indicate the maximum value among the degradation values in the previous slice accumulation data SLAD_P. The previous checksum CS_P may be generated based on the degradation values in the previous slice accumulation data SLAD_P. In addition, the current slice accumulation dataset (i.e., the current slice accumulation dataset) SLADS_C may include the current slice accumulation data (i.e., the current slice accumulation data) SLAD_C, the current maximum value (i.e., the current maximum value) MAX_C, and the current checksum (i.e., the current checksum) CS_C. The current slice accumulation data SLAD_C may include degradation values of pixels included in the selected slice data. The current maximum value MAX_C may indicate the maximum value among the degradation values in the current slice accumulation data SLAD_C. The current checksum CS_C may be generated based on the degradation values in the current slice accumulation data SLAD_C.

[0091] Return to reference Figure 5 , the compensation circuit 300 may include a cumulative stress memory (i.e., a first memory) 310, a compensator 340, a sampler 350, a data processor 400, a static random access memory (“SRAM”) (i.e., a second memory) 360, an error detector 370, and a memory interface 380.

[0092] Reference Figure 5 and Figure 1 When the display driver integrated circuit 105 is powered on, the memory interface 380 can provide the first memory 310 with Figure 1 The accumulated stress data ASD loaded from the third memory 200 in the first memory 310 may be stored, and a backup operation of storing the accumulated stress data ASD stored in the first memory 310 in the third memory 200 at a predetermined cycle may be performed.

[0093] The first memory 310 may store the accumulated stress data ASD loaded from the third memory 200 and may provide the accumulated stress data ASD to the compensator 340 .

[0094] The compensator 340 may generate output data DTA for image display by compensating the input image data IMG based on the accumulated stress data ASD associated with compensating for degradation of the plurality of pixels. The compensator 340 may compensate the input image data IMG based on image sticking compensation ("ISC").

[0095] In degradation compensation techniques (e.g., ISC), stress data (stress profile or accumulated data) may be generated by accumulating driving time and / or grayscale values for each pixel, compensation data may be generated based on a predetermined life curve and the stress data, and the voltage value may be compensated based on the generated compensation data. The predetermined life curve indicates the degree of degradation according to the passage of time, and the compensation data may be stored in the compensator 340 together with the stress data in the form of a separate lookup table.

[0096] The sampler 350 may select slice data in slice units from each of a plurality of frames of the input image data IMG based on the clock signal CLK, and may provide the selected slice data SSLD to the data processor 400. In addition, the sampler 350 may provide the first memory 310 with a target address TG_ADDR associated with the selected slice data SSLD.

[0097] The first memory 310 may provide the previous slice accumulated data set SLADS_P to the second memory 360 in response to the target address TG_ADDR, and the second memory 360 may provide the previous slice accumulated data set SLADS_P to the data processor 400 .

[0098] Reference Figure 5 and Figure 6 , the data processor 400: can generate current slice accumulation data SLAD_C of the current slice accumulation data set SLADS_C associated with the selected frame by adding the selected slice data SSLD and the previous slice accumulation data SLAD_P of the previous slice accumulation data set SLADS_P associated with the frame selected from the multiple frames; can select a maximum value as the current maximum value MAX_C from among the degradation values of the pixels included in the current slice accumulation data SLAD_C; can determine whether the current slice accumulation data SLAD_C is abnormal based on comparing the previous maximum value MAX_P of the previous slice accumulation data set SLADS_P with the current maximum value MAX_C; and can selectively update the previous slice accumulation data set SLADS_P by selectively storing the current slice accumulation data set SLADS_C in the first memory 310 based on the determination.

[0099] The data processor 400 may provide the current slice accumulation dataset SLADS_C to the second memory 360. When the current maximum value MAX_C of the current slice accumulation dataset SLADS_C is normal, the second memory 360 may update the previous slice accumulation dataset SLADS_P stored in the first memory 310 with the current slice accumulation dataset SLADS_C by providing the current slice accumulation dataset SLADS_C to the first memory 310.

[0100] The data processor 400 may selectively suspend operations of the second memory 360 and the memory interface 380 by providing the second memory 360 and the memory interface 380 with a first interrupt signal ITR1 indicating whether the current maximum value MAX_C of the current slice accumulation data set SLADS_C is abnormal.

[0101] The second memory 360 may provide the current slice accumulation data set SLADS_C to the first memory 310 in response to the first interrupt signal ITR1 indicating that the current maximum value MAX_C is normal. The second memory 360 may suspend (i.e., stop) operation in response to the first interrupt signal ITR1 indicating that the current maximum value MAX_C is abnormal, and not provide the current slice accumulation data set SLADS_C to the first memory 310.

[0102] In response to the first interrupt signal ITR1 indicating that the current maximum value MAX_C is normal, the memory interface 380 may perform a backup operation of storing the accumulated stress data ASD stored in the first memory 310 in the third memory 200 at a predetermined cycle.

[0103] In response to the first interrupt signal ITR1 indicating that the current maximum value MAX_C is abnormal, the memory interface 380 may skip a backup operation of storing the accumulated stress data ASD stored in the first memory 310 in the third memory 200 .

[0104] Reference Figure 5 、 Figure 6 and Figure 1 When the display driver integrated circuit 105 is powered on, the error detector 370 may determine whether the accumulated stress data ASD loaded from the third memory 200 is abnormal based on the maximum value and the checksum among the accumulated stress data ASD loaded from the third memory 200, and may provide the second memory 360 with a second interrupt signal ITR2 indicating whether the accumulated stress data ASD is abnormal.

[0105] The second memory 360 may suspend operation in response to the second interrupt signal ITR2 indicating that the accumulated stress data ASD is abnormal.

[0106] Therefore, when a defect occurs in the accumulated stress data ASD stored in the first memory 310 due to electrostatic discharge ("ESD"), a memory access failure, a hardware failure, etc., the data processor 400 can verify the integrity of the accumulated stress data ASD based on a change in the maximum value of the slice data selected from the accumulated stress data ASD, and can suspend updating the slice accumulated data in the first memory 310 or suspend the backup operation of storing the accumulated stress data ASD in the third memory 200 when it is determined that the accumulated stress data ASD is abnormal (i.e., a defect occurs in the accumulated stress data ASD). When the accumulated stress data ASD is determined to be abnormal, after the display device 100 is powered off and then powered on, the accumulated stress data ASD is loaded from the third memory 200 to the first memory 310, and the compensation circuit 300 can perform accumulation and compensation operations based on the normal slice accumulated data.

[0107] Figure 7 Show Figure 6 An embodiment in which a sampler selects slice data from a plurality of frames.

[0108] Reference Figure 7 , each of the plurality of frames FR1, FR2, FR3, etc. may include data set in the first direction DR1 and the second direction DR2, and the sampler 350 may select a corresponding one of the slices SL1, SL2, SL3, etc. from each of the plurality of frames FR1, FR2, FR3, etc. Each of the slices SL1, SL2, SL3, etc. may include data corresponding to at least one pixel row in the first direction DR1 in the corresponding one of the plurality of frames FR1, FR2, FR3, etc. Figure 7 In the embodiment, it is assumed that the slice SL3 in the frame FR3 is provided as the selected slice data SSLD. That is, the slicing unit may include data corresponding to at least one pixel row in the first direction DR1 in a corresponding one of the plurality of frames FR1, FR2, FR3, etc.

[0109] Figure 8 Show Figure 6 An embodiment in which a sampler selects slice data from a plurality of frames.

[0110] Reference Figure 8, each of the plurality of frames FR1, FR2, FR3, etc. may include data arranged in the first direction DR1 and the second direction DR2, and the sampler 350 may select a corresponding one of the slices SL1a, SL2a, SL3a, etc. from each of the plurality of frames FR1, FR2, FR3, etc. Each of the slices SL1a, SL2a, SL3a, etc. may include data corresponding to at least one pixel column in the second direction DR2 in the corresponding one of the plurality of frames FR1, FR2, FR3, etc. That is, the slicing unit may include data corresponding to at least one pixel column in the second direction DR2 in the corresponding one of the plurality of frames FR1, FR2, FR3, etc.

[0111] Figure 9 Show Figure 5 A compensation circuit in a first memory embodiment.

[0112] Reference Figure 9 The first memory 310 may store a plurality of slice accumulation data sets SLADS_a, SLADS_b, SLADS_c, ..., SLADS_i selected and accumulated from each of a plurality of frames FR1, FR2, FR3, etc. in slice units, and each of the plurality of slice accumulation data sets SLADS_a, SLADS_b, SLADS_c, ..., SLADS_i may include slice accumulation data SLAD, a maximum value MAX among degradation values of the slice accumulation data SLAD, and a checksum CS generated based on the degradation value of the slice accumulation data SLAD.

[0113] When the degradation value of at least one of the degradation values of the slice accumulation data SLAD of the plurality of slice accumulation data sets SLADS_a, SLADS_b, SLADS_c, ..., SLADS_i is relatively large due to ESD, the degradation value may affect the maximum value MAX and a defect may occur in the accumulated stress data ASD. The accumulated stress data ASD is updated by accumulating the degradation amount to the previous stress data at the current time point. Figure 9 and Figure 5 ,because Figure 5 The compensator 340 in FIG. 3 compensates the input image data IMG based on the accumulated stress data ASD having defects, so erroneous compensation for degradation may continuously occur.

[0114] Reference Figure 9 、 Figure 5 and Figure 6However, the compensation circuit 300 in the embodiment can determine whether each of the plurality of slice accumulation data sets SLADS_a, SLADS_b, SLADS_c, ..., SLADS_i is abnormal based on comparing the previous maximum value MAX_P of each of the plurality of slice accumulation data sets SLADS_a, SLADS_b, SLADS_c, ..., SLADS_i with the current maximum value MAX_C of a corresponding one of the plurality of slice accumulation data sets SLADS_a, SLADS_b, SLADS_c, ..., SLADS_i, and does not store the defective slice accumulation data set in the first memory 310. Therefore, the compensation circuit 300 can prevent the accumulated stress data ASD from being affected by the abnormal degradation value.

[0115] Figure 10 It shows Figure 5 A block diagram of an embodiment of a compensation circuit in a data processor.

[0116] Reference Figure 10 , the data processor 400 may include an accumulator 410 , a maximum value generator 420 , a maximum value checker 430 , a checksum generator 440 , and an interrupt signal generator 450 .

[0117] The accumulator 410 may generate current slice accumulation data SLAD_C by adding the selected slice data SSLD to the previous slice accumulation data SLAD_P.

[0118] Reference Figure 10 and Figure 9 , the maximum value generator 420 may select the maximum value MAX as the current maximum value MAX_C from among the degradation values of the pixels included in the current slice accumulation data SLAD_C.

[0119] The maximum value checker 430 may generate a difference between a current maximum value MAX_C and a previous maximum value MAX_P, may compare the difference with a reference value REF_M and generate a check signal CKS indicating whether the current slice accumulation data SLAD_C is abnormal based on the comparison.

[0120] The reference value REF_M may be a maximum cumulative value that the degradation value may have, and may represent an amount of degradation by which the corresponding block may be maximally degraded during an update period of the maximum degradation value (eg, during one frame).

[0121] In an embodiment, the maximum value checker 430 may compare the current maximum value MAX_C with a first reference value and may generate a check signal CKS indicating whether the current maximum value MAX_C is abnormal based on the comparison. The first reference value may be greater than the reference value REF_M.

[0122] The checksum generator 440 may generate a current checksum CS_C of the current slice accumulation data set SLADS_C by performing a cyclic redundancy check (“CRC”) operation on degraded values of pixels included in the current slice accumulation data SLAD_C.

[0123] The interrupt signal generator 450 may generate a first interrupt signal ITR1 that is activated when the current maximum value MAX_C is abnormal based on the check signal CKS.

[0124] The maximum value checker 430 can output a check signal CKS having a first logic level (e.g., a relatively low logic level) in response to the difference being equal to or less than the reference value REF_M, and the checksum generator 440 can perform a CRC operation on the degradation value of the pixel in response to the check signal CKS having the first logic level, and can output a current checksum CS_C.

[0125] The maximum value checker 430 can output a check signal CKS having a second logic level (e.g., a relatively high logic level) different from the first logic level in response to the difference being greater than the reference value REF_M, and the checksum generator 440 can suspend performing a CRC operation on the degradation value of the pixel in response to the check signal CKS having the second logic level.

[0126] Reference Figure 10 and Figure 5 The current slice accumulation data SLAD_C, the current maximum value MAX_C and the current checksum CS_C can be provided to the current slice accumulation data set SLADS_C as Figure 5 The second memory 360 in.

[0127] Figure 11 It shows Figure 10 Block diagram of an embodiment of a maximum value checker in .

[0128] Reference Figure 11 , the maximum value checker 430 may include a difference generator 431 and a comparator 433 .

[0129] The difference generator 431 can generate a difference value MAX_DIF by subtracting the previous maximum value MAX_P from the current maximum value MAX_C. The comparator 433 can generate a check signal CKS by comparing the difference value MAX_DIF with the reference value REF_M, and can determine the logic level of the check signal CKS based on the comparison result. When the difference value MAX_DIF is equal to or less than the reference value REF_M, the comparator 433 can output the check signal CKS with a first logic level. When the difference value MAX_DIF is greater than the reference value REF_M, the comparator 433 can output the check signal CKS with a second logic level.

[0130] Figure 12 An embodiment of slicing an accumulated data set is shown.

[0131] Reference Figure 12 The slice accumulation data set SLADS may include slice accumulation data SLAD, maximum value MAX, average value MV and checksum CS.

[0132] Reference Figure 12 and Figure 10 , Figure 10 The data processor 400 may generate a mean value MV by averaging the degradation values in the slice accumulation data SLAD. That is, the data processor 400 may generate a mean value MV by dividing the sum of the degradation values by the number of degradation values. In this case, the data processor 400 may further include a mean value generator.

[0133] The data processor 400 may determine whether the slice accumulation data SLAD is abnormal based on a difference between multiple average values of previous slice accumulation data and current slice accumulation data, or based on a difference between multiple maximum values and a difference between multiple average values of previous slice accumulation data and current slice accumulation data.

[0134] Figure 13 It shows Figure 1 A block diagram of an embodiment of a compensation circuit in a display driver integrated circuit is provided.

[0135] Reference Figure 13 , the compensation circuit 300a may include an accumulated stress memory (i.e., a first memory) 310a, a compensator 340, a sampler 350, a data processor 400, an SRAM (i.e., a second memory) 360a, an error detector 370a, a memory interface 380a, an encoding / decoding (“ENC / DEC”) logic 390, and a decoding logic 395.

[0136] Reference Figure 13 and Figure 1 When the display driver integrated circuit 105 is powered on, the memory interface 380a can provide the first memory 310a with Figure 1 The encoded accumulated stress data EASD is loaded into the third memory 200 in the first memory 310a, and a backup operation of storing the encoded accumulated stress data EASD stored in the first memory 310a in the third memory 200 at a predetermined cycle may be performed.

[0137] The first memory 310 a may store the encoded accumulated stress data EASD loaded from the third memory 200 and may provide the encoded accumulated stress data EASD to the decoding logic 395 .

[0138] The decoding logic 395 may generate accumulated stress data ASD by decoding the encoded accumulated stress data EASD, and may provide the accumulated stress data ASD to the compensator 340 .

[0139] The compensator 340 may generate output data DTA for image display by compensating the input image data IMG based on the accumulated stress data ASD associated with compensating for degradation of the plurality of pixels. The compensator 340 may compensate the input image data IMG based on the ISC.

[0140] The sampler 350 may select slice data in slice units from each of a plurality of frames of the input image data IMG based on the clock signal CLK, and may provide the selected slice data SSLD to the data processor 400. In addition, the sampler 350 may provide the first memory 310a with a target address TG_ADDR associated with the selected slice data SSLD.

[0141] The first memory 310 a may provide the encoded previous slice accumulation data set ESLADS_P to the second memory 360 a in response to the target address TG_ADDR, and the second memory 360 a may provide the encoded previous slice accumulation data set ESLADS_P to the encoding / decoding logic 390 .

[0142] The encoding / decoding logic 390 may generate a previous slice accumulation dataset SLADS_P by decoding the encoded previous slice accumulation dataset ESLADS_P, and may provide the previous slice accumulation dataset SLADS_P to the data processor 400 .

[0143] Reference Figure 13 、 Figure 12 and Figure 6 , the data processor 400: can generate current slice accumulation data SLAD_C of the current slice accumulation data set SLADS_C associated with the selected frame by adding the selected slice data SSLD and the previous slice accumulation data SLAD_P of the previous slice accumulation data set SLADS_P associated with the frame selected from the multiple frames; can select the maximum value MAX from the degradation values of the pixels included in the current slice accumulation data SLAD_C as the current maximum value MAX_C; can determine whether the current slice accumulation data SLAD_C is abnormal based on comparing the previous maximum value MAX_P of the previous slice accumulation data set SLADS_P with the current maximum value MAX_C; and can selectively update the previous slice accumulation data set SLADS_P by selectively storing the current slice accumulation data set SLADS_C in the first memory 310a based on the determination.

[0144] The data processor 400 may provide the current slice accumulation data set SLADS_C to the encoding / decoding logic 390. The encoding / decoding logic 390 may generate an encoded current slice accumulation data set ESLADS_C by encoding the current slice accumulation data set SLADS_C and may provide the encoded current slice accumulation data set ESLADS_C to the second memory 360a. When the current maximum value MAX_C of the encoded current slice accumulation data set ESLADS_C is normal, the second memory 360a may update the encoded previous slice accumulation data set ESLADS_P stored in the first memory 310 with the encoded current slice accumulation data set ESLADS_C by providing the encoded current slice accumulation data set ESLADS_C to the first memory 310a.

[0145] The data processor 400 may selectively suspend operations of the second memory 360a and the memory interface 380a by providing the second memory 360a and the memory interface 380a with a first interrupt signal ITR1 indicating whether the current maximum value MAX_C of the current slice accumulation data set SLADS_C is abnormal.

[0146] The second memory 360a may provide the encoded current slice accumulation data set ESLADS_C to the first memory 310a in response to the first interrupt signal ITR1 indicating that the current maximum value MAX_C is normal. The second memory 360a may suspend (i.e., stop) operation in response to the first interrupt signal ITR1 indicating that the current maximum value MAX_C is abnormal, and not provide the encoded current slice accumulation data set ESLADS_C to the first memory 310a.

[0147] In response to the first interrupt signal ITR1 indicating that the current maximum value MAX_C is normal, the memory interface 380 a may perform a backup operation of storing the encoded accumulated stress data EASD stored in the first memory 310 a in the third memory 200 at a predetermined cycle.

[0148] In response to the first interrupt signal ITR1 indicating that the current maximum value MAX_C is abnormal, the memory interface 380 a may skip a backup operation of storing the encoded accumulated stress data EASD stored in the first memory 310 a in the third memory 200 .

[0149] Reference Figure 13 、 Figure 12 and Figure 1When the display driver integrated circuit 105 is powered on, the error detector 370a can determine whether the encoded accumulated stress data EASD loaded from the third memory 200 is abnormal based on the maximum value MAX in the encoded accumulated stress data EASD loaded from the third memory 200 and the checksum CS, and can provide the second memory 360a with a second interrupt signal ITR2 indicating whether the encoded accumulated stress data EASD is abnormal.

[0150] In response to the second interrupt signal ITR2 indicating that the encoded accumulated stress data EASD is abnormal, the second memory 360 a may suspend operation.

[0151] Therefore, when a defect occurs in the encoded accumulated stress data EASD stored in the first memory 310a due to ESD, a memory access failure, a hardware failure, etc., the data processor 400 can verify the integrity of the encoded accumulated stress data EASD based on a change in the maximum value MAX of the slice data selected from the encoded accumulated stress data EASD, and when it is determined that the encoded accumulated stress data EASD is abnormal (i.e., a defect occurs in the encoded accumulated stress data EASD), it can suspend updating the slice accumulated data in the first memory 310a or can suspend the backup operation of storing the encoded accumulated stress data EASD in the third memory 200. When it is determined that the encoded accumulated stress data EASD is abnormal, after the display device 100 is powered off and then powered on, the encoded accumulated stress data EASD is loaded from the third memory 200 to the first memory 310a, and the compensation circuit 300a can perform accumulation and compensation operations based on the normal slice accumulated data.

[0152] Figure 14 is a flowchart illustrating an embodiment of a method of driving a display device.

[0153] Reference Figure 1 、 Figures 5 to 12 ,as well as Figure 14 In the method of driving the display device 100 in the embodiment, the display device 100 is powered on (operation S110), and accumulated stress data ASD for compensating for degradation of a plurality of pixels is loaded to the first memory 310 (operation S120).

[0154] Based on the maximum value MAX of the accumulated stress data ASD and the checksum CS, it is determined whether the accumulated stress data ASD is fault-free (operation S130). When it is determined that the accumulated stress data ASD is not fault-free ("No" in operation S130), the compensation operation is suspended (i.e., compensation is turned off), and the backup operation of storing the accumulated stress data ASD in the third memory 200 is suspended (operation S220).

[0155] When it is determined that the accumulated stress data ASD has no fault (YES in operation S130 ), the compensator 340 generates output data DTA by compensating the input image data IMG based on the accumulated stress data ASD (ie, compensated) (operation S140 ).

[0156] The sampler 350 selects slice data in slice units from each of the plurality of frames of the input image data IMG and provides the selected slice data SSLD to the data processor 400 (i.e., sampling) (operation S150), and the data processor 400 generates current slice accumulation data SLAD_C of the current slice accumulation data set SLADS_C by adding the selected slice data SSLD to the previous slice accumulation data SLAD_P of the previous slice accumulation data set SLADS_P (i.e., accumulation) (operation S160). The data processor 400 selects the maximum value MAX from among the degradation values of the pixels included in the current slice accumulation data SLAD_C as the current maximum value MAX_C (i.e., a new maximum value MAX is generated) (operation S170).

[0157] The data processor 400 determines whether the current maximum value MAX_C is abnormal (ie, is the new maximum value MAX acceptable?) based on comparing the previous maximum value MAX_P with the current maximum value MAX_C (operation S180 ).

[0158] When it is determined that the current maximum value MAX_C is abnormal (No in operation S180 ), the compensation operation is suspended (ie, compensation is off) and the backup operation of storing the accumulated stress data ASD in the third memory 200 is suspended (operation S220 ).

[0159] When it is determined that the current maximum value MAX_C is not abnormal ("Yes" in operation S180), the current slice accumulation data set SLADS_C is stored (i.e., written) in the first memory 310 (operation S190). When the process returns to operation S140, the memory interface 380 backs up the accumulated stress data ASD in the third memory 200 (operation S210).

[0160] Figure 15 is a block diagram illustrating an embodiment of a display system.

[0161] Reference Figure 15 , the display system 800 may include an application processor (“AP”) 810 and a display device 820 . The display device 820 may include a display driver integrated circuit 830 , a display panel (ie, an OLED display) 840 , and a power supply 850 .

[0162] The power supply 850 can provide a higher power supply voltage ELVDD and a lower power supply voltage ELVSS to the display panel 840 in response to a power control signal PCTL from the display driver integrated circuit 830 (also referred to as the driving circuit 830). In addition, the power supply 850 can provide a first voltage VGL and a second voltage VGH to the driving circuit 830 in response to the power control signal PCTL.

[0163] The display system 800 can be a portable device such as a cellular phone, a smart phone, a personal computer (“PC”) (e.g., a laptop computer), a personal digital assistant (“PDA”), a portable multimedia player (“PMP”), a Moving Picture Experts Group Audio Layer 3 (MP3) player, a navigation system, etc.

[0164] The application processor 810 provides the image signal RGB, the control signal CTL, and the main clock signal MCLK to the display device 820 , and the display driver integrated circuit 830 may provide the output data DTA to the display panel 840 .

[0165] The display driver integrated circuit 830 , the display panel 840 , and the power supply 850 are substantially the same as the display driver integrated circuit 105 , the display panel 110 , and the power supply 180 , respectively.

[0166] Figure 16 is a block diagram illustrating an embodiment of an electronic device including an OLED display device. Figure 17 It shows Figure 16 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a smart phone.

[0167] Reference Figure 16 and Figure 17 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output ("I / O") device 1040, a power supply 1050, and an OLED display device 1060. The electronic device 1000 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus ("USB") device, other electronic systems, etc. In an embodiment, as Figure 17 As shown in , the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. In embodiments, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop computer, or a head-mounted display ("HMD") device, etc.

[0168] The processor 1010 can perform various computing functions or tasks. For example, the processor 1010 can be a microprocessor, a central processing unit ("CPU"), etc. The processor 1010 can be connected to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 can be coupled to an expansion bus such as a peripheral component interconnect ("PCI") bus.

[0169] The memory device 1020 may store data used for the operation of the electronic device 1000 (also referred to as the electronic system 1000). In embodiments, the memory device 1020 may include at least one non-volatile memory device such as a flash memory device and / or at least one volatile memory device such as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a mobile dynamic random access memory ("mobile DRAM") device, and the like.

[0170] The storage device 1030 may be, for example, a solid-state drive ("SSD") device, a hard disk drive ("HDD") device, a compact disc read-only memory ("CD-ROM") device, etc. The I / O device 1040 may be, for example, an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and / or an output device such as a printer, a speaker, etc. The power supply 1050 may supply power for the operation of the electronic system 1000. The OLED display device 1060 may communicate with other components via a bus or other communication links.

[0171] Reference Figure 16 and Figure 1 , the OLED display device 1060 can be used Figure 1 The display device 100. Therefore, the OLED display device 1060 may include a compensation circuit. The compensation circuit: may select slice data in slice units from each of a plurality of frames of input image data; may generate current slice accumulation data of a current slice accumulation data set associated with a selected frame by adding the selected slice data and previous slice accumulation data of a previous slice accumulation data set associated with a frame selected from the plurality of frames; may select a maximum value as a current maximum value from among degradation values of pixels included in the current slice accumulation data; may determine whether the current slice accumulation data is abnormal based on comparing the previous maximum value of the previous slice accumulation data set with the current maximum value; may selectively update the previous slice accumulation data set by selectively storing the current slice accumulation data set in a first memory based on the determination; and may perform a backup operation of storing the accumulated stress data in a non-volatile memory device outside the compensation circuit.

[0172] The present invention can be applied to any display device or any electronic device including a display device. In an embodiment, for example, the present invention can be applied to a television, a computer monitor, a laptop computer, a digital camera, a cellular phone, a smart phone, a personal digital assistant ("PDA"), a portable multimedia player ("PMP"), an MP3 player, a navigation system, a video phone, etc.

[0173] The foregoing is an illustration of embodiments and should not be construed as limiting the embodiments. Although a few embodiments have been described, it will be readily apparent to those skilled in the art that many modifications may be made to the embodiments without materially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention as defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various embodiments and should not be construed as limiting the disclosed predetermined embodiments, and that modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display driver integrated circuit, wherein: The display driver integrated circuit is used to drive a display panel including a plurality of pixels, and the display driver integrated circuit includes: a first memory storing accumulated stress data for compensating for degradation of the plurality of pixels; a compensator that generates output data for image display by compensating input image data based on the accumulated stress data; a sampler that selects slice data in slice units from each of a plurality of frames of the input image data based on a clock signal; and Data Processor: generating current slice accumulation data of a current slice accumulation data set associated with a selected frame from the plurality of frames by adding the selected slice data to previous slice accumulation data of a previous slice accumulation data set associated with the selected frame from the plurality of frames; selecting a maximum value from among degradation values of pixels included in the current slice accumulated data as a current maximum value; determining whether the current slice accumulation data is abnormal based on comparing a previous maximum value of the previous slice accumulation data set with the current maximum value; and Based on the determination of whether the current slice accumulation data set is abnormal, the previous slice accumulation data set is selectively updated by selectively storing the current slice accumulation data set in the first memory.

2. The display driver integrated circuit according to claim 1, wherein: The slice unit includes at least one pixel row from among the plurality of pixels or at least one pixel column from among the plurality of pixels.

3. The display driver integrated circuit according to claim 1, wherein: The data processor comprises: an accumulator for generating the current slice accumulated data by adding the selected slice data to the previous slice accumulated data; a maximum value generator that selects a maximum value from among the degradation values of the pixels included in the current slice accumulated data as the current maximum value; a maximum value checker that generates a difference between the current maximum value and the previous maximum value, compares the difference with a reference value, and generates a check signal indicating whether the current slice accumulated data is abnormal based on the comparison of the difference with the reference value; a checksum generator that generates a current checksum of the current slice accumulated data set by performing a cyclic redundancy check operation on the degradation values of the pixels included in the current slice accumulated data; and An interrupt signal generator generates an interrupt signal based on the check signal, which is activated when the current maximum value is abnormal.

4. The display driver integrated circuit according to claim 3, wherein: The maximum value checker comprises: a difference value generator that generates the difference value by subtracting the previous maximum value from the current maximum value; and A comparator generates the check signal by comparing the difference value with the reference value, and determines a logic level of the check signal based on a result of the comparison of the difference value and the reference value.

5. The display driver integrated circuit according to claim 1, wherein: The display driver integrated circuit further includes a second memory, wherein, when the display driver integrated circuit is powered on, the accumulated stress data is loaded from a third memory provided outside the display driver integrated circuit and stored in the first memory; wherein the sampler provides the first memory with a target address associated with the selected slice data, and The first memory provides the previous slice accumulation data set to the second memory in response to the target address.

6. The display driver integrated circuit according to claim 5, wherein: The display driver integrated circuit further includes an error detector, Wherein, the error detector: determining whether the accumulated stress data loaded from the third memory is abnormal based on a maximum value and a checksum among the accumulated stress data loaded from the third memory; and An interrupt signal is provided to the second memory, indicating whether the accumulated stress data is abnormal.

7. The display driver integrated circuit according to claim 5, wherein: The display driver integrated circuit further includes a memory interface, Wherein, the memory interface: providing the first memory with the accumulated stress data loaded from the third memory; and A backup operation of storing the accumulated stress data stored in the first memory in the third memory at a predetermined period is performed.

8. The display driver integrated circuit according to claim 1, wherein: The display driver integrated circuit further includes: a second memory; Encoding / decoding logic, the encoding / decoding logic: by encoding the current slice accumulation dataset provided from the data processor, and providing the encoded current slice accumulation dataset to the second memory; and The previous slice cumulative data set is provided to the second memory by decoding the encoded previous slice cumulative data set provided from the first memory; and a decoding logic is provided to the compensator by decoding the encoded cumulative stress data.

9. The display driver integrated circuit according to claim 8, in, When the display driver integrated circuit is powered on, the encoded accumulated stress data is loaded from a third memory provided outside the display driver integrated circuit and stored in the first memory, wherein the sampler provides the first memory with a target address associated with the selected slice data, and Wherein, the first memory provides the encoded previous slice accumulation data set to the encoding / decoding logic in response to the target address.

10. A display device, wherein: The display device includes: A display panel comprising a plurality of pixels; and A display driver integrated circuit drives the display panel, the display driver integrated circuit comprising: a first memory storing accumulated stress data for compensating for degradation of the plurality of pixels; a compensator that generates output data for image display by compensating input image data based on the accumulated stress data; a sampler that selects slice data in slice units from each of a plurality of frames of the input image data based on a clock signal; and Data Processor: generating current slice accumulation data of a current slice accumulation data set associated with a selected frame from the plurality of frames by adding the selected slice data to previous slice accumulation data of a previous slice accumulation data set associated with the selected frame from the plurality of frames; selecting a maximum value from among degradation values of pixels included in the current slice accumulated data as a current maximum value; determining whether the current slice accumulation data is abnormal based on comparing a previous maximum value of the previous slice accumulation data set with the current maximum value; and Based on the determination of whether the current slice accumulation data set is abnormal, the previous slice accumulation data set is selectively updated by selectively storing the current slice accumulation data set in the first memory.

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