Three-dimensional memory array, memory search engine circuit and encoding method thereof

Abstract

The invention provides a three-dimensional memory array, a memory search engine circuit and a coding method thereof. A three-dimensional memory array includes a plurality of NAND strings. The NAND strings are each configured to store storage data including a plurality of bits and receive a search input including a plurality of bits. A plurality of bits for storing data and searching input respectively belong to a bit 0, a bit 1, a universal bit or an invalid bit. At least one continuous bit in the stored data is used as a data bit, at least one continuous bit in the search input is used as a search bit, and both the data bit and the search bit belong to bit 0 or bit 1. When the position of the data bit in the stored data is overlapped with the position of the search bit in the search input, the NAND string storing the stored data is turned off. When the position of the data bit in the stored data is not overlapped with the position of the search bit in the search input, the NAND string storing the stored data generates an output current.

Description

Technical Field

[0001] The present disclosure relates to encoding technology for a memory search engine circuit, and more particularly to a three-dimensional memory array that encodes stored data and search input using specific rules, a memory search engine circuit, and an encoding method thereof. Background Art

[0002] With the evolution of flash memory technology, three-dimensional flash memory has gradually replaced traditional planar flash memory due to its lower cost per bit. Furthermore, as big data and artificial intelligence technologies require extensive computing, data search and comparison within three-dimensional flash memory have become crucial functions.

[0003] Current in-memory search technology typically determines search results by evaluating the output current of a NAND string. However, using current to determine search results can lead to inconsistent criteria across different memory search engine circuits. Furthermore, over time, the output current of a memory search engine circuit can vary, leading to inaccurate search results. Therefore, improving the search accuracy of memory search engine circuits remains a key challenge in this field. Summary of the Invention

[0004] The present disclosure provides a three-dimensional memory array comprising a plurality of NAND (NAND) strings. Each of the plurality of NAND strings is configured to store stored data comprising a plurality of bits and to receive a search input comprising a plurality of bits. The plurality of bits of the stored data and the plurality of bits of the search input are each bit 0, bit 1, a common bit, or an invalid bit. At least one of the plurality of bits of the stored data is configured to serve as at least one data bit, and at least one of the plurality of bits of the search input is configured to serve as at least one search bit, and both the at least one data bit and the at least one search bit are bit 0 or bit 1. When the position of the at least one data bit in the stored data overlaps with the position of the at least one search bit in the search input, at least one of the plurality of NAND strings storing the stored data is turned off. When the position of the at least one data bit in the stored data does not overlap with the position of the at least one search bit in the search input, at least one of the plurality of NAND strings storing the stored data generates an output current.

[0005] In some embodiments of a three-dimensional memory array, the at least one data bit and the at least one search bit are both bit 0, at least one other of the plurality of bits of stored data that does not belong to the at least one data bit is both bit 1, and at least one other of the plurality of bits of the search input that does not belong to the at least one search bit is both an invalid bit.

[0006] In some embodiments of a three-dimensional memory array, the at least one data bit and the at least one search bit are both bit 0, at least one other of the plurality of bits of stored data that does not belong to the at least one data bit is an invalid bit, and at least one other of the plurality of bits of the search input that does not belong to the at least one search bit is both bit 1.

[0007] In some embodiments of a three-dimensional memory array, the at least one data bit and the at least one search bit are both bit 1, at least one other of the plurality of bits of stored data that does not belong to the at least one data bit is both bit 0, and at least one other of the plurality of bits of the search input that does not belong to the at least one search bit is both an invalid bit.

[0008] In some embodiments of a three-dimensional memory array, the at least one data bit and the at least one search bit are both bit 1, at least one other of the plurality of bits of stored data that does not belong to the at least one data bit is an invalid bit, and at least one other of the plurality of bits of the search input that does not belong to the at least one search bit is both bit 0.

[0009] In some embodiments of a three-dimensional memory array, each of the multiple NAND strings includes multiple memory cells connected in series, each corresponding to a plurality of bits of stored data. Each of the multiple memory cells includes a first transistor and a second transistor connected in series along the direction of an output current. The first transistor and the second transistor have a first threshold voltage or a second threshold voltage, wherein the second threshold voltage is greater than the first threshold voltage. When the first transistor and the second transistor of one of the multiple memory cells have the first threshold voltage and the second threshold voltage, respectively, the corresponding bit corresponding to the one of the multiple memory cells is bit 0. When the first transistor and the second transistor of one of the multiple memory cells have the second threshold voltage and the first threshold voltage, respectively, the corresponding bit corresponding to the one of the multiple memory cells is bit 1. When both the first transistor and the second transistor of one of the multiple memory cells have the second threshold voltage, the corresponding bit corresponding to the one of the multiple memory cells is a common bit. When both the first transistor and the second transistor of one of the multiple memory cells have the first threshold voltage, the corresponding bit corresponding to the one of the multiple memory cells is an invalid bit.

[0010] In some embodiments of a three-dimensional memory array, a first transistor and a second transistor are respectively configured to receive a first driving voltage and a second driving voltage from a plurality of word lines, the first driving voltage and the second driving voltage corresponding to one of a plurality of bits of a search input. When the one of the plurality of bits of the search input is bit 0, the first driving voltage is greater than a second threshold voltage, and the second driving voltage is greater than the first threshold voltage and less than the second threshold voltage. When the one of the plurality of bits of the search input is bit 1, the first driving voltage is greater than the first threshold voltage and less than the second threshold voltage, and the second driving voltage is greater than the second threshold voltage. When the one of the plurality of bits of the search input is a common bit, both the first driving voltage and the second driving voltage are greater than the first threshold voltage and less than the second threshold voltage. When the one of the plurality of bits of the search input is an invalid bit, both the first driving voltage and the second driving voltage are greater than the second threshold voltage.

[0011] The present disclosure provides a memory search engine circuit comprising a three-dimensional memory array, a plurality of word lines, and a sensing circuit. The three-dimensional memory array comprises a plurality of NAND strings, each of which is configured to store stored data comprising a plurality of bits and to receive a search input comprising a plurality of bits. A plurality of word lines are coupled to the plurality of NAND strings in the three-dimensional memory array and are configured to transmit the search input to the plurality of NAND strings. The sensing circuit is coupled to the three-dimensional memory array and is configured to generate a search result when receiving an output current. The plurality of bits of stored data and the plurality of bits of the search input are each bit 0, bit 1, a common bit, or an invalid bit. At least one of the plurality of bits of stored data is used as at least one data bit, and at least one of the plurality of bits of the search input is used as at least one search bit, and both the at least one data bit and the at least one search bit are bit 0 or bit 1. When the position of the at least one data bit in the stored data overlaps with the position of the at least one search bit in the search input, at least one of the plurality of NAND strings storing the stored data is turned off. At least one of the plurality of NAND strings storing the stored data generates an output current when a position of the at least one data bit in the stored data does not overlap with a position of the at least one search bit in the search input.

[0012] In some embodiments of the memory search engine circuit, at least two consecutive bits of a plurality of stored data are used as at least two data bits; or at least two consecutive bits of a plurality of search input bits are used as at least two search bits.

[0013] In some embodiments of the memory search engine circuit, the at least one data bit and the at least one search bit both belong to bit 0, at least one other of the multiple bits of stored data that does not belong to the at least one data bit both belongs to bit 1, and at least one other of the multiple bits of the search input that does not belong to the at least one search bit both belongs to an invalid bit.

[0014] In some embodiments of the memory search engine circuit, the at least one data bit and the at least one search bit both belong to bit 0, at least one other of the multiple bits of stored data that does not belong to the at least one data bit both belongs to an invalid bit, and at least one other of the multiple bits of the search input that does not belong to the at least one search bit both belongs to bit 1.

[0015] In some embodiments of the memory search engine circuit, the at least one data bit and the at least one search bit both belong to bit 1, at least one other of the multiple bits of stored data that does not belong to the at least one data bit both belongs to bit 0, and at least one other of the multiple bits of the search input that does not belong to the at least one search bit both belongs to an invalid bit.

[0016] In some embodiments of the memory search engine circuit, the at least one data bit and the at least one search bit both belong to bit 1, at least one other of the multiple bits of stored data that does not belong to the at least one data bit both belongs to an invalid bit, and at least one other of the multiple bits of the search input that does not belong to the at least one search bit both belongs to bit 0.

[0017] In some embodiments of a memory search engine circuit, each of the plurality of NAND strings includes a plurality of memory cells connected in series, each of the plurality of memory cells corresponding to a plurality of bits of stored data. Each of the plurality of memory cells includes a first transistor and a second transistor connected in series along the direction of an output current. The first transistor and the second transistor have a first threshold voltage or a second threshold voltage, wherein the second threshold voltage is greater than the first threshold voltage. When the first transistor and the second transistor of one of the plurality of memory cells have the first threshold voltage and the second threshold voltage, respectively, the corresponding bit corresponding to the one of the plurality of memory cells is bit 0. When the first transistor and the second transistor of one of the plurality of memory cells have the second threshold voltage and the first threshold voltage, respectively, the corresponding bit corresponding to the one of the plurality of memory cells is bit 1. When both the first transistor and the second transistor of one of the plurality of memory cells have the second threshold voltage, the corresponding bit corresponding to the one of the plurality of memory cells is a common bit. When both the first transistor and the second transistor of one of the plurality of memory cells have the first threshold voltage, the corresponding bit corresponding to the one of the plurality of memory cells is an invalid bit.

[0018] In some embodiments of the memory search engine circuit, a first transistor and a second transistor are respectively configured to receive a first drive voltage and a second drive voltage from a plurality of word lines, the first drive voltage and the second drive voltage corresponding to one of a plurality of bits of a search input. When the one of the plurality of bits of the search input is bit 0, the first drive voltage is greater than a second threshold voltage, and the second drive voltage is greater than the first threshold voltage and less than the second threshold voltage. When the one of the plurality of bits of the search input is bit 1, the first drive voltage is greater than the first threshold voltage and less than the second threshold voltage, and the second drive voltage is greater than the second threshold voltage. When the one of the plurality of bits of the search input is a common bit, both the first drive voltage and the second drive voltage are greater than the first threshold voltage and less than the second threshold voltage. When the one of the plurality of bits of the search input is an invalid bit, both the first drive voltage and the second drive voltage are greater than the second threshold voltage.

[0019] This disclosure provides an encoding method applicable to a memory search engine circuit. The memory search engine circuit includes multiple NAND strings, wherein the multiple NAND strings are configured to receive a search input comprising multiple bits. The encoding method includes: storing stored data comprising multiple bits in each of the multiple NAND strings, wherein at least one of the multiple bits of the stored data is used as at least one data bit; and setting multiple bits of the search input in the memory search engine circuit, wherein at least one of the multiple bits of the search input is used as at least one search bit. The multiple bits of the stored data and the multiple bits of the search input are each bit 0, bit 1, a common bit, or an invalid bit. In response to the position of the at least one data bit in the stored data overlapping with the position of the at least one search bit in the search input, at least one of the multiple NAND strings storing the stored data is turned off. In response to the position of the at least one data bit in the stored data not overlapping with the position of the at least one search bit in the search input, at least one of the multiple NAND strings storing the stored data generates an output current.

[0020] In some embodiments of the encoding method, storing storage data comprising a plurality of bits via each of the plurality of NAND strings includes setting the at least one data bit to bit 0 and setting at least one other bit of the plurality of bits of the storage data that is not the at least one data bit to an invalid bit. Setting a plurality of bits of a search input via a memory search engine circuit includes setting the at least one search bit to bit 0 and setting at least one other bit of the plurality of bits of the search input that is not the at least one search bit to bit 1.

[0021] In some embodiments of the encoding method, storing storage data comprising a plurality of bits via each of the plurality of NAND strings includes setting the at least one data bit to bit 0 and setting at least one other bit of the plurality of bits of the storage data that is not the at least one data bit to bit 1. Setting a plurality of bits of a search input via a memory search engine circuit includes setting the at least one search bit to bit 0 and setting at least one other bit of the plurality of bits of the search input that is not the at least one search bit to an invalid bit.

[0022] In some embodiments of the encoding method, storing storage data comprising a plurality of bits via each of the plurality of NAND strings includes setting the at least one data bit to bit 1 and setting at least one other bit of the plurality of bits of the storage data that is not the at least one data bit to an invalid bit. Setting a plurality of bits of a search input via a memory search engine circuit includes setting the at least one search bit to bit 1 and setting at least one other bit of the plurality of bits of the search input that is not the at least one search bit to bit 0.

[0023] In some embodiments of the encoding method, storing storage data comprising a plurality of bits via each of the plurality of NAND strings includes setting the at least one data bit to bit 1 and setting at least one other bit of the plurality of bits of the storage data that is not the at least one data bit to bit 0. Setting a plurality of bits of a search input via a memory search engine circuit includes setting the at least one search bit to bit 1 and setting at least one other bit of the plurality of bits of the search input that is not the at least one search bit to an invalid bit.

[0024] Through the three-dimensional memory array, memory search engine circuit and encoding method of the disclosed document, the result of the memory search can be judged according to the conduction or disconnection of the NAND string to prevent inaccurate judgment of the memory search caused by errors in the conduction current. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To make the above and other objects, features, advantages and embodiments of the present disclosure more apparent and understandable, the accompanying drawings are described as follows:

[0026] Figure 1 is a schematic diagram of a memory search engine circuit according to some embodiments of the present disclosure;

[0027] Figure 2 is a schematic diagram illustrating a correspondence between a NAND string, stored data, and a search input according to some embodiments of the present disclosure;

[0028] Figure 3ASchematic diagrams of memory cells corresponding to different storage data configurations according to some embodiments of the present disclosure;

[0029] Figure 3B is a schematic diagram illustrating configurations of word line voltages corresponding to different search inputs according to some embodiments of the present disclosure;

[0030] Figure 3C is a schematic diagram illustrating the conduction status of a memory cell under different storage data and search input conditions according to some embodiments of the present disclosure;

[0031] Figure 4A is a schematic diagram illustrating a matching situation between stored data and search input according to some embodiments of the present disclosure;

[0032] Figure 4B is a schematic diagram illustrating a matching situation between stored data and search input according to some embodiments of the present disclosure;

[0033] Figure 4C is a schematic diagram illustrating a matching situation between stored data and search input according to some embodiments of the present disclosure;

[0034] Figure 4D is a schematic diagram illustrating a matching situation between stored data and search input according to some embodiments of the present disclosure;

[0035] Figure 4E is a schematic diagram illustrating a matching situation between stored data and search input according to some embodiments of the present disclosure;

[0036] Figure 4F is a schematic diagram illustrating a matching situation between stored data and search input according to some embodiments of the present disclosure; and

[0037] Figure 5 The flowchart is a method for encoding a memory search engine circuit according to some embodiments of the present disclosure.

[0038] Description of reference numerals:

[0039] 100: Memory search engine circuit

[0040] 110: Three-dimensional memory array

[0041] 120: Sensing circuit

[0042] 500: Encoding method

[0043] S510, S520, S530, S540: Steps

[0044] S550, S560, S570: Steps

[0045] BL0~BL(p): bit lines

[0046] CSL: Grounding Line

[0047] DATA1~DATA48: Storage data

[0048] DATA1[1]~DATA1

[48] :bit

[0049] GSL0~GSL(m): Ground selection line

[0050] IN: Search input

[0051] IN[1]~IN

[48] :bit

[0052] Iout: output current

[0053] MC1~MC48: memory cells

[0054] MS: Select transistor

[0055] N0: NAND string

[0056] SSL0~SSL(m): string selection line

[0057] T1_1, T1_2: transistors

[0058] TL, TH: transistor

[0059] VDL, VDH: driving voltage

[0060] WL0_0~WL96_0: word lines DETAILED DESCRIPTION

[0061] The following will illustrate the embodiments of the present disclosure with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar elements or method flows.

[0062] In this disclosure, when an element is referred to as "connected", it may refer to "electrical connection" or "optical connection", and when an element is referred to as "coupled", it may refer to "electrical coupling" or "optical coupling". "Connected" or "coupled" can also be used to indicate the coordinated operation or interaction between two or more elements. Unless otherwise specified in the text, "one" and "the" may refer to a single or multiple elements. It will be further understood that "comprising", "including", "having" and similar words used herein indicate the features, regions, integers, steps, operations, elements and / or components described therein, but do not exclude the described or additional one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0063] Figure 1 FIG2 is a schematic diagram of a memory search engine circuit 100 according to some embodiments of the present disclosure. In some embodiments, the memory search engine circuit 100 includes a three-dimensional memory array 110, a sensing circuit 120, bit lines BL0-BL(p), and a plurality of word lines (for simplicity, only word lines WL0_0-WL96_0 are labeled), where p is a positive integer.

[0064] The three-dimensional memory array 110 is coupled to the sensing circuit 120 to store a plurality of stored data DATA and is turned on or off according to the received search input IN. In some embodiments, the three-dimensional memory array 110 includes a plurality of NAND strings (not labeled for simplicity of the figure, and will be described in subsequent paragraphs and figures). In some embodiments, such as Figure 1 As shown, bit lines BL0-BL(p) extend along a first direction (e.g., direction X), multiple word lines extend along a second direction (e.g., direction Y), and multiple NAND strings extend along a third direction (e.g., direction Z). Therefore, bit lines BL0-BL(p), multiple word lines, and multiple NAND strings form a three-dimensional structure.

[0065] Bit lines BL0-BL(p) are connected to a sensing circuit 120 to generate an output current Iout when the NAND string is turned on. Each word line is connected to multiple NAND strings to control the conduction state of each NAND string based on a search input IN. Each NAND string is connected between one of the bit lines BL0-BL(p) and a ground line CSL to turn it on or off based on the stored data DATA and the received search input IN.

[0066] In operation, each NAND string in the three-dimensional memory array 110 stores a storage data DATA and receives search inputs IN from multiple word lines. When the storage data DATA stored in a NAND string does not match the search input IN, the NAND string turns on and generates an output current Iout. Conversely, when the storage data DATA stored in a NAND string matches the search input IN, the NAND string turns off and does not generate an output current Iout.

[0067] The sensing circuit 120 is coupled to the three-dimensional memory array 110 and is configured to sense whether each NAND string generates an output current Iout, thereby generating a search result. Specifically, when the sensing circuit 120 senses that a NAND string generates an output current Iout, it determines whether the stored data DATA of the NAND string matches the search input IN and generates a search result corresponding to the NAND string.

[0068] For more information on the correspondence between NAND strings, stored data, and search input, please refer to Figure 2 . Figure 2 FIG. 1 is a schematic diagram illustrating a corresponding relationship between a NAND string N0 , storage data DATA1 , and a search input IN according to some embodiments of the present disclosure.

[0069] NAND string N0 is coupled between bit line BL0 and ground line CSL. In some embodiments, NAND string N0 includes memory cells MC1-MC48 connected in series and two selection transistors MS. Memory cells MC1-MC48 are respectively used to store 48 bits of a storage data DATA1. For example, memory cell MC1 is used to store the first bit DATA1[1] of the storage data DATA1, memory cell MC2 is used to store the second bit DATA1[2] of the storage data DATA1, and so on. The two selection transistors MS are respectively connected to a corresponding one of string selection lines SSL0-SSL(m) (e.g., string selection line SSL0) and a corresponding one of ground selection lines GSL0-GSL(m) (e.g., ground selection line GSL0), where m is a positive integer.

[0070] In some embodiments, each memory cell includes two transistors connected in series. Figure 2 For example, memory cell M1 includes transistors T1_1 and T1_2, memory cell M2 includes transistors T2_1 and T2_2, and so on. The configuration of the two transistors in a memory cell can determine whether the memory cell (i.e., the corresponding bit of stored data DATA1) is bit 0, bit 1, a wildcard bit, or an invalid bit.

[0071] Please refer to Figure 3A , Figure 3A FIG2 is a schematic diagram illustrating configurations of memory cell MC1 corresponding to different stored data DATA according to some embodiments of the present disclosure. In some embodiments, each transistor in memory cell MC1 may be implemented as a transistor TH or a transistor TL, where transistor TH and transistor TL have a threshold voltage VTH and a threshold voltage VTL, respectively, and threshold voltage VTH is greater than threshold voltage VTL.

[0072] In operation, when the voltage received by the control terminal of the transistor TH is higher than the threshold voltage VTH, the transistor TH is turned on; when the voltage received by the control terminal of the transistor TL is higher than the threshold voltage VTL, the transistor TL is turned on.

[0073] Taking transistors T1_1 and T1_2 in memory cell MC1 as an example, when transistors T1_1 and T1_2 are implemented by transistors TL and TH, respectively, memory cell MC1 (and the corresponding bit DATA1[1]) is bit 0; when transistors T1_1 and T1_2 are implemented by transistors TH and TL, respectively, memory cell MC1 (and the corresponding bit DATA1[1]) is bit 1; when both transistors T1_1 and T1_2 are implemented by transistors TL, memory cell MC1 (and the corresponding bit DATA1[1]) is a common bit. When both transistors T1_1 and T1_2 are implemented by transistors TH, memory cell MC1 (and the corresponding bit DATA1[1]) is an invalid bit.

[0074] Please refer again Figure 2 Memory cells MC1-MC48 are also configured to receive 48 bits of search input IN from word lines WL1_0-WL96_0, respectively. Specifically, the voltages provided by word lines WL1_0 and WL2_0 correspond to the first bit IN[1] of search input IN, the voltages provided by word lines WL3_0 and WL4_0 correspond to the second bit IN[2] of search input IN, and so on. The voltage configuration of the two word lines determines whether the corresponding bit of search input IN is bit 0, bit 1, a common bit, or an invalid bit.

[0075] Please refer to Figure 3B , Figure 3B FIG2 is a diagram illustrating voltages of word lines WL1_0 to WL2_0 corresponding to different search input IN configurations according to some embodiments of the present disclosure. In some embodiments, word lines WL1_0 to WL2_0 each have a driving voltage VDH or a driving voltage VDL, and driving voltage VDH is greater than driving voltage VDL.

[0076] Taking word lines WL1_0 and WL2_0 as an example, when the voltages provided by word lines WL1_0 and WL2_0 are respectively the driving voltage VDH and the driving voltage VDL, the bit IN[1] of the search input IN corresponding to word lines WL1_0 and WL2_0 is bit 0; when the voltages provided by word lines WL1_0 and WL2_0 are respectively the driving voltage VDL and the driving voltage VDH, the bit IN[1] of the search input IN corresponding to word lines WL1_0 and WL2_0 is bit 0. The bit IN[1] of the input IN is bit 1. When the voltages provided by the word lines WL1_0 and WL2_0 are both the driving voltage VDL, the bit IN[1] of the search input IN corresponding to the word lines WL1_0 and WL2_0 is a common bit. When the voltages provided by the word lines WL1_0 and WL2_0 are both the driving voltage VDH, the bit IN[1] of the search input IN corresponding to the word lines WL1_0 and WL2_0 is an invalid bit.

[0077] In some embodiments, the driving voltage VDL is greater than the threshold voltage VTL and less than the threshold voltage VTH, while the driving voltage VDH is greater than the threshold voltage VTH. In other words, the driving voltage VDH can turn on a transistor having either the threshold voltage VTH or the threshold voltage VTL, while the driving voltage VDL can only turn on a transistor having the threshold voltage VTL but cannot turn on a transistor having the threshold voltage VTH.

[0078] Figure 3C Schematic diagram of the conduction status of a memory cell under different storage data DATA and search input IN according to some embodiments of the present disclosure. Figure 3C , the transistors marked with arrow symbols represent transistors that are turned on, and the transistors marked with cross symbols represent transistors that are turned off.

[0079] For example, when one bit of the stored data DATA is bit 0 and the corresponding bit of the search input IN is also bit 0, the transistor with a threshold voltage VTL in the memory cell will be turned on due to receiving the driving voltage VDH, but the other transistor with a threshold voltage VTH in the memory cell will be turned off due to receiving another driving voltage VDL, thereby turning off the entire memory cell. Vice versa, when one bit of the stored data DATA and the corresponding bit of the search input IN are both bit 1, the memory cell will also be turned off.

[0080] In another example, when a bit of the stored data DATA is bit 0 and the corresponding bit of the search input IN is bit 1, the transistor in the memory cell having a threshold voltage VTL is turned on by receiving the driving voltage VDL, and the other transistor in the memory cell having a threshold voltage VTH is also turned on by receiving the other driving voltage VDH, thereby turning on the memory cell. Conversely, when a bit of the stored data DATA is bit 1 and the corresponding bit of the search input IN is bit 0, the memory cell is also turned on.

[0081] In addition, when one bit of the stored data DATA or the corresponding bit of the search input IN is an invalid bit, the memory cell corresponding to this bit will be turned on; when one bit of the stored data DATA or the corresponding bit of the search input IN is a common bit, the memory cell corresponding to this bit will be turned off.

[0082] According to the above-mentioned configuration method of bit and threshold voltage / driving voltage, the storage data DATA and search input IN can be encoded in different ways. Figures 4A to 4F , Figures 4A to 4F Schematic diagram illustrating the matching between storage data DATA and search input IN according to different embodiments of the present disclosure.

[0083] In some embodiments, at least one of the multiple bits included in each of the stored data DATA1-DATA48 is used as a data bit, at least one of the multiple bits included in the search input IN is used as a search bit, and both the data bit and the search bit are bit 0 or both are bit 1. When the position of the data bit in the stored data DATA overlaps with the position of the search bit in the search input IN, the NAND string storing the stored data DATA is turned off; when the position of the data bit in the stored data DATA does not overlap with the position of the search bit in the search input IN, the NAND string storing the stored data DATA generates an output current Iout.

[0084] by Figure 4A For example, the second bit of the search input IN is set as the search bit and belongs to bit 0, and the other bits of the search input IN are set to invalid bits (marked with the letter "v"); the first bit of the storage data DATA1 is set as the data bit and belongs to bit 0, the second bit of the storage data DATA2 is set as the data bit and belongs to bit 0, the third bit of the storage data DATA3 is set as the data bit and belongs to bit 0, and so on, and the other bits of the storage data DATA1 to DATA48 that are not set as data bits are set to bit 1. Therefore, in Figure 4AIn the embodiment, since the position of the data bit of the storage data DATA2 in the storage data DATA2 overlaps with the position of the search bit in the search input IN (i.e., it is located at the second bit), the NAND string storing the storage data DATA2 will be turned off and the other NAND strings will be turned on. The sensing circuit 120 can then determine that the memory search engine circuit 100 has successfully searched for the NAND string that matches the search input IN.

[0085] Figure 4B Examples and Figure 4A The embodiment is similar to the embodiment of FIG. 1 , except that the other bits in the search input IN that are not set as search bits are set to bit 1, and the other bits in the storage data DATA1 to DATA48 that are not set as data bits are set to invalid bits. Figure 4B Search results for Figure 4A Similar, no repetition here.

[0086] In some embodiments, multiple consecutive bits in the search input IN may also be used as search bits. Figure 4C In the embodiment of the present invention, the first to fourth bits of the search input IN are set as search bits and belong to bit 0, and the other bits of the search input IN are set as invalid bits; the first bit of the storage data DATA1 is set as a data bit and belongs to bit 0, the second bit of the storage data DATA2 is set as a data bit and belongs to bit 0, the third bit of the storage data DATA3 is set as a data bit and belongs to bit 0, and so on, and the other bits of the storage data DATA1 to DATA48 that are not set as data bits are set to bit 1. Therefore, in Figure 4C In the embodiment, since the positions of the data bits of the storage data DATA1~DATA4 in the storage data DATA1~DATA4 overlap with the positions of the search bits in the search input IN (that is, the four data bits of the four storage data overlap with the search bits), the NAND strings storing the storage data DATA1~DATA4 will be turned off and the other NAND strings will be turned on, and the sensing circuit 120 can then determine that the memory search engine circuit 100 has successfully searched for the NAND string that matches the search input IN.

[0087] Figure 4D Examples and Figure 4C The embodiment is similar to the embodiment of FIG. 1 , except that the other bits in the search input IN that are not set as search bits are set to bit 1, and the other bits in the storage data DATA1 to DATA48 that are not set as data bits are set to invalid bits. Figure 4D Search results for Figure 4C Similar, no repetition here.

[0088] In some embodiments, a plurality of consecutive bits in the stored data DATA1 to DATA48 may also be used as data bits. Figure 4E In the embodiment, the second bit of the search input IN is set as the search bit and belongs to bit 0, and the other bits of the search input IN are set as invalid bits; the first to third bits of the storage data DATA1 are set as data bits and belong to bit 0, the first to fourth bits of the storage data DATA2 are set as data bits and belong to bit 0, the first to fifth bits of the storage data DATA3 are set as data bits and belong to bit 0, the second to sixth bits of the storage data DATA4 are set as data bits and belong to bit 0, the third to seventh bits of the storage data DATA5 are set as data bits and belong to bit 0, and so on, and the other bits of the storage data DATA1-DATA48 that are not set as data bits are set to bit 1. Therefore, in Figure 4E In the embodiment, since the positions of the data bits of the storage data DATA1~DATA4 in the storage data DATA1~DATA4 overlap with the positions of the search bits in the search input IN (that is, the search bits overlap with the data bits of the four storage data), the NAND strings storing the storage data DATA1~DATA4 will be turned off and the other NAND strings will be turned on, and the sensing circuit 120 can then determine that the memory search engine circuit 100 has successfully searched for the NAND string that matches the search input IN.

[0089] Figure 4F Examples and Figure 4E The embodiment is similar to the embodiment of FIG. 1 , except that the other bits in the search input IN that are not set as search bits are set to bit 1, and the other bits in the storage data DATA1 to DATA48 that are not set as data bits are set to invalid bits. Figure 4F Search results for Figure 4E Similar, no repetition here.

[0090] It should be noted that Figures 4A to 4F The configuration of bit 0 and bit 1 in the embodiment can be swapped. Figure 4A Taking the embodiment as an example, the search bit in the search input IN and the data bits in the stored data DATA1~DATA48 can belong to bit 1, and the other bits in the stored data DATA1~DATA48 that are not set as data bits are set to bit 0 at this time (the bits in the search input IN originally set as invalid bits are not changed).

[0091] It should be noted that the number of word lines, bit lines, and memory cells in a single NAND string, as well as the number of bits of stored data and search input, in this disclosure are provided for illustrative purposes only and are not intended to limit this disclosure. Other numbers of word lines, bit lines, and memory cells in a single NAND string, as well as the number of bits of stored data and search input, are within the scope of this disclosure. In some embodiments, a single NAND string may include fewer than 48 memory cells, and the stored data and search input may each include fewer than 48 bits. In other embodiments, a single NAND string may include more than 48 memory cells, and the stored data and search input may each include more than 48 bits.

[0092] Figure 5 FIG. 5 is a flow chart of an encoding method 500 of the memory search engine circuit 100 according to some embodiments of the present disclosure. In some embodiments, the encoding method 500 includes steps S510 , S520 , S530 , S540 , S550 , S560 , and S570 .

[0093] In step S510, the memory search engine circuit 100 determines whether to set the data bit of the storage data DATA to bit 0 or bit 1. If the memory search engine circuit 100 determines to set the data bit to bit 0, step S520 is executed; if the memory search engine circuit 100 determines to set the data bit to bit 1, step S550 is executed.

[0094] In step S520, the memory search engine circuit 100 determines whether to set the bits other than the data bits in the stored data DATA to bit 1 or invalid bits. If the memory search engine circuit 100 determines to set the bits other than the data bits in the stored data DATA to bit 1, step S530 is then executed. If the memory search engine circuit 100 determines to set the bits other than the data bits in the stored data DATA to invalid bits, step S540 is then executed.

[0095] In step S530, the memory search engine circuit 100 sets the data bit of the storage data DATA to bit 0, sets the search bit of the search input IN to bit 0, sets the other bits in the storage data DATA to bit 1, and sets the other bits in the search input IN to invalid bits to complete the encoding of the storage data DATA and the search input IN.

[0096] In step S540, the memory search engine circuit 100 sets the data bit of the storage data DATA to bit 0, sets the search bit of the search input IN to bit 0, sets the other bits in the storage data DATA to invalid bits, and sets the other bits in the search input IN to bit 1 to complete the encoding of the storage data DATA and the search input IN.

[0097] In step S550, the memory search engine circuit 100 determines whether to set the bits other than the data bits in the stored data DATA to bit 0 or invalid bits. If the memory search engine circuit 100 determines to set the bits other than the data bits in the stored data DATA to bit 0, step S560 is then executed. If the memory search engine circuit 100 determines to set the bits other than the data bits in the stored data DATA to invalid bits, step S570 is then executed.

[0098] In step S560, the memory search engine circuit 100 sets the data bit of the storage data DATA to bit 1, sets the search bit of the search input IN to bit 1, sets the other bits in the storage data DATA to bit 0, and sets the other bits in the search input IN to invalid bits to complete the encoding of the storage data DATA and the search input IN.

[0099] In step S570, the memory search engine circuit 100 sets the data bit of the storage data DATA to bit 1, sets the search bit of the search input IN to bit 1, sets the other bits in the storage data DATA to invalid bits, and sets the other bits in the search input IN to bit 0 to complete the encoding of the storage data DATA and the search input IN.

[0100] It should be noted that the number and order of steps in encoding method 500 in this disclosure are merely examples and are not intended to limit this disclosure. Other numbers and orders of steps are within the scope of this disclosure. In some embodiments, encoding method 500 may further include step S580. Step S580 is performed after steps S530, S540, S560, and S570. In step S580, memory search engine circuit 100 resets search input IN.

[0101] The memory search engine circuit 100 and encoding method 500 of the present disclosure can determine the search result within the memory by determining the conductivity of the NAND string, instead of determining the search result based on the current level. This avoids the problem of inaccurate judgment due to current level errors, thereby improving the accuracy of the judgment. In addition, the various encoding embodiments of the storage data DATA and the search input IN proposed in the present disclosure also help to increase the flexibility of the encoding process.

[0102] The above are merely preferred embodiments of the present disclosure. Various modifications and equivalent variations may be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In summary, all modifications and equivalent variations made to the present disclosure within the scope of the appended claims are intended to be encompassed by the present disclosure.

Claims

1. A three-dimensional memory array comprising: A plurality of NAND strings, each for storing a storage data comprising a plurality of bits, and for receiving a search input comprising a plurality of bits, wherein the plurality of bits of the storage data and the plurality of bits of the search input are respectively bit 0, bit 1, common bits or invalid bits, wherein at least one of the plurality of bits of the stored data is used as at least one data bit, at least one of the plurality of bits of the search input is used as at least one search bit, and the at least one data bit and the at least one search bit are both bit 0 or both bit 1, When the position of the at least one data bit in the stored data overlaps with the position of the at least one search bit in the search input, at least one of the plurality of NAND strings storing the stored data is turned off, and The at least one of the plurality of NAND strings storing the stored data generates an output current when the position of the at least one data bit in the stored data does not overlap with the position of the at least one search bit in the search input.

2. The three-dimensional memory array according to claim 1 , wherein the at least one data bit and the at least one search bit both belong to bit 0, At least one of the plurality of bits of the stored data that does not belong to the at least one data bit belongs to bit 1, and At least one other bit of the plurality of bits of the search input that does not belong to the at least one search bit belongs to the invalid bit.

3. The three-dimensional memory array according to claim 1 , wherein the at least one data bit and the at least one search bit are both bit 0, At least one of the plurality of bits of the stored data that does not belong to the at least one data bit belongs to the invalid bit, and At least one other bit of the plurality of bits of the search input that does not belong to the at least one search bit belongs to bit 1 .

4. The three-dimensional memory array according to claim 1 , wherein the at least one data bit and the at least one search bit both belong to bit 1, At least one of the plurality of bits of the stored data that does not belong to the at least one data bit belongs to bit 0, and At least one of the plurality of bits of the search input that does not belong to the at least one search bit belongs to the invalid bit.

5. The three-dimensional memory array according to claim 1 , wherein the at least one data bit and the at least one search bit both belong to bit 1, At least one of the plurality of bits of the stored data that does not belong to the at least one data bit belongs to the invalid bit, and At least one of the plurality of bits of the search input that does not belong to the at least one search bit belongs to bit 0.

6. The three-dimensional memory array according to claim 1 , wherein each of the plurality of NAND strings comprises a plurality of memory cells connected in series, the plurality of memory cells corresponding to the plurality of bits of the stored data, respectively. wherein each of the plurality of memory cells comprises a first transistor and a second transistor connected in series along a current direction of the output current, the first transistor and the second transistor having a first threshold voltage or a second threshold voltage, wherein the second threshold voltage is greater than the first threshold voltage; When the first transistor and the second transistor of one of the plurality of memory cells have the first threshold voltage and the second threshold voltage, respectively, a corresponding bit corresponding to the one of the plurality of memory cells is bit 0; When the first transistor and the second transistor of the one of the plurality of memory cells have the second threshold voltage and the first threshold voltage, respectively, the corresponding bit corresponding to the one of the plurality of memory cells is bit 1; When the first transistor and the second transistor of the one of the plurality of memory cells both have the second threshold voltage, the corresponding bit corresponding to the one of the plurality of memory cells belongs to the universal bit; and When the first transistor and the second transistor of the one of the plurality of memory cells both have the first threshold voltage, the corresponding bit corresponding to the one of the plurality of memory cells is the invalid bit.

7. The three-dimensional memory array according to claim 6 , wherein the first transistor and the second transistor are respectively configured to receive a first driving voltage and a second driving voltage from a plurality of word lines, the first driving voltage and the second driving voltage corresponding to one of the plurality of bits of the search input. When the one of the plurality of bits of the search input is bit 0, the first driving voltage is greater than the second threshold voltage, and the second driving voltage is greater than the first threshold voltage and less than the second threshold voltage; When the one of the plurality of bits of the search input belongs to bit 1, the first driving voltage is greater than the first threshold voltage and less than the second threshold voltage, and the second driving voltage is greater than the second threshold voltage; When the one of the plurality of bits of the search input belongs to the universal bit, the first driving voltage and the second driving voltage are both greater than the first threshold voltage and less than the second threshold voltage; and When the one of the plurality of bits of the search input is the invalid bit, both the first driving voltage and the second driving voltage are greater than the second threshold voltage.

8. A memory search engine circuit comprising: A three-dimensional memory array includes a plurality of NAND strings, each of the plurality of NAND strings is used to store a storage data including a plurality of bits and is used to receive a search input including a plurality of bits; a plurality of word lines coupled to the plurality of NAND strings of the three-dimensional memory array for transmitting the search input to the plurality of NAND strings; as well as A sensing circuit is coupled to the three-dimensional memory array and is used to generate a search result when receiving an output current. wherein the plurality of bits of the stored data and the plurality of bits of the search input are respectively bit 0, bit 1, general purpose bits or invalid bits, wherein at least one of the plurality of bits of the stored data is used as at least one data bit, at least one of the plurality of bits of the search input is used as at least one search bit, and the at least one data bit and the at least one search bit are both bit 0 or both bit 1, When the position of the at least one data bit in the stored data overlaps with the position of the at least one search bit in the search input, at least one of the plurality of NAND strings storing the stored data is turned off, and The at least one of the plurality of NAND strings storing the stored data generates the output current when the position of the at least one data bit in the stored data does not overlap with the position of the at least one search bit in the search input.

9. The memory search engine circuit according to claim 8, wherein at least two consecutive bits of the plurality of bits of the stored data are used as at least two data bits; or At least two consecutive bits of the plurality of bits of the search input are used as at least two search bits.

10. The memory search engine circuit according to claim 8, wherein the at least one data bit and the at least one search bit are both bit 0, At least one of the plurality of bits of the stored data that does not belong to the at least one data bit belongs to bit 1, and At least one other bit of the plurality of bits of the search input that does not belong to the at least one search bit belongs to the invalid bit.

11. The memory search engine circuit according to claim 8, wherein the at least one data bit and the at least one search bit are both bit 0, At least one of the plurality of bits of the stored data that does not belong to the at least one data bit belongs to the invalid bit, and At least one other bit of the plurality of bits of the search input that does not belong to the at least one search bit belongs to bit 1 .

12. The memory search engine circuit according to claim 8, wherein the at least one data bit and the at least one search bit both belong to bit 1, At least one of the plurality of bits of the stored data that does not belong to the at least one data bit belongs to bit 0, and At least one other bit of the plurality of bits of the search input that does not belong to the at least one search bit belongs to the invalid bit.

13. The memory search engine circuit according to claim 8, wherein the at least one data bit and the at least one search bit both belong to bit 1, At least one of the plurality of bits of the stored data that does not belong to the at least one data bit belongs to the invalid bit, and At least one of the plurality of bits of the search input that does not belong to the at least one search bit belongs to bit 0.

14. The memory search engine circuit according to claim 8, wherein each of the plurality of NAND strings comprises a plurality of memory cells connected in series, the plurality of memory cells respectively corresponding to the plurality of bits of the stored data, wherein each of the plurality of memory cells comprises a first transistor and a second transistor connected in series along a current direction of the output current, the first transistor and the second transistor having a first threshold voltage or a second threshold voltage, wherein the second threshold voltage is greater than the first threshold voltage; When the first transistor and the second transistor of one of the plurality of memory cells have the first threshold voltage and the second threshold voltage, respectively, a corresponding bit corresponding to the one of the plurality of memory cells is bit 0; When the first transistor and the second transistor of the one of the plurality of memory cells have the second threshold voltage and the first threshold voltage, respectively, the corresponding bit corresponding to the one of the plurality of memory cells is bit 1; When the first transistor and the second transistor of the one of the plurality of memory cells both have the second threshold voltage, the corresponding bit corresponding to the one of the plurality of memory cells belongs to the universal bit; and When the first transistor and the second transistor of the one of the plurality of memory cells both have the first threshold voltage, the corresponding bit corresponding to the one of the plurality of memory cells is the invalid bit.

15. The memory search engine circuit of claim 14 , wherein the first transistor and the second transistor are respectively configured to receive a first driving voltage and a second driving voltage from the plurality of word lines, the first driving voltage and the second driving voltage corresponding to one of the plurality of bits of the search input. When the one of the plurality of bits of the search input is bit 0, the first driving voltage is greater than the second threshold voltage, and the second driving voltage is greater than the first threshold voltage and less than the second threshold voltage; When the one of the plurality of bits of the search input belongs to bit 1, the first driving voltage is greater than the first threshold voltage and less than the second threshold voltage, and the second driving voltage is greater than the second threshold voltage; When the one of the plurality of bits of the search input belongs to the universal bit, the first driving voltage and the second driving voltage are both greater than the first threshold voltage and less than the second threshold voltage; and When the one of the plurality of bits of the search input is the invalid bit, both the first driving voltage and the second driving voltage are greater than the second threshold voltage.

16. An encoding method, applied to a memory search engine circuit, wherein the memory search engine circuit comprises a plurality of NAND strings, wherein the plurality of NAND strings are configured to receive a search input comprising a plurality of bits, the encoding method comprising: storing a storage data including a plurality of bits through each of the plurality of NAND strings, wherein at least one of the plurality of bits of the storage data is used as at least one data bit; and setting the plurality of bits of the search input by the memory search engine circuit, wherein at least one of the plurality of bits of the search input is used as at least one search bit, wherein the plurality of bits of the stored data and the plurality of bits of the search input are respectively bit 0, bit 1, general purpose bits or invalid bits, In response to the at least one data bit in the stored data overlapping with the at least one search bit in the search input, at least one of the plurality of NAND strings storing the stored data is turned off, In response to a position of the at least one data bit in the stored data not overlapping with a position of the at least one search bit in the search input, the at least one of the plurality of NAND strings storing the stored data generates an output current.

17. The encoding method according to claim 16, wherein storing the stored data including the plurality of bits by each of the plurality of NAND strings comprises: The at least one data bit is set to bit 0, and at least one other bit of the plurality of bits of the stored data that does not belong to the at least one data bit is set to an invalid bit, and Setting the plurality of bits of the search input by the memory search engine circuit comprises: The at least one search bit is set to bit 0, and at least one other bit of the plurality of bits of the search input that does not belong to the at least one search bit is set to bit 1.

18. The encoding method according to claim 16, wherein storing the stored data including the plurality of bits by each of the plurality of NAND strings comprises: The at least one data bit is set to bit 0, and at least one other bit of the plurality of bits of the stored data that does not belong to the at least one data bit is set to bit 1, and Setting the plurality of bits of the search input by the memory search engine circuit comprises: The at least one search bit is set to bit 0, and at least one other bit of the plurality of bits of the search input that does not belong to the at least one search bit is set to an invalid bit.

19. The encoding method according to claim 16, wherein storing the stored data including the plurality of bits by each of the plurality of NAND strings comprises: The at least one data bit is set to bit 1, and at least one other bit of the plurality of bits of the stored data that does not belong to the at least one data bit is set to an invalid bit, and Setting the plurality of bits of the search input by the memory search engine circuit comprises: The at least one search bit is set to bit 1, and at least one other bit of the plurality of bits of the search input that does not belong to the at least one search bit is set to bit 0.

20. The encoding method according to claim 16, wherein storing the stored data including the plurality of bits by each of the plurality of NAND strings comprises: The at least one data bit is set to bit 1, and at least one other bit of the plurality of bits of the stored data that does not belong to the at least one data bit is set to bit 0, and Setting the plurality of bits of the search input by the memory search engine circuit comprises: The at least one search bit is set to bit 1, and at least one other bit of the plurality of bits of the search input that does not belong to the at least one search bit is set to an invalid bit.

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