Reconfigurable tap finite impulse response filter device based on random calculation

Abstract

The invention relates to a random calculation-based reconfigurable tap finite impulse response filter device, which supports a user to dynamically configure a tap starting state and a filtering weight, and realizes symbol-perceived bit stream coding through external random number driving. A dynamically reconstructed multi-stage MUX weighting path is combined, so that the filtering task requirements in which different taps participate are effectively met; and the integrator performs statistical estimation on the weighting result and outputs a filtering result. The whole process realizes closed-loop control through software and hardware cooperation and state management, has good flexibility and resource efficiency, and is suitable for a multi-mode low-power-consumption signal processing scene.

Description

Technical Field

[0001] The invention belongs to the technical field of low-resource reconfigurable digital filters and relates to a reconfigurable tap finite impulse response filter device based on random calculation. Background Art

[0002] Finite impulse response (FIR) filters, as an important fundamental operator in signal processing, are widely used in scenarios such as audio processing, image filtering, and communication systems. Their inherent stability, linear phase characteristics, and ease of hardware implementation make them key modules for many real-time processing tasks. However, traditional FIR filters typically rely on multiplier arrays and high-precision arithmetic logic, resulting in high hardware resource consumption in multi-tap, high-order designs, making them particularly difficult to deploy in resource-constrained edge computing and low-power devices.

[0003] In recent years, stochastic computing (SC) has become an important research area for digital filter structure optimization due to its low resource usage, simple logical structure, and strong soft error resilience. SC-based FIR filters (SC-FIR) replace traditional multiplication-addition units by using bitstream encoding and probabilistic logic operations, significantly reducing reliance on multipliers and wide bit buses, improving resource utilization and fault tolerance. This type of structure has been validated in selected studies, demonstrating a good balance between resource and accuracy.

[0004] However, existing SC-FIR filters generally adopt a fixed-length fixed-tap design, which makes it difficult to dynamically adjust the number and layout of taps according to different task requirements. This rigid structure not only limits resource utilization, but also reduces adaptability and scalability in multi-mode and multi-specification signal processing, making it difficult to meet the needs of flexible deployment and performance tuning.

[0005] Therefore, it is necessary to develop a reconfigurable SC-FIR filter structure that can support dynamic configuration of the number of taps and path reconstruction, while maintaining the advantages of random computing resources, improving the structural flexibility and adaptability, and meeting the comprehensive requirements of resources, performance and energy efficiency for diverse signal processing tasks. Summary of the Invention

[0006] In response to the problems existing in the above-mentioned traditional technologies, the present invention proposes a reconfigurable tapped finite impulse response filter device based on random computing, which can meet the comprehensive requirements of resources, performance and energy efficiency of diversified signal processing tasks.

[0007] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: Provided is a reconfigurable tap finite impulse response filter device based on random computing, comprising a tap configuration control module, a bit stream encoding module, a symbol processing module, a multi-stage unbalanced MUX tree weighting module, an integrator and an output estimation module; The tap configuration control module includes a configuration register, a state machine, a trigger detection module, a control command register, and an output result register. The configuration register is used to dynamically enable or disable each tap path of the multi-level unbalanced MUX tree weighting module according to external instructions, and adjust the number and layout structure of taps involved in the filtering calculation. The state machine is used to control the operation of the filter device. The trigger detection module is used to detect the configuration enable signal transmitted by the main control through register-level interaction. The control command register is used to store the start signal and status signal. The output result register is used to store the filtering result. The bitstream encoding module is used to receive a random number stream provided externally, and then generate a symbol-aware bitstream through unsigned number mapping and random number comparison. The symbol processing module is used to decide whether to invert the symbol-aware bitstream based on the configured tap sign bit. The multi-level unbalanced MUX tree weighting module is used to weightedly combine the symbol-aware bitstream passing through the symbol processing module according to the configured weight path. The integrator and output estimation module is used to perform window integration on the output bitstream of the multi-level unbalanced MUX tree weighting module to obtain a probability estimation of the filtering result.

[0008] In one embodiment, the configuration register includes an input configuration register, a tap configuration register, and a coefficient configuration register. The input configuration register is used to slide write window data, the tap configuration register is used to store tap configuration, indicating the selection of enabled tap paths, and the coefficient configuration register is used to store weight configuration, indicating the weights of the taps in the multi-stage unbalanced MUX tree weighting module.

[0009] In one embodiment, the multi-stage unbalanced MUX tree weighting module is a three-stage reconfigurable MUX tree, including four first-stage dual-input MUXs, two second-stage dual-input MUXs, and a third-stage dual-input MUX.

[0010] In one embodiment, the control signal of each stage of the MUX in the multi-stage unbalanced MUX tree weighting module is determined by the ratio of the absolute weights of adjacent taps or combined taps.

[0011] In one embodiment, the state machine is a three-state finite state machine, including an idle state, a configuration state, and a calculation state.

[0012] In one embodiment, the reconfigurable tapped finite impulse response filter device is implemented in an FPGA.

[0013] One of the above technical solutions has the following advantages and beneficial effects: This reconfigurable tapped finite impulse response filter device, based on random computation, supports dynamic user configuration of tap activation states and filter weights, achieving symbol-aware bitstream encoding through external random number drivers. Combined with a dynamically reconfigured multi-stage MUX weighted path, it effectively adapts to filtering tasks involving different taps. An integrator statistically estimates the weighted results and outputs the filtering result. The entire process achieves closed-loop control through software and hardware collaboration and state management, offering excellent flexibility and resource efficiency, making it suitable for multi-mode, low-power signal processing scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 1 is a schematic diagram of the overall architecture of a reconfigurable tapped finite impulse response filter device based on stochastic calculation in one embodiment; Figure 2 A schematic diagram of the structure of a comparator in one embodiment; Figure 3 Schematic diagram of symbol processing, multi-stage unbalanced MUX tree weighting, and reconfigurable tap control mechanism in one embodiment; Figure 4 1 is a schematic diagram of state transition of a reconfigurable tapped finite impulse response filter device based on random calculation in one embodiment; Figure 5 Schematic diagram of register level configuration and complete filtering process in one embodiment. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0017] It should be noted that, when the present invention refers to an "embodiment", it means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The display of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described in the present invention may be combined with other embodiments. The term "and / or" used in the description of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0018] The following describes the implementation of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0019] In one embodiment, Figure 1 As shown, a reconfigurable tapped finite impulse response filter device based on stochastic computing is provided, comprising a tap configuration control module, a bitstream encoding module, a symbol processing module, a multi-stage unbalanced MUX tree weighting module, an integrator, and an output estimation module. The tap configuration control module includes a configuration register, a state machine, a trigger detection module, a control command register, and an output result register. The configuration register is used to dynamically enable or disable each tap path of the multi-stage unbalanced MUX tree weighting module based on external instructions, adjusting the number and layout structure of taps involved in the filtering calculation. The state machine is used to control the operation of the filter device. The trigger detection module is used to detect the configuration enable signal transmitted by the main control through register-level interaction. The control command register is used to store the start signal and status signal. The output result register is used to store the filtering result. The bitstream encoding module is used to receive a random number stream provided externally, and then generate a symbol-aware bitstream through unsigned number mapping and random number comparison. The symbol processing module is used to decide whether to invert the symbol-aware bitstream based on the configured tap sign bit. The multi-level unbalanced MUX tree weighting module is used to weightedly combine the symbol-aware bitstream passing through the symbol processing module according to the configured weight path. The integrator and output estimation module is used to perform window integration on the output bitstream of the multi-level unbalanced MUX tree weighting module to obtain a probability estimation of the filtering result.

[0020] As can be understood, the tap configuration control module serves as the filter entry configuration unit, allowing users to dynamically enable or disable each tap path based on task requirements (or external instructions) through the configuration register interface, flexibly adjusting the number and layout of taps involved in the filter calculation. Specific implementations include tap number reconstruction (to achieve filter adjustment from low-order to high-order), path structure reconstruction (dynamically adjusting the MUX tree depth and branching structure to adapt to different resource and performance requirements), and coefficient and input configuration (receiving filter coefficients and input data to adapt to various signal processing tasks).

[0021] The bitstream encoding module is used to receive a high-quality random number stream provided by an external source (such as a linear feedback shift register (LFSR) and a physical entropy source (MTJ) magnetic tunnel junction); map the input signal to a probability threshold, and generate a symbol-aware bitstream through random number comparison.

[0022] The symbol processing module is used to positively and negatively regulate the symbol-aware bit stream according to the tap coefficients, and supports bipolar weighted operations to improve the filter's adaptability to positive and negative weights.

[0023] The multi-level unbalanced MUX tree weighting module is used to dynamically reconstruct the multi-level MUX tree structure according to the tap configuration results; the weighted combination of the tap bit stream is realized through the probability control signal, completing the random calculation equivalent implementation of the filter multiplication and addition operation.

[0024] The integrator and output estimation module is used to perform multi-cycle integration and estimation on the output bit stream of the MUX tree to achieve statistical approximation of the numerical output; it adopts fixed-point hold and sliding window mechanisms to balance calculation accuracy and delay overhead.

[0025] It should be noted that the improvements in this embodiment do not involve the internal structure of the random number generator, but are based on external high-quality random source input, such as a physical entropy source like an MTJ magnetic tunnel junction. Taps, weights, and inputs are dynamically configured by the user through a configuration register interface to accommodate diverse filtering tasks. The overall architecture supports multi-mode, customizable filtering through software and hardware collaboration to accommodate diverse signal processing needs. Furthermore, no resynthesis or layout is required, enhancing the system's flexibility and adaptability.

[0026] The above-mentioned reconfigurable tapped finite impulse response filter device based on random calculation can be divided into three paths: a data path (including (input bit stream) comparator, symbol processing layer, multi-level MUX weighted tree and integrator in sequence, used to complete random encoding, symbol control, weighted calculation and integral estimation of input data), a control path (including state machine and trigger detection module, used to manage module state transfer and calculation process control) and a communication path (including various configuration registers, control command registers and output result registers, used to realize interface interaction with the main control software).

[0027] like Figure 2As shown, the input data first undergoes random encoding via a comparator. Specifically, the input signal X_IN is a signed fixed-point number in Q1.15 format (a commonly used signed fixed-point representation method, part of the Q-format fixed-point system), with a range of [-1, 1). Its value is represented in two's complement binary notation. To achieve symmetric probabilistic encoding, the input signal X_IN must be uniformly mapped to an unsigned number. The mapping formula is as follows: threshold = (X_IN + 0x8000) >> k, where 0x8000 shifts the Q1.15 signed fixed-point number to unsigned form. k represents the bit width parameter used to truncate the high-order bits for comparison accuracy. Here, k = 8, corresponding to an 8-bit random number (i.e., rns[7:0]), maps the input signal X_IN to the probability domain of [0, 255]. Figure 2 In the , RNG is a random number generator, and TH generation means threshold generation.

[0028] The generated unsigned number threshold is compared with the random number rns of the same width. If the random number rns is less than the unsigned number threshold, the output bit is 0 (indicating +1), otherwise the output bit is 1 (indicating -1), and a sign-aware bit stream is obtained, thereby realizing probability-based sign-aware coding.

[0029] The converted symbol-aware bit stream passes through the symbol processing layer (i.e., the symbol processing module, such as Figure 3 As shown, a conventional simple exclusive OR gate XOR is used to decide whether to invert the bit stream according to the configured tap sign bit.

[0030] Then the symbol-aware bitstream processed by the symbol processing layer passes through a dynamically reconstructed multi-level MUX tree (such as Figure 3 The output bit stream Y is finally sent to the integrator to complete the window integration and obtain the probability estimation of the filtering result.

[0031] Compared to existing technologies, this reconfigurable tapped finite impulse response filter device based on random computation supports dynamic user configuration of tap activation states and filter weights, enabling symbol-aware bitstream encoding through external random number drive. Combined with a dynamically reconfigured multi-stage MUX weighted path, it effectively adapts to filtering tasks involving different taps. An integrator statistically estimates the weighted results and outputs the filtered result. The entire process achieves closed-loop control through software and hardware collaboration and state management, offering excellent flexibility and resource efficiency, making it suitable for multi-mode, low-power signal processing scenarios.

[0032] In one embodiment, the reconfigurable tapped finite impulse response filter device is implemented on an FPGA.

[0033] It can be understood that in this embodiment, the implementation method of the above-mentioned reconfigurable tapped finite impulse response filter device based on random calculation based on the FPGA platform may include: Hardware structure configuration: Based on the random computing logic and reconfigurable tap architecture design, the corresponding RTL (Register-Transfer Level Description) is generated and deployed on the FPGA. It is an abstract modeling method in digital circuit design that describes the logical behavior of circuits transferring data between registers and is the key link between hardware architecture design and specific gate-level circuit implementation.

[0034] Register interface design: Provides a configuration register interface to support software dynamic setting of tap enable status, MUX tree structure, and filter coefficients.

[0035] Software-hardware collaborative control: The Zynq SoC platform's PS-side software configures the PL-side filtering structure (i.e., the ARM processor (PS, Processing System) runs the software code to dynamically configure the digital filter circuit in the FPGA logic part (PL, Programmable Logic)), achieving real-time reconstruction and dynamic loading.

[0036] Compared with the existing SC-FIR filter, the above-mentioned reconfigurable tapped finite impulse response filter device based on random computing has the following advantages: flexible structure, supports dynamic trimming and reconstruction, and adapts to changing application requirements; resource efficiency, enables taps and paths on demand, and avoids unnecessary waste of resources; easy integration, based on the standard APB interface, supports software and hardware collaboration and platform adaptation; maintains advantages and inherits the low power consumption and high fault tolerance characteristics of random computing.

[0037] In one embodiment, the multi-stage unbalanced MUX tree weighting module is a three-stage reconfigurable MUX tree, including four first-stage dual-input MUXs, two second-stage dual-input MUXs, and a third-stage dual-input MUX.

[0038] It can be understood that in the above data path, the unbalanced multi-level MUX tree assumes the function of reconstructing the multiplication and addition structure using the random computing idea. Figure 3 As shown in the figure, this multi-stage MUX tree structure is based on a three-stage reconfigurable MUX tree weighting mechanism. It includes eight sign-aware bitstream inputs (from input bitstream x_in_0 to input bitstream x_in_7). After sign bit inversion (from sign bit Sign(H0) to sign bit Sign(H7)) to adjust the sign direction, the inputs are fed into four first-stage dual-input MUXs (Mux0 through Mux3). H0 through H7 represent the tap coefficients, which can be configured by the user through the APB interface.

[0039] The first-stage dual-input MUX combines two adjacent inputs and outputs four weighted results (i.e., m0 to m3) to the second-stage two dual-input MUXs (including Mux4 and Mux5), which are then combined into two intermediate results (i.e., m4 and m5). Finally, the third-stage MUX6 summarizes and outputs the final result (i.e., output bit stream Y).

[0040] The reconfigurability of the multi-level MUX tree structure is reflected in: 1. Enable tap control: This means that the number of enabled input channels can be dynamically configured by software through the configuration register interface. Here, we take enabling x_in_0, x_in_1, x_in_2, x_in_4, and x_in_5, and disabling x_in_3, x_in_6, and x_in_7 as an example: The first-level MUX behavior analysis is as follows: MUX0: Both inputs x_in_0 and x_in_1 are enabled. Normal operation, with probabilistic selection based on control signal W0 (weight).

[0041] MUX1: x_in_2 is enabled, x_in_3 is disabled. This degenerates into a straight-through path, directly sending the output of XOR2 to MUX4 without the need for probabilistic selection.

[0042] MUX2: Inputs x_in_4 and x_in_5 are both enabled. Normal operation, with probabilistic selection based on control signal W2.

[0043] MUX3: x_in_6 and x_in_7 are both disabled. They are completely disabled and do not participate in any subsequent operations.

[0044] The second-level MUX behavior analysis is as follows: MUX4: Inputs come from both MUX0 (enabled) and MUX1 (degenerate pass-through). Normal operation, with probabilistic selection based on control signal W4.

[0045] MUX5: Only MUX2 has valid input, MUX3 has no valid input. It degenerates into a straight-through path, directly sending the output of MUX2 to MUX6.

[0046] The third-level MUX behavior analysis is as follows: MUX6: It has inputs from both MUX4 and MUX5. It operates normally and makes the final probability selection based on the control signal W6.

[0047] 2. Weights are updated on demand: that is, the control signals W0 to W6 can be recalculated by software based on the currently enabled taps and coefficients to ensure that the MUX weighted path is consistent with actual needs.

[0048] Furthermore, the control signal of each level of MUX in the multi-level unbalanced MUX tree weighting module is determined by the ratio of absolute weights of adjacent taps or combined taps.

[0049] It can be understood that for each level of MUX, its control signal Determined by the ratio of the absolute weights of adjacent taps or combined taps, continuing with the above example, the following is the weight update calculation formula for the corresponding MUX: MUX0's (weight) control signal W0:

[0050] MUX2's (weight) control signal W2:

[0051] MUX4's (weight) control signal W4:

[0052] MUX6 (weight) control signal W6:

[0053] Advantages: Flexible configurations from 2 to 8 taps are supported to meet diverse filtering requirements. The system retains its original advantages of low power consumption and high fault tolerance. It also improves adaptability and scalability, making it suitable for multi-mode, customizable signal processing applications.

[0054] In one embodiment, the state machine is a three-state finite state machine including an idle state, a configuration state, and a calculation state.

[0055] like Figure 4 Specifically, the reconfigurable tapped finite impulse response filter device based on random computing is controlled by a three-state finite state machine (FSM), including: 1. Idle state (IDLE), in which the filter device is in standby mode, awaiting configuration instructions, with no computational activity, and maintaining low resource consumption. 2. Configuration state (CONFIG), in which the device responds to the configuration enable signal sent by the master control via the APB3.0 interface to load parameters such as tap enable status, weight coefficients, symbol information, and input data. After configuration is complete, the device waits for a start signal to enter calculation. 3. Calculation state (CALC), in which the device enters the calculation state upon receiving a start signal (FIRE); bitstream generation, symbol processing, MUX weighting, and integral estimation are automatically completed. After calculation is complete, the data ready signal (data_ready) is set to 1 (valid) to notify the master control to read the filtering results. A status signal PRESETn = 0 indicates configuration loading.

[0056] The above-mentioned master control and the reconfigurable tap finite impulse response filter device based on random calculation interact at the register level, and can be operated as follows: Figure 5 The following flow completes a complete filtering task: 1. Configuration and Enable: Write a level 1 to the register enable (CONFIG_EN) register to enter the configuration state. 2. Tap and Weight Configuration: Write to the tap configuration register to select the tap path to enable (e.g., enable x_in_0, x_in_1, x_in_2, x_in_4, and x_in_5). Calculate the W0-W6 (weight) control signals and write them to the coefficient (weight) configuration register. Extract the highest bit of the coefficient and write it to the sign control register (in the control command register) to configure the tap sign bit. 3. Input Data Loading: Slide the window data into the input configuration register. 4. Start the calculation: Write a level 1 to the fire register to start the calculation state. 5. Read the result: Poll the data_ready signal in the status (STATUS) register. When the data_ready signal is set, read the output result (DATA_OUT) register to obtain the filtering result.

[0057] Taking the activation of five taps (e.g., x_in_0, x_in_1, x_in_2, x_in_4, and x_in_5) as an example, the specific operations are as follows: The master controller enters the configuration state via the CONFIG_EN trigger; the taps are enabled (enabling corresponds to five taps); weight and sign information are uploaded, W0 through W6 are calculated according to the weight update formula described above, and written to the coefficient configuration register. The five input data of the sliding window are continuously transferred to the input configuration register. The FIRE trigger initiates the calculation, and the reconfigurable tapped finite impulse response filter device based on random calculation automatically operates according to the state machine. The STATUS register is polled until the data_ready bit is set. The filtering results are read, completing the filtering task.

[0058] The entire process does not require user intervention in the data path and control logic. It only requires register-level configuration and startup. The reconfigurable tapped finite impulse response filter device based on random computing can independently complete the complete software and hardware collaborative computing closed loop.

[0059] The reconfigurable tapped finite impulse response filter device based on stochastic computation consists of three parts: a data path, a control path, and a communication path. The communication path provides a register interface, supporting input configuration, structural reconstruction, and result interaction. The data path integrates symbol-aware probability coding, multi-stage MUX imbalance weighting, and integral estimation functions. The control path is responsible for state management and operation scheduling. It supports dynamic user configuration of tap enable states and filter weights, and implements symbol-aware bitstream encoding through an external random number driver. Combined with a dynamically reconfigurable multi-stage MUX weighting path, it effectively adapts to the filtering tasks involving different taps. The integrator performs statistical estimation on the weighted results and outputs the filtering result. The entire process achieves closed-loop control through software and hardware collaboration and state management, offering excellent flexibility and resource efficiency, making it suitable for multi-mode, low-power signal processing scenarios.

[0060] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0061] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of the present invention.

Claims

1. A reconfigurable tapped finite impulse response filter device based on random computing, characterized in that: It includes tap configuration control module, bit stream encoding module, symbol processing module, multi-level unbalanced MUX tree weighting module, integrator and output estimation module; The tap configuration control module includes a configuration register, a state machine, a trigger detection module, a control command register, and an output result register. The configuration register is used to dynamically enable or disable each tap path of the multi-level unbalanced MUX tree weighting module according to external instructions, and adjust the number and layout structure of taps involved in the filtering calculation. The state machine is used to control the operation of the filter device. The trigger detection module is used to detect the configuration enable signal transmitted by the main control through register-level interaction. The control command register is used to store the start signal and status signal. The output result register is used to store the filtering result. The bitstream encoding module is used to receive a random number stream provided externally, and then generate a symbol-aware bitstream through unsigned number mapping and random number comparison. The symbol processing module is used to decide whether to invert the symbol-aware bitstream based on the configured tap sign bit. The multi-level unbalanced MUX tree weighting module is used to weightedly combine the symbol-aware bitstream passing through the symbol processing module according to the configured weight path. The integrator and output estimation module is used to perform window integration on the output bitstream of the multi-level unbalanced MUX tree weighting module to obtain a probability estimation of the filtering result.

2. The reconfigurable tap finite impulse response filter device based on random calculation according to claim 1, characterized in that: The configuration register includes an input configuration register, a tap configuration register and a coefficient configuration register. The input configuration register is used to slide write window data, the tap configuration register is used to store tap configuration, indicating the selection of enabled tap path, and the coefficient configuration register is used to store weight configuration, indicating the weight of the tap in the multi-level unbalanced MUX tree weighting module.

3. The reconfigurable tap finite impulse response filter device based on random calculation according to claim 1 or 2, characterized in that: The multi-level unbalanced MUX tree weighting module is a three-level reconfigurable MUX tree, including four first-level dual-input MUXs, two second-level dual-input MUXs and a third-level dual-input MUX.

4. The reconfigurable tap finite impulse response filter device based on random calculation according to claim 3, characterized in that: The control signal of each level of MUX in the multi-level unbalanced MUX tree weighting module is determined by the ratio of the absolute weights of adjacent taps or combined taps.

5. The reconfigurable tap finite impulse response filter device based on random calculation according to claim 1, characterized in that: The state machine is a three-state finite state machine, including idle state, configuration state and calculation state.

6. The reconfigurable tap finite impulse response filter device based on random calculation according to claim 1, characterized in that: The reconfigurable tap finite impulse response filter device is deployed on an FPGA.

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