Data verification method and device, electronic equipment and storage medium

Abstract

The invention provides a data verification method and device, electronic equipment and a storage medium. The method comprises the following steps: receiving first data; performing initialization setting on the code word and the verification result corresponding to the first data to obtain an initial code word and an initial verification result, and receiving second data at the same time; the first data is current to-be-verified data, and the second data is next to-be-verified data after the first data; performing LDPC (Low Density Parity Check) code increment check on the first data based on the initial code word and the initial check result to obtain a target code word and a target check result; and outputting the target code word in response to the fact that the target code word meets a set first condition and the target verification result meets a set second condition. By means of the data verification method and device, the data verification efficiency can be improved, and the data verification logic is simplified.

Description

Technical Field

[0001] The present application relates to the field of data verification technology, and in particular to a data verification method, device, electronic device and storage medium. Background Art

[0002] Traditional data verification methods typically require a one-time verification of the complete data. When processing large amounts of data or requiring high real-time performance, this complete data verification results in long wait times and high computing resource usage, impacting overall data verification efficiency. Consequently, traditional data verification methods lack flexibility, fail to fully utilize data processing time and resources, and suffer from low data verification efficiency and logical redundancy. Summary of the Invention

[0003] Embodiments of the present application provide a data verification method, device, electronic device, and storage medium.

[0004] According to a first aspect of the present application, a data verification method is provided, the method comprising: receiving first data; initializing a codeword and a verification result corresponding to the first data to obtain an initial codeword and an initial verification result, and simultaneously receiving second data; the first data is current data to be verified, and the second data is next data to be verified after the first data; based on the initial codeword and the initial verification result, performing an LDPC low-density parity check code incremental verification on the first data to obtain a target codeword and a target verification result; in response to the target codeword satisfying a set first condition and the target verification result satisfying a set second condition, outputting the target codeword.

[0005] According to one embodiment of the present application, the codeword and verification result corresponding to the first data are initialized to obtain the initial codeword and the initial verification result, including: obtaining a virtual codeword and a virtual verification result corresponding to the virtual codeword; based on the virtual codeword and the virtual verification result, the codeword and verification result corresponding to the first data are initialized to obtain the initial codeword and the initial verification result; the initial codeword is an all-zero codeword, and the initial verification result is an all-zero verification result.

[0006] According to one embodiment of the present application, based on the initial codeword and the initial check result, the first data is incrementally checked with an LDPC low-density parity-check code to obtain a target codeword and a target check result, including: determining the LDPC check matrix corresponding to the first data based on the number of codewords of the first data; based on the LDPC check matrix and the first data, iteratively updating the initial codeword and the initial check result through a row layered decoding algorithm to obtain the target codeword and the target check result.

[0007] According to one embodiment of the present application, determining the LDPC check matrix corresponding to the first data based on the number of codewords of the first data includes: determining the LDPC check matrix corresponding to the first data from multiple preset LDPC check matrices based on the number of codewords of the first data; the LDPC check matrix includes at least a sub-check matrix, and the sub-check matrix includes a non-zero matrix and a zero matrix; the number of sub-check matrices included in each row of the LDPC check matrix is the same as the number of codewords of the first data; each row in the LDPC check matrix corresponds to a check result.

[0008] According to one embodiment of the present application, based on the LDPC check matrix and the first data, the initial codeword and the initial check result are iteratively updated through a row layered decoding algorithm to obtain the target codeword and the target check result, including: traversing the non-zero matrix in the LDPC check matrix according to a set calculation order, and based on the first data and each non-zero matrix in each row, calculating the change in the codeword corresponding to the non-zero matrix relative to the codeword at the last iteration.

[0009] The codeword is iteratively updated based on the variation, and the verification result associated with the codeword is synchronously iteratively updated to obtain the target codeword and target verification result.

[0010] According to one embodiment of the present application, the method further includes: configuring a corresponding status register for each codeword of the first data; the status register being in the first state represents that the codeword is an all-zero codeword, and the status register being in the second state represents that the codeword is a non-zero codeword; configuring the initial state of the status register to the first state; and updating the status register to the second state in response to a change in the codeword.

[0011] According to one embodiment of the present application, in response to the target codeword satisfying a set first condition and the target verification result satisfying a set second condition, outputting the target codeword includes: reading a status register corresponding to each of the codewords to obtain a state corresponding to the target codeword; in response to the status registers of all target codewords being in the second state and all target verification results indicating that the verification has passed, outputting the target codeword.

[0012] According to a second aspect of the present application, a data verification device is provided, comprising: a receiving module for receiving first data; an initialization module for initializing a codeword and a verification result corresponding to the first data to obtain an initial codeword and an initial verification result, the receiving module for simultaneously receiving second data; the first data is current data to be verified, and the second data is next data to be verified after the first data; a verification module for performing an LDPC low-density parity check code incremental verification on the first data based on the initial codeword and the initial verification result to obtain a target codeword and a target verification result; and an output module for outputting the target codeword in response to the target codeword satisfying a set first condition and the target verification result satisfying a set second condition.

[0013] According to a third aspect of the present application, an electronic device is provided, including:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method described in this application.

[0017] According to a fourth aspect of the present application, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the method described in the present application.

[0018] The method of an embodiment of the present application receives first data; initializes the codeword and verification result corresponding to the first data to obtain an initial codeword and initial verification result, and simultaneously receives second data; the first data is the current data to be verified, and the second data is the next data to be verified after the first data; based on the initial codeword and initial verification result, the first data is incrementally verified using an LDPC low-density parity check code to obtain a target codeword and a target verification result; and in response to the target codeword satisfying a set first condition and the target verification result satisfying a set second condition, the target codeword is output. In this way, the efficiency of data verification is improved and the logic of data verification is simplified.

[0019] It should be understood that the teachings of this application do not necessarily achieve all of the beneficial effects described above, but that specific technical solutions can achieve specific technical effects, and other embodiments of this application can also achieve beneficial effects not mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present application are shown in an illustrative and non-limiting manner, in which:

[0021] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0022] Figure 1 The processing flow diagram of the data verification method provided in the embodiment of the present application is shown as follows Figure 1 ;

[0023] Figure 2 The processing flow diagram of the data verification method provided in the embodiment of the present application is shown as follows Figure 2 ;

[0024] Figure 3 The processing flow diagram of the data verification method provided in the embodiment of the present application is shown as follows Figure 3 ;

[0025] Figure 4 The processing flow diagram of the data verification method provided in the embodiment of the present application is shown as follows Figure 4 ;

[0026] Figure 5 The processing flow diagram of the data verification method provided in the embodiment of the present application is shown as follows Figure 5 ;

[0027] Figure 6 A schematic diagram of the data verification process of the LDPC codeword provided in an embodiment of the present application is shown;

[0028] Figure 7 The application scenario of the data verification method provided by the embodiment of the present application is shown Figure 1 ;

[0029] Figure 8 The application scenario of the data verification method provided by the embodiment of the present application is shown Figure 2 ;

[0030] Figure 9 The application scenario of the data verification method provided by the embodiment of the present application is shown Figure 3 ;

[0031] Figure 10 An optional schematic diagram of a data verification device provided in an embodiment of the present application is shown;

[0032] Figure 11 An optional schematic diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] In order to make the purpose, features, and advantages of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0034] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0035] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0037] The processing flow of the data verification method provided in the embodiment of the present application is described. Figure 1 , Figure 1 This is a schematic diagram of the processing flow of the data verification method provided in the embodiment of the present application. Figure 1 , will combine Figure 1 Steps S101-S104 are shown for explanation.

[0038] Step S101: receiving first data.

[0039] Step S102, initialize the codeword and verification result corresponding to the first data to obtain the initial codeword and initial verification result, and simultaneously receive the second data; the first data is the current data to be verified, and the second data is the next data to be verified after the first data.

[0040] In some embodiments, the first data may include input data that needs to be verified. The codeword may include: a specific sequence obtained after the first data is encoded. Specifically, the codeword may be an LDPC (Low-Density Parity-Check Code) codeword, which is a linear block code. The verification result may include the result obtained by performing data verification on the first data. The verification result can be used to determine whether there is an error in transmission or storage in the first data. The second data may include: the next set of data to be verified after the first data. In the initial state of the first data, there is no need to perform a complete data verification step. The initialization verification result does not take up the data input time, and the second data can continue to be received when the first data enters the decoding iteration. The data input time can be made to not take up the decoding time.

[0041] Step S103 : Based on the initial codeword and the initial verification result, perform LDPC low-density parity check code incremental verification on the first data to obtain a target codeword and a target verification result.

[0042] In some embodiments, the target codeword may include: a codeword obtained after LDPC incremental verification. The target codeword may specifically include: original data and redundant information added for verification and error correction. The target verification result may include: the verification result obtained during the LDPC incremental verification process. The target verification result can be used to determine whether the first data can pass the LDPC incremental verification. According to the LDPC check matrix, the codeword of the first data and the initial codeword are subjected to matrix operations, and the codeword and verification results corresponding to the first data are gradually iterated and updated to obtain the target codeword and target verification result. During the matrix operation process, each iterative update only calculates the newly added data part, and the result is accumulated to the initial codeword and initial verification result to obtain the target codeword and target verification result.

[0043] Step S104 : In response to the target codeword satisfying the set first condition and the target verification result satisfying the set second condition, outputting the target codeword.

[0044] In some embodiments, the first condition may include a judgment condition set for the target codeword. Specifically, the first condition may include whether the length, format, or value of a specific field of the target codeword meets set requirements. The second condition may include a judgment condition set for a target verification result. Specifically, the second condition may include whether the verification result meets the expected value. The target codeword is output only when both the target codeword and the target verification result meet their respective conditions. The output target codeword is data that has passed data verification.

[0045] The method of the embodiment of the present application improves the efficiency and flexibility of data verification by receiving the second data simultaneously with the first data and performing initialization. By performing initialization simultaneously with data reception, the calculation results can be updated along with the codeword block, simplifying the data verification logic, reducing the data verification waiting time, and making the verification process more compact and efficient.

[0046] In some embodiments, the processing flow of the data verification method is as follows: Figure 2 ,like Figure 2 As shown, the initialization setting of the code word and the verification result corresponding to the first data in step S102 to obtain the initial code word and the initial verification result may include:

[0047] Step S201: Obtain a virtual codeword and a virtual verification result corresponding to the virtual codeword.

[0048] Step S202 : Initializing the code word and the verification result corresponding to the first data based on the virtual code word and the virtual verification result to obtain an initial code word and an initial verification result.

[0049] In this embodiment, the virtual codeword can be a temporarily generated codeword. The virtual codeword can be used as the initial codeword for the LDPC incremental check. The virtual check result can be a check result calculated based on the virtual codeword. The virtual check result can be used as the initial check result for the LDPC incremental check. The virtual codeword can be an all-zero codeword. For an all-zero codeword, the virtual check result calculated by the check matrix corresponding to all LDPC incremental checks must be all zero. Based on the virtual codeword and the virtual check result, the set initial codeword is an all-zero codeword, and the set initial check result is an all-zero check result.

[0050] As an example, based on the obtained virtual codeword and virtual check result, the codeword and check result corresponding to the first data are initialized. In this process, the initial codeword is set to an all-zero codeword, that is, each bit of the initial codeword is 0, and the initial check result is set to an all-zero check result, that is, each check bit of the initial check result is 0.

[0051] The method of the embodiment of the present application obtains an initial codeword and initial verification result by acquiring a virtual codeword and a virtual verification result, wherein the initial codeword is an all-zero codeword and the initial verification result is an all-zero verification result. The all-zero initial codeword and verification result eliminate the need to consider the previous verification status during incremental verification, simplifying the logic of the data verification process and improving the efficiency and flexibility of data verification.

[0052] In some embodiments, the processing flow of the data verification method is as follows: Figure 3 ,like Figure 3As shown, step S103 of performing LDPC low-density parity check code incremental check on the first data based on the initial codeword and the initial check result to obtain the target codeword and the target check result may include:

[0053] Step S301: Determine an LDPC check matrix corresponding to the first data based on the number of codewords of the first data.

[0054] In this embodiment, the number of codewords for the first data may include the number of codewords corresponding to the first data. The LDPC check matrix may include a calculation matrix used for encoding and checking in LDPC incremental check. The LDPC check matrix may be composed of 0s and 1s. The layered decoding algorithm may include layering the LDPC check matrix and performing decoding operations layer by layer, with a check result for each layer.

[0055] In some embodiments, step S301 may include: based on the number of codewords of the first data, determining the LDPC check matrix corresponding to the first data from multiple preset LDPC check matrices. The LDPC check matrix includes at least a sub-check matrix, and the sub-check matrix includes a non-zero matrix and a zero matrix; the number of sub-check matrices included in each row of the LDPC check matrix is the same as the number of codewords of the first data; each row in the LDPC check matrix corresponds to a check result. From multiple pre-stored LDPC check matrices, search and determine an LDPC check matrix that matches the number of codewords. The preset LDPC check matrix may include different numbers of rows, columns, and different check bit distributions. The preset LDPC check matrix may be applicable to different numbers of codewords. The LDPC check matrix of the first data is determined based on the correspondence between the number of codewords of the first data and the number of columns of the check matrix.

[0056] like Figure 6 As shown, the number of codewords for the first data is 5. The blank in the figure is the zero matrix of the LDPC check matrix, H0-H14 is the non-zero matrix of the LDPC check matrix, distributed in different rows and columns of the LDPC check matrix, C0-C5 is the codeword block of the first data, and D0-D3 is the check result block of the first data. Each non-zero matrix corresponds to a codeword block, and each codeword block can correspond to multiple non-zero matrices. For example, C0 corresponds to H0, H8 and H12. Each check result block can correspond to multiple non-zero matrices, for example, D0 corresponds to H0, H1, H2 and H3.

[0057] Step S302 : Based on the LDPC check matrix and the first data, the initial codeword and the initial check result are iteratively updated by a row layered decoding algorithm to obtain a target codeword and a target check result.

[0058] In this embodiment, the row layered decoding algorithm may include: dividing the LDPC check matrix into layers, performing decoding operations layer by layer, and each layer corresponds to a check result.

[0059] In some embodiments, step S301 may include: traversing the non-zero matrices in the LDPC check matrix according to a set calculation order, and calculating the change in the codeword corresponding to the non-zero matrix relative to the codeword at the last iteration based on the first data and each non-zero matrix in each row. Iteratively updating the codeword based on the change, and synchronously iteratively updating the check result associated with the codeword to obtain the target codeword and the target check result. The set calculation order may include: a predefined order for processing the non-zero matrix in the LDPC check matrix. The set calculation order may specifically be calculation by row, by column, or in other specific order.

[0060] As an example, Figure 6 As shown, the first data is verified. After the codewords and verification results corresponding to the first data are initialized, the codewords C0-C5 are all-zero codewords, and the verification results D0-D3 are all-zero verification results.

[0061] According to the calculation order of calculating row by row from H0 to H14, start traversing H0-H14 in the LDPC check matrix, and first calculate the non-zero matrix H0. The system reads the old value C0_o of the codeword C0 (all zeros at this time) and calculates the new value C0_n of C0 based on the first data. Then, the change C0_n-C0_o is calculated. Then, the change C0_n-C0_o is calculated according to the check value update algorithm to obtain the change H0*(C0_n-C0_o) of the check result, and the change of the check result is added to the old value of the corresponding check results D0, D2, and D3 to obtain the new check results D0_n, D2_n, and D3_n. At this time, the codeword C0 is updated to C0_n, and the check results D0, D2, and D3 are also updated synchronously.

[0062] Next, the non-zero matrix H1 is calculated. The system reads the old value C2_o of the codeword C2 (all zeros at this time) and calculates the new value C2_n of C2 based on the first data. The change C2_n-C2_o is calculated, and then the change C2_n-C2_o is calculated according to the check value update algorithm to obtain the change H1*(C2_n-C2_o) of the check result. The change of the check result is added to the old value of the corresponding check results D0 and D2 to obtain the new check results D0_n and D2_n. At this time, the codeword C2 is updated to C2_n, and the check results D0 and D2 are also updated synchronously.

[0063] Continue to calculate other non-zero matrices, such as H2, H3, etc., in the same order. Each time a non-zero block is calculated, the corresponding codeword and verification result are updated according to the above steps.

[0064] In the embodiment of the present application, the corresponding LDPC check matrix is determined by the number of codewords in the first data. The check process can be flexibly adjusted for different data sizes, improving the adaptability of data verification. The use of a row-layered decoding algorithm for iterative updates can more effectively utilize the structural characteristics of the check matrix, reduce computational complexity, speed up verification, and ensure the accuracy of the verification results. In addition, the incremental verification method allows the calculation results to be updated along with the codeword blocks, simplifying the logic of the data verification process and improving the efficiency and flexibility of data verification.

[0065] In some embodiments, the processing flow of the data verification method is as follows: Figure 4 ,like Figure 4 As shown, the data verification method may further include:

[0066] Step S401: configure a corresponding status register for each codeword of the first data.

[0067] Step S402: configure the initial state of the state register to be the first state.

[0068] Step S403: in response to the code word changing, updating the state register to a second state.

[0069] In this embodiment, the status register may include: a register for storing a codeword state. The status register may be used to indicate the current state of the codeword. The status register being in the first state may indicate that the codeword is an all-zero codeword, and the status register being in the second state may indicate that the codeword is a non-zero codeword. Configuring the initial state of the status register to the first state may include: before starting the LDPC incremental check, initializing the status registers corresponding to all codewords to the first state indicating an all-zero codeword. In response to a change in the codeword, updating the status register to the second state may include: when the value of the codeword changes from all zeros to non-zero, updating the status register corresponding to the codeword to the second state indicating a non-zero codeword.

[0070] As an example, Figure 6 As shown, the first data is divided into multiple code words, including: C0, C1, C2, C3, C4, C5, etc. An independent state register is designed for each code word, and the bit width of each state register is 1 bit. When the code word is initialized, the initial state of the state register is configured as the first state, and all state registers are configured to 0, indicating that the code word is an all-zero code word. According to the set calculation order, the non-zero matrix blocks in the LDPC check matrix are traversed. For Figure 6For the LDPC parity check matrix in [1], the first parity check matrix blocks corresponding to all codewords are: H0, H4, H1, H2, H6, and H3. When updating to a corresponding codeword, if the status register is 0, the old value of the codeword is directly set to 0 without reading the old value. After the codeword update is complete, the status register corresponding to the codeword is updated to 1, indicating that the old value of the codeword is no longer 0.

[0071] In the embodiments of the present application, the status register can be used to determine whether each codeword is currently in an all-zero or non-zero state. This state management mechanism can quickly determine which codewords have changed and which codewords remain in their initial state, thereby more accurately assessing the data verification status of the entire data when determining the verification results. This simplifies the logic of the data verification process and improves the efficiency and flexibility of data verification.

[0072] In some embodiments, the processing flow of the data verification method is as follows: Figure 5 ,like Figure 5 As shown, in step S104, in response to the target codeword satisfying the set first condition and the target verification result satisfying the set second condition, outputting the target codeword may include:

[0073] Step S501 , reading the status register corresponding to each codeword to obtain the status corresponding to the target codeword.

[0074] Step S502 : In response to the state registers of all target codewords being in the second state and all target verification results indicating verification passing, output the target codeword.

[0075] In this embodiment, after all codewords have completed a round of updates, the values of all status registers corresponding to the target codeword are detected. If the values of all status registers are updated to 1, it means that the old values of all target codewords are no longer 0. At this time, the target verification result no longer contains virtual codewords, and the verification result is available. It is further determined whether the target verification result meets the set second condition, such as whether all check bits are set values, to determine whether the first data has passed the verification. If the verification passes, the target codeword can be output for subsequent processing. The specific second condition may include: a judgment condition set for the target verification result. The second condition may specifically include whether the verification result is the expected value. The target codeword is output only when the target codeword and the target verification result simultaneously meet their respective conditions. The output target codeword is the data that has passed the data verification.

[0076] In an embodiment of the present application, a status register can be used to determine whether each codeword is currently in an all-zero or non-zero state. This state management mechanism can quickly determine which codewords have changed and which remain in their initial state, thereby enabling a more accurate assessment of the data verification status of the entire data when determining the verification results. This simplifies the logic of the data verification process and improves the efficiency and flexibility of data verification. This ensures that the output codewords have undergone sufficient verification and status confirmation, improving the reliability and accuracy of the output results.

[0077] Figure 7 The application scenario of the data verification method provided by the embodiment of the present application is shown Figure 1 .

[0078] refer to Figure 7 The application scenario of the data verification method provided in the embodiment of the present application is applied to the timing of LDPC incremental verification.

[0079] 1. Clock. A clock signal is a periodic square wave that synchronizes all operations in a system. Each clock cycle represents a unit of time. The clock signal has a rising edge at the beginning of each unit of time, indicating the start of a new clock cycle.

[0080] 2. Data 1 Input. Data 1 Input is the input signal for the first set of data, indicating the timing of the first data input. At the rising edge of clock cycle 2, the Data 1 Input signal goes high, indicating the start of the first data input. At the rising edge of clock cycle 5, the Data 1 Input signal goes low, indicating the completion of the first data input. At the rising edge of clock cycle 2, the Data 1 Input signal goes high, indicating the start of the data input after the second data.

[0081] 3. Data 2 Input. Data 2 Input is the input signal for the second set of data, indicating the timing of the second data input. At the rising edge of clock cycle 5, the Data 2 Input signal goes high, indicating the start of the second data input. At the rising edge of clock cycle 8, the Data 2 Input signal goes low, indicating the completion of the second data input.

[0082] 4. Verification initialization. Verification initialization indicates the initialization of the codeword and verification result corresponding to the data. At the rising edge of clock cycle 5, the verification initialization signal goes high, indicating the start of initialization of the first data. At the rising edge of clock cycle 6, the verification initialization signal goes low, indicating that initialization is complete. At the rising edge of clock cycle 12, the verification initialization signal goes high, indicating the start of initialization of the second data. At the rising edge of clock cycle 13, the verification initialization signal goes low, indicating that initialization is complete.

[0083] 5. Iterative Update. Iterative update indicates that the data codeword and checksum are being iteratively updated. On the rising edge of clock cycle 5, the iterative update signal goes high, indicating the start of the first data iterative update. On the rising edge of clock cycle 11, the iterative update signal goes low, indicating the completion of the first data iterative update. On the rising edge of clock cycle 12, the iterative update signal goes high, indicating the start of the second data iterative update.

[0084] 6. Incremental Verification. Incremental verification indicates that the data is undergoing an LDPC incremental verification operation. On the rising edge of clock cycle 5, the incremental verification signal goes high, indicating that incremental verification of the first data has begun. On the rising edge of clock cycle 11, the incremental verification signal goes low, indicating that incremental verification of the first data has completed. On the rising edge of clock cycle 12, the incremental verification signal goes high, indicating that incremental verification of the first data has begun.

[0085] 7. Verification Passed. Verification Passed indicates whether the final verification result of the first data has passed. At the rising edge of clock cycle 10, the Verification Passed signal goes high, indicating that the first data verification has passed. At the rising edge of clock cycle 11, the Verification Passed signal goes low, indicating that the first data verification process has ended.

[0086] I understand. Figure 7 The application scenarios of the data verification method are only some exemplary implementations in the embodiments of the present application. The application scenarios of the data verification method in the embodiments of the present application include but are not limited to Figure 7 Application scenarios of the data verification method shown.

[0087] Figure 8 The application scenario of the data verification method provided by the embodiment of the present application is shown Figure 2 .

[0088] refer to Figure 8 The application scenario of the data verification method provided in the embodiment of the present application is applied to the LDPC incremental verification structure.

[0089] The LDPC incremental check structure may include: codeword SRAM (Static Random-Access Memory), check SRAM, codeword calculation module and check calculation module. The codeword SRAM can be used to: store the old and new values of the codeword, mainly used in the data input stage, provide the old value of the codeword to the codeword calculation module, and store the updated new value of the codeword. The check SRAM can be used to: store the old and new values of the check result, mainly used in the data output stage, provide the old value of the check result to the check calculation module, and store the updated new value of the check result. It is suitable for scenarios with fewer matrix blocks and higher requirements for throughput than area.

[0090] The LDPC incremental verification process may include:

[0091] 1. Initialization: Load the preset parity check matrix. Initialize the codeword SRAM module and the parity SRAM module to all zeros. Initialize the parity check result to all zeros.

[0092] 2. Data input: The codeword calculation module reads the old codeword value (initially all zeros) from the codeword SRAM, combines the input data with the check matrix, calculates the new codeword value, and writes the new codeword value back to the codeword SRAM.

[0093] 3. Checksum calculation: The checksum calculation module reads the new codeword value from the codeword SRAM. The checksum calculation module reads the old checksum result from the checksum SRAM, combines the checksum matrix and the codeword change, and calculates the new checksum result. The new checksum result is written back to the checksum SRAM.

[0094] 4. Verification judgment: The verification calculation module reads the latest verification result from the verification SRAM to determine whether the verification pass conditions are met. If the conditions are met, the verification SRAM outputs the corresponding verification pass data.

[0095] I understand. Figure 8 The application scenarios of the data verification method are only some exemplary implementations in the embodiments of the present application. The application scenarios of the data verification method in the embodiments of the present application include but are not limited to Figure 8 Application scenarios of the data verification method shown.

[0096] Figure 9 The application scenario of the data verification method provided by the embodiment of the present application is shown Figure 3 .

[0097] refer to Figure 9 The application scenario of the data verification method provided in the embodiment of the present application is applied to the LDPC incremental verification structure.

[0098] The LDPC incremental parity check architecture includes a codeword SRAM, a codeword calculation module, and a parity calculation module. The codeword SRAM can be used to store old and new codeword values and is used for both data input and output. It is suitable for scenarios with a large number of matrix blocks, high bit error rates, and high area requirements.

[0099] The LDPC incremental verification process may include:

[0100] 1. Initialization: Load the preset parity check matrix. Initialize the codeword SRAM module to all zeros. Initialize the parity check result to all zeros.

[0101] 2. Data input: The codeword calculation module reads the old codeword value (initially all zeros) from the codeword SRAM, combines the input data with the check matrix, calculates the new codeword value, and writes the new codeword value back to the codeword SRAM.

[0102] 3. Check Calculation: The check calculation module reads the new codeword value from the codeword SRAM. The check calculation module reads the codeword change from the codeword calculation module, combines the check matrix and the codeword change, and calculates the new check result.

[0103] 4. Verification: The verification calculation module directly uses the judgment value of the codeword block for verification, eliminating the need to store the verification results separately. The judgment value of the codeword block directly determines whether the verification conditions are met based on the current value and change of the codeword block. The verification calculation module determines whether the verification pass conditions are met. If the conditions are met, the codeword SRAM outputs the corresponding verification pass data.

[0104] I understand. Figure 9 The application scenarios of the data verification method are only some exemplary implementations in the embodiments of the present application. The application scenarios of the data verification method in the embodiments of the present application include but are not limited to Figure 9 Application scenarios of the data verification method shown.

[0105] The following continues to describe the exemplary structure of the software modules included in the data verification device 90 provided in the embodiment of the present application. In some embodiments, such as Figure 10 As shown, the data verification device 90 may include: a receiving module 901, used to receive first data; an initialization module 902, used to initialize the codeword and verification result corresponding to the first data to obtain an initial codeword and an initial verification result, and the receiving module 901 is also used to simultaneously receive second data; the first data is the current data to be verified, and the second data is the next data to be verified after the first data; a verification module 903, used to perform an LDPC low-density parity check code incremental verification on the first data based on the initial codeword and the initial verification result to obtain a target codeword and a target verification result; an output module 904, used to output the target codeword in response to the target codeword satisfying the set first condition and the target verification result satisfying the set second condition.

[0106] In some embodiments, the initialization module 902 can be used to: obtain a virtual codeword and a virtual verification result corresponding to the virtual codeword; based on the virtual codeword and the virtual verification result, initialize the codeword and verification result corresponding to the first data to obtain an initial codeword and an initial verification result; the initial codeword is an all-zero codeword, and the initial verification result is an all-zero verification result.

[0107] In some embodiments, the check module 903 can be used to: determine the LDPC check matrix corresponding to the first data based on the number of codewords of the first data; iteratively update the initial codeword and the initial check result through a row layered decoding algorithm based on the LDPC check matrix and the first data to obtain the target codeword and the target check result.

[0108] In some embodiments, the check module 903 can be used to: determine the LDPC check matrix corresponding to the first data from multiple preset LDPC check matrices based on the number of codewords of the first data; the LDPC check matrix includes at least a sub-check matrix, and the sub-check matrix includes a non-zero matrix and a zero matrix; the number of sub-check matrices included in each row of the LDPC check matrix is the same as the number of codewords of the first data; each row in the LDPC check matrix corresponds to a check result.

[0109] In some embodiments, the check module 903 may be configured to: traverse the non-zero matrices in the LDPC check matrix according to a predetermined calculation order, and calculate, based on the first data and each non-zero matrix in each row, a change in the codeword corresponding to the non-zero matrix relative to the codeword at the previous iteration. Iteratively update the codeword based on the change, and simultaneously iteratively update the check result associated with the codeword, to obtain a target codeword and a target check result.

[0110] In some embodiments, the data verification device 90 may further include a configuration module, which may be used to: configure a corresponding status register for each codeword of the first data; when the status register is in the first state, the codeword is represented as an all-zero codeword, and when the status register is in the second state, the codeword is represented as a non-zero codeword; configure the initial state of the status register to the first state; and update the status register to the second state in response to a change in the codeword.

[0111] In some embodiments, the output module 904 can be used to: read the status register corresponding to each codeword to obtain the state corresponding to the target codeword; in response to the status registers of all target codewords being in the second state and all target verification results indicating verification passing, output the target codeword.

[0112] It should be noted that the description of the device in the embodiment of the present application is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment, so it will not be repeated here. Figures 1 to 9 The present invention shall be understood by reference to the description of any of the accompanying drawings.

[0113] According to an embodiment of the present application, the present application also provides an electronic device and a non-transitory computer-readable storage medium.

[0114] Figure 11A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0115] like Figure 11 As shown, electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in ROM 802 or a computer program loaded from storage unit 808 into RAM 803. Various programs and data required for the operation of electronic device 800 can also be stored in RAM 803. Computing unit 801, ROM 802, and RAM 803 are connected to each other via bus 804. I / O interface 805 is also connected to bus 804.

[0116] Multiple components in the electronic device 800 are connected to the I / O interface 805, including an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0117] The computing unit 801 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as the data verification method. For example, in some embodiments, the data verification method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the data verification method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform the data verification method in any other appropriate manner (e.g., by means of firmware).

[0118] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0119] The program code for implementing the methods of the present application can be written in any combination of one or more programming languages. Such program code can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the program code is executed by the processor or controller, the functions / operations specified in the flow charts and / or block diagrams are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0120] In the context of the present application, a machine-readable medium can be a tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0121] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0122] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0123] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0124] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this application can be achieved. This is not a limitation herein.

[0125] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0126] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A data verification method, characterized in that: The method comprises: receiving first data; Initializing and setting the codeword and verification result corresponding to the first data to obtain an initial codeword and an initial verification result, and simultaneously receiving second data; the first data is the current data to be verified, and the second data is the next data to be verified after the first data; Based on the initial codeword and the initial check result, performing an LDPC low-density parity check code incremental check on the first data to obtain a target codeword and a target check result; In response to the target codeword satisfying a set first condition and the target check result satisfying a set second condition, the target codeword is output.

2. The method according to claim 1, characterized in that Initializing the codeword and the verification result corresponding to the first data to obtain the initial codeword and the initial verification result includes: Obtaining a virtual codeword and a virtual verification result corresponding to the virtual codeword; Initializing the code word and the verification result corresponding to the first data based on the virtual code word and the virtual verification result to obtain an initial code word and an initial verification result; The initial codeword is an all-zero codeword, and the initial check result is an all-zero check result.

3. The method according to claim 2, characterized in that The step of performing an LDPC low-density parity check code incremental check on the first data based on the initial codeword and the initial check result to obtain a target codeword and a target check result includes: Determining an LDPC check matrix corresponding to the first data based on the number of codewords of the first data; Based on the LDPC check matrix and the first data, the initial codeword and the initial check result are iteratively updated through a row layered decoding algorithm to obtain the target codeword and the target check result.

4. The method according to claim 3, characterized in that The determining, based on the number of codewords of the first data, an LDPC check matrix corresponding to the first data includes: Determining, based on the number of codewords of the first data, an LDPC check matrix corresponding to the first data from a plurality of preset LDPC check matrices; The LDPC check matrix includes at least a sub-check matrix, and the sub-check matrix includes a non-zero matrix and a zero matrix; the number of sub-check matrices included in each row of the LDPC check matrix is the same as the number of codewords of the first data; each row in the LDPC check matrix corresponds to a check result.

5. The method according to claim 4, characterized in that The iteratively updating the initial codeword and the initial check result by a row layered decoding algorithm based on the LDPC check matrix and the first data to obtain the target codeword and the target check result includes: According to a set calculation order, traverse the non-zero matrices in the LDPC check matrix, and calculate, based on the first data and each non-zero matrix in each row, a change in the codeword corresponding to the non-zero matrix relative to the codeword at the last iteration; The codeword is iteratively updated based on the variation, and the verification result associated with the codeword is synchronously iteratively updated to obtain the target codeword and target verification result.

6. The method according to claim 1, characterized in that The method further comprises: Configuring a corresponding status register for each codeword of the first data; wherein the status register being in a first state indicates that the codeword is an all-zero codeword, and the status register being in a second state indicates that the codeword is a non-zero codeword; Configuring the initial state of the state register to be a first state; In response to a change in the codeword, the state register is updated to a second state.

7. The method according to claim 6, characterized in that In response to the target codeword satisfying a set first condition and the target verification result satisfying a set second condition, outputting the target codeword includes: Reading the status register corresponding to each codeword to obtain the status corresponding to the target codeword; In response to the state registers of all target codewords being in the second state and all target check results indicating a check pass, the target codewords are output.

8. A data verification device, characterized in that: The device comprises: A receiving module, configured to receive first data; an initialization module, configured to initialize and set a codeword and a verification result corresponding to the first data to obtain an initial codeword and an initial verification result; and a receiving module, configured to simultaneously receive second data; the first data being current data to be verified, and the second data being next data to be verified after the first data; A verification module, configured to perform an LDPC low-density parity check code incremental verification on the first data based on the initial codeword and the initial verification result to obtain a target codeword and a target verification result; The output module is configured to output the target codeword in response to the target codeword satisfying a set first condition and the target verification result satisfying a set second condition.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 7.

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