Decoder and launch vehicle

Abstract

The embodiment of the present application provides a kind of decoder and carrier rocket, comprising: jump edge detection module, for receiving the voltage signal encoded using Manchester II code and converted by physical layer transceiver, integrator, for using positive value to integrate and obtain integral value when received RX is high level, using negative value to integrate and obtain integral value when received RX# is high level;Synchronization head detection and window comparator, for using the symmetry of synchronization head, according to the start time of the jump edge of RX or the start time of the jump edge of RX#, the synchronization head is pre-judged according to integral value, in turn according to integral value appears in upper decision window or lower decision window, and according to the jump edge of RX or RX#, the code element value corresponding to data bit is determined, and when decoding or decoding is completed after the data bit of synchronization head, it is regarded as synchronization head decision success.Can deal with the problem that bus is too long code shape distortion is serious, and reliably decodes synchronization head and data bit.

Description

Technical Field

[0001] This invention relates to the field of decoding, and more specifically to a decoder and a launch vehicle. Background Technology

[0002] In the context of the current commercial spaceflight industry, rocket bodies are becoming increasingly longer, with the 1553B bus length almost exceeding 150 meters. Long-distance bus transmission leads to severe code distortion at the receiving end, and traditional methods have a high bit error rate in decoding under complex long-distance environments.

[0003] The closest current approach is a decoder that utilizes the integral concept to decode Manchester II codes with fixed synchronization headers. However, the 1553B standard uses two synchronization headers to represent data words and command words, which traditional fixed synchronization header decoding methods cannot accommodate. Furthermore, similar methods lack fault detection functionality.

[0004] In the process of developing this invention, the applicant discovered at least the following problems in the prior art:

[0005] Large launch vehicles suffer from severe code distortion due to the excessive length of the 1553B bus, resulting in high error rates and poor reliability of traditional decoders. Summary of the Invention

[0006] This invention provides a decoder and a launch vehicle that can solve the technical problem in the prior art where the traditional decoder has a high error rate and poor reliability due to severe code distortion caused by the excessive length of the 1553B bus.

[0007] To achieve the above objectives, in one aspect, embodiments of the present invention provide a decoder, comprising:

[0008] The edge-changing detection module is used to receive voltage signals encoded in Manchester II code and converted by the physical layer transceiver. The voltage signals include two digital level signals: RX and RX#. The module detects the edge-changing of RX and RX# respectively.

[0009] An integrator is used to integrate a positive value when the received RX is high and to obtain an integral value when the received RX# is high.

[0010] The synchronization header detection and window comparator is used to utilize the symmetry of the synchronization header to pre-determine the synchronization header based on the integral value and the start time of the RX transition edge or the RX# transition edge. Then, it determines the symbol value corresponding to the data bit based on the integral value appearing in the upper or lower decision window and the RX or RX# transition edge. The synchronization header is considered to be successfully determined when decoding the data bits after the synchronization header or when decoding is completed.

[0011] On the other hand, embodiments of the present invention provide a launch vehicle including the aforementioned decoder, the decoder being connected to a physical layer transceiver, the physical layer transceiver being connected to a 1553B bus, wherein the decoder is integrated on an FPGA.

[0012] The above technical solution has the following beneficial effects:

[0013] For the two digital level signals RX and RX# to be received, since RX is 1 and RX# is 0 when the voltage signal is a forward voltage difference, RX is 0 and RX# is 1 when the voltage signal is a reverse voltage difference, and both RX and RX# are 0 when the voltage difference is small, when the received current RX is high, a positive value is integrated to obtain the integral value, and the integration is performed upwards. Therefore, by decoding the current RX, the symbol value of the corresponding synchronization header or data bit can be obtained; since the corresponding symbol value is obtained by decoding the current RX, the symbol value corresponding to the current RX# can also be obtained.

[0014] Similarly, when the received current RX# is high, a negative value is used for integration to obtain the integral value, and the negative value is integrated downwards. That is, when the received voltage signal RX is 1, the integrator increments by 1; when RX# is 1, the integrator decrements by 1; otherwise, the integrator remains unchanged. Thus, by decoding the current RX#, the symbol value of the corresponding synchronization header or data bit can be obtained; since the corresponding symbol value is obtained by decoding the current RX#, the symbol value corresponding to the current RX can also be obtained. Then, it is necessary to determine the start time of the bit corresponding to the current RX or current RX#; using the embodiment of the present invention, the start time of the synchronization header is pre-determined based on the integral value and the start time of the transition edge of RX or the transition edge of RX#, and naturally, the end time of the first half of the synchronization header can be known. Using the symmetry of the synchronization header, the symbol value of the second half of the synchronization header and the corresponding end time can be known. And then, according to the integral value appearing in the upper or lower decision window, and according to the transition edge of RX or RX#, the symbol value corresponding to the data bit and the start and end times of the data bit are determined. The synchronization header is considered to have been successfully determined and locked when the data bits after the synchronization header are decoded or when decoding is completed.

[0015] The technical means employed in this invention—integral value, transition edge, and decision window—can address the technical problems of severe code distortion of voltage signals caused by the excessive length of the 1553B bus, which transmits voltage signals encoded in Manchester II code and converted into voltage signals by the physical layer transceiver. This results in high error rates and poor reliability in traditional decoders. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a structural diagram of a decoder according to an embodiment of the present invention;

[0018] Figure 2 This is a circuit block diagram containing a decoder according to an embodiment of the present invention;

[0019] Figure 3 This is a logic block diagram of the decoder algorithm according to an embodiment of the present invention;

[0020] Figure 4 This is a Manchester Type II biphase level diagram according to an embodiment of the present invention;

[0021] Figure 5 This is the synchronization header waveform of the Manchester Type II encoding in an embodiment of the present invention;

[0022] Figure 6 This is a decoding state machine diagram according to an embodiment of the present invention;

[0023] Figure 7 This is a simulation waveform of the decoding in an embodiment of the present invention;

[0024] Figure 8 This is a simulation of data bit decoding in an embodiment of the present invention;

[0025] Figure 9 This is a typical command / status word in an embodiment of the present invention, whose data area is encoded as hexadecimal (A123)H. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The abbreviations used in the embodiments of this invention are defined as follows:

[0028] Manchester II code: a biphase level code where 1 / -1 represents bit 1 and -1 / 1 represents bit 0.

[0029] Bit time: The time required to transmit one symbol bit as specified in the 1553B standard, also known as the cycle of one symbol in the field of communications.

[0030] Code element: A symbol that carries information. It can be a set of voltage waveforms with certain characteristics and patterns. A single waveform can be a code element.

[0031] bit: a single binary digit.

[0032] FPGA: Field Programmable Gate Array.

[0033] IP core: Intellectual Property core, is a hardware description language program with specific circuit functions.

[0034] like Figure 1 As shown, in conjunction with embodiments of the present invention, a decoder is provided, comprising:

[0035] The edge-changing detection module is used to receive voltage signals encoded in Manchester II code and converted by the physical layer transceiver. The voltage signals include two digital level signals: RX and RX#. The module detects the edge-changing of RX and RX# respectively.

[0036] An integrator is used to integrate a positive value when the received RX is high and to obtain an integral value when the received RX# is high.

[0037] The synchronization header detection and window comparator is used to utilize the symmetry of the synchronization header to pre-determine the synchronization header based on the integral value and the start time of the RX transition edge or the RX# transition edge. Then, it determines the symbol value corresponding to the data bit based on the integral value appearing in the upper or lower decision window and the RX or RX# transition edge. The synchronization header is considered to be successfully determined when decoding the data bits after the synchronization header or when decoding is completed.

[0038] For the two digital level signals RX and RX# to be received, since RX is 1 and RX# is 0 when the voltage signal is a forward voltage difference, RX is 0 and RX# is 1 when the voltage signal is a reverse voltage difference, and both RX and RX# are 0 when the voltage difference is small, when the received current RX is high, a positive value is integrated to obtain the integral value, and the integration is performed upwards. Therefore, by decoding the current RX, the symbol value of the corresponding synchronization header or data bit can be obtained; since the corresponding symbol value is obtained by decoding the current RX, the symbol value corresponding to the current RX# can also be obtained.

[0039] Similarly, when the received current RX# is high, a negative value is used for integration to obtain the integral value, and the negative value is integrated downwards. That is, when the received voltage signal RX is 1, the integrator increments by 1; when RX# is 1, the integrator decrements by 1; otherwise, the integrator remains unchanged. Thus, by decoding the current RX#, the symbol value of the corresponding synchronization header or data bit can be obtained; since the corresponding symbol value is obtained by decoding the current RX#, the symbol value corresponding to the current RX can also be obtained. Then, it is necessary to determine the start time of the bit corresponding to the current RX or current RX#; using the embodiment of the present invention, the start time of the synchronization header is pre-determined based on the integral value and the start time of the transition edge of RX or the transition edge of RX#, and naturally, the end time of the first half of the synchronization header can be known. Using the symmetry of the synchronization header, the symbol value of the second half of the synchronization header and the corresponding end time can be known. And then, according to the integral value appearing in the upper or lower decision window, and according to the transition edge of RX or RX#, the symbol value corresponding to the data bit and the start and end times of the data bit are determined. The synchronization header is considered to have been successfully determined and locked when the data bits after the synchronization header are decoded or when decoding is completed.

[0040] The technical means employed in this invention—integral value, transition edge, and decision window—can address the technical problems of severe code distortion of voltage signals caused by the excessive length of the 1553B bus, which transmits voltage signals encoded in Manchester II code and converted into voltage signals by the physical layer transceiver. This results in high error rates and poor reliability in traditional decoders.

[0041] Preferably, the transition edge refers to the rising edge;

[0042] The synchronization header detection and window comparator includes a synchronization header decision submodule, which is used for:

[0043] While waiting for the synchronization header, if, starting from the rising edge of RX#, the integral value corresponding to RX for the first half of the synchronization header is higher than the upper limit threshold of the synchronization header in the upper limit threshold comparator, then the instruction / status word is marked as 1 and the data word is marked as 0, wherein the upper limit threshold of the synchronization header is a positive value.

[0044] If, starting from the rising edge of RX, the integral value corresponding to RX# for the first half of the synchronization header is lower than the synchronization header lower limit threshold in the lower limit threshold comparator, then the instruction / status word is marked as 0, and the data word is marked as 1, wherein the synchronization header lower limit threshold is a negative value.

[0045] The 1553B bus is half-duplex (data transmission means that data can be transmitted in both directions on a single signal carrier, but not simultaneously), and uses a time-division multiplexing transmission mode. For example... Figure 4As shown, data on the 1553B bus is transmitted serially. The physical layer transceiver uses Manchester Type II biphase level encoding, where 1 / -1 represents bit 1, -1 / 1 represents bit 0, and 0 / 0 indicates the bus is idle. The typical bit transmission rate is 1 Mbps. Figure 5 As shown, the word format of the 1553B bus differs from that of general Manchester encoded communication in that its data bit synchronization header has two types: instruction / status word and data word. The instruction / status word consists of a high level at bit 1.5 and a low level at bit 1.5, while the data word is the opposite, consisting of a low level at bit 1.5 and a high level at bit 1.5. Therefore, accurate detection of the synchronization header is crucial for correct decoding of the 1553B bus. The instruction / status word is a synchronization header waveform with two meanings specified by the 1553B standard. The instruction word is sent by the master controller (BC), and the status word is returned by the remote terminal (RT). Because the waveforms of the "instruction" and the "status word" are consistent, in this embodiment of the invention, the "instruction" and the "status word" are treated as the same variable. Figure 4 The first line is the reference code rate clock; the second, third, and fourth lines are non-return-to-zero code waveforms (binary digital signals (signals before encoding)).

[0046] Based on the characteristic of Manchester II code as a symmetrical bipolar encoded signal, this embodiment of the invention employs the "integral threshold window comparison method" for decoding. The integral threshold window comparison method refers to the decoder having two window comparators (upper and lower) for decoding, and two threshold comparators (upper and lower limits) for determining the synchronization header. Ideally, the integral value of the symbol waveform within one symbol period is 0, when the symbol is one bit in the 1553B bus standard, and when a synchronization header occupies three bits.

[0047] Both the upper and lower limits of the synchronization header are set to the integral value corresponding to half the duration of the synchronization header. When the upper limit of the synchronization header is positive, it is used to determine the synchronization header of the instruction / status word. When the lower limit of the synchronization header is negative, it is used to determine the synchronization header of the data word.

[0048] The synchronization header decision submodule employs two threshold comparators: an upper threshold comparator and a lower threshold comparator. To determine the synchronization header type, when the integral value exceeds the upper threshold of the synchronization header in the upper threshold comparator, the `flag_csw` register is marked as 1, indicating that the `flag_csw` register may contain an instruction / status word, signifying that the instruction / status word is valid. In this case, the data word is marked as 0, indicating that the data word is invalid. When the integral value is less than the lower threshold of the synchronization header in the lower threshold comparator, the `flag_dw` register is marked as 1, indicating that the `flag_dw` register may contain a data word, signifying that the data word is valid. In this case, the instruction / status word is marked as 0, indicating that the instruction / status word is invalid. During normal operation, the two register values ​​are mutually exclusive (cannot be 0 or 1 simultaneously). When the first valid bit (data bit) after the synchronization header appears or decoding is complete, the synchronization header decision is considered successful, and the final synchronization header state is latched. Simultaneously, the decoding state machine jumps to the decoding in progress state.

[0049] Preferably, the synchronization head detection and window comparator further includes a decision window, which comprises the upper decision window and the lower decision window, wherein:

[0050] The decision window is used to display the integral value corresponding to the data bits after the synchronization header and to make a judgment based on the integral value corresponding to the data bits;

[0051] If the integral value corresponding to the current data bit falls within the upper decision window and RX# has a rising edge within the lower decision window, it indicates that the current data bit is valid and satisfies the decoding condition of decoding the current data bit into symbol 1. Therefore, the current data bit is decoded into a symbol with a value of 1; or...

[0052] If the integral value corresponding to the current data bit falls within the lower decision window and RX has a rising edge within the upper decision window, it indicates that the current data bit is valid and satisfies the decoding condition of decoding the current data bit into symbol 0. Then, the current data bit is decoded into a symbol with a symbol value of 0.

[0053] When decoding one of the voltage signals, the decision time is based on the decision window (upper or lower decision window) where the integral value of the corresponding voltage signal is located, and the transition (i.e., the appearance of a rising edge) of the other voltage signal. Because the two level signals are exactly 180 degrees apart, and because each signal has distortion, the transition edges of the two voltage signals that would normally coincide at the same time may be misaligned. That is, the influence on each voltage signal causes a change in the signal width, resulting in the two voltage signal transition edges not coinciding. This means that when the other voltage signal appears with a rising edge, the integral value of the voltage signal is already very high, i.e., it has entered the corresponding decision window. Therefore, it is possible to determine very clearly and accurately that the voltage signal is valid, indicating that the current data bit is valid and meets the decoding condition of decoding the current data bit into code 0 or 1.

[0054] Repeat the above decoding process until all data bits have been decoded.

[0055] Preferably, the decoder further includes:

[0056] A data receive shift register is used to receive and latch the symbol value 1 after decoding the current data bit into a symbol with a symbol value of 1; or, after decoding the current data bit into a symbol with a symbol value of 0, receive and latch the symbol value 0.

[0057] And after obtaining the next symbol value, shift the previous symbol values ​​one bit in sequence, and then receive and latch the next symbol value.

[0058] The decoded code value is either 1 or 0. The data receiving shift register is shifted sequentially according to the result of the synchronization header detection and the window comparator to receive the state of the decoded code. The shift reception is to use the serial-in parallel-out shift register to receive and store these successfully decoded codewords in sequence. The reception process continues until all 17 bits of data are received.

[0059] Preferably, the upper decision window has a first upper threshold and a first lower threshold, and the position and range of the upper decision window are determined by the first upper threshold and the first lower threshold; the lower decision window has a second upper threshold and a second lower threshold, and the position and range of the lower decision window are determined by the second upper threshold and the second lower threshold.

[0060] The decision window is specifically used for:

[0061] If the integral value corresponding to the current data bit exceeds the first lower limit threshold of the upper decision window but is less than the first upper limit threshold, it indicates that the integral value corresponding to the current data bit falls within the upper decision window.

[0062] If the integral value corresponding to the current data bit crosses the second upper limit threshold of the decision window and is greater than the second lower limit threshold, it indicates that the integral value corresponding to the current data bit falls within the decision window.

[0063] For decoding data bits, an upper decision window and a lower decision window are set. Each decision window has an upper threshold and a lower threshold. Reasonable upper and lower thresholds are set so that the difference between the upper and lower thresholds of each window can adapt to the decoder's ability to adapt to voltage signals (code patterns).

[0064] Preferably, the decoder further includes a state machine, wherein:

[0065] The synchronization header decision submodule is also used to consider the synchronization header decision as successful when the corresponding symbol value is obtained by decoding the first data bit after the synchronization header, and to determine the second half of the synchronization header by utilizing the symmetry of the synchronization header and latch the synchronization header mark.

[0066] The state machine is used to transition from the current state to the next state based on state changes during the decoding process. The decoder's decoding state machine is as follows: Figure 6 As shown, the state machine includes the following states: waiting for synchronization header, decoding in progress, decoding error, and idle / complete. When in the waiting for synchronization header state, it jumps to the decoding progress state when the synchronization header is found. It remains in the waiting for synchronization header state when the bus is idle or the synchronization header condition is not met. When decoding is complete, it jumps from the decoding progress state to the idle / complete state, or from the decoding error state to the decoding error state if a decoding error occurs. It can also jump from the decoding error state to the idle / complete state. When the number of bits to be decoded is 17 and the parity bit and the first 16 bits of data pass verification, the state machine will jump to the idle / complete state. The state machine uses one-hot encoding, which has a certain degree of fault tolerance. Of course, other encodings, such as Gray code, can also be used.

[0067] Preferably, the integrator is further configured to, while decoding the current data bit into a symbol value, correct the integral value corresponding to the current data bit to the integral value corresponding to half of the current data bit.

[0068] For data bit decoding, an upper and lower decision window are set. Each decision window has an upper and lower threshold. The difference between the upper and lower thresholds of the window affects the decoder's ability to adapt to code distortion. The ideal value of the difference between the center value of the decision window ((upper threshold + lower threshold) / 2, i.e., the middle position of the decision window) and the value of the upper and lower thresholds is the integral value corresponding to half a bit. Therefore, the integral value corresponding to the current data bit is corrected to the integral value corresponding to half a bit of the current data bit to eliminate the integral error caused by code distortion. Figure 8In this process, an integrator is used to integrate the received RX and RX#. Simultaneously, while decoding the current data bit into a symbol value, the integrated value (shown in the circle) is corrected to the straight line below. This eliminates the accumulation of code width errors caused by signal distortion and data clock jitter on the 1553B bus within the integrator. Otherwise, this accumulated error would continuously affect the decision of subsequent symbols (because the integrated value of the previous symbol is also used in the integration process of the next symbol). For example... Figure 8 As shown, the first column is the signal name, and the second column is the signal value indicated by the vertical line (a vertical line located between adjacent numbers 00001 and 00002 and running vertically through the entire image).

[0069] Preferably, the decoder further includes a decoding error detection module, which is used to:

[0070] When the synchronization header is severely distorted, making it impossible to determine a valid synchronization header, the synchronization header decoding is deemed to be incorrect.

[0071] While waiting for the synchronization head status, compare the difference between the rise and fall times of the integrator to see if it is seriously out of tolerance. If it is out of tolerance, set the corresponding error indicator to 1. After a successful decoding, the value will be automatically cleared to zero.

[0072] If the number of valid symbols cannot be correctly determined within the preset time, the data bit decoding is judged to be incorrect.

[0073] or,

[0074] If the parity bit is incorrect, the data bit decoding is determined to be incorrect. The parity bit is the result of the real-time verification of the symbol value received in the data receiving shift register by the parity check module.

[0075] or,

[0076] When the width difference between the first 1.5 bits and the last 1.5 bits of the synchronization header is greater than the preset value, the output value of the integrator at the position of the first symbol after the synchronization header is not within the two decision windows above and below the integration, and the synchronization header is judged to be decoded incorrectly.

[0077] If the binary status code representing the state machine has more than one bit set to 1 or all bits set to 0, then the state machine is considered to have encountered an error.

[0078] If the error exceeds the tolerance, the corresponding error indicator is set to 1, and it is automatically reset to zero after each correct decoding. The decoding error judgment module can identify different errors and mark them with corresponding identifiers; therefore, rich identifiers are beneficial for debugging under complex operating conditions.

[0079] Preferably, the edge-jumping detection module is specifically used for:

[0080] It receives voltage signals encoded in Manchester II code from the 1553B bus and converted by the physical layer transceiver. Figure 2 This is a partial circuit block diagram of the decoder used in a specific system according to an embodiment of the present invention. It includes a decoder, shared message memory, a 1553BBC controller, a 1553BRT controller, a 1553BMT controller, and a bus interface. The decoder is located separately and is used within the 1553B bus controller. The 1553B bus is a redundant bus, requiring at least two paths, bus A (BUSA) and bus B (BUSB), for mutual backup. Decoder A and decoder B each serve one bus, BUSA or BUSB. After decoder A and decoder B, a protocol layer handles the 1553B bus protocol (AB bus selection), and this protocol layer has the authority to decide whether to receive data from bus A or bus B.

[0081] Decoder A and Decoder B are connected to 1553B bus physical layer transceiver A and B, respectively. The interfaces of Decoder A and Decoder B are standardized, with inputs of RX and RX# signals for easy connection to the 1553B bus physical layer transceiver chip. The output is a standard AXI-STREAM interface for ease of use and integration. AXI-STREAM is a CPU standard bus protocol jointly defined by ARM and other companies. AXI (Advanced Extensible Interface) is usually expressed in English.

[0082] In summary, as Figure 3 The diagram shows the logic block diagram of the decoder algorithm in this embodiment of the invention. The left side is the input of the 1553B bus signal to be decoded. This signal consists of two digital level signals from the physical layer transceiver channel of the 1553B bus (used for mutual conversion between binary digital signals and analog waveforms on the bus). The two signals are denoted as RX and RX#. When there is a positive voltage difference on the 1553B bus, RX is 1 and RX# is 0. When there is a reverse voltage difference on the bus, RX is 0 and RX# is 1. When the bus voltage difference is small, both RX and RX# are 0.

[0083] 1. The rising edge detection module is used to detect the rising edge and falling edge of the above RX and RX# signals respectively.

[0084] 2. The integrator integrates the RX and RX# signals: when RX is 1, the integrator increments by 1; when RX# is 1, the integrator decrements by 1; otherwise, the integrator remains constant. The upper and lower limits of the integrator's integration are limited based on parameters such as the operating master clock frequency, oversampling rate, decision window threshold, etc., which are necessary parameters for the decoder's operation. The integration time step is the clock cycle of the operating clock. This is achieved when half a synchronization header is 1.5 bits and subsequent data symbols are 1 bit. The integrator has a reasonable limiting range, set according to the communication symbol rate to prevent integrator overflow. It also features integration error correction and the ability to self-reset based on bus idle conditions to prevent error accumulation and propagation.

[0085] 3. The synchronization header detection and window comparator is used to determine the state (i.e., symbol value) of the synchronization header and data bits based on the rising edge time of the RX or RX# signal and the integral value of the integrator. Simultaneously, it corrects the integral value of the integrator according to the respective states (i.e., symbol values) of the synchronization header and data bits to eliminate integration errors caused by code distortion.

[0086] 4. The timeout counter and receive counter module is used to determine the receive decoding timeout. For example, if the decision condition cannot be met after finding the synchronization header if more than one bit has passed, the decoding timeout will occur. It also counts the correctly received symbols and provides a decision basis for the error detection logic of the decoding error judgment module.

[0087] 5. The error detection logic of the decoding error judgment module is used to indicate the working status of the decoder. The working status is an indicator signal indicating whether the decoder is working normally or abnormally.

[0088] 6. The parity check module is used to perform real-time verification of the symbol values ​​received in the data receiving shift register to obtain the verification result.

[0089] 7. The data receive shift register is used to sequentially shift the received decoded code elements (code element values) according to the decoding results of the synchronization head detection and the window comparator.

[0090] 8. The AXI-STREAM interface logic is used to summarize received data, verification results, and error status to form the standard AXI-STREAM bus protocol interface logic.

[0091] like Figure 7 The image shows the simulated voltage signal. `decoder_int` (a variable name representing the integrator output value) is the integrator output waveform. This series of waveforms represents the sequential transmission of instruction / status words (instruction word and status word, respectively). Figure 7In the middle, the bottom two lines are used to pre-determine and mark whether the current data packet is an instruction / status word or a data word; flag_csw represents the flag (flag bit) for instruction / status words, and flag_dw represents the flag (flag bit) for data words.

[0092] Figure 9 For a typical command / status word, its data area is encoded as hexadecimal (A123)H. The first column is the signal name, and the second column is the signal value indicated by the yellow vertical line at the time.

[0093] First, there's the synchronization header occupying 3 bits. The integrator output waveform (decoder_int) shows a large triangular waveform. When the integral value exceeds the upper threshold of the lower decision window, flag_csw is set to 1, indicating a possible command / status word. Then, when the integrator output value falls within the upper window threshold range and the rising edge of the RX# signal (rx_data_n signal in the diagram) arrives, it indicates that the decoding condition for one symbol is met, representing a logic level of 1. Similarly, when the subsequent integrator output value falls within the lower decision window threshold range and the rising edge of the RX signal (rx_data signal in the diagram) arrives, it indicates that the decoding condition for one symbol is met, representing a logic level of 0. This continues until the next 15 symbols are decoded. Simultaneously latching the values ​​of the receive shift register, the parity check module, and the error detection logic of the decoding error judgment module yields the final decoder output. This output timing is then formed via the AXI-STREAM interface logic to create the standard interface output timing.

[0094] Preferably, the 1553B bus is widely used in aerospace, railway, and other fields. Its voltage signal decoding algorithm is the core of 1553B bus-related products. Therefore, this decoder can be used in any equipment or facility requiring the 1553B bus in aviation, aerospace, railway, drilling exploration, and other fields. Any equipment or facility requiring the 1553B bus includes 1553B bus monitoring equipment, 1553B active couplers, 1553B bus controller chip design, 1553B bus controllers, and all other products that need to decode 1553B bus signals. For the 1553B active coupler, it can be modified to decode and encode simultaneously. For example, encoding can begin immediately after finding the synchronization header, and each decoded symbol is pushed into a buffer. The encoder continuously reads the data from the buffer and re-encodes it, thereby enabling the development of a high-reliability 1553B bus signal repeater function.

[0095] In conjunction with embodiments of the present invention, a launch vehicle is provided, including any of the aforementioned decoders, wherein the decoder is connected to a physical layer transceiver, the physical layer transceiver is connected to a 1553B bus, and wherein the decoder is integrated on an FPGA.

[0096] The beneficial effects achieved by the embodiments of the present invention are as follows:

[0097] 1. In accordance with the 1553B bus standard, this embodiment of the invention employs a synchronization header detection and window comparator based on integral values ​​to fully realize the synchronization header detection, data bit decoding, and error indication functions of the 1553B voltage signal. In a test environment with the same length of 1553B bus as in the prior art, no bit errors occurred when using this decoder.

[0098] Integrating the decoder into an FPGA minimizes FPGA resource consumption (approximately 194 LUTs and 160 FFs). This improves decoder reliability, eliminates the need for a dedicated decoder chip, reduces production and R&D costs, decreases PCB area, conserves FPGA resources, and offers simplicity and efficiency; it also breaks the monopoly of foreign companies. The advantages of using FPGAs include flexibility, reconfigurability, strong real-time performance, adaptability to existing hardware, and the elimination of the need for additional processor hardware.

[0099] 2. The synchronization header detection and window comparator based on integral values ​​does not require a dedicated sampling clock recovery function. It has a symbol waveform filtering and glitching function, which can cope with the problem of severe code shape distortion due to the excessive length of the 1553B bus. It does not require a dedicated filter circuit, and the integration step size can be flexibly set to reliably decode the synchronization header and data bits. It has high reliability, effectively reducing the bit error rate in complex interference environments with long 1553B buses. Theoretically, it can still reliably decode even when the symbol waveform is skewed by 25%. It solves the problem that traditional decoders are difficult to estimate the optimal decision time in long-distance complex environments, and the decoding is easily affected by interference. It solves the problem that "existing decoders mostly rely on their own transition edges (rising edge and falling edge) in the symbol as the basis for generating the decision time, which is more sensitive to severely distorted signals and is not easy to accurately predict the optimal decision time, resulting in excessively high bit error rates in complex environments. Traditional decoders mostly use 16x oversampling, which has limited adaptability to the large-amplitude random waveform width distortion of Manchester II code shape, making it difficult to accurately select the optimal sampling decision time."

[0100] 3. It has complete decoding error indication function and error indication signal, which facilitates fault location and troubleshooting in debugging and practical applications, realizes the fault diagnosis function when integrating it, and realizes the system-level bus error diagnosis function of the integrated system.

[0101] 4. A standard AXI-STREAM bus interface has been developed, which is convenient for use and integration into specific systems.

[0102] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to the specific order or hierarchy described.

[0103] In the above detailed description, various features are combined together in a single embodiment to simplify this disclosure. This approach to disclosure should not be construed as reflecting an intention that embodiments of the claimed subject matter require more features than are explicitly stated in each claim. Rather, as reflected in the appended claims, the invention is presented with fewer features than all of the features of the single disclosed embodiment. Therefore, the appended claims are hereby explicitly incorporated into the detailed description, wherein each claim stands alone as a preferred embodiment of the invention.

[0104] The disclosed embodiments have been described above to enable any person skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not limited to the embodiments given herein, but is consistent with the broadest scope of the principles and novel features disclosed in this application.

[0105] The foregoing description includes examples of one or more embodiments. It is certainly impossible to describe all possible combinations of components or methods in order to describe the above embodiments, but those skilled in the art will recognize that further combinations and arrangements of the various embodiments are possible. Therefore, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of the appended claims. Furthermore, the term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as interpreted when used as a conjunction in the claims. Additionally, the use of any term "or" in the specification of the claims is intended to mean "non-exclusive or."

[0106] Those skilled in the art will also understand that the various illustrative logical blocks, units, and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of both. To clearly demonstrate the interchangeability of hardware and software, the functions of the various illustrative components, units, and steps described above have been generally described. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the described functions using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of the present invention.

[0107] The various illustrative logic blocks or units described in the embodiments of this invention can be implemented or operate the described functions using a general-purpose processor, digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor; alternatively, it can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented using a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0108] The steps of the methods or algorithms described in the embodiments of this invention can be directly embedded in hardware, a software module executed by a processor, or a combination of both. The software module can be stored in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and storage medium can be housed in an ASIC, which can be housed in a user terminal. Optionally, the processor and storage medium can also be housed in different components of the user terminal.

[0109] In one or more exemplary designs, the functions described in the embodiments of the present invention can be implemented in hardware, software, firmware, or any combination of these three. If implemented in software, these functions can be stored on a computer-readable medium or transmitted on a computer-readable medium in the form of one or more instructions or code. Computer-readable media include computer storage media and communication media that facilitate the transfer of computer programs from one place to another. Storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, such computer-readable media can include, but is not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store program code in the form of instructions or data structures and other forms that can be read by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Furthermore, any connection can be suitably defined as a computer-readable medium, for example, if the software is transmitted from a website, server or other remote resource via a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wirelessly, such as infrared, wireless and microwave, it is also included in the defined computer-readable medium. The disks and discs mentioned include compressed disks, laser discs, optical discs, DVDs, floppy disks, and Blu-ray discs. Disks typically copy data magnetically, while disks typically copy data optically using lasers. Combinations of the above can also be contained in computer-readable media.

[0110] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A decoder, characterized in that, include: The rising edge detection module is used to receive a voltage signal encoded in Manchester II code and converted by the physical layer transceiver. The voltage signal includes two digital level signals: RX and RX#. The module detects the rising edge of each of RX and RX#. An integrator is used to integrate a positive value when the received RX is high and to obtain an integral value when the received RX# is high. The synchronization header detection and window comparator is used to utilize the symmetry of the synchronization header to pre-determine the synchronization header based on the integral value and the start time of the RX transition edge or the RX# transition edge. Then, it determines the symbol value corresponding to the data bit based on the integral value appearing in the upper or lower decision window and the RX or RX# transition edge. The synchronization header is considered to be successfully determined when decoding the data bits after the synchronization header or when decoding is completed. The synchronization header detection and window comparator includes a synchronization header decision submodule, which is used for: While waiting for the synchronization header, if, starting from the rising edge of RX#, the integral value corresponding to RX for the first half of the synchronization header is higher than the upper limit threshold of the synchronization header in the upper limit threshold comparator, then the instruction / status word is marked as 1 and the data word is marked as 0, wherein the upper limit threshold of the synchronization header is a positive value. If, starting from the rising edge of RX, the integral value corresponding to RX# for the first half of the synchronization header is lower than the synchronization header lower limit threshold in the lower limit threshold comparator, then the instruction / status word is marked as 0, and the data word is marked as 1, wherein the synchronization header lower limit threshold is a negative value.

2. The decoder according to claim 1, characterized in that, The synchronization head detection and window comparator further includes a decision window, which comprises an upper decision window and a lower decision window, wherein: The decision window is used to display the integral value corresponding to the data bits after the synchronization header and to make a judgment based on the integral value corresponding to the data bits; If the integral value corresponding to the current data bit falls within the upper decision window and RX# has a rising edge within the lower decision window, it indicates that the current data bit is valid and satisfies the decoding condition of decoding the current data bit into symbol 1. Therefore, the current data bit is decoded into a symbol with a value of 1; or... If the integral value corresponding to the current data bit falls within the lower decision window and RX has a rising edge within the upper decision window, it indicates that the current data bit is valid and satisfies the decoding condition of decoding the current data bit into symbol 0. Then, the current data bit is decoded into a symbol with a symbol value of 0.

3. The decoder according to claim 2, characterized in that, Also includes: A data receiving shift register is used to receive and latch the symbol value 1 after decoding the current data bit into a symbol value of 1. Alternatively, after decoding the current data bit into a symbol with a symbol value of 0, the symbol value 0 is received and latched. And after obtaining the next symbol value, shift the previous symbol values ​​one bit in sequence, and then receive and latch the next symbol value.

4. The decoder according to claim 2, characterized in that, The upper decision window has a first upper threshold and a first lower threshold, and the position and range of the upper decision window are determined by the first upper threshold and the first lower threshold. The lower decision window has a second upper threshold and a second lower threshold, and the position and range of the lower decision window are determined by the second upper threshold and the second lower threshold. The decision window is specifically used for: If the integral value corresponding to the current data bit exceeds the first lower limit threshold of the upper decision window but is less than the first upper limit threshold, it indicates that the integral value corresponding to the current data bit falls within the upper decision window. If the integral value corresponding to the current data bit crosses the second upper limit threshold of the decision window and is greater than the second lower limit threshold, it indicates that the integral value corresponding to the current data bit falls within the decision window.

5. The decoder according to claim 3, characterized in that, It also includes state machines, where: The synchronization header decision submodule is also used to consider the synchronization header decision as successful when the corresponding symbol value is obtained by decoding the first data bit after the synchronization header, and to determine the second half of the synchronization header by utilizing the symmetry of the synchronization header and latch the synchronization header mark. The state machine is used to transition from the current state to the next state based on state changes during the decoding process.

6. The decoder according to claim 2, characterized in that, The integrator is also used to correct the integral value corresponding to the current data bit to the integral value corresponding to half of the current data bit while decoding the current data bit into a symbol value.

7. The decoder according to claim 5, characterized in that, It also includes a decoding error detection module, which is used for: When the synchronization header is severely distorted, making it impossible to determine a valid synchronization header, the synchronization header decoding is deemed to be incorrect. If the number of valid symbols cannot be correctly determined within the preset time, the data bit decoding is judged to be incorrect. or, If the parity bit is incorrect, the data bit decoding is determined to be incorrect. The parity bit is the result of the real-time verification of the symbol value received in the data receiving shift register by the parity check module. or, If the difference between the width of the first 1.5 bits and the width of the last 1.5 bits of the synchronization header is greater than a preset value, then the synchronization header is determined to be in decoding error. If the binary status code representing the state machine has more than one bit set to 1 or all bits set to 0, then the state machine is considered to have encountered an error.

8. The decoder according to claim 1, characterized in that, The edge-jumping detection module is specifically used for: It receives voltage signals encoded in Manchester II code from the 1553B bus and converted by the physical layer transceiver.

9. A launch vehicle, characterized in that, The decoder includes any one of claims 1-8, the decoder being connected to a physical layer transceiver, the physical layer transceiver being connected to a 1553B bus, wherein the decoder is integrated on an FPGA.

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