Method for testing DDR3 series protocol signal consistency

Abstract

The invention discloses a method for testing DDR3 series protocol signal consistency, and relates to the technical field of communication protocol testing. In order to solve the problems of high cost, low manual test efficiency and test result errors of DDR protocol conformance test in the prior art, the method comprises the following steps: step 1, acquiring protocol signals of a DDR3 series protocol; step 2, preprocessing the protocol signal, intercepting a data segment and obtaining important parameters; and step 3, based on the JEDEC standard, carrying out consistency analysis on the preprocessed signal, calculating at least 49 test indexes, and generating a test report containing a PASS / FAIL conclusion. According to the invention, the test requirements of current industrial products are met, and technical reserve is provided for the construction of a subsequent high-speed protocol test system.

Description

Technical Field

[0001] The present invention relates to the technical field of communication protocol testing, and in particular to a method for testing the consistency of DDR3 series protocol signals. Background Art

[0002] With the iterative evolution of information and communication technology, modern industrial production and daily application scenarios have placed higher demands on the real-time and reliability of data transmission. As information density continues to grow exponentially, the data transmission rate of communication protocols continues to increase, prompting the widespread application of high-speed communication protocols in fields such as intelligent manufacturing, Internet of Things devices, and high-performance computing. To ensure the stable operation of communication systems, the International Organization for Standardization (ISO / IEC) clearly stipulates that the compliance of transmission signals must be verified through protocol conformance testing. This means that the actual transmission signal must be compared and verified with the technical parameters of the protocol standard specifications using professional test equipment. This testing has become a key link in the research, development, and manufacturing of communication equipment.

[0003] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), as the core storage protocol in computer architecture, is widely deployed in key areas such as personal computers, data center servers, and smart terminal devices. According to the DDR standard specification released by the JEDEC Solid State Technology Association, its data transmission rate has been increased to 6000+MT / s. The exponential growth of protocol complexity has made consistency testing increasingly necessary. However, the current global high-speed protocol testing field presents a significant technological monopoly. International test equipment manufacturers represented by Keysight and Tektronix use hardware encryption locks to bind dedicated test software (such as the N7010A DDR5 test suite), forming a technical barrier to software and hardware collaboration. After research and analysis, the current DDR protocol consistency test system mainly has the following problems:

[0004] 1. Mature foreign solutions are expensive and subject to technical controls, which restrict the purchase and use of domestic high-end industrial chains and make it difficult to meet the independent testing needs of my country's scientific research institutions and enterprises.

[0005] 2. The existing manual analysis method cannot achieve automatic analysis of DDR read and write signals, resulting in a complex test process, low efficiency, and increased workload for engineers.

[0006] 3. Manually calculated test indicators have accuracy limitations, and the test indicators vary at different DDR protocol rates, which can easily lead to misjudgments and affect the accuracy and reliability of test results.

[0007] In summary, the research on automated, localized, and low-cost solutions for DDR protocol consistency testing has important practical significance. It not only helps to reduce testing costs, but also enhances my country's independent and controllable capabilities in the field of high-speed communication protocol testing. Summary of the Invention

[0008] The present invention aims to solve the problems of high cost, low manual test efficiency and error in test results in the prior art DDR protocol consistency test, and further proposes a method for testing the consistency of DDR3 series protocol signals.

[0009] The technical solution adopted by the present invention to solve the above problems is:

[0010] The method for testing the consistency of DDR3 series protocol signals described in the present invention comprises the following steps:

[0011] Step 1: Get the protocol signal of the DDR3 series protocol;

[0012] Step 2: Preprocess the protocol signal, intercept the data segment and obtain important parameters;

[0013] Step 3: Based on the JEDEC standard, perform consistency analysis on the preprocessed signal, calculate at least 49 test indicators, and generate a test report with PASS / FAIL conclusions.

[0014] Furthermore, the main purpose of step 1 is to obtain the protocol signal to provide to this method. Since this method can not only be used directly in a programmable oscilloscope, but also can be used offline without a signal acquisition machine, it is sufficient to set up a test environment to collect the protocol signal. Step 1 specifically includes the following steps:

[0015] Step 1.1 Configure the board to be tested: Use different test boards and configure them accordingly depending on the type and speed of the protocol being tested.

[0016] Step 1.2 Connect the test points: Connect the test points of the signal to be tested on the board to the probe as differential or single-ended signals, and then connect to the oscilloscope;

[0017] Step 1.3 Save real data: Set the trigger conditions, intercept the signal, and export the real data; or generate the protocol signal through simulation.

[0018] Furthermore, the main purpose of step 2 is to separate the specific signal according to the protocol specification and set different calibration parameters according to the actual signal characteristics. The specific operation includes the following steps:

[0019] Step 2.1 Signal separation: Determine the read / write state of each waveform segment based on the phase difference between the clock and data signals, and then segment and reassemble the waveform into the read and write states. is the phase difference between the data signal and the clock signal, and the relationship is as follows:

[0020]

[0021] Step 2.2 Signal frequency identification: Since protocols with different rates have different consistency indicators, the signal frequency needs to be calculated using the clock signal.

[0022] Step 2.3 Reference voltage calculation: According to the test signal, confirm the AC level and DC level, and calculate the reference voltage Vref and AC high and low level thresholds V according to the JEDEC specification. IH(AC) With V IL(AC) The relevant formula is as follows, where VDD is the supply voltage, AC_offset and DC_offset are the AC level and DC level respectively:

[0023] V ref =0.5×VDD

[0024] V IH(AC) =V ref +AC_offset

[0025] V IL(AC) =V ref -AC_offset

[0026] V IH(DC) =V ref +DC_offset

[0027] V IL(DC) =V ref -DC_offset

[0028] Furthermore, the main purpose of step 3 is to calculate all test indicators according to the protocol specifications, including tDH, tDS, etc., a total of 49 indicators, and its specific operations include the following steps:

[0029] Step 3.1 Read signal index calculation: Some indicators are only tested under read data. The read signal separated in the previous step is analyzed and calculated to obtain the corresponding index results.

[0030] Step 3.2 Write signal indicator calculation: Some indicators are only tested under write data. The write signal separated in the previous step is analyzed and calculated to obtain the corresponding indicator results.

[0031] Step 3.3 Calculation of other indicators: Some indicators have additional requirements for the length of the data cycle, so the overshoot indicator is calculated after the data reaches the corresponding length.

[0032] The beneficial effects of the present invention are:

[0033] 1. Localization and low cost, breaking the technological monopoly

[0034] This invention, through its independently developed testing solution, eliminates reliance on high-end testing equipment from foreign manufacturers, such as Keysight and Tektronix. It utilizes a general-purpose oscilloscope combined with automated software, significantly reducing hardware procurement costs. Furthermore, it supports offline simulation testing, further reducing the need for specialized hardware and providing a self-sufficient and controllable testing solution for Chinese research institutions and enterprises.

[0035] 2. Automated testing process, flexible adaptation to multi-protocol and multi-rate scenarios

[0036] This invention reduces manual operation errors through automatic signal separation (read / write status identification), automatic parameter calculation (such as frequency and reference voltage), and batch index analysis. It supports the full range of DDR3, DDR3L, and LPDDR3 protocols and a rate range of 800-2133MT / s. By dynamically identifying signal frequencies and adjusting calibration parameters, it achieves "one solution, multiple adaptations."

[0037] 3. Standardized test output to quickly locate data anomalies

[0038] The present invention automatically generates test results including PASS / FAIL conclusions through this solution, which facilitates engineers to quickly verify and trace problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is the waveform diagram of DDR3 CK and DQ signals of the present invention;

[0040] Figure 2 The present invention is to separate reading and writing and obtain key parameters;

[0041] Figure 3 This is the DDR Write signal waveform diagram of the present invention;

[0042] Figure 4 This is the DDR Write test result of the present invention;

[0043] Figure 5 is the DDR Read signal waveform of the present invention;

[0044] Figure 6 This is the DDR Read test result of the present invention;

[0045] Figure 7is the DDR analog test signal waveform of the present invention;

[0046] Figure 8 This is the test result of the DDR simulation test of the present invention;

[0047] Figure 9 This is a flow chart of the method for testing the consistency of DDR3 series protocol signals of the present invention. DETAILED DESCRIPTION

[0048] Specific embodiment 1: A method for testing the consistency of DDR3 series protocol signals described in this embodiment includes the following steps:

[0049] ① Obtain test data of the DDR protocol to be tested;

[0050] ②Preprocess the test data, including intercepting data segments to achieve read-write separation and obtain important parameters;

[0051] ③ Based on the data characteristics, all consistency-related indicators are calculated and compared with the standard specifications to give a conclusion on whether the test indicators pass.

[0052] This implementation uses CK, DQ, and DQS signals collected from a DDR3 test board. These signals include both read and write signals. The DDR3 protocol signal rate for this data is 1066MHz, with 8000 points. These signals contain four segments: read, write, read, and read. The resulting plot of the CK and DQ signals is shown in Figure 1. The blue line represents the single-ended CK signal, and the blue line represents the single-ended DQ signal.

[0053] This solution will first perform read-write separation and important parameter analysis, and the results are as follows Figure 2 As shown: It can be seen that:

[0054] 1. Points 153 to 1895 of readStartEnd: corresponding to the read signal;

[0055] 2.Points 2139 to 3882 of writeStartEnd: correspond to write signals;

[0056] 3. Points 4153 to 5895 of readStartEnd: corresponding to the read signal;

[0057] 4. Points 6153 to 7895 of readStartEnd: correspond to the read signal.

[0058] The corresponding "read-write-read-read" is consistent with the actual signal, and the key parameters VIHac, VILac, VIHdc, and VILdc are obtained.

[0059] After completing the preprocessing, this method will calculate the read signal test indicators, write signal test indicators, and other situation test indicators (CK independent test) respectively, and provide PASS or FAIL results if there are standard specifications.

[0060] Among them, a section of the read signal such as Figure 3 As shown, it includes single-ended and differential signals of DQ, DQS, and CK.

[0061] The test results are as follows Figure 4 As shown in the figure: This solution calculates 18 test indicators for the separated Write data. If the indicator meets the evaluation criteria in the official specification, a test conclusion of PASS or FAIL is given.

[0062] Among them, a section of the write signal such as Figure 5 As shown, it includes single-ended and differential signals of DQ, DQS, and CK.

[0063] like Figure 6 As shown in the figure, this solution calculates nine test indicators for the separated Read data. If the indicator meets the evaluation criteria in the official specifications, a test conclusion of PASS or FAIL is given.

[0064] Since the remaining indicators have high requirements for signal cycles, at least 203 cycles are needed for testing. Also, some indicators are more accurate when calculated with more cycles. Therefore, the remaining indicators are tested using simulated data, such as Figure 7 As shown, it includes single-ended and differential signals of DQ, DQS, and CK.

[0065] like Figure 8 As shown in the figure, this solution calculates 22 test indicators for the simulated test signal. If the indicator meets the evaluation criteria in the official specification, a test conclusion of PASS or FAIL is given.

[0066] The flow chart of the present invention is as follows Figure 9 As shown, the method described in this solution implements a method for testing DDR3 series protocol signal consistency through automated data acquisition, preprocessing, key parameter identification, and test index calculation. This method not only overcomes the challenges of obtaining and costly foreign technical solutions, but also enhances the rapid deployment of DDR3 series protocol signal consistency analysis. It is suitable for current memory signal electrical standard testing for embedded applications, providing reliable support for the localization of related functions and efficient support for subsequent ultra-high-speed protocol analysis.

[0067] Specific implementation method 2: Calculation method of test indicators. The test method of the present invention is based on the JEDEC standard and calculates 49 key indicators in the DDR3 series protocol signal consistency test. The following are the specific calculation steps for each indicator:

[0068] 1.1tDH(base) calculation steps are as follows:

[0069] 1. Determine the first valid WRITE burst and select a DDR write data burst that meets the test conditions.

[0070] 2. Find the time points when all DQ rising edges cross VIL(DC), limit them to the same burst data, and filter out all DQ signal crossing points that meet the conditions.

[0071] 3. Find the time points when all DQ falling edges cross VIH (DC), also limited to the same burst data (Burst), and filter out all DQ signal crossing points that meet the conditions.

[0072] 4. Determine the corresponding DQS zero-crossing point (0V crossing point). For each DQ crossing point found, find the time point when the next DQS signal crosses 0V (Vref). This point is used as the sampling reference point for the data.

[0073] 5. Calculate tDH (data hold time). For each DQ crossing point, calculate tDH = DQS zero crossing time - DQ crossing time to obtain all possible tDH values.

[0074] 6. Collect all tDH measurements and count all calculated tDH values in the burst data to form a data set.

[0075] 7. Select the minimum tDH value as the final test result, that is, the worst tDH value, and compare it with the JEDEC specification for test judgment.

[0076] 1.2tDH(derate) calculation steps are as follows

[0077] 1. Determine the first valid WRITE burst and select a DDR write data burst that meets the test conditions.

[0078] 2. Find the time points when all DQ signal rising edges cross VIL(DC), limit them to the burst data range, and filter out all DQ crossing points that meet the conditions.

[0079] 3. Find the time points when all DQ signal falling edges cross VIH(DC) and ensure that these crossing points belong to the same burst data range.

[0080] 4. Determine the DQS sampling point. For all DQ crossing points found, find the corresponding next DQS zero crossing point (0V crossing point) as the data sampling reference time.

[0081] 5. Calculate tDH (data hold time). For all DQ crossing points, calculate tDH = DQS zero crossing time - DQ crossing time, and record all calculated values.

[0082] 6. Collect all tDH measurements and count all tDH results in the burst data to form a complete data set.

[0083] 7. Filter out the minimum tDH value as the final test result, i.e. the worst tDH (Worst-CasetDH), and output it in the test report.

[0084] 8. Measure the average slew rate of all DQ and DQS edges and calculate the rise / fall slew rate of the DQ and DQS signals.

[0085] 9. Calculate the tDH derating correction value according to the derating table. Use the average slew rate of DQ and DQS to find the ΔtDH derating value and apply it to the calculation.

[0086] 10. Calculate the tDH test limit and compare it with the JEDEC specification for test judgment. The final test value is calculated according to the formula:

[0087] DH limit =tDH base +ΔtDH

[0088] 1.3 The calculation steps for Slew Rise on Setup Region are as follows:

[0089] 1. Acquire signals and extract target signals from the data set for analysis, including DQ, DQS, or CK signals.

[0090] 2. Find all valid rising edges in the entire acquisition and filter the signal changes that meet the conditions, that is, starting from the VIL (ac) intersection point and ending at the VIH (ac) intersection point to form a complete rising edge.

[0091] 3. Calculate the rising edge transition time (ΔTR). For all valid rising edges, calculate the time interval from the VREF crossing point to the VIH(ac) crossing point. Then calculate the rising slew rate:

[0092]

[0093] 4. Filter the worst rising slew rate and find the minimum value (the slowest slew rate) among all calculated rising slew values as the final result of the test report.

[0094] 1.4 The steps for calculating Slew Fall on Setup Region are as follows:

[0095] 1. Acquire signals and extract target signals from the data set for analysis, including DQ, DQS, or CK signals.

[0096] 2. Find all valid falling edges in the entire acquisition and filter the signal changes that meet the conditions, that is, starting from the VIH(ac) crossing point and ending at the VIL(ac) crossing point to form a complete falling edge.

[0097] 3. Calculate the falling edge transition time (ΔTF). For all valid falling edges, calculate the time interval from the VREF crossing point to the VIL(ac) crossing point. Then calculate the falling slew rate:

[0098]

[0099] 4. Filter the worst falling slew rate and find the minimum value (the slowest slew rate) among all calculated falling slew values as the final result of the test report.

[0100] 1.5 The calculation steps for Slew Rise on Hold Region are as follows:

[0101] 1. Acquire signals and extract target signals from the data set for analysis, including DQ, DQS, or CK signals.

[0102] 2. Find all valid rising edges in the entire acquisition and filter the signal changes that meet the conditions, that is, starting from the VIL (ac) intersection point and ending at the VIH (ac) intersection point to form a complete rising edge.

[0103] 3. Calculate the rising edge transition time (ΔTR). For all valid rising edges, calculate the time interval from the VREF crossing point to the VIH(ac) crossing point, and then calculate the rising slew rate.

[0104]

[0105] 4. Filter the worst rising slew rate and find the minimum value (the slowest slew rate) among all calculated rising slew values as the final result of the test report.

[0106] 1.6 The calculation steps for Slew Fall on Hold Region are as follows:

[0107] 1. Acquire signals and extract target signals from the data set for analysis, including DQ, DQS, or CK signals.

[0108] 2. Find all valid falling edges in the entire acquisition and filter the signal changes that meet the conditions, that is, starting from the VIH(ac) crossing point and ending at the VIL(ac) crossing point to form a complete falling edge.

[0109] 3. Calculate the falling edge transition time (ΔTF). For all valid falling edges, calculate the time interval from the VREF crossing point to the VIL(ac) crossing point, and then calculate the falling slew rate.

[0110]

[0111] 4. Filter the worst falling slew rate and find the minimum value (the slowest slew rate) among all calculated falling slew values as the final result of the test report.

[0112] 1.7tDQSH calculation steps are as follows:

[0113] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements.

[0114] 2. Find all valid rising and falling DQS crossing points in the burst data to ensure that the complete DQS signal transition range is covered.

[0115] 3. Calculate tDQSH (DQS High Time), which is the time from the rising edge of DQS to the next falling edge.

[0116] 4. Collect all tDQSH measurements and count the tDQSH results calculated from all burst data to form a complete data set.

[0117] 5. Select the worst tDQSH as the final test result, that is, the smallest tDQSH among all measured values, and compare it with the JEDEC specification for test judgment.

[0118] The steps for calculating 1.8tDQSL are as follows:

[0119] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements.

[0120] 2. Find all valid rising and falling DQS crossing points in the burst data to ensure that the complete DQS signal transition range is covered.

[0121] 3. Calculate tDQSL (DQS Low Time), which is the time from the falling edge of DQS to the next rising edge.

[0122] 4. Collect all tDQSL measurements and count the tDQSL results calculated from all burst data to form a complete data set.

[0123] 5. Select the worst tDQSL as the final test result, that is, the smallest tDQSL among all measured values, and compare it with the JEDEC specification for test judgment.

[0124] The steps for calculating 1.9tDQSS are as follows:

[0125] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements.

[0126] 2. Find all valid DQS rising intermediate crossing points in the burst data, that is, all rising edges where DQS signals cross Vref.

[0127] 3. Determine the tDQSS strobe point. Among all the DQS crossing points found, search for the earliest DQS rising crossing point and use it as the tDQSS strobe point (the first DQS rising edge).

[0128] 4. Find the nearest clock-DQS relationship point. In the burst data, find the CK (clock) signal rising crossing point closest to the first DQS rising crossing point.

[0129] 5. Calculate the tDQSS test result, which is tDQSS strobe point - tDQSS clock point.

[0130] 6. Mark the tDQSS strobe point and tDQSS clock point on the waveform to visualize the tDQSS test point for debugging and verification of measurement location.

[0131] 7. Compare the tDQSS result with the compliance test limit. If the test value exceeds the tDQSS range specified by JEDEC, the test is considered to have failed, otherwise it is considered to have passed.

[0132] 1.10tDS(base) calculation steps are as follows:

[0133] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements.

[0134] 2. Find all valid DQ rising crossing points in the burst data and filter out the time points when all DQ signal rising edges cross Vih(ac).

[0135] 3. Find all valid DQ falling crossing points in the burst data and filter out the time points when all DQ signal falling edges cross Vil(ac).

[0136] 4. Determine the DQS sampling point. For all DQ crossing points found, find the corresponding next DQS zero crossing point (0V crossing point) as the data sampling reference time.

[0137] 5. Calculate tDS (data setup time), record the time interval between each DQ crossing point and its corresponding DQS crossing point, and collect all tDS measurements.

[0138] 6. Select the worst tDS as the final test result, that is, the minimum tDS among all measured values, and compare it with the JEDEC specification for test judgment.

[0139] 1.11tDS-Diff(derate) calculation steps are as follows:

[0140] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements.

[0141] 2. Find all valid DQ rising crossing points in the burst data and filter out the time points when all DQ signal rising edges cross VIH(AC).

[0142] 3. Find all valid DQ falling crossing points in the burst data and filter out the time points when all DQ signal falling edges cross VIL(AC).

[0143] 4. Determine the DQS sampling point. For all DQ crossing points found, find the corresponding next DQS zero crossing point (0V crossing point) as the data sampling reference time.

[0144] 5. Calculate tDS (data setup time), defined as the time between DQ crossing and DQS crossing.

[0145] 6. Collect all tDS and count the tDS results calculated from all burst data to form a complete data set.

[0146] 7. Filter out the worst tDS as the final test result, that is, the smallest tDS among all measured values, and output it to the test report.

[0147] 8. Measure the average slew rate of all DQ and DQS signals and calculate the rise / fall slew rate of the DQ and DQS signals for subsequent derating calculations.

[0148] 9. Calculate the tDS derating correction value according to the derating table. Use the average slew rate of DQ and DQS to find the ΔtDS derating value and apply it to the calculation.

[0149] 10. Calculate the tDS test limit using the formula:

[0150] tDS limit =tDS base +ΔtDS

[0151] 1.12tDSS calculation steps are as follows:

[0152] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements.

[0153] 2. Find all valid DQS falling crossing points in the burst data and filter all the time points where the falling edge of the DQS signal crosses Vref.

[0154] 3. For all found DQS falling crossing points, locate the nearest clock (CK) rising edge and find the CK signal rising crossing point closest to the DQS falling edge.

[0155] 4. Calculate tDSS (DQS Fall to Clock Rise Skew), which is the time between the falling DQS crossing point and the detection of the clock rising edge.

[0156] 5. Collect all tDSS measurements and count the tDSS results calculated from all burst data to form a complete data set.

[0157] 6. Select the worst tDSS as the final test result, that is, the smallest tDSS among all measured values, and compare it with the JEDEC specification for test judgment.

[0158] 1.13tDSH calculation steps are as follows:

[0159] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements.

[0160] 2. Find all valid DQS falling crossing points in the burst data and filter all the time points where the falling edge of the DQS signal crosses Vref.

[0161] 3. For all found DQS falling crossing points, locate the nearest clock (CK) rising edge and find the CK signal rising crossing point closest to the DQS falling edge.

[0162] 4. Calculate tDSH (DQS Fall to Clock Rise Hold Time), which is the time between the DQS fall point and the crossing point of the clock rise edge.

[0163] 5. Collect all tDSH measurements and count the tDSH results calculated from all burst data to form a complete data set.

[0164] 6. Select the worst tDSH as the final test result, that is, the minimum tDSH among all measured values, and compare it with the JEDEC specification for test judgment.

[0165] 1.14tDVAC(Clock) calculation steps are as follows:

[0166] 1. Trigger on the rising edge of the measured clock signal to ensure that data acquisition starts from a stable clock rising edge to ensure measurement accuracy.

[0167] 2. Find the rising / falling edge of the measured signal and V ILdiff(AC) For all intersections, record the intersection time.

[0168] 3. Find the rising / falling edge of the measured signal and V IHdiff(AC) For all intersections, record the intersection time.

[0169] 4. Calculate tVAC (clock), which is the time it takes to generate a rising V IHdiff(AC) Starting from the intersection point, to the next descending ViHdiff(AC)

[0170] The time when the intersection ends.

[0171] 5. Calculate tVVAC(clock), which is the time from a falling V ILdiff(AC) The intersection starts and ends at the next rising V ILdiff(AC) intersection.

[0172] 6. Collect all tVAC (clocks) and count all measurement data.

[0173] 7. Filter out the worst tVAC (clock) as the final test result, that is, the maximum or minimum tVAC (clock) among all measured values, depending on the measurement target.

[0174] 8. The worst-case tDVAC(clock) value is reported. However, no compliance limit check is performed; the measurement result is only recorded for further analysis.

[0175] 1.15 tDVAC(Strobe) calculation steps are as follows:

[0176] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements.

[0177] 2. Find the burst data, DQS signal at V IHdiff(AC) and V ILdiff(AC) All valid rising and falling crossing points on the DQS signal are recorded, ensuring that the complete changes of all DQS signals are recorded.

[0178] 3. Calculate tDVAC (Strobe), which is the time from the DQS rising edge through V IHdiff(AC) The crossing point starts at the next DQS falling edge crossing the V IHdiff(AC) The time when the intersection ends.

[0179] 4. Calculate tDVAC (Strobe), which is the time from the DQS falling edge through V ILdiff(AC) The crossing point starts at the next DQS rising edge crossing the V ILdiff(AC) The time when the intersection ends.

[0180] 5. Collect all tDVAC(Strobe) and count the tDVAC(Strobe) results calculated from all burst data.

[0181] 6. Select the worst tDVAC(Strobe) as the final test result, that is, the maximum or minimum tDVAC(Strobe) among all the measured values, depending on the measurement target.

[0182] 7. Report the worst tDVAC(Strobe) value and output it to the test report for further analysis and compliance verification.

[0183] 1.16 tDIPW calculation steps are as follows:

[0184] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements.

[0185] 2. Find all valid DQ crossing points in the above burst and filter out the time points when all DQ signal rising and falling edges cross VREF.

[0186] 3. Calculate tDIPW (DQ input pulse width time), which is the time from the rising / falling edge of DQ to the next falling / rising edge (the next edge cannot be in the same direction).

[0187] 4. Collect all tDIPW measurements and count the tDIPW results calculated from all burst data.

[0188] 5. Filter out the worst tDIPW as the final test result, that is, the smallest tDIPW among all measured values, and output it to the test report.

[0189] 1.17 The calculation steps for tWPRE are as follows:

[0190] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements as the analysis target.

[0191] 2. Find the tLZBeginPoint of the burst, that is, the starting time point of DQS failure (de-driving), for subsequent calculation of tWPRE (write precharge time).

[0192] 3. In the DQS signal of the burst data, find the first rising edge, that is, the rising crossing point where the DQS signal first crosses VREF, as the reference time point.

[0193] 4. Calculate tWPRE (write precharge time), which is the time interval from the first rising DQS edge to tLZBeginPoint.

[0194] 5. Record the calculated tWPRE results in the test report and compare them with the JEDEC specification for test judgment.

[0195] 1.18 The calculation steps for tWPST are as follows:

[0196] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements as the analysis target.

[0197] 2. Find the tHZEndPoint of the burst, that is, the end time point of DQS failure (entering the high-impedance state), for subsequent calculation of tWPST (write hold time).

[0198] 3. Before the found tHZEndPoint, find the last falling edge on the DQS signal, that is, the falling crossing point where the DQS signal crosses VREF for the last time, as the reference time point.

[0199] 4. Calculate tWPST (write hold time), which is the time interval between the last falling edge of DQS and tHZEndPoint.

[0200] 5. Record the calculated tWPST results in the test report and compare them with the JEDEC specification for test judgment.

[0201] 1.19 The SRQdiff-Rise calculation steps are as follows:

[0202] 1. Take the first valid READ burst found and select the DDR write data burst that meets the test requirements as the analysis target.

[0203] 2. Find all valid Strobe (DQS) rising edges in this burst. Filter out all rising edges from V OLdiff(AC) Starts at the intersection and ends at the next V OHdiff(AC) Strobe rising edge between intersections.

[0204] 3. Calculate the transition time T of the Strobe rising edge R , T R From V OLdiff(AC) The intersection starts at the next V OHdiff(AC) The time when the intersection ends. Then calculate SRQdiffR, the formula is as follows.

[0205]

[0206] 4. Select the worst SRQdiffR as the final test result and compare it with the JEDEC specification for test judgment.

[0207] 1.20 SRQdiff-Fall calculation steps are as follows:

[0208] 1 Take the first valid READ burst (Burst) found and select the DDR write data burst that meets the test requirements as the analysis target.

[0209] 2. Find all valid Strobe (DQS) falling edges in this burst. Filter out all the falling edges from V OHdiff(AC) Starts at the intersection and ends at the next V OLdiff(AC) Strobe rising edge between intersections.

[0210] 3 Calculate the transition time T of the falling edge of Strobe R , T R From V OHdiff(AC) The intersection starts at the next V OLdiff(AC) The time when the intersection ends. Then calculate SRQdiffF, the formula is as follows.

[0211]

[0212] 4. Filter the worst SRQdiffF as the final test result and compare it with the JEDEC specification for test judgment.

[0213] 1.21 tDQSCK calculation steps are as follows:

[0214] 1. Take the first valid READ burst found and select the DDR read data burst that meets the test requirements as the analysis target.

[0215] 2. Find all valid DQS rising crossing points in the burst data and filter the time points when all DQS signal rising edges cross VREF.

[0216] 3. For all discovered DQS crossing points, find the nearest clock (CK) rising crossing point at 0V, that is, the CK signal rising edge closest to the DQS crossing point to ensure data synchronization.

[0217] 4. Calculate tDQSCK (DQS to clock synchronization time), that is, the different time from DQS crossing to the corresponding clock crossing as tDQSCK.

[0218] 5. Select the worst tDQSCK as the final test result and compare it with the JEDEC specification for test judgment.

[0219] 1.22 tDQSQ calculation steps are as follows:

[0220] 1. Take the first valid READ burst found and select the DDR read data burst that meets the test requirements as the analysis target.

[0221] 2. In the above burst data, find all valid DQ rising and falling crossing points, that is, the crossing time points of all DQ signals at VREF.

[0222] 3. For all DQ crossing points found, find the nearest DQS crossing point (rising or falling), that is, the rising or falling edge of the DQS signal closest to the DQ crossing point to ensure relative synchronization of the data.

[0223] 4. Calculate tDQSQ (DQS to DQ timing skew), which is the time difference between DQ crossing and DQS crossing.

[0224] 5. Select the worst tDQSQ as the final test result and compare it with the JEDEC specification for test judgment.

[0225] 1.23 tQH calculation steps are as follows:

[0226] 1. Take the first valid READ burst found and select the DDR read data burst that meets the test requirements as the analysis target.

[0227] 2. In the above burst data, find all valid DQ rising and falling crossing points, that is, the crossing time points of all DQ signals at VREF.

[0228] 3. For all found DQ crossing points, find the nearest DQS rising crossing point, that is, the DQS signal rising edge closest to the DQ crossing point, to ensure the reference time of data sampling.

[0229] 4. Use the discovered DQS rising crossing to locate its previous DQS rising crossing point (prior crossing point), that is, the time point when the previous rising edge of the DQS signal crossed VREF.

[0230] 5. Calculate tQH (DQ hold time), which is the time difference between the DQ point and the DQS point.

[0231] 6. Select the worst tQH as the final test result and compare it with the JEDEC specification for test judgment.

[0232] 1.24 tRPRE calculation steps are as follows:

[0233] 1. Take the first valid READ burst found and select the DDR read data burst that meets the test requirements as the analysis target.

[0234] 2. Find the tLZBeginPoint of the burst, which is the starting time point when DQS enters the low-impedance state (drive valid), for subsequent calculation of tRPRE (read precharge time)

[0235] 3. In the DQS signal of the burst data, find the first rising edge, that is, the rising crossing point where the DQS signal first crosses VREF, as the reference time point.

[0236] 4. Calculate tRPRE (read precharge time), which is the time between the DQS edge rising to tLZBeginPoint.

[0237] 5. Report tRPRE and compare it to the JEDEC specification for test judgment.

[0238] 1.25 tRPST calculation steps are as follows:

[0239] 1. Take the first valid READ burst found and select the DDR read data burst that meets the test requirements as the analysis target.

[0240] 2. Find the tHZEndPoint of the burst, that is, the end time point when DQS enters the high-impedance state (driver failure), which is used for subsequent calculation of tRPST (read hold time).

[0241] 3. Before the found tHZEndPoint, find the last falling edge on the DQS signal, that is, the falling crossing point where the DQS signal crosses VREF for the last time, as the reference time point.

[0242] 4. Calculate tRPST (post-read hold time), which is the time between the crossing point of the falling DQS edge and finding tHZEndPoint.

[0243] 5. Report tRPST and compare it to the JEDEC specification for test judgment.

[0244] 1.26 tQSH calculation steps are as follows:

[0245] 1. Take the first valid READ burst found and select the DDR read data burst that meets the test requirements as the analysis target.

[0246] 2. Find all valid DQS rising and falling crossing points in the burst data, and filter out the rising and falling time points where all DQS signals cross VREF.

[0247] 3. Calculate tQSH (DQS high time), which is the time interval from the rising edge of DQS to the next falling edge.

[0248] 4. Collect all tQSH and count the tQSH results calculated from all burst data.

[0249] 5. Select the worst tQSH as the final test result, that is, the smallest tQSH among all measured values, and compare it with the JEDEC specification for test judgment.

[0250] 1.27 tQSL calculation steps are as follows:

[0251] 1. Take the first valid READ burst found and select the DDR read data burst that meets the test requirements as the analysis target.

[0252] 2. Find all valid DQS rising and falling crossing points in the burst data, and filter out the rising and falling time points where all DQS signals cross VREF.

[0253] 3. Calculate tQSL (DQS low time), which is the time interval from the falling edge of DQS to the next rising edge.

[0254] 4. Collect all tQSL and count the tQSH results calculated from all burst data.

[0255] 5. Select the worst tQSH as the final test result, that is, the smallest tQSH among all measured values, and compare it with the JEDEC specification for test judgment.

[0256] 1.28 tCH(abs) calculation steps are as follows:

[0257] This parameter can be calculated only when the signal to be analyzed meets the following restrictions: frequency 1 kHz, number of cycles obtained ≥ 202.

[0258] Calculation steps:

[0259] 1. Calculate the average period tCK(avg) of periods 1-202.

[0260] 2. Find the maximum high pulse width, PWMAX(s) for period 1-202.

[0261] 3. Find the minimum high pulse width, PWMIN(s), for period 1-202.

[0262] 4. Calculate PWMAX(tCK) = PWMAX(s) / tCK(avg).

[0263] 5. Calculate PWMIN(tCK) = PWMIN(s) / tCK(avg).

[0264] 6. Check the worst-case values of PWMAX(tCK) and PWMIN(tCK).

[0265] 7. Compare the test results to the compliance test limits according to JEDEC specifications.

[0266] 1.29 tCH(avg) calculation steps are as follows:

[0267] This parameter can be calculated only when the signal to be analyzed meets the following restrictions: frequency 1 kHz, number of cycles obtained ≥ 202.

[0268] Calculation steps:

[0269] 1. Measure a sliding "window" of 200 cycles.

[0270] 2. Measure the width of the high pulse 1-200 and determine the average value of this window. (Generates 1 measurement result).

[0271] 3. Measure the width of the high pulse 2-201 and determine the average value of the window. (So far, a total of 2 measurements have been generated).

[0272] 4. Measure the width of the high pulse 3-202 and determine the average value of the window. (So far, a total of 3 measurements have been generated).

[0273] 5. Check the minimum and maximum values (worst case values) among the total 3 results.

[0274] 6. Compare test results to compliance test limits against JEDEC specifications.

[0275] 1.30 tCK(abs) calculation steps are as follows:

[0276] This parameter can be calculated only when the signal to be analyzed meets the following restrictions: frequency 1 kHz, number of cycles obtained ≥ 202.

[0277] Calculation steps:

[0278] 1. Calculate the maximum period value of periods 1-202.

[0279] 2. Calculate the minimum period value of period 1-202.

[0280] 3. For the above two results, check the worst result.

[0281] 4. Compare the test results to the compliance limits against the JEDEC specifications.

[0282] 1.31 tCK(avg) calculation steps are as follows:

[0283] This parameter can be calculated only when the signal to be analyzed meets the following restrictions: frequency 1 kHz, number of cycles obtained ≥ 202.

[0284] Calculation steps:

[0285] 1. Calculate the average period value for periods 1-200.

[0286] 2. Calculate the average value for period 2-201.

[0287] 3. Calculate the average period value for period 3-202 (so far, 3 measurements have been generated).

[0288] 4. Check the minimum and maximum values (worst case values) in the results.

[0289] 5. Compare test results to compliance test limits against JEDEC specifications.

[0290] 1.32 tCL(abs) calculation steps are as follows:

[0291] This parameter can be calculated only when the signal to be analyzed meets the following restrictions: frequency 1 kHz, number of cycles obtained ≥ 202.

[0292] Calculation steps:

[0293] 1. Calculate the average period tCK(avg) of periods 1-202.

[0294] 2. Find the maximum low pulse width, PWMAX(s), of period 1-202.

[0295] 3. Find the minimum low pulse width, PWMIN(s), for period 1-202.

[0296] 4. Calculate PWMAX(tCK) = PWMAX(s) / tCK(avg).

[0297] 5. Calculate PWMIN(tCK) = PWMIN(s) / tCK(avg).

[0298] 6. Check the worst-case values of PWMAX(tCK) and PWMIN(tCK).

[0299] 7. Compare the test results to the compliance test limits according to JEDEC specifications.

[0300] 1.33 tCL(avg) calculation steps are as follows:

[0301] This parameter can be calculated only when the signal to be analyzed meets the following restrictions: frequency 1 kHz, number of cycles obtained ≥ 202.

[0302] Calculation steps:

[0303] 1. Measure the width of the low pulse 1-200 and determine the average value of this window. (Generates 1 measurement result).

[0304] 2. Measure the width of the low pulse 2-201 and determine the average value of this window. (So far, a total of 2 measurements have been generated).

[0305] 3. Measure the width of the low pulse 3-202 and determine the average value of this window. (So far, a total of 3 measurements have been generated).

[0306] 4. Check the minimum and maximum values (worst case values) among the total 3 results.

[0307] 5. Compare the results to the compliance test limits against the JEDEC specifications.

[0308] 1.34 The calculation steps for Overshoot Amplitude / Area for Clock Plus Tests are as follows:

[0309] 1. Find the overshoot region in the acquired waveform. The overshoot region starts at the rising VDDQ (or VDDCA) crossing point and ends at the falling VDDQ (or VDDCA) crossing point.

[0310] 2. In overshoot region #1, perform the following steps:

[0311] a) Evaluate the overshoot amplitude by performing the following steps:

[0312] i. Use overshoot amplitude = VMAX-VDDQ (or VDDCA).

[0313] ii. Calculate the area below VDDQ (or VDDCA) = (end of overshoot region - start of overshoot region) × VDDQ (or VDDCA).

[0314] b) Calculate the total area above 0 volts using the trapezoidal area method.

[0315] c) Calculate the area above VDDQ (or VDDCA) = total area above 0 V - area below VDDQ (or VDDCA).

[0316] d) Store the following calculation results:

[0317] i. Excessive amplitude

[0318] ii. Area above VDDQ (or VDDCA)

[0319] 3. Repeat the previous step for the remaining overshoot regions found in the acquired waveform.

[0320] 4. Find the worst result below from the stored results.

[0321] 5. Compare the following test results with the compliance test limits.

[0322] a) Excessive amplitude

[0323] b) Area above VDDQ (or VDDCA)

[0324] 1.35 Undershoot Amplitude / Area for Clock Plus Tests calculation steps are as follows:

[0325] 1. Get the undershoot region. The undershoot region starts at the falling 0V crossing and ends at the rising 0V crossing.

[0326] 2. In undershoot region #1, perform the following steps:

[0327] a) Perform the following steps to evaluate the undershoot amplitude:

[0328] i. Use TMIN and VMIN to get the timestamp of the maximum voltage in the undershoot area of the acquired waveform

[0329] ii. Calculation: Undershoot amplitude = 0-VMIN

[0330] b) Calculate the total area below 0 volts using the trapezoidal area calculation method

[0331] c) The calculation results are as follows, which will be used for the worst case search process later:

[0332] i. Negative pulse signal amplitude

[0333] ii. Total area below 0V

[0334] 3. Repeat the previous step for the remaining undershoot regions found in the acquired waveform.

[0335] 4. Find the worst result below from the stored results.

[0336] 5. Compare the following test results with the compliance test limits.

[0337] a) Negative pulse signal amplitude

[0338] b) The total area is below 0V

[0339] 1.36 VSEH (Clock Plus) calculation steps are as follows:

[0340] 1. Trigger on the rising edge of the clock signal to ensure that the measurement reference point is synchronized with the clock signal to improve measurement accuracy.

[0341] 2. Find all valid clock positive pulses in the entire waveform. Filter out all positive pulses starting from the rising edge of the clock crossing VREF and ending at the falling edge of the clock crossing the next VREF to ensure data integrity.

[0342] 3. Measure the first valid clock positive pulse and the pulse width TMAX, that is, the maximum pulse duration.

[0343] 4. Measure VTIME at TMAX, obtain the maximum voltage value of the pulse, and use the measurement result as the VSEH value.

[0344] 5. Repeat the measurement for the other nine valid clock positive pulses to ensure the statistical reliability of the data and record all VSEH values.

[0345] 6. Select the worst VSEH as the final test result, that is, the maximum or minimum VSEH among all measured values, and compare it with the JEDEC specification for test judgment.

[0346] 1.37VSEL (Clock Plus) calculation steps are as follows:

[0347] 1. Trigger on the rising edge of the clock signal to ensure that the measurement reference point is synchronized with the clock signal to improve measurement accuracy.

[0348] 2. Find all valid clock negative pulses in the entire waveform. Filter out all negative pulses starting from the falling edge of the clock crossing VREF and ending at the rising edge of the clock crossing the next VREF to ensure data integrity.

[0349] 3. For the first valid clock negative pulse, amplify the pulse so that it appears on the oscilloscope display and measure TMIN.

[0350] 4. Measure VTIME at the found TMIN to obtain the minimum voltage of the pulse. The VTIME measurement result is used as the VSEL value.

[0351] 5. Continue with the previous steps using another 9 valid negative pulses found in the waveform.

[0352] 6. Determine the worst-case result from the measured VSEL and compare it to the JEDEC specification for test justification.

[0353] 1.38VIX for Clock calculation steps are as follows:

[0354] 1. Use the subtraction function to subtract the two input sources to obtain the differential signal.

[0355] 2. Ensure that all correct differential clock signals (differential CLK) cross 0V, that is, find the points where all CLK+ and CLK- signals cross 0V as valid crossing points.

[0356] 3. Obtain the actual voltage value of each intersection and record the timestamp of the intersection to ensure data accuracy.

[0357] 4. Calculate VIX(AC) (intersection voltage). For each intersection voltage, calculate VIX(AC) = intersection voltage

[0358] -VDD / 2.

[0359] 5. Select the worst VIX(AC) as the final test result, that is, the maximum or minimum VIX(AC) among all measured values, and compare it with the JEDEC specification for test judgment.

[0360] 1.39Overshoot Amplitude / Area (Strobes Plus) calculation steps are as follows:

[0361] 1. Get the overshoot region. The overshoot region starts at the rising VDDQ intersection and ends at the falling VDDQ intersection.

[0362] 2. In overshoot region #1, perform the following steps:

[0363] a) Evaluate the overshoot amplitude by performing the following steps:

[0364] i. Use TMAX and VMAX to get the timestamp of the maximum voltage in the overshoot region of the acquired waveform.

[0365] ii. Calculation: Overshoot amplitude = VMAX - VDDQ.

[0366] b) Evaluation area below VDDQ = (overshoot region end - overshoot region start) * VDDQ.

[0367] c) Calculate the total area above 0 volts using the trapezoidal area method.

[0368] d) Calculate the area above VDDQ = total area above 0V - area below VDDQ.

[0369] e) Store the calculation results as follows for future worst case discovery process

[0370] i. Excessive amplitude

[0371] ii.VDDQ or above

[0372] 3. Repeat the previous step for the remaining overshoot regions found in the acquired waveform.

[0373] 4. Find the worst result below from the stored results.

[0374] 5. Compare the following test results with the compliance test limits.

[0375] a) Excessive amplitude

[0376] b) VDDQ or above

[0377] 1.40 Undershoot Amplitude / Area (Strobes Plus) calculation steps are as follows:

[0378] 1. Get the undershoot region. The undershoot region starts at the falling 0V crossing and ends at the rising 0V crossing.

[0379] 2. In undershoot zone #1;

[0380] a) Perform the following steps to evaluate the undershoot amplitude:

[0381] i. Use TMIN and VMIN to get the timestamp of the maximum voltage in the undershoot region of the acquired waveform.

[0382] ii. Calculation: Undershoot amplitude = O-VMIN

[0383] b) Calculate the total area below 0 volts using the trapezoidal area calculation method

[0384] c) The Store calculation results are as follows:

[0385] i. Negative pulse signal amplitude

[0386] ii. Total area below 0V

[0387] 3. Repeat the previous step for the remaining undershoot regions found in the acquired waveform.

[0388] 4. Find the worst result below from the stored results.

[0389] 5. Compare the following test results with the compliance test limits.

[0390] a) Negative pulse signal amplitude

[0391] b) The total area is below 0V

[0392] 1.41VSEH (Strobes Plus) calculation steps are as follows:

[0393] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements as the analysis target.

[0394] 2. Find all valid DQS strobe positive pulses in the burst and filter out all positive pulses starting from the DQS rising edge of the VREF crossing and ending at the DQS falling edge of the next VREF crossing to ensure data integrity.

[0395] 3. Measure the first valid DQS strobe positive pulse and the width TMAX of the pulse, i.e. the duration of the pulse.

[0396] Maximum

[0397] 4. Measure VTIME at TMAX, obtain the maximum voltage value of the pulse, and use the measurement result as the VSEH value.

[0398] 5. Repeat the previous step for other valid DQS strobe positive pulses in the burst to ensure statistical reliability of the data and record all VSEH values.

[0399] 6. Select the worst VSEH as the final test result, that is, the maximum or minimum VSEH among all measured values, and compare it with the JEDEC specification for test judgment.

[0400] 1.42VSEL (Strobes Plus) calculation steps are as follows:

[0401] 1. Take the first valid WRITE burst found and select the DDR write data burst that meets the test requirements as the analysis target.

[0402] 2. Find all valid DQS strobe negative pulses in the burst and filter out all negative pulses starting from the DQS falling edge of the VREF crossing and ending at the DQS rising edge of the next VREF crossing to ensure data integrity.

[0403] 3. Measure the first valid DQS strobe negative pulse and measure the pulse width TMIN, which is the minimum pulse duration.

[0404] 4. Measure VTIME at TMIN, obtain the minimum voltage value of the pulse, and use the measurement result as the VSEL value.

[0405] 5. Repeat the previous step for other valid DQS strobe negative pulses in the burst to ensure the statistical reliability of the data and record all VSEL values.

[0406] 6. Select the worst VSEL as the final test result, that is, the maximum or minimum VSEL among all measured values, and compare it with the JEDEC specification for test judgment.

[0407] 1.43Overshoot Amplitude / Area (Data) calculation steps are as follows:

[0408] 1. Get the overshoot region. The overshoot region starts at the rising VDDQ intersection and ends at the falling VDDQ intersection.

[0409] 2. In overshoot region #1, perform the following steps:

[0410] a) Evaluate the overshoot amplitude by performing the following steps:

[0411] i. Use TMAX and VMAX to get the timestamp of the maximum voltage in the overshoot region of the acquired waveform.

[0412] ii. Calculation: Overshoot amplitude = VMAX - VDDQ.

[0413] b) Evaluation area below VDDQ = (overshoot region end - overshoot region start) * VDDQ.

[0414] c) Calculate the total area above 0 volts using the trapezoidal area method.

[0415] d) Calculate the area above VDDQ = total area above 0V - area below VDDQ.

[0416] e) Store the calculation results as follows for future worst case discovery process

[0417] i. Excessive amplitude

[0418] ii.VDDQ or above

[0419] 3. Repeat the previous step for the remaining overshoot regions found in the acquired waveform.

[0420] 4. Find the worst result below from the stored results.

[0421] 5. Compare the following test results with the compliance test limits.

[0422] a) Excessive amplitude

[0423] b) VDDQ or above

[0424] 1.44Undershoot Amplitude / Area (Data) calculation steps are as follows:

[0425] 1. Get the undershoot region. The undershoot region starts at the falling 0V crossing and ends at the rising 0V crossing.

[0426] 2. In undershoot zone #1;

[0427] a) Perform the following steps to evaluate the undershoot amplitude:

[0428] i. Use TMIN and VMIN to get the timestamp of the maximum voltage in the undershoot region of the acquired waveform.

[0429] ii. Calculation: Undershoot amplitude = O-VMIN

[0430] b) Calculate the total area below 0 volts using the trapezoidal area calculation method

[0431] c) The Store calculation results are as follows:

[0432] i. Negative pulse signal amplitude

[0433] ii. Total area below 0V

[0434] 3. Repeat the previous step for the remaining undershoot regions found in the acquired waveform.

[0435] 4. Find the worst result below from the stored results.

[0436] 5. Compare the following test results with the compliance test limits.

[0437] a) Negative pulse signal amplitude

[0438] b) The total area is below 0V

[0439] The calculation steps for 1.45tIH(base) are as follows:

[0440] 1. Trigger on the rising or falling edge of the address / control signal being tested.

[0441] 2. Find all the rising edges of the measured signal that cross V IL(DC) The intersection point of VIL(DC) is recorded, and the time point when the signal changes from below VIL(DC) to above VIL(DC) is recorded.

[0442] 3. Find all the points that cross V on the falling edge of the measured signal. IH(DC) The crossing point of the signal is recorded from above VIH(DC) to below VIH(DC).

[0443] 4. For all found crossing points, find the nearest clock crossing point that intersects 0V

[0444] 5. Take the time difference between the measured signal and the corresponding clock crossing as tIH.

[0445] 6. Collect all measured tIH.

[0446] 7. Select the worst tIH as the final test result, that is, the smallest tIH among all measured values, and compare it with the JEDEC specification for test judgment.

[0447] The calculation steps for 1.46tIH(derate) are as follows:

[0448] 1. Trigger on the rising or falling edge of the address / control signal being tested.

[0449] 2. Find all intersections of the rising edge of the measured signal with Vil(dc) and record the time when the signal changes from below VIL(DC) to above VIL(DC).

[0450] 3. Find all the intersections of the falling edge of the measured signal that cross Vih(dc) and record the time when the signal changes from above VIH(DC) to below VIH(DC).

[0451] 4. For all found crossing points, find the nearest clock crossing point that crosses 0V.

[0452] 5. Take the time difference between the measured signal and the corresponding clock point as tIH.

[0453] 6. Collect all measured tIH.

[0454] 7. Screen the worst tIH as the final test result, that is, the smallest tIH among all measured values.

[0455] 8. Measure the average slew rate of all ADD / CMD and CK edges.

[0456] 9. Based on the derating table, use the average slew rate of ADD / CMD and CK to determine the ΔtIH derating value.

[0457] 10. Test limit of tIH test = tIH(base) + ΔtIH.

[0458] The calculation steps for 1.47tIS(base) are as follows:

[0459] 1. Trigger on the rising or falling edge of the address / control signal being tested.

[0460] 2. Find all the crossing points of the rising edge of the measured signal that cross VIH(AC) and record the time when the signal changes from below VIH(AC) to above VIH(AC).

[0461] 3. Find all intersections of the falling edge of the measured signal with VIL(AC) and record the time when the signal changes from being above VIL(AC) to being below VIL(AC).

[0462] 4. For all found crossing points, find the nearest clock crossing point that intersects 0V

[0463] 5. The time difference between the crossing of the measured signal and the corresponding clock crossing is referred to as tIS.

[0464] 6. Collect all measured tIS.

[0465] 7. Select the worst tIS as the final test result, that is, the minimum tIS among all measured values, and compare it with the JEDEC specification for test judgment.

[0466] 1.48tIS(derate) calculation steps are as follows:

[0467] 1. Trigger on the rising or falling edge of the address / control signal being tested.

[0468] 2. Find all intersections of the rising edge of the measured signal and VIH(AC), and record the signal from below VIH(AC)

[0469] The time point when it becomes higher than VIH(AC)

[0470] 3. Find all intersections of the falling edge of the measured signal with VIL(AC) and record the time when the signal changes from being above VIL(AC) to being below VIL(AC).

[0471] 4. For all found crossing points, find the nearest clock crossing point that intersects 0V

[0472] 5. The time difference between the crossing of the measured signal and the corresponding clock crossing is referred to as tIS.

[0473] 6. Collect all measured tIS.

[0474] 7. Select the worst tIS as the final test result, that is, the smallest tIS among all measured values.

[0475] 8. Measure the average slew rate of all ADD / CMD and CK edges.

[0476] 9. According to the derating table, use the average derating rate of ADD / CMD and CK to determine the derating value of ΔtIS.

[0477] 10. Test limit of tIS test = tIS(base) + ΔtIS.

[0478] The steps for calculating 1.49tIPW are as follows:

[0479] 1. Trigger on the rising or falling edge of the measured address or control signal.

[0480] 2. Find all intersection points of the rising / falling edge of the measured signal with Vref, and record all change points of the signal at Vref.

[0481] 3. Calculate tIPW (address / control signal pulse width time), which is the time interval from the rising edge / falling edge of the measured signal to the subsequent falling edge / rising edge (the subsequent edge must be in the opposite direction).

[0482] 4. Collect all tIPW measurements and count the tIPW results calculated from all burst data.

[0483] 5. Select the worst tIPW as the final test result, that is, the smallest tIPW among all measured values, and compare it with the JEDEC specification for test judgment.

[0484] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for testing the consistency of DDR3 series protocol signals, characterized in that: The method comprises the following steps: Step 1: Get the protocol signal of the DDR3 series protocol; Step 2: Preprocess the protocol signal, intercept the data segment and obtain important parameters; Step 3: Based on the JEDEC standard, perform consistency analysis on the preprocessed signal, calculate at least 49 test indicators, and generate a test report with PASS / FAIL conclusions.

2. The method for testing the consistency of DDR3 series protocol signals according to claim 1, wherein: Step 1 specifically includes the following steps: Step 1.1 Configure the board to be tested: Use different test boards and configure them accordingly depending on the type and speed of the protocol being tested. Step 1.2 Connect the test points: Connect the test points of the signal to be tested on the board to the probe as differential or single-ended signals, and then connect to the oscilloscope; Step 1.3 Save real data: Set the trigger conditions, intercept the signal, and export the real data; or generate the protocol signal through simulation.

3. The method for testing the consistency of DDR3 series protocol signals according to claim 1, characterized in that: The step 2 specifically includes the following steps: Step 2.1 Signal separation: Determine the read / write state of each waveform segment based on the phase difference between the clock and data signals, and then segment and reassemble the waveform into the read and write states. Step 2.2 Signal frequency identification: Since protocols with different rates have different consistency indicators, the signal frequency needs to be calculated using the clock signal. Step 2.3 Reference voltage calculation: According to the test signal, confirm the AC level and DC level, and calculate the reference voltage Vref and AC high and low level thresholds V according to the JEDEC specification. IH(AC) With V IL(AC) The values of other parameters.

4. The method for testing the consistency of DDR3 series protocol signals according to claim 1, wherein: The step 3 specifically includes the following steps: Step 3.1 Read signal index calculation: Some indicators are only tested under read data. The read signal separated in the previous step is analyzed and calculated to obtain the corresponding index results. Step 3.2 Write signal indicator calculation: Some indicators are only tested under write data. The write signal separated in the previous step is analyzed and calculated to obtain the corresponding indicator results. Step 3.3 Calculation of other indicators: Some indicators have additional requirements for the length of the data cycle, so the overshoot indicator is calculated after the data reaches the corresponding length.

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