Method and device for converting SLVS-EC to C-PHY interface and integrated circuit chip

Abstract

The invention provides an SLVS-EC to C-PHY interface conversion method and device and an integrated circuit chip, and belongs to the field of data processing, and the method applied to the integrated circuit chip comprises the following steps: receiving an SLVS-EC image data stream sent by an image sensor, and obtaining effective load data from the SLVS-EC image data stream; writing the payload data into a transmission cache; acquiring a conversion clock frequency of converting the SLVS-EC data to the C-PHY data; and reading the payload data from the transmission cache according to the conversion clock frequency, converting the read payload data into C-PHY data, and transmitting the C-PHY data. Therefore, the SLVS-EC data stream collected and output by the image sensor is converted into C-PHY data by an integrated circuit chip such as an FPGA (Field Programmable Gate Array) and the like and then is synchronously output, so that image data with higher bandwidth can be output by using fewer connecting lines, the image transmission performance is greatly improved, meanwhile, the logic and functions of an SLVS-EC interface do not need to be customized, and the cost and the power consumption are greatly reduced.

Description

Technical Field

[0001] The present application relates to the field of data processing, and more specifically, to a method, device, and integrated circuit chip for converting an SLVS-EC to a C-PHY interface. Background Art

[0002] Scalable Low-Voltage Signaling with EmbeddedClock (SLVS-EC) is a high-speed interface standard developed for fast, high-resolution image sensors. The SLVS-EC interface's simple protocol makes it easy to build camera systems, and its embedded clock signal makes it ideal for applications requiring greater capacity, higher speed, or longer-distance transmission. The SLVS-EC interface is widely used in industrial CMOS image sensors, most notably high-speed industrial cameras.

[0003] During application, images captured by industrial CMOS image sensors need to be transmitted to processors such as System on Chip (SOC). However, most current SOC processors do not integrate the SLVS-EC interface and cannot directly acquire data from image sensors. Therefore, developers typically leverage the programmability of FPGAs to customize the logic and functionality of the SLVS-EC interface to their specific needs. The output is then transmitted to the SOC via high-speed interfaces such as PCIe, Ethernet, or traditional parallel ports. However, these methods suffer from poor image transmission performance and are associated with high power consumption and cost. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a SLVS-EC to C-PHY interface method, device and integrated circuit chip, which uses integrated circuit chips such as FPGA to implement high-bandwidth, low-latency image data transmission from the SLVS-EC interface to the C-PHY interface, thereby improving performance and reducing power consumption and cost.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0006] In a first aspect, the present application provides a method for converting an SLVS-EC to a C-PHY interface, which is applied to an integrated circuit chip, wherein the integrated circuit chip is communicatively connected to an image sensor, and the method includes:

[0007] receiving an SLVS-EC image data stream sent by the image sensor, and acquiring payload data from the SLVS-EC image data stream;

[0008] Writing the payload data into a transmission buffer;

[0009] Get the conversion clock frequency from SLVS-EC data to C-PHY data;

[0010] The effective payload data is read from the transmission buffer according to the conversion clock frequency, and the read effective payload data is converted into C-PHY data before transmission.

[0011] Optionally, the step of reading the payload data from the transmission buffer according to the conversion clock frequency, and converting the read payload data into C-PHY data before transmitting includes:

[0012] Reading the payload data of a target length from the transmission buffer as target data according to the conversion clock frequency and the first-in-first-out rule; wherein the target length is a single data transmission length of the C-PHY interface of the integrated circuit chip;

[0013] Encapsulating the target data, and matching the encapsulated data with a symbol mapping rule of a C-PHY interface to obtain C-PHY data;

[0014] The C-PHY data is transmitted through a C-PHY driver of the C-PHY interface.

[0015] Optionally, the step of writing the payload data into a transmission buffer includes:

[0016] Converting the payload data from byte data to pixel data, and writing the converted payload data into a transmission buffer;

[0017] The step of reading the payload data of the target length from the transmission buffer as the target data comprises:

[0018] The payload data of the target length is read from the transmission buffer, and the read payload data is converted from pixel data to byte data to obtain target data.

[0019] Optionally, the step of obtaining a conversion clock frequency for converting SLVS-EC data to C-PHY data includes:

[0020] Acquire the number of SLVS-EC channels of the image sensor and a first data bit width of a single SLVS-EC channel, and the number of C-PHY channels of the integrated circuit chip and a second data bit width of a single C-PHY channel;

[0021] Obtaining a clock frequency ratio according to the number of SLVS-EC channels, the first data bit width, the number of C-PHY channels, and the second data bit width;

[0022] A conversion clock frequency is obtained according to the clock frequency ratio and the clock frequency of the SLVS-EC image data stream.

[0023] Optionally, the SLVS-EC interface of the image sensor includes a plurality of SLVS-EC channels;

[0024] The step of receiving the SLVS-EC image data stream sent by the image sensor and acquiring payload data from the SLVS-EC image data stream includes:

[0025] For each of the SLVS-EC channels, decoding the SLVS-EC image data stream received from the SLVS-EC channel to obtain valid data;

[0026] Synchronizing and integrating the valid data of each SLVS-EC channel to obtain restored data consistent with the original order; wherein the original order is the order in which the image sensor sends the data;

[0027] The recovered data is verified, and payload data is extracted according to the verification result.

[0028] Optionally, the integrated circuit chip further includes a plurality of synchronization caches, and the plurality of synchronization caches correspond one-to-one to the plurality of SLVS-EC channels;

[0029] The step of synchronizing and integrating the valid data of each SLVS-EC channel to obtain restored data consistent with the original order includes:

[0030] For each of the SLVS-EC channels, writing the valid data obtained from the SLVS-EC channel into the synchronization buffer corresponding to the SLVS-EC channel in the order of receipt to complete synchronization;

[0031] For each valid data in the synchronous cache, removing redundant data in the valid data to obtain protocol layer data;

[0032] According to the arrangement order of the protocol layer data in each synchronization buffer and the data sending order of the SLVS-EC channel, all the protocol layer data are integrated to obtain restored data.

[0033] Optionally, the step of verifying the recovered data and extracting payload data according to the verification result includes:

[0034] Taking the first packet header in the restored data as the target packet header, and performing decoding and CRC check on the target packet header;

[0035] If the CRC check succeeds, extract the packet header information of the target packet header;

[0036] When the packet header information indicates that the data is valid, extracting and verifying the payload data of the target packet header;

[0037] If the payload data verification succeeds, the payload data is used as effective payload data, and the process returns to the step of using the first packet header in the restored data as the target packet header.

[0038] Optionally, the method further includes:

[0039] If the CRC check of the target packet header fails or the payload data check fails, generating and recording error information;

[0040] The data between the target packet header and the next packet header are deleted from the restored data, and the step of using the first packet header in the restored data as the target packet header is executed again.

[0041] In a second aspect, the present application provides an SLVS-EC to C-PHY interface device, which is applied to an integrated circuit chip, wherein the integrated circuit chip is communicatively connected to an image sensor, and the device includes a receiving decoding module, a data buffer module, and a sending processing module;

[0042] The receiving and decoding module is configured to receive the SLVS-EC image data stream sent by the image sensor and obtain payload data from the SLVS-EC image data stream;

[0043] The data cache module is used to write the payload data into the transmission cache;

[0044] The sending processing module is used to obtain the conversion clock frequency of SLVS-EC data to C-PHY data, read the payload data from the transmission buffer according to the conversion clock frequency, and convert the read payload data into C-PHY data before transmission.

[0045] In a third aspect, the present application provides an integrated circuit chip, comprising a processor and a memory, wherein the memory stores a computer program executable by the processor, and the processor can execute the computer program to implement the SLVS-EC to C-PHY interface method as described in the first aspect.

[0046] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the SLVS-EC to C-PHY interface method as described in the first aspect is implemented.

[0047] The SLVS-EC to C-PHY interface method, device, and integrated circuit chip provided in the embodiments of the present application, when applied to an integrated circuit chip, include: receiving an SLVS-EC image data stream sent by an image sensor, obtaining payload data from the SLVS-EC image data stream; writing the payload data into a transmission buffer; obtaining a conversion clock frequency for converting the SLVS-EC data to C-PHY data; reading the payload data from the transmission buffer according to the conversion clock frequency, and converting the read payload data into C-PHY data for transmission. In this way, an integrated circuit chip such as an FPGA converts the SLVS-EC data stream captured and output by the image sensor into C-PHY data and then outputs it synchronously, thereby enabling the output of higher-bandwidth image data using fewer connections, greatly improving image transmission performance, and eliminating the need to customize the logic and functions of the SLVS-EC interface, significantly reducing cost and power consumption.

[0048] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 A schematic diagram of the system architecture of the SLVS-EC to C-PHY interface system provided in an embodiment of the present application is shown.

[0051] Figure 2 A schematic diagram of the module architecture of an electronic device provided in an embodiment of the present application is shown.

[0052] Figure 3 A flow chart of the SLVS-EC to C-PHY interface conversion method provided in an embodiment of the present application is shown.

[0053] Figure 4 Shown Figure 3 Flowchart of some sub-steps of step 11 in FIG.

[0054] Figure 5 Shown Figure 4 Schematic diagram of the flow of some sub-steps of step 113.

[0055] Figure 6 Shown Figure 4 Schematic diagram of the flow of some sub-steps of step 115.

[0056] Figure 7 Shown Figure 3 Flowchart of some sub-steps of step 15.

[0057] Figure 8 Shown Figure 3 Flowchart of some sub-steps of step 17.

[0058] Figure 9 A schematic diagram of the module architecture of the SLVS-EC to C-PHY interface device provided in an embodiment of the present application is shown.

[0059] Explanation of the accompanying drawings: 10-SLVS-EC to C-PHY interface system; 110-integrated circuit chip; 120-image sensor; 130-processing device; 20-electronic device; 210-memory; 220-processor; 230-communication module; 30-SLVS-EC to C-PHY interface device; 310-receiving and decoding module; 320-data cache module; 330-transmitting processing module. DETAILED DESCRIPTION

[0060] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present application.

[0062] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0063] The SLVS-EC to C-PHY interface method provided in the embodiment of the present application can be applied to Figure 1 In the SLVS-EC to C-PHY interface system 10 shown, the SLVS-EC to C-PHY interface system 10 includes an integrated circuit chip 110, an image sensor 120 and a processing device 130, and the image sensor 120 is communicatively connected to the image sensor 120 and the processing device 130 respectively in a wired manner.

[0064] The integrated circuit chip 110 may be an FPGA chip or an ASIC chip. The processing device 130 may be any processor 220, such as a system on chip (SOC), a digital signal processor 220 (DSP), a microcontroller (MCU), or a microprocessor 220 (MPU). The image sensor 120 may be an industrial camera, a webcam, or the like.

[0065] The image sensor 120 is used to collect image data of the surrounding environment in real time and send it to the integrated circuit chip 110 in the form of SLVS-EC image data stream.

[0066] Integrated circuit chip 110 is used to implement the SLVS-EC to C-PHY interface method provided in an embodiment of the present application, including: receiving an SLVS-EC image data stream sent by image sensor 120, obtaining payload data from the SLVS-EC image data stream; writing the payload data into a transmission buffer; obtaining a conversion clock frequency for converting SLVS-EC data to C-PHY data; reading payload data from the transmission buffer according to the conversion clock frequency, and converting the read payload data into C-PHY data for transmission.

[0067] The processing device 130 is configured to receive C-PHY data transmitted by the integrated circuit chip 110. It should be noted that the payload data is byte data, and the C-PHY data is MIPI pixel data.

[0068] The above-mentioned SLVS-EC to C-PHY interface system 10 can be applied to medical procedure equipment (such as endoscopes, ultrasound equipment), drone and robot vision systems, camera modules for mobile devices, automotive camera systems, industrial vision systems, AR / VR devices, security monitoring systems, consumer electronic devices 20 (such as smart home cameras, sports cameras), etc.

[0069] Please refer to Figure 2 , is a block diagram of an electronic device 20, which may be Figure 1The integrated circuit chip 110 in the SLVS-EC to C-PHY interface system 10 is shown. The electronic device 20 includes a memory 210, a processor 220, and a communication module 230. The memory 210, processor 220, and communication module 230 are electrically connected to each other, directly or indirectly, to enable data transmission or interaction. For example, these components can be electrically connected via one or more communication buses or signal lines.

[0070] The memory 210 is used to store programs or data and can be, but is not limited to, a random access memory, a read-only memory, a programmable read-only memory, an erasable read-only memory, an electrically erasable read-only memory, etc.

[0071] The processor 220 is used to read / write data or programs stored in the memory 210 and execute corresponding functions. For example, Figure 1 In the illustrated SLVS-EC to C-PHY interface system 10 , the processor 220 of the integrated circuit chip 110 executes the computer program stored in the memory 210 to implement the SLVS-EC to C-PHY interface method provided in the embodiment of the present application.

[0072] The communication module 230 is used to establish a communication connection between the electronic device 20 and other communication terminals, and to send and receive data. For example, Figure 1 In the SLVS-EC to C-PHY interface system 10 shown, the communication module 230 of the integrated circuit chip 110 transmits and receives data with the image sensor 120 and the processing device 130 respectively.

[0073] It should be understood that Figure 2 The structure shown is only a schematic diagram of the structure of the electronic device 20. The electronic device 20 may also include Figure 2 More or fewer components than shown, or with Figure 1 Different configurations shown. Figure 2 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0074] Currently, when transmitting the image data stream captured by the image sensor 120 from its SLVS-EC interface to a processing device 130, such as a SOC, the logic and functionality of the SLVS-EC interface must be customized on an FPGA. The output is then transmitted to the SOC via a high-speed interface (such as PCIE, Ethernet, or a traditional parallel port). This method suffers from poor image transmission performance and is associated with high power consumption and cost.

[0075] In order to improve the above problems, the embodiment of the present application provides a SLVS-EC to C-PHY interface method, referring to Figure 3, including steps 11 to 17. And, Figure 1 The integrated circuit chip 110 in the SLVS-EC to C-PHY interface system 10 can Figure 2 The structure shown implements the execution of steps 11 to 17 when the processor 220 reads the computer program stored in the memory 210 .

[0076] Step 11: Receive the SLVS-EC image data stream sent by the image sensor, and obtain payload data from the SLVS-EC image data stream.

[0077] Step 13: Write the payload data into the transmission buffer.

[0078] Step 15: Obtain the conversion clock frequency of SLVS-EC data to C-PHY data.

[0079] Step 17: Read the payload data from the transmission buffer according to the conversion clock frequency, convert the read payload data into C-PHY data, and then transmit it.

[0080] Among them, step 13 and step 15 can be executed in parallel or in any order, and the execution method of the two is not limited.

[0081] For example, in combination Figure 1 When the SLVS-EC to C-PHY interface system 10 enters operation, the image sensor 120 captures images of its surroundings in real time and transmits them in the form of an SLVS-EC image data stream over the SLVS-EC interface in real time. An integrated circuit chip 110 (e.g., an FPGA chip) connected to the image sensor 120 continuously receives the SLVS-EC image data stream from the SerDes physical layer and extracts payload data from the SLVS-EC image data stream.

[0082] Integrated circuit chip 110 writes the acquired payload data into the transmission buffer and simultaneously obtains the conversion clock frequency for SLVS-EC data to C-PHY data. Furthermore, integrated circuit chip 110 reads the payload data from the transmission buffer according to the conversion clock frequency, converts the read payload data into C-PHY data, and transmits it. This synchronizes the clock frequency of the converted C-PHY data with the clock frequency of the SLVS-EC image data stream generated by image sensor 120, effectively synchronizing the reception of the SLVS-EC image data stream by integrated circuit chip 110 and the transmission of C-PHY data.

[0083] Currently, some developers choose to use FPGA to parse the image data of the SLVS-EC protocol, but the parsed image can only be used inside the FPGA, does not have a conversion function, and cannot share data with processors 220 such as SOC.

[0084] Some developers have also attempted to use FPGAs to parse the SLVS-EC protocol and transmit data through other communication interfaces of the SOC processor 220. For example, SLVS-EC can be converted to PCIe, Ethernet, or traditional parallel ports. This bridging method then connects the data to the SOC processor 220 for use. These approaches currently have their limitations. For example, the PCIE structure is complex, making SOCs with this interface expensive. Furthermore, the FPGA chip requires SerDes ports for interconnection, which also increases costs. The data bandwidth of Ethernet and other traditional parallel ports is limited, significantly different from the bandwidth required by SLVS-EC. This results in reduced image performance and frame rate. Adding image compression algorithms to address this frame rate reduction issue increases design complexity, resources, and power consumption, hindering product integration.

[0085] In addition, these methods are subject to protocol constraints, making it difficult to accurately synchronize clocks and output images synchronously. DDR memory 210 is generally required for image frame buffering, resulting in a relatively large image delay and increased costs.

[0086] Compared to the aforementioned methods, in steps 11 to 17 of the SLVS-EC to C-PHY interface method provided in this application, an integrated circuit chip, such as an FPGA, converts the SLVS-EC data stream captured and output by the image sensor into C-PHY data and then outputs it synchronously. The C-PHY interface is compatible with protocol layers such as CSI-2 and DSI, offering a simpler connection and higher bandwidth (maximum bandwidth of 6Gsps / Trio (13.68Gbps / Trio)). It can output higher-bandwidth image data using fewer wires, and the C-PHY interface consumes less power. This significantly improves image transmission performance while eliminating the need to customize the logic and functionality of the SLVS-EC interface, significantly reducing cost and power consumption.

[0087] In the above step 11, payload data refers to a field containing image data. The method for obtaining the payload can be flexibly set. For example, the payload data can be obtained by directly parsing the SLVS-EC image data stream, or by processing the SLVS-EC image data stream according to preset rules.

[0088] The SLVS-EC interface of the image sensor 120 includes multiple SLVS-EC channels. Specifically, the connection between the SLVS-EC interface of the image sensor 120 and the integrated circuit chip 110, such as an FPGA, includes multiple SLVS-EC channels, for example, eight or six. Due to factors such as PCB trace delays, data from different SLVS-EC channels may arrive at the integrated circuit chip 110 at different times, potentially leading to errors.

[0089] In order to solve the problem of time difference and error information in data arrival of different channels, the idea of synchronizing and sequentially integrating the data received from different channels is introduced in step 11 to recover the clock of the data, and to perform parsing and verification to extract only the payload data. Figure 4 The implementation process of step 11 may include steps 111 to 115.

[0090] Step 111 : For each SLVS-EC channel, decode the SLVS-EC image data stream received from the SLVS-EC channel to obtain valid data.

[0091] Step 113 : Based on the embedded clock, synchronize and integrate the valid data of each SLVS-EC channel to obtain restored data that is consistent with the original sequence.

[0092] The original order is the order in which the image sensor sends data.

[0093] Step 115 , verifying the recovered data and extracting the payload data based on the verification result.

[0094] When image sensor 120 transmits data, it periodically transmits an SLVS-EC image data stream at a preset clock frequency. The SLVS-EC image data stream includes an embedded clock (i.e., an embedded clock signal, which serves as the time reference for the SLVS-EC image data stream). In step 111, the SLVS-EC image data stream received from the SLVS-EC channel is analyzed for signal variations, extracting the clock information (i.e., the embedded clock). This information is then recovered using components such as the phase detector, loop filter, and voltage-controlled oscillator (VCO) of the PLL (Program Loop Link), generating a clock signal with the same frequency and phase as the SLVS-EC image data stream. The recovered clock signal can be used to identify data bit boundaries, and is therefore used to sample the SLVS-EC image data stream to decode valid data.

[0095] In step 113, by synchronizing and integrating the valid data of each channel, the restored data in the original order is obtained to eliminate the influence of factors such as PCB routing delay, which causes the data of different channels to arrive at the integrated circuit chip 110 at different times, resulting in data disorder and error.

[0096] In order to implement step 113, the integrated circuit chip 110 further includes a plurality of synchronization buffers, and the plurality of synchronization buffers correspond to the plurality of SLVS-EC channels one by one. Figure 5 , the implementation method of step 113 may include steps 1131 to 1135.

[0097] Step 1131 : For each SLVS-EC channel, write the valid data obtained from the SLVS-EC channel into the synchronization buffer corresponding to the SLVS-EC channel in the order of receipt to complete synchronization.

[0098] Taking the first SLVS-EC channel as an example, if valid data is obtained after decoding the first SLVS-EC image data stream received from the first SLVS-EC channel, it is placed in the first position of the synchronization buffer corresponding to the first SLVS-EC channel. The second valid data obtained after decoding is placed in the second position, and so on. Similarly, the relevant data of the other SLVS-EC channels is placed in the corresponding synchronization buffer in the same manner. In this way, the first data sent on each channel is placed in the first position, and the second data is placed in the second position. The cache positions of subsequent data types are similar, achieving synchronization.

[0099] Step 1133 : For each valid data in the synchronous cache, remove redundant data in the valid data to obtain protocol layer data.

[0100] By analyzing the valid data and removing redundant data such as the PT code and various control codes of the PHY layer in the valid data, the protocol layer data can be obtained.

[0101] Step 1135 : According to the arrangement order of the protocol layer data in each synchronization buffer and the data sending order of the SLVS-EC channel, all the protocol layer data are integrated to obtain restored data.

[0102] For example, the protocol layer data with the highest order is extracted from each synchronization cache, and the extracted protocol layer data is integrated according to the data sending order of the corresponding SLVS-EC channels to obtain an intermediate group. Then, the next group of protocol layer data with the highest order is extracted from each synchronization cache. The same processing method is used to obtain a second intermediate group and combine it after the first intermediate group. The above process is repeated until all protocol layer data is extracted. The final intermediate group is the restored data.

[0103] For example, assuming there are three SLVS-EC channels, 1 to 3, and the data is sent in the order from 1 to 3, and the protocol layer data in the synchronization buffer corresponding to the three SLVS-EC channels is three, the final recovered data is: in, This represents the third protocol layer data in the synchronization buffer corresponding to the third SLVS-EC channel. The other examples are similar and will not be described in detail here.

[0104] Through the above steps 1131 to 1135, the original order of the data is restored, the influence of factors such as PCB wiring delay is eliminated, and the decoding accuracy and quality of the data are improved.

[0105] After the restored data is obtained, in step 115 , the entire restored data may be directly verified, or verified according to a preset rule, and the implementation method is not limited.

[0106] Considering that the image sensor 120 continuously transmits multiple data packets (ie, multiple lines of data), the verification of the entire recovered data cannot ensure the quality of the data. Therefore, the packet verification is introduced in step 115, and the packet header is verified first and then the payload data is verified. Figure 6 , step 115 includes steps 1151 to 1157.

[0107] Step 1151: Use the first packet header in the restored data as the target packet header, and perform decoding and CRC check on the target packet header.

[0108] Step 1153: If the CRC check succeeds, extract the packet header information of the target packet header.

[0109] Step 1155: When the packet header information indicates that the data is valid, the payload data of the target packet header is extracted and verified.

[0110] In step 1157, if the payload data verification is successful, the payload data is used as the effective payload data. After executing step 1157, the process returns to step 1151.

[0111] Here, the target packet header's payload data is the data segment from the target packet header to the next packet header. If the target packet header is the first packet header, then the data segment from the first packet header to the second packet header is the target packet header's payload data. After extracting the payload data in step 1157, only the data following the target packet header remains in the recovered data.

[0112] The header CRC check fails or the payload data check fails. The data packet corresponding to the target header is unreliable and has errors. In order to enable the user to know the error data packet, after step 1151 and step 1155, refer to Figure 6 , also including step 1156 and step 1158.

[0113] Step 1156: If the CRC check of the target packet header fails or the payload data check fails, generate and record error information.

[0114] Step 1158: Delete the data between the target packet header and the next packet header from the restored data. After executing step 1158, return to step 1151.

[0115] For example, the header of the first data packet in the recovered data (i.e., the target packet header) is decoded and CRC-checked. If the CRC check fails, the first data packet is unreliable. The SLVS-EC control unit of integrated circuit chip 110 generates and records an error message for the user to query. If the CRC check is correct, the header information (including the field synchronization signal, the line valid signal, etc.) is extracted. If the header information indicates that the data row (i.e., the data packet) is invalid (i.e., does not contain image data), it is not transmitted to the next level for processing. If the data row is valid (i.e., contains image data), the CRC check or ECC check of the payload data is continued. If the check fails, the information is unreliable, and the SLVS-EC control unit generates and records an error message for the user to query. If the check succeeds, the payload data (including the field synchronization signal, the line valid flag, the line data length, etc.) is transmitted in real time to the SLVS-EC control unit for query by the CPHY control and PLL units of integrated circuit chip 110 or the user.

[0116] By performing header verification first and then payload verification in this manner, correct and valid payload data can be obtained, improving the accuracy and quality of data transmission. Furthermore, in this manner, if header verification fails, subsequent verification is not required, reducing verification time and improving data transmission time.

[0117] Because the SLVS-EC interface supports RAW8 / RAW10 / RAW12 / RAW14 / RAW16 data formats, image sensor 120 converts the captured pixel data into byte data before transmission to facilitate transmission. Therefore, the SLVS-EC image data stream is byte data, and the payload data obtained in step 11 is also byte data containing image information.

[0118] In step 13, the manner of writing the payload data into the transmission buffer can be flexibly set, and can be standard processing or optimized processing, and its implementation manner is not limited.

[0119] For example, in step 13, when the standard processing is performed, the payload data is converted from byte data to pixel data, and the converted payload data is written into the transmission buffer.

[0120] The transmission buffer here can be a dual-port RAM buffer. Through reverse conversion, the byte data can be converted back to pixel data and written to the dual-port RAM buffer. The output pixel data is in a standard format, suitable for use as input for C-PHY conversion processing.

[0121] The MIPI-CPY protocol used by the C-PHY interface, SLVS-EC, and MIPI C-PHY protocols share the same conversion method for RAW8 / RAW10 / RAW12 / RAW14 / RAW16 data formats. Therefore, to reduce data conversion time in this input scenario, an optimization process is employed in step 13: the payload data in byte format is directly written to the dual-port RAM buffer. In this case, data can also be read directly from the dual-port RAM buffer during C-PHY transmission.

[0122] For step 15, the method for obtaining the conversion clock frequency of SLVS-EC data to C-PHY data can be flexibly set. For example, it can be a table lookup, real-time calculation, or the conversion clock frequency can be initially calculated according to a rule and stored and then directly used. The implementation method is not limited.

[0123] When looking up the table, the conversion clock frequency between the SLVS-EC interface and the C-PHY interface on the image sensor 120 can be pre-calculated and stored in the record table. Thus, when executing the SLVS-EC to C-PHY interface conversion method provided in the embodiment of the present application, the conversion clock frequency can be found from the record table.

[0124] In step 15, when calculating in real time, according to the rules or in advance, refer to Figure 7 The step of obtaining the conversion clock frequency of SLVS-EC data to C-PHY data includes steps 151 to 155.

[0125] Step 151 : Acquire the number of SLVS-EC channels of the image sensor and the first data bit width of a single SLVS-EC channel, as well as the number of C-PHY channels of the integrated circuit chip and the second data bit width of a single C-PHY channel.

[0126] Step 153 : Obtain a clock frequency ratio according to the number of SLVS-EC channels, the first data bit width, the number of C-PHY channels, and the second data bit width.

[0127] Step 155 : Obtain a conversion clock frequency according to the clock frequency ratio and the clock frequency of the SLVS-EC image data stream.

[0128] Here, the number of SLVS-EC channels, the first data bit width of a single SLVS-EC channel, the number of C-PHY channels, and the second data bit width of a single C-PHY channel can all be configured as needed. Figure 1 The device of the application scenario of the SLVS-EC to C-PHY interface system 10 shown is provided with a configuration interface, through which the parameters of the hardware platform such as the image sensor 120, the processing device 130 and the integrated circuit chip 110 can be dynamically set to meet the image format requirements in different scenarios. Among them, the configurable parameters include: (1) image sensor 120 parameters, such as basic configuration parameters, frame rate, resolution, refresh rate and number of output SerDes lanes; (2) SLVS-EC data parsing parameters, such as the SerDes physical layer can be configured as 1, 2, 4, 6 or 8 channels, the bit width is 16 bits or 32 bits, the rate parameter is 2.4Gbps or above, the pixel bit width, the length of each line of data, the check method CRC or ECC, the channel bonding parameters, etc.; (3) C-PHY transmission parameters, such as the input data bit width of each C-PHY channel, the number of C-PHY channels, etc.; (4) status parameters such as whether the internal image data check is correct and whether the conversion process is normal.

[0129] The calculation formula of the clock frequency ratio can be expressed as:

[0130]

[0131] Among them, f I_PIXEL_CLK Characterizes the clock frequency of the SLVS_EC image data stream (i.e., the pixel clock domain on the input side), f I_BYTE_CLK Indicates the clock frequency of C-PHY data (i.e., the clock frequency on the output side), W1 represents the first data bit width, D1 represents the number of SLVS-EC channels, W2 represents the second data bit width, and D2 represents the number of C-PHY channels.

[0132] The TX data organization bit width of the 16:1TX C-PHY data organization mode is 16, while the 32:1TX data organization bit width is 32.

[0133] For example, if the SLVS-EC interface on the input side is RAW8, with two SLVS-EC channels and a first data width of 16 bits (16 bits of data output per clock), the C-PHY interface on the output side is 1:16: the C-PHY data organization bit width is 16 bits. In this case, the C-PHY interface is configured as two triplets (i.e., two channels / trios), and the clock frequency ratio (the ratio of the PLL input clock to the output clock) is 1:1, achieving synchronous data output. If the C-PHY interface is configured as a single triplet, the clock frequency ratio is 1:2, achieving synchronous data output.

[0134] If the clock frequency of the SLVS-EC image data stream is 100 MHz and the clock frequency ratio is 1:2, the conversion clock frequency (i.e., the clock frequency for sending C-PHY data) is 50 MHz. If the clock frequency of the SLVS-EC image data stream is 100 MHz and the clock frequency ratio is 1:1, the conversion clock frequency (i.e., the clock frequency for sending C-PHY data) is 100 MHz.

[0135] After obtaining the conversion clock frequency, if the payload data in the transmission buffer is byte data (ie, stored in the transmission buffer after optimization processing in step 13), then refer to Figure 8 In step 17, the process of reading the payload data from the transmission buffer according to the conversion clock frequency and converting the read payload data into C-PHY data for transmission may include steps 171 to 175.

[0136] Step 171 : Read the payload data of the target length from the transmission buffer as the target data according to the conversion clock frequency and the first-in-first-out rule.

[0137] The target length is the length of a single data transmission of the C-PHY interface of the integrated circuit chip 110 .

[0138] Step 173: encapsulate the target data, match the encapsulated data with the symbol mapping rule of the C-PHY interface, and obtain C-PHY data.

[0139] Step 175: Transmit the C-PHY data through the C-PHY driver of the C-PHY interface.

[0140] If the payload data in the transmission cache is pixel data (i.e., stored in the transmission cache after standard processing in step 13), based on the above steps, the target data acquisition process in step 171 is: read the payload data of the target length from the transmission cache, and convert the read payload data from pixel data to byte data to obtain the target data.

[0141] For example, in combination Figure 1In the illustrated SLVS-EC to C-PHY interface system 10, integrated circuit chip 110 reads data from the dual-port RAM cache according to the conversion clock frequency and first-in, first-out rules. Under standard processing, the read data is converted into byte data to obtain the target data. Under optimized processing, the read data is directly used as the target data. If the C-PHY interface has three triplet channels and the data bit width of a single channel is 32 bits, the data length of each channel is 32 / 8 = 4 bytes, and the target data length is 4*3 = 12 bytes. The target data is encapsulated into a DSI or CSI-2 data frame, matching the C-PHY symbol mapping rules, and generated into a three-phase signal (i.e., C-PHY data) through the MIPI C-PHY driver and output to the processing device 130.

[0142] also, Figure 1 In the illustrated SLVS-EC to C-PHY interface system 10, parameter registers are provided between the integrated circuit chip 110 and the image sensor 120 for configuring basic parameters of the image sensor 120. The integrated circuit chip 110 may also include an SLVS-EC control unit and a CPHY control and PLL unit.

[0143] The SLVS-EC control unit has the following functions: (1) Complete parameter setting and query: receive instructions and parameters from hardware platforms such as SOC, assist in completing SLVS-EC protocol parsing, and output image data; (2) dynamically update the parameters of the parameter register according to the instructions, and complete dynamic parameter switching; (3) distribute parameters such as the number of serdes lanes, check type, and data type; (4) Data packet header decoding and CRC check: complete data packet header CRC check and complete PHY layer data processing. In addition, it can also control the transmission of data in the above step 11 and its related substeps.

[0144] The CPHY control and PLL unit is used to: (1) complete SOC parameter setting and query: receive SOC and other hardware platform instructions and parameters, and assist in completing C-PHY protocol conversion; (2) complete C-PHY peripheral parameter setting and query: DSC command information processing, configure peripheral parameters through C-PHY, or receive peripheral commands to complete parameter setting or query; (3) realize clock recovery and data synchronization function: according to the set parameters, with the clock recovered by the SerDes physical layer as a reference, dynamically calculate and adjust the PLL frequency according to the formula, output the conversion clock frequency, and complete data synchronization.

[0145] Based on the same concept as the above SLVS-EC to C-PHY interface method, refer to Figure 9The embodiment of the present application also provides a SLVS-EC to C-PHY interface device 30, including a receiving decoding module 310, a data buffer module 320 and a sending processing module 330. The SLVS-EC to C-PHY interface device 30 can be applied to Figure 1 The integrated circuit chip 110 of the SLVS-EC to C-PHY interface system 10 is shown.

[0146] The receiving and decoding module 310 is configured to receive the SLVS-EC image data stream sent by the image sensor and obtain payload data from the SLVS-EC image data stream.

[0147] The data cache module 320 is configured to write payload data into the transmission cache.

[0148] The transmission processing module 330 is used to obtain the conversion clock frequency of SLVS-EC data to C-PHY data, read the payload data from the transmission buffer according to the conversion clock frequency, and convert the read payload data into C-PHY data for transmission.

[0149] The SLVS-EC to C-PHY interface device 30, through the collaborative work of a receive decoding module 310, a data buffer module 320, and a transmit processing module 330, uses an integrated circuit chip, such as an FPGA, to convert the SLVS-EC data stream captured and output by the image sensor into C-PHY data for synchronous output. The C-PHY interface is compatible with protocol layers such as CSI-2 and DSI, offering a simpler connection and higher bandwidth (maximum bandwidth of 6 GHz / Trio (13.68 Gbps / Trio)). This allows for output of higher-bandwidth image data using fewer wires, while also reducing power consumption. This significantly improves image transmission performance while eliminating the need to customize the logic and functionality of the SLVS-EC interface, significantly reducing cost and power consumption.

[0150] For the specific implementation and effect of the SLVS-EC to C-PHY interface device 30, please refer to the above description of the implementation of the SLVS-EC to C-PHY interface method. For example, for the specific implementation and effect of the receiving decoding module 310, please refer to the description of the relevant content of step 11 above. For the specific implementation and effect of the data cache module 320, please refer to the description of the relevant content of step 13 above. For the specific implementation and effect of the sending processing module 330, please refer to the description of the relevant content of steps 15 and 17 above, which will not be repeated here.

[0151] In addition, each module of the SLVS-EC to C-PHY interface device 30 can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor 220 in the electronic device 20 in hardware form, or can be stored in the memory 210 of the electronic device 20 in software form, so that the processor 220 can call and execute the corresponding operations of each module to implement the SLVS-EC to C-PHY interface method provided above.

[0152] The embodiment of the present application also provides an integrated circuit chip 110, including a processor 220 and a memory 210. The memory 210 stores a computer program that can be executed by the processor 220. The processor 220 can execute the computer program to implement the SLVS-EC to C-PHY interface method provided above.

[0153] The embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by the processor 220, the SLVS-EC to C-PHY interface method proposed in the embodiment of the present application is implemented.

[0154] An embodiment of the present application further provides an electronic device 20, comprising the integrated circuit chip 110 provided above, or the computer-readable storage medium provided above.

[0155] In summary, the SLVS-EC to C-PHY interface method, device, and integrated circuit chip provided in the embodiments of the present application have at least the following beneficial effects:

[0156] (1) Outputting higher-bandwidth image data using fewer wires greatly improves image transmission performance while eliminating the need to customize the logic and functionality of the SLVS-EC interface, significantly reducing cost and power consumption.

[0157] (2) Dynamic parameter configuration: Through the configuration interface inside the integrated circuit chip, using UART, SPI or I2C and other methods to communicate with the outside world, receive configuration information, and complete the configuration of operating parameters such as image sensor, SLVS-EC data parsing, and C-PHY transmission.

[0158] (3) Real-time performance: After parsing the image data from multiple parallel SLVS-EC streams, the data is parsed directly within the integrated circuit chip, rather than using the traditional DDR memory chip frame buffering method, which has a high latency. This process only requires caching one row of data through registers or internal RAM, avoiding the need for caching a single frame of data, ensuring low latency in data transmission.

[0159] (IV) Clock recovery and data synchronization: SLVS-EC uses an embedded clock, while C-PHY relies on symbol encoding to transmit clock information. Therefore, a clock data recovery (CDR) circuit is used to extract the clock from the SLVS-EC signal. Based on the data ratio, the recovered clock is output through the PLL inside the integrated circuit chip to a clock signal that matches the C-PHY transmit data rate. The clock signal is then input into the C-PHY module to synchronize the SLVS-EC input data rate with the C-PHY transmit symbol encoding rate.

[0160] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0161] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0162] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0163] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for converting SLVS-EC to C-PHY interface, characterized in that: Applied to an integrated circuit chip, the integrated circuit chip being communicatively connected to an image sensor, the method comprising: receiving an SLVS-EC image data stream sent by the image sensor, and acquiring payload data from the SLVS-EC image data stream; Writing the payload data into a transmission buffer; Get the conversion clock frequency from SLVS-EC data to C-PHY data; The effective payload data is read from the transmission buffer according to the conversion clock frequency, and the read effective payload data is converted into C-PHY data before transmission.

2. The SLVS-EC to C-PHY interface method according to claim 1, characterized in that: The step of reading the payload data from the transmission buffer according to the conversion clock frequency, and converting the read payload data into C-PHY data for transmission includes: Reading the payload data of a target length from the transmission buffer as target data according to the conversion clock frequency and the first-in-first-out rule; wherein the target length is a single data transmission length of the C-PHY interface of the integrated circuit chip; Encapsulating the target data, and matching the encapsulated data with a symbol mapping rule of a C-PHY interface to obtain C-PHY data; The C-PHY data is transmitted through a C-PHY driver of the C-PHY interface.

3. The SLVS-EC to C-PHY interface method according to claim 2, characterized in that: The step of writing the payload data into a transmission buffer comprises: Converting the payload data from byte data to pixel data, and writing the converted payload data into a transmission buffer; The step of reading the payload data of the target length from the transmission buffer as the target data comprises: The payload data of the target length is read from the transmission buffer, and the read payload data is converted from pixel data to byte data to obtain target data.

4. The SLVS-EC to C-PHY interface method according to claim 1, characterized in that: The step of obtaining the conversion clock frequency of SLVS-EC data to C-PHY data includes: Acquire the number of SLVS-EC channels of the image sensor and a first data bit width of a single SLVS-EC channel, and the number of C-PHY channels of the integrated circuit chip and a second data bit width of a single C-PHY channel; Obtaining a clock frequency ratio according to the number of SLVS-EC channels, the first data bit width, the number of C-PHY channels, and the second data bit width; A conversion clock frequency is obtained according to the clock frequency ratio and the clock frequency of the SLVS-EC image data stream.

5. The SLVS-EC to C-PHY interface method according to any one of claims 1 to 4, characterized in that: The SLVS-EC interface of the image sensor includes a plurality of SLVS-EC channels; The step of receiving the SLVS-EC image data stream sent by the image sensor and acquiring payload data from the SLVS-EC image data stream includes: For each of the SLVS-EC channels, decoding the SLVS-EC image data stream received from the SLVS-EC channel to obtain valid data; Synchronizing and integrating the valid data of each SLVS-EC channel to obtain restored data consistent with the original order; wherein the original order is the order in which the image sensor sends the data; The recovered data is verified, and payload data is extracted according to the verification result.

6. The SLVS-EC to C-PHY interface method according to claim 5, characterized in that: The integrated circuit chip further includes a plurality of synchronization caches, wherein the plurality of synchronization caches correspond one-to-one to the plurality of SLVS-EC channels; The step of synchronizing and integrating the valid data of each SLVS-EC channel to obtain restored data consistent with the original order includes: For each of the SLVS-EC channels, writing the valid data obtained from the SLVS-EC channel into the synchronization buffer corresponding to the SLVS-EC channel in the order of receipt to complete synchronization; For each valid data in the synchronous cache, removing redundant data in the valid data to obtain protocol layer data; According to the arrangement order of the protocol layer data in each synchronization buffer and the data sending order of the SLVS-EC channel, all the protocol layer data are integrated to obtain restored data.

7. The SLVS-EC to C-PHY interface method according to claim 5, characterized in that: The step of verifying the recovered data and extracting the payload data according to the verification result includes: Taking the first packet header in the restored data as the target packet header, and performing decoding and CRC check on the target packet header; If the CRC check succeeds, extract the packet header information of the target packet header; When the packet header information indicates that the data is valid, extracting and verifying the payload data of the target packet header; If the payload data verification succeeds, the payload data is used as effective payload data, and the process returns to the step of using the first packet header in the restored data as the target packet header.

8. The SLVS-EC to C-PHY interface method according to claim 7, characterized in that: The method further comprises: If the CRC check of the target packet header fails or the payload data check fails, generating and recording error information; The data between the target packet header and the next packet header are deleted from the restored data, and the step of using the first packet header in the restored data as the target packet header is returned to be executed.

9. An SLVS-EC to C-PHY interface device, characterized in that: Applied to an integrated circuit chip, the integrated circuit chip is communicatively connected to an image sensor, and the device includes a receiving decoding module, a data buffer module, and a sending processing module; The receiving and decoding module is configured to receive the SLVS-EC image data stream sent by the image sensor and obtain payload data from the SLVS-EC image data stream; The data cache module is used to write the payload data into the transmission cache; The sending processing module is used to obtain the conversion clock frequency of SLVS-EC data to C-PHY data, read the payload data from the transmission buffer according to the conversion clock frequency, and convert the read payload data into C-PHY data before transmission.

10. An integrated circuit chip, characterized in that: The method comprises a processor and a memory, wherein the memory stores a computer program executable by the processor, and the processor can execute the computer program to implement the SLVS-EC to C-PHY interface method according to any one of claims 1 to 8.

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