Combined passivation back contact battery and preparation method thereof

Abstract

The invention discloses a combined passivation back contact battery which comprises an N-type silicon wafer, a second intrinsic amorphous silicon layer, a microcrystalline silicon layer, an anti-reflection layer, a second semiconductor opening region, a first semiconductor opening region and a transition region, the anti-reflection layer is a single-layer amorphous silicon carbonitride layer or a laminated structure composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer, and the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer. The first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer, and an opening is etched in the transparent conductive film on the surface of the transition area to form an insulation groove. Amorphous silicon carbonitride or amorphous silicon carbide / amorphous silicon carbonitride laminated layers are adopted as the anti-reflection layers, so that reflection loss is reduced, the reliability and durability of the cell are improved, and the conversion efficiency of the cell is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of back contact batteries, and in particular to a combined passivation back contact battery and a preparation method thereof. Background Art

[0002] Existing back-contact heterojunction cells consist of an N-type monocrystalline silicon wafer, a pyramidal velvet surface, an intrinsic amorphous silicon layer, and an anti-reflection layer, sequentially located on the front of the wafer. On the P-region surface on the back of the wafer, an intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film layer, and a metal gate layer are sequentially located. On the N-region surface on the back of the wafer, an intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a transparent conductive film layer, and a metal gate layer are sequentially located.

[0003] Existing back-contact solar cells generally use non-stoichiometric SiNx or SiO2 / SiNx stacks as anti-reflection coatings on the front side, which can effectively reduce surface reflectivity and increase light absorption. However, SiNx struggles to achieve optimal anti-reflection effects across the entire spectrum. While SiO2 / SiNx stacks can improve reflectivity, they suffer from poor interlayer stress matching, leading to film cracking or peeling during deposition. Furthermore, their thermal stability and acid and alkali corrosion resistance are insufficient, compromising the mechanical stability and long-term reliability of the cell. Summary of the Invention

[0004] In response to the above problems, the present invention provides a combined passivated back contact battery and a preparation method thereof, which reduces reflection loss, helps to increase the short-circuit current of the back contact battery, and further improves the conversion efficiency of the battery.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: a combined passivation back contact cell, comprising an N-type silicon wafer, a second intrinsic amorphous silicon layer, a microcrystalline silicon layer and an anti-reflection layer arranged in sequence on the front side of the silicon wafer, and a transition region between the second semiconductor opening region and the first semiconductor opening region and the second semiconductor opening region and the first semiconductor opening region on the back side of the silicon wafer, wherein the anti-reflection layer is a single layer of amorphous silicon carbon nitride layer (a-SiCxNy:H) or a combination of an amorphous silicon carbide layer (a-SiCx:H) and an amorphous silicon carbon nitride layer (a-SiCxNy:H). ), the second semiconductor opening region is composed of a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film, and a metal electrode sequentially arranged on the back side of the silicon wafer; the first semiconductor opening region is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film, and a metal electrode sequentially arranged on the back side of the silicon wafer; the transition region is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, and a transparent conductive film sequentially arranged on the back side of the silicon wafer; an insulating groove is formed by etching an opening in the transparent conductive film on the surface of the transition region.

[0006] Furthermore, the anti-reflection layer is a single-layer amorphous silicon carbon nitride layer (a-SiCxNy:H) with a thickness of 80-120 nm, a carbon doping concentration of 1×1019 cm-3-1×1022 cm-3, and a refractive index of 1.9-2.0.

[0007] Furthermore, the anti-reflection layer is a stacked structure of an amorphous silicon carbide layer (a-SiCx:H) and an amorphous silicon carbon nitride layer (a-SiCxNy:H), the amorphous silicon carbide layer has a thickness of 10-50 nm, a carbon doping concentration of 1×1020 cm-3-1×1023 cm-3, and a refractive index of 2.01-2.2, and the amorphous silicon carbon nitride layer has a thickness of 50-100 nm, a carbon doping concentration of 1×1019 cm-3-1×1022 cm-3, and a refractive index of 1.9-2.0.

[0008] Furthermore, the band gap of the amorphous silicon carbide layer is 2.3-3.3 eV.

[0009] A method for preparing the combined passivation back contact battery comprises the following steps:

[0010] S01: Provide polished and cleaned N-type single crystal silicon wafers;

[0011] S02: forming a first semiconductor layer and a mask layer on the back side of the silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and an N-type polysilicon layer;

[0012] S03: performing an opening on the back side of the silicon wafer by laser etching to remove the mask layer, the N-type polysilicon layer, and the tunnel oxide layer in the second semiconductor opening region;

[0013] S04: performing texturing and cleaning on the silicon wafer to remove the residual mask layer, N-type polysilicon layer and tunnel oxide layer in the second semiconductor opening region, and forming a textured surface on the surface of the silicon wafer;

[0014] S05: depositing a first intrinsic amorphous silicon layer of a second semiconductor layer on the back side of the silicon wafer;

[0015] S06: forming a third semiconductor layer on the front side of the silicon wafer;

[0016] S07: depositing a P-type amorphous silicon layer as a second semiconductor layer on the back side of the silicon wafer;

[0017] S08: Depositing an anti-reflection layer on the front side of the silicon wafer, specifically including:

[0018] Solution 1: The anti-reflection layer 701 is composed of an amorphous silicon carbonitride layer, and its preparation method is as follows: PECVD deposition is performed at a process temperature of 100-300°C. The process parameters for the amorphous silicon carbonitride layer are: gas flow rates [CH4] = 400-1000 sccm, [SiH4] = 800-3000 sccm, [NH3] = 200-800 sccm, [N2] = 300-1000 sccm, and [H2] = 2400-5000 sccm. Deposition pressure P = 100-200 Pa; plasma power density RF = 0.5 W / cm2-1.2 W / cm2.

[0019] Option 2: The anti-reflection layer is composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer, and its preparation method is as follows: continuous coating is performed using a PECVD process at a process temperature of 100-300°C;

[0020] The process parameters for the amorphous silicon carbide layer are: gas flow rates CH4 = 800-1000 sccm, SiH4 = 800-2000 sccm, Ar = 3000-4000 sccm, H2 = 2400-3000 sccm; deposition pressure P = 50-200 Pa; plasma power density RF = 0.3 W / cm2-0.6 W / cm2;

[0021] Amorphous silicon carbonitride layer process parameters: gas flow rate CH4 = 400-1000sccm, SiH4 = 800-3000sccm, NH3 = 200-800sccm, N2 = 300-1000sccm, H2 = 2400-5000sccm; deposition pressure P = 100-200Pa; plasma power density RF = 0.5W / cm2-1.2W / cm2;

[0022] S09: Opening the back of the silicon wafer by laser etching to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning;

[0023] S10: depositing a transparent conductive film on the back of the silicon wafer;

[0024] S11: etching an opening in the transparent conductive film on the surface of the transition area between the second semiconductor opening area and the first semiconductor opening area on the back side of the silicon wafer to form an insulating groove to isolate the first semiconductor layer from the second semiconductor layer;

[0025] S12: forming metal electrodes on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer respectively.

[0026] Furthermore, the tunnel oxide layer is formed by a dry method with a thickness of 1-2nm; the N-type polysilicon layer is diffused after depositing the intrinsic polysilicon layer by LPCVD, with a thickness of 100-200nm; the mask layer is silicon nitride, formed by PECVD deposition, with a thickness of 60-80nm.

[0027] Furthermore, the third semiconductor layer is formed by depositing a second intrinsic amorphous silicon layer with a thickness of 4-8 nm and a microcrystalline silicon layer with a thickness of 6-20 nm through plate-type PECVD.

[0028] Furthermore, the interfacial bonding strength between the amorphous silicon carbide layer and the amorphous silicon carbonitride layer is achieved by matching the hardness and Young's modulus ratio (H / E≈0.13), resulting in good interlayer bonding strength and less prone to film bursting and peeling during the deposition process.

[0029] Furthermore, the transparent conductive film is a doped indium oxide or tin oxide system, formed by PVD deposition, and has a thickness of 50-150 nm.

[0030] It can be seen from the above description of the present invention that, compared with the prior art, the present invention has the following advantages:

[0031] 1. Using amorphous silicon carbon nitride as the anti-reflection layer can effectively reduce the reflectivity compared to SiNx film. At the same time, the mechanical properties and chemical resistance of the film are also better, which can improve the reliability and durability of the battery.

[0032] 2. Amorphous silicon carbide / amorphous silicon carbon nitride stack is used as the anti-reflection layer to achieve wide-spectrum low reflection, and realize an anti-reflection layer structure with high interface stability and surface passivation function. The amorphous silicon carbide layer provides excellent interface passivation and reduces the surface recombination rate. The amorphous silicon carbon nitride layer suppresses long-wavelength reflection and improves the utilization rate of infrared light, which is beneficial to increase the short-circuit current of the back-contact battery, thereby improving the conversion efficiency of the battery.

[0033] 3. Amorphous silicon carbide and amorphous silicon carbonitride materials themselves have good chemical stability and mechanical properties, excellent thermal stability, acid and alkali corrosion resistance, oxidation resistance, and film density are stronger than silicon nitride anti-reflection film. They can work stably for a long time in harsh environments and have excellent anti-LID performance. The use of low-temperature process is conducive to reducing production energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0035] Figure 1 This is a schematic cross-sectional view of a combined passivated back contact battery according to Example 1 of the present invention;

[0036] Figure 2 This is a schematic cross-sectional structural diagram of a combined passivated back contact battery according to Example 2 of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0038] refer to Figure 1 A combined passivation back contact cell comprises an N-type silicon wafer 10, a second intrinsic amorphous silicon layer 41, a microcrystalline silicon layer 42 and an anti-reflection layer 50 sequentially arranged on the front surface of the silicon wafer 10, a transition region C between a second semiconductor opening region B and a first semiconductor opening region A and a second semiconductor opening region and the first semiconductor opening region arranged on the back surface of the silicon wafer 10, the anti-reflection layer 50 being a single layer amorphous silicon carbon nitride layer 51 or a stacked structure consisting of an amorphous silicon carbide layer 51 and an amorphous silicon carbon nitride layer 52, the second semiconductor opening region B being a first semiconductor opening region A sequentially arranged on the back surface of the silicon wafer The first semiconductor opening region A is composed of a tunneling oxide layer 21, an N-type polysilicon layer 22, a transparent conductive film 60, and a metal electrode 70, which are sequentially arranged on the back of the silicon wafer. The transition region C is composed of a tunneling oxide layer 21, an N-type polysilicon layer 22, a first intrinsic amorphous silicon layer 31, a P-type amorphous silicon layer 32, and a transparent conductive film 60, which are sequentially arranged on the back of the silicon wafer. An opening is formed by etching the transparent conductive film on the surface of the transition region C to form an insulating groove 80.

[0039] Example 1

[0040] refer to Figure 1 The anti-reflection layer 50 is a stacked structure of an amorphous silicon carbide layer 51 and an amorphous silicon carbonitride layer 52. The thickness of the amorphous silicon carbide layer 51 is 30 nm. Under this condition, the refractive index of the amorphous silicon carbide film is within the optimal refractive index range, and the band gap width of the amorphous silicon carbide is 2.6, which is beneficial to improving the passivation quality of the interface, reducing the surface recombination center, and increasing the carrier lifetime; the carbon doping concentration is 1×10 20 cm -3 , the refractive index is 2.01, the thickness of the amorphous silicon carbon nitride layer 52 is 60 nm, and the carbon doping concentration is 1×10 19 cm -3 , with a refractive index of 1.9. By utilizing the lower refractive index of amorphous silicon carbon nitride, the reflection in the visible light band and near-infrared band can be reduced, thereby improving the utilization rate of light, which is beneficial to increasing the short-circuit current and improving the conversion efficiency of the battery.

[0041] A method for preparing a combined passivation back contact battery comprises the following steps:

[0042] S01: Provide polished and cleaned N-type single crystal silicon wafers;

[0043] S02: forming a first semiconductor layer and a mask layer on the back side of the silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and an N-type polysilicon layer;

[0044] The tunnel oxide layer is formed by dry deposition and has a thickness of 1 nm. The N-type polysilicon layer is formed by LPCVD deposition of an intrinsic polysilicon layer followed by diffusion and has a thickness of 100 nm. The mask layer is silicon nitride and is formed by PECVD deposition and has a thickness of 60 nm.

[0045] S03: performing an opening on the back side of the silicon wafer by laser etching to remove the mask layer, the N-type polysilicon layer, and the tunnel oxide layer in the second semiconductor opening region;

[0046] S04: performing texturing and cleaning on the silicon wafer to remove the residual mask layer, N-type polysilicon layer and tunnel oxide layer in the second semiconductor opening region, and forming a textured surface on the surface of the silicon wafer;

[0047] S05: depositing a first intrinsic amorphous silicon layer of a second semiconductor layer on the back side of the silicon wafer;

[0048] S06: forming a third semiconductor layer on the front side of the silicon wafer, wherein the third semiconductor layer is formed by depositing a second intrinsic amorphous silicon layer with a thickness of 5 nm and a microcrystalline silicon layer with a thickness of 10 nm by plate-type PECVD;

[0049] S07: depositing a P-type amorphous silicon layer as a second semiconductor layer on the back side of the silicon wafer;

[0050] S08: Depositing an anti-reflection layer on the front side of the silicon wafer. The anti-reflection layer is composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer. The preparation method is as follows: continuous coating is performed using a PECVD process at a process temperature of 120°C.

[0051] The process parameters for the amorphous silicon carbide layer are: gas flow rates CH4 = 800 sccm, SiH4 = 1200 sccm, Ar = 3000 sccm, H2 = 2400 sccm. Deposition pressure P = 100 Pa; plasma power density RF = 0.3 W / cm;

[0052] Amorphous silicon carbonitride layer process parameters: gas flow rates CH4 = 400 sccm, SiH4 = 1000 sccm, NH3 = 200 sccm, N2 = 300 sccm, H2 = 2400 sccm. Deposition pressure P = 100 Pa; plasma power density RF = 0.5 W / cm 2 ;

[0053] The ratio of hardness to Young's modulus H / E of the two materials of the amorphous silicon carbide layer and the amorphous silicon carbonitride layer is about 0.13, the interlayer bonding strength is good, and the film explosion and peeling are not likely to occur during the deposition process;

[0054] S09: Opening the back of the silicon wafer by laser etching to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning;

[0055] S10: depositing a transparent conductive film on the back of the silicon wafer, wherein the transparent conductive film is a doped indium oxide or tin oxide system, formed by PVD deposition, and has a thickness of 100 nm;

[0056] S11: etching an opening in the transparent conductive film on the surface of the transition area between the second semiconductor opening area and the first semiconductor opening area on the back side of the silicon wafer to form an insulating groove to isolate the first semiconductor layer from the second semiconductor layer;

[0057] S12: forming metal electrodes on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer respectively.

[0058] Example 2

[0059] refer to Figure 2 The anti-reflection layer 50 is an amorphous silicon carbon nitride layer 52 structure, the amorphous silicon carbon nitride layer 52 has a thickness of 100 nm and a carbon doping concentration of 1×10 19 cm -3 , with a refractive index of 1.9. By utilizing the lower refractive index of amorphous silicon carbon nitride, the reflection in the visible light band and near-infrared band can be reduced, thereby improving the utilization rate of light, which is beneficial to increasing the short-circuit current and improving the conversion efficiency of the battery.

[0060] A method for preparing a combined passivation back contact battery comprises the following steps:

[0061] S01: Provide polished and cleaned N-type single crystal silicon wafers;

[0062] S02: forming a first semiconductor layer and a mask layer on the back side of the silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and an N-type polysilicon layer;

[0063] The tunnel oxide layer is formed by dry deposition and has a thickness of 1 nm. The N-type polysilicon layer is formed by LPCVD deposition of an intrinsic polysilicon layer followed by diffusion and has a thickness of 100 nm. The mask layer is silicon nitride and is formed by PECVD deposition and has a thickness of 60 nm.

[0064] S03: performing an opening on the back side of the silicon wafer by laser etching to remove the mask layer, the N-type polysilicon layer, and the tunnel oxide layer in the second semiconductor opening region;

[0065] S04: performing texturing and cleaning on the silicon wafer to remove the residual mask layer, N-type polysilicon layer and tunnel oxide layer in the second semiconductor opening region, and forming a textured surface on the surface of the silicon wafer;

[0066] S05: depositing a first intrinsic amorphous silicon layer of a second semiconductor layer on the back side of the silicon wafer;

[0067] S06: forming a third semiconductor layer on the front side of the silicon wafer, wherein the third semiconductor layer is formed by depositing a second intrinsic amorphous silicon layer with a thickness of 5 nm and a microcrystalline silicon layer with a thickness of 10 nm by plate-type PECVD;

[0068] S07: depositing a P-type amorphous silicon layer as a second semiconductor layer on the back side of the silicon wafer;

[0069] S08: Depositing an anti-reflection layer on the front side of the silicon wafer. The anti-reflection layer is composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer. The preparation method is as follows: continuous coating is performed using a PECVD process at a process temperature of 120°C.

[0070] Amorphous silicon carbonitride layer process parameters: gas flow rates CH4 = 400 sccm, SiH4 = 1000 sccm, NH3 = 200 sccm, N2 = 300 sccm, H2 = 2400 sccm. Deposition pressure P = 100 Pa; plasma power density RF = 0.5 W / cm 2 ;

[0071] S09: Opening the back of the silicon wafer by laser etching to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning;

[0072] S10: depositing a transparent conductive film on the back of the silicon wafer, wherein the transparent conductive film is a doped indium oxide or tin oxide system, formed by PVD deposition, and has a thickness of 100 nm;

[0073] S11: etching an opening in the transparent conductive film on the surface of the transition area between the second semiconductor opening area and the first semiconductor opening area on the back side of the silicon wafer to form an insulating groove to isolate the first semiconductor layer from the second semiconductor layer;

[0074] S12: forming metal electrodes on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer respectively.

[0075] The present invention uses amorphous silicon carbon nitride as an anti-reflection layer, which can effectively reduce reflectivity compared to SiNx films. At the same time, the film has better mechanical properties and chemical resistance, which can improve the reliability and durability of the battery. Using an amorphous silicon carbide / amorphous silicon carbon nitride stack as an anti-reflection layer achieves low reflection across a wide spectrum, creating an anti-reflection layer structure with high interface stability and surface passivation. The amorphous silicon carbide layer provides excellent interface passivation, reducing the surface recombination rate, while the amorphous silicon carbon nitride layer suppresses long-wavelength reflection, improving infrared light utilization, and helping to increase the short-circuit current of the back-contact battery, thereby improving the battery's conversion efficiency. Amorphous silicon carbide and amorphous silicon carbon nitride materials themselves have good chemical stability and mechanical properties, excellent thermal stability, and better acid and alkali corrosion resistance, oxidation resistance, and film density than silicon nitride anti-reflection films. They can operate stably and long-term in harsh environments, have excellent anti-LID performance, and use a low-temperature process, which helps to reduce production energy consumption.

[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A combined passivated back contact battery, characterized in that: The invention comprises an N-type silicon wafer, a second intrinsic amorphous silicon layer, a microcrystalline silicon layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, and a transition zone between a second semiconductor opening region and a first semiconductor opening region on the back side of the silicon wafer and the second semiconductor opening region and the first semiconductor opening region. The anti-reflection layer is a single-layer amorphous silicon carbonitride layer or a stacked structure composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer. The second semiconductor opening region is composed of a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film and a metal electrode sequentially arranged on the back side of the silicon wafer. The first semiconductor opening region is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode sequentially arranged on the back side of the silicon wafer. The transition zone is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer and a transparent conductive film sequentially arranged on the back side of the silicon wafer. An insulating groove is formed by etching the transparent conductive film on the surface of the transition zone.

2. The combined passivated back contact cell according to claim 1, characterized in that: The anti-reflection layer is a single-layer amorphous silicon carbon nitride layer with a thickness of 80-120 nm and a carbon doping concentration of 1×10 19 cm -3 -1×10 22 cm -3 , refractive index is 1.9-2.

0.

3. The combined passivated back contact cell according to claim 1, characterized in that: The anti-reflection layer is a stacked structure of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer, the thickness of the amorphous silicon carbide layer is 10-50nm, and the carbon doping concentration is 1×10 20 cm -3 -1×10 23 cm -3 , the refractive index is 2.01-2.2, the thickness of the amorphous silicon carbon nitride layer is 50-100 nm, and the carbon doping concentration is 1×10 19 cm -3 -1×10 22 cm -3 , refractive index is 1.9-2.

0.

4. The combined passivated back contact cell according to claim 3, characterized in that: The band gap width of the amorphous silicon carbide layer is 2.3-3.3 eV.

5. A method for preparing a combined passivated back contact cell according to any one of claims 1 to 4, characterized in that: The following steps are involved: S01: Provide polished and cleaned N-type single crystal silicon wafers; S02: forming a first semiconductor layer and a mask layer on the back side of the silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and an N-type polysilicon layer; S03: performing an opening on the back side of the silicon wafer by laser etching to remove the mask layer, the N-type polysilicon layer, and the tunnel oxide layer in the second semiconductor opening region; S04: performing texturing and cleaning on the silicon wafer to remove the residual mask layer, N-type polysilicon layer and tunnel oxide layer in the second semiconductor opening region, thereby forming a textured surface on the surface of the silicon wafer; S05: depositing a first intrinsic amorphous silicon layer of a second semiconductor layer on the back side of the silicon wafer; S06: forming a third semiconductor layer on the front side of the silicon wafer; S07: depositing a P-type amorphous silicon layer as a second semiconductor layer on the back side of the silicon wafer; S08: Depositing an anti-reflection layer on the front side of the silicon wafer, specifically including: Option 1: The anti-reflection layer 701 is composed of an amorphous silicon carbonitride layer, and its preparation method is as follows: PECVD deposition is performed at a process temperature of 100-300°C. The process parameters for the amorphous silicon carbonitride layer are: CH4 = 400-1000sccm, SiH4 = 800-3000sccm, NH3 = 200-800sccm, N2 = 300-1000sccm, H2 = 2400-5000sccm. The deposition pressure P = 100-200Pa; the plasma power density RF = 0.5W / cm 2 -1.2W / cm 2 ; Option 2: The anti-reflection layer is composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer, and its preparation method is as follows: continuous coating is performed using a PECVD process at a process temperature of 100-300°C; The process parameters for the amorphous silicon carbide layer are: gas flow rates CH4 = 800-1000 sccm, SiH4 = 800-2000 sccm, Ar = 3000-4000 sccm, H2 = 2400-3000 sccm; deposition pressure P = 50-200 Pa; plasma power density RF = 0.3 W / cm 2 -0.6W / cm 2 ; Amorphous silicon carbonitride layer process parameters: gas flow rate CH4 = 400-1000sccm, SiH4 = 800-3000sccm, NH3 = 200-800sccm, N2 = 300-1000sccm, H2 = 2400-5000sccm; deposition pressure P = 100-200Pa; plasma power density RF = 0.5W / cm 2 -1.2W / cm 2 ; S09: Opening the back of the silicon wafer by laser etching to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning; S10: Depositing a transparent conductive film on the back of the silicon wafer; S11: etching an opening in the transparent conductive film on the surface of the transition area between the second semiconductor opening area and the first semiconductor opening area on the back side of the silicon wafer to form an insulating groove to isolate the first semiconductor layer from the second semiconductor layer; S12: forming metal electrodes on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer respectively.

6. The preparation method according to claim 5, characterized in that The tunnel oxide layer is formed by a dry method with a thickness of 1-2nm; the N-type polysilicon layer is diffused after depositing an intrinsic polysilicon layer by LPCVD, with a thickness of 100-200nm; the mask layer is silicon nitride, formed by PECVD deposition, with a thickness of 60-80nm.

7. The preparation method according to claim 5, characterized in that The third semiconductor layer is formed by depositing a second intrinsic amorphous silicon layer with a thickness of 4-8 nm and a microcrystalline silicon layer with a thickness of 6-20 nm by plate-type PECVD.

8. The preparation method according to claim 5, characterized in that The interfacial bonding strength between the amorphous silicon carbide layer and the amorphous silicon carbonitride layer is achieved by matching the hardness and Young's modulus ratio (H / E≈0.13).

9. The preparation method according to claim 5, characterized in that The transparent conductive film is a doped indium oxide or tin oxide system, formed by PVD deposition, and has a thickness of 50-150 nm.

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