96-channel parallel trigger acquisition method and system

Abstract

The 96-channel parallel independent trigger acquisition system comprises a computer, a bottom plate and a daughter card, the bottom plate is a communication board card of a PXIe interface based on an FPGA, and data acquisition and transmission are achieved; the daughter card comprises a signal conditioning module, an acquisition module and a power conversion circuit, and the signal conditioning module comprises a voltage reduction and following circuit; the acquisition module performs 96-channel independent parallel trigger acquisition and comprises 6 16-path acquisition board cards; after the daughter card is connected with an acquisition object through an interface, an acquisition signal firstly passes through a voltage reduction and following circuit, an input signal is conditioned, the conditioned signal enters an acquisition module for acquisition and then enters an FPGA, the conditioned signal is compared with a reference voltage at the same time, and when the input signal exceeds the reference voltage, the daughter card is connected with the acquisition object. The trigger signal generation circuit generates a trigger signal and sends the trigger signal to the FPGA; by adopting the method provided by the invention, parallel trigger acquisition can be simultaneously carried out on each channel signal so as to realize complete acquisition of all channels.

Description

Technical Field

[0001] The present invention relates to a 96-channel high-speed analog signal parallel triggering acquisition method and system, belonging to the field of signal acquisition. Background Art

[0002] Jammers are a common electronic jamming technology weapon in modern advanced equipment. They are used to confuse the enemy radar's search and tracking system, interfere with the enemy's communication network, and destroy the enemy's command system. The pulse width and amplitude of the jammer's transmission signal play an important role in the delivery strategy. Therefore, the launch performance test of the jammer is a key process to ensure the intact combat performance of the equipment.

[0003] During the test, the launch signal of the delivery strategy needs to be checked to see if it meets the launch standards. Otherwise, it will cause incorrect release, seriously affecting combat performance. The test process has two characteristics: first, the delivery instructions have random characteristics; second, there are many launch channels, at least 32 channels. Existing testing technology cannot meet this test process.

[0004] Currently, there are a variety of data acquisition and analysis devices available on the market. Oscilloscopes, for example, are a common data acquisition and analysis tool. While using an oscilloscope for data acquisition can indeed collect and analyze a large amount of signal characteristic data from specific channels, it is unable to collect and capture data from random channels, such as signals emitted by jammers. This is primarily due to the limited number of channels on a single oscilloscope (typically 4-8 channels), making it difficult to acquire data from more channels. Furthermore, due to the oscilloscope's triggering mechanism, when one acquisition channel is triggered, the remaining channels also stop acquiring data, making it impossible to acquire and analyze parallel signals. 16- and 48-channel acquisition boards are now common off-the-shelf products. However, like the triggering mechanism of an oscilloscope, these boards only offer single-channel triggering, making them incapable of parallel data acquisition. Furthermore, these acquisition boards often lack the ability to extract specific characteristic data, hindering signal analysis. Therefore, for instantaneous and random data acquisition of multiple channels, a multi-channel data parallel triggering acquisition system is required. This system can perform multi-channel data parallel triggering, extract key characteristic data, and analyze key data.

[0005] Triggering is when the user sets specific conditions for certain signals during data acquisition. The preset conditions are usually related to a certain characteristic of the signal (such as level, edge, etc.), such as the rising voltage threshold or falling voltage threshold of a signal. Once these specific conditions are met, the data acquisition system is triggered, starts acquiring and transmits data to the system.

[0006] During the signal data acquisition process, three trigger modes, automatic, standard, and single, are generally used to collect trigger signals. The corresponding trigger mode needs to be set according to different signal types to accurately collect the required signal data.

[0007] In automatic mode, the system will always scan all signal data. However, when the signal is unstable or the trigger conditions are difficult to meet, the automatic trigger mode may cause the waveform display to be unstable or unable to capture the valid waveform, and manual signal data latching is required. The automatic trigger mode is suitable for situations where the signal is stable and continuous and the trigger conditions are easy to meet.

[0008] In standard mode, when the trigger level is out of the signal level range, the system will not refresh the waveform, but keep the last displayed waveform unchanged. Only when the trigger level is within the signal level range again will the system continue to capture and refresh the waveform. Standard trigger mode is suitable for situations where the signal is complex, the trigger conditions are relatively fixed, and high waveform stability is required;

[0009] In single trigger mode, the waveform is captured and displayed only when a signal that meets the trigger condition occurs once, and then the capture of new waveform data stops. Single trigger mode is suitable for situations where you need to capture the signal waveform of a specific event or abnormal situation.

[0010] During data acquisition, single-shot trigger mode is often used to capture data for high-speed analog signals, transient pulse signals, or abnormal signals. However, due to limitations in the trigger mechanism, automatic mode cannot be used to acquire these signals. Signals in this mode are not automatically latched, and valid signal data cannot be collected. Furthermore, standard and single-shot modes are only effective for a single channel. Once a channel is triggered, all channels cease acquisition. This makes it impossible to acquire high-speed signals in parallel across multiple channels or unspecified channels.

[0011] The existing technology for parallel acquisition of multi-channel trigger signals is mainly used to collect continuous data from specific channels, and then use feature extraction algorithms to identify trigger signals and extract data. For example, the multi-channel acquisition systems described in patents CN202410628347.4 and CN109284247A all store specific data and then use algorithms to extract trigger signals. The above technologies, first, extract and analyze trigger signals based on cyclic, continuous data or known data types and sizes, and do not have the ability to capture instantaneous trigger signals online in real time; second, it cannot guarantee that the complete trigger signal can be collected within the data acquisition cycle; third, this method has high requirements for storage space and is not suitable for long-term data acquisition; fourth, the multi-channel trigger modes affect each other, and each channel cannot be triggered independently in parallel. Summary of the Invention

[0012] Aiming at the problem that multi-channel parallel independent triggering and acquisition cannot be carried out, the present invention proposes a 96-channel parallel independent triggering and acquisition system, which can realize multi-channel data parallel independent triggering and acquisition, real-time acquisition and complete trigger signal data acquisition, and is suitable for parallel triggering and acquisition of pulse signals, transient signals, abnormal signals and random channel high-speed analog signals.

[0013] The technical solutions of the present invention are as follows:

[0014] A 96-channel parallel independent trigger acquisition system includes a computer, a baseboard and a daughter card. The baseboard is a communication board with a PXIe interface based on FPGA, which realizes data acquisition and transmission. The daughter card includes a signal conditioning module, an acquisition module and a power conversion circuit. The signal conditioning module includes a step-down and follower circuit. The acquisition module performs 96-channel independent parallel trigger acquisition. The acquisition module includes 6 16-channel acquisition boards, and the acquisition board includes an ADC acquisition circuit, a trigger signal generation circuit, and a DAC comparison voltage generation circuit. After the daughter card is connected to the acquisition object through an interface, the acquisition signal first passes through the step-down and follower circuit to condition the input signal. The conditioned signal enters the acquisition module for acquisition and then enters the FPGA. The conditioned signal is compared with a reference voltage at the same time. When the input signal exceeds the reference voltage, The trigger signal generation circuit generates a trigger signal and sends it to the FPGA; the signal conditioning module converts the analog signal of the port into a digital signal that can be recognized by the acquisition board. After the analog-to-digital conversion, the collected trigger signal is transmitted to the Thunderbolt interface through the PXIe interface, and then transmitted to the computer through the Thunderbolt interface to the PXIe conversion board; the six 16-channel acquisition boards include a total of 96 acquisition channels, and each channel is set with a separate software identification code for module identification. Each channel is equipped with a 16-bit circular memory for storing data collected by the acquisition module. The first 4 bits of data are used as channel identification data and then sent to the memory write enable, and the actual collected data is written to the data bits of the memory; after the system starts acquisition, the data collected by each channel is stored in the memory one by one and cyclically overwritten, and waits for the generation of the trigger signal.

[0015] The 96-channel parallel independent trigger acquisition system has all channels independently performing cyclic signal acquisition according to the trigger mode at the same time. Each channel is independent of each other, does not interfere with each other, and acquires data at the same time. All channels continue to acquire data in a cyclic manner when there is no trigger signal. If a trigger signal arrives, the complete trigger signal acquisition of the current channel is performed according to the signal storage position, and the trigger acquisition of the current channel is reported to the system. The remaining untriggered channels continue to acquire data in a cyclic manner until all channels complete the trigger signal acquisition, or the system stop command arrives, and the system acquisition task stops.

[0016] The described 96-channel parallel independent trigger acquisition system stores the trigger data and can collect the data before and after the trigger position as required to ensure the integrity of the trigger signal for data analysis.

[0017] For the described 96-channel parallel independent trigger acquisition system, the method for storing trigger data includes the following steps:

[0018] 1) Before acquisition, according to the storage depth of the system channels, set the data length L to be collected and the trigger position X% as required. X% means that with the trigger position as the boundary, L*X% is the data before the trigger and L*(1 - X%) is the data after the trigger. The data stored in each channel is data[i][L - 1] (i represents the channel numbers from 0 to 95);

[0019] 2) To ensure the effectiveness of system trigger analysis, data acquisition starts as soon as the power is on. According to the storage length, the data is sequentially stored in the memory. Let the data increment during the storage process be j, that is, data[i][0], data[i][1], data[i][2]... data[i][j]... data[i][L - 1], and judge the trigger situation in real time; 3) If there is no trigger and the data fills the length L, the data storage starts from the 0th position of the memory in a loop; at the same time, judge the trigger situation and the trigger position in real time;

[0020] 4) When data trigger is detected, calculate the trigger position as j / L = A%;

[0021] 41) If A% = X%, store the data after the trigger, and the data length is L - j. The data in the memory is: the data before the trigger data[i][j - 1] + the data after the trigger data[i][j ~ L - 1];

[0022] 42) If A% < X%, store the data after the trigger, and the data length is L*(1 - X%). The data in the memory is: the data before the trigger data[i][j + L*(1 - X%) ~ L - 1] + data[i][j - 1] + the data after the trigger data[i][j ~ j + L*(1 - X%)];

[0023] 43) If A% > X%, store the data after the trigger, and the data length is L*(1 - X%). The data in the memory is: the data before the trigger data[i][j - L*X% ~ j - 1] + the data after the trigger data[i][j ~ L - 1] + data[i][j - L*X%];

[0024] 5) After the signal acquisition is completed, store the acquired data data[i][L] in the memory of each channel.

[0025] The 96-channel parallel trigger acquisition method according to any of the above systems. All channels simultaneously perform cyclic signal acquisition independently according to the trigger mode. Each channel is independent of each other, without interference, and acquires simultaneously. All channels continuously perform cyclic acquisition when there is no trigger signal. If a trigger signal arrives, a complete trigger signal acquisition of the current channel is performed according to the signal storage position, and the system is reported to complete the trigger acquisition of the current channel. The remaining untriggered channels continue to perform cyclic acquisition until all channels complete the trigger signal acquisition or the system stop instruction arrives, and the system acquisition task stops.

[0026] For the described 96-channel parallel independent trigger acquisition method, the trigger data is stored, and data before and after the trigger position can be acquired according to requirements, ensuring the integrity of the trigger signal for easy data analysis.

[0027] For the described 96-channel parallel independent trigger acquisition method, the method for storing trigger data includes the following steps:

[0028] 1) Before acquisition, according to the storage depth of the system channels, set the data length L and trigger position X% to be acquired as needed. X% means that with the trigger position as the boundary, L*X% is the data before the trigger, and L*(1 - %X) is the data after the trigger. The stored data for each channel is data[i][L - 1] (i represents the channel numbers from 0 to 95).

[0029] 2) To ensure the effectiveness of system trigger analysis, data acquisition starts as soon as the power is on. According to the storage length, the data is sequentially stored in the memory. Let the data increment during the storage process be j, that is, data[i][0], data[i][1], that is, data[i][2]…data[i][j]…data[i][L - 1], and the trigger situation is judged in real time. 3) If there is no trigger all the time, and after the data fills the length L, the data is cyclically stored starting from the 0th position of the memory in turn. At the same time, the trigger situation and trigger position are judged in real time.

[0030] 4) When data trigger is found, calculate the trigger position as j / L = A%.

[0031] 41) If A% = X%, store the data after the trigger, and the data length is L - j. The memory data is: the data before the trigger data[i][j - 1] + the data after the trigger data[i][j~L - 1].

[0032] 42) If A% < X%, store the data after the trigger, and the data length is L*(1 - X%). The memory data is: the data before the trigger data[i][j + L*(1 - X%)~L - 1] + data[i][j - 1] + the data after the trigger data[i][j~j + L*(1 - X%)].

[0033] 43) If A%>X%, store the post-trigger data. The data length is L*(1-X%). The memory data is: pre-trigger data data[i][jL*X%~j-1] + post-trigger data data[i][j~L-1] + data[i][jL*X%];

[0034] 5) After signal acquisition is completed, the acquired data data[i][L] is stored in the memory of each channel.

[0035] By adopting the above scheme, the present invention will be beneficial for the parallel, random triggering and acquisition of 32 or more transmission signals. For example, the emission signals of jammers are at least 32 channels, and for rockets, at least 96 channels. Detecting these signals requires parallel acquisition of 32 or more channels, and each channel must be independently triggered and independent of each other to detect the emission signals. The emission strategy is random, and the above invention method can simultaneously trigger and acquire signals from each channel in parallel, achieving complete acquisition of all channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a block diagram of a 96-channel parallel trigger acquisition system of the present invention;

[0037] Figure 2 The 96-channel parallel trigger acquisition hardware design of the present invention;

[0038] Figure 3 This is the 96-channel independent parallel triggering method of the present invention;

[0039] Figure 4 This is the 96-channel parallel triggering process of the present invention;

[0040] Figure 5 This is a schematic diagram of single-channel cyclic storage in the present invention;

[0041] Figure 6 This is the single-channel cyclic acquisition process of the present invention; DETAILED DESCRIPTION

[0042] The present invention is described in detail below with reference to specific embodiments.

[0043] A 96-channel parallel independent trigger acquisition system, as follows:

[0044] The hardware design block diagram of the acquisition system is as follows: Figure 1As shown in the figure, this system is designed based on the FPGA+PXIe architecture and includes a computer, a baseboard, and a daughter card. The baseboard is a communication card with a PXIe interface designed based on FPGA, which realizes data acquisition and transmission. The daughter card includes a signal conditioning module, an acquisition module, and a power conversion circuit, and the signal conditioning module includes a step-down and follower circuit. The acquisition module includes six 16-channel acquisition boards, each of which includes an ADC acquisition circuit, a trigger signal generation circuit, and a DAC comparison voltage generation circuit. After the daughter card is connected to the acquisition object through the interface, the acquisition signal first passes through the step-down and follower circuit to condition the input signal. The conditioned signal enters the acquisition module for acquisition and then enters the FPGA. The conditioned signal is simultaneously compared with a reference voltage. When the input signal exceeds the reference voltage, the trigger signal generation circuit generates a trigger signal and sends it to the FPGA. The signal conditioning module converts the analog signal of the port into a digital signal that can be recognized by the acquisition board. After the analog-to-digital conversion, the acquired trigger signal is transmitted to the Thunderbolt interface through the PXIe interface, and then transmitted to the computer through the Thunderbolt interface to PXIe converter board.

[0045] The specific steps are as follows:

[0046] S1. Set the trigger mode, storage data length, and trigger position of each channel in the system;

[0047] S2. The interface module connects to the acquisition target and, through the signal conditioning module, sets the amplitude to 0-30V to condition the signal to a voltage range that the acquisition module can handle.

[0048] S3. After signal conditioning, the signal is sent to a high-precision acquisition module;

[0049] S4. The acquisition module performs 96-channel independent parallel trigger acquisition as follows:

[0050] S4.1. Figure 2 As shown in the figure, a total of 96 signal trigger acquisition channels are designed with 6*16 channels. Six modules are set with individual software identification codes for module identification. Each channel is equipped with a 16-bit circular memory to store the data collected by the acquisition module. The first 4 bits of data are used as channel identification data and then sent to the memory write enable. The actual collected data is written to the data bits of the memory. When the system starts acquisition, the data collected by each channel is stored one by one in the 16 memories and cyclically overwritten, and then waits for the generation of the trigger signal;

[0051] S4.2. Figure 3As shown, to ensure the acquisition of abnormal signals and random data, a method for independent triggering of each channel is proposed. All channels in the system have independent triggering capabilities, which does not affect the triggering of the remaining channels. All channels in the system simultaneously and independently perform cyclic signal acquisition according to the trigger mode. Each channel is independent of each other and does not interfere with each other, and acquires data simultaneously. All channels continue to acquire data in a cyclic manner when there is no trigger signal. If a trigger signal arrives, the complete trigger signal acquisition of the current channel is performed according to the signal storage location, and the trigger acquisition of the current channel is reported to the system to complete. The remaining untriggered channels continue to acquire data in a cyclic manner until all channels complete trigger signal acquisition or the system stop command arrives, and the system acquisition task stops. This ensures the independence of each channel. That is, all channels have independent triggering capabilities, and after one channel is triggered, the remaining channels continue to perform real-time trigger acquisition, realizing parallel and independent trigger acquisition of 96 channels in the system.

[0052] S4.3. Store the trigger data. Collect data before and after the trigger position as needed to ensure the integrity of the trigger signal for easy data analysis. Circularly collect and store the trigger data according to the system-set trigger position and specific data storage length, such as Figure 4-6 , a trigger signal data storage method is proposed as follows:

[0053] 1) Before acquisition, according to the system channel storage depth, set the data length L (i.e., data cycle storage capacity) and trigger position X% as needed. X% represents the trigger position as the boundary, L*X% is the pre-trigger data, and L*(1-%X) is the post-trigger data (it should be noted that each channel has an independent trigger mode setting, which can be set for each channel or all channels). The data stored in each channel is data[i][L-1] (i represents the channel number from 0 to 95);

[0054] 2) To ensure the effectiveness of the system trigger analysis, data acquisition is performed as soon as the power is turned on. According to the storage length, the data is stored in the memory in sequence. The increment of the storage process data is set to j, that is, data[i][0], data[i][1], that is, data[i][2]…data[i][j]…data[i][L-1], and the trigger situation is judged in real time;

[0055] 3) If there is no trigger and the data storage reaches the full length L, the data will be stored in a loop starting from the 0th position of the memory; at the same time, the trigger situation and trigger position will be determined in real time;

[0056] 4) Found the data trigger and calculated the trigger position as j / L=A%;

[0057] 41) If A% = X%, store the data after triggering. The data length is L - j, and the memory data is: the data before triggering data[i][j - 1] + the data after triggering data[i][j to L - 1];

[0058] 42) If A% < X%, store the data after triggering. The data length is L * (1 - X%), and the memory data is: the data before triggering data[i][j + L * (1 - X%) to L - 1] + data[i][j - 1] + the data after triggering data[i][j to j + L * (1 - X%)];

[0059] 43) If A% > X%, store the data after triggering. The data length is L * (1 - X%), and the memory data is: the data before triggering data[i][j - L * X% to j - 1] + the data after triggering data[i][j to L - 1] + data[i][j - L * X%];

[0060] 5) After signal acquisition is completed, store the acquired data data[i][L] into the memories of each channel;

[0061] As Figure 6 shown below, an example is given as follows:

[0062] (1) The data acquisition length is related to the system channel capacity. The acquisition length is not greater than the system channel capacity, and the trigger position determines the amount of data before and after triggering;

[0063] (2) Assume the data storage length L = 10M, and the trigger position is X% = 40%. Then, it is necessary to store the amount of data L * 40% = 4M before triggering and the amount of data L * (1 - 40%) = 6M after triggering;

[0064] (3) The system continuously performs acquisition, and the data is stored cyclically. There are two cases of storing triggered and untriggered data:

[0065] ① If not triggered, the system continuously writes data into the memory in a loop. When the memory length reaches the upper limit, the loop starts storing data from the 0th position;

[0066] ② During the process, if it is judged that triggering has occurred and it has been triggered, there are the following three cases, but only one can occur at the same time:

[0067] If the trigger position j = 4M, continue to acquire and store data into the memory until the memory storage upper limit is reached;

[0068] If the trigger position j = 3M, continue to acquire 6M of data and store it into the memory. At this time, the acquisition of this channel stops and stores data. The data from 9M - 10M + 0 to (3M - 1) is the data before triggering, and the data segment from 3M to 9M is the data after triggering;

[0069] Trigger position j = 7M, and 6M data needs to be collected and stored. At this time, 3M is left, which reaches the capacity limit. The 3M collected data needs to be stored from the beginning to the 3M position. At this time, the channel stops collecting and storing data. The data segment is 3M to (7M-1) as the pre-trigger data, and 7M-10M+0-3M as the post-trigger data.

[0070] S5. Data transmission is displayed according to the display mode;

[0071] S6.9 Acquisition stops when all 6 channels are triggered or the system issues a stop acquisition command.

[0072] Description of system setting mode:

[0073] 1) Trigger mode refers to the triggering method of each channel, specifically rising edge, falling edge or other triggering methods;

[0074] 2) Data length refers to the data storage depth of each channel set by the user. This setting cannot exceed the total data depth of each channel;

[0075] 3) The trigger position specifically refers to the position of the first trigger data at the set data storage depth, which is conducive to the effective analysis of the signals before and after the trigger data, and also ensures the complete collection of the data before and after the trigger.

[0076] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A 96-channel parallel independent trigger acquisition system, characterized in that: The system includes a computer, a baseboard, and daughter cards. The baseboard is a communication card based on the FPGA's PXIe interface, which realizes data acquisition and transmission. The daughter card includes a signal conditioning module, an acquisition module, and a power conversion circuit. The signal conditioning module includes a step-down and follower circuit. The acquisition module performs 96-channel independent parallel trigger acquisition and includes six 16-channel acquisition boards. The acquisition boards include an ADC acquisition circuit, a trigger signal generation circuit, and a DAC comparison voltage generation circuit. After the daughter card is connected to the acquisition object through the interface, the acquisition signal first passes through the step-down and follower circuit to condition the input signal. The conditioned signal enters the acquisition module for acquisition and then enters the FPGA. The conditioned signal is also compared with the reference voltage. When the input signal exceeds the reference voltage, the trigger signal generation circuit generates a trigger signal and sends it to the FPGA. The signal conditioning module converts the analog signal of the port into a digital signal that can be recognized by the acquisition board. After the analog-to-digital conversion, the collected trigger signal is transmitted to the Thunderbolt interface through the PXIe interface, and then transmitted to the computer through the Thunderbolt interface to the PXIe conversion board; the six 16-channel acquisition boards include a total of 96 acquisition channels, and each channel has a separate software identification code for module identification. Each channel is equipped with a 16-bit circular memory for storing the data collected by the acquisition module. The first 4 bits of data are used as channel identification data and then sent to the memory write enable, and the actual collected data is written to the data bits of the memory; after the system starts acquisition, the data collected by each channel is stored in the memory one by one and cyclically overwritten, and waits for the generation of the trigger signal.

2. The 96-channel parallel independent trigger acquisition system according to claim 1, characterized in that: All channels simultaneously and independently perform cyclic signal acquisition according to the trigger mode. Each channel is independent of each other, does not interfere with each other, and acquires data at the same time. All channels continue to acquire data in a cyclic manner when there is no trigger signal. If a trigger signal arrives, the complete trigger signal acquisition of the current channel is performed according to the signal storage location, and the trigger acquisition of the current channel is reported to the system. The remaining untriggered channels continue to acquire data in a cyclic manner until all channels complete the trigger signal acquisition, or the system stop command arrives and the system acquisition task stops.

3. The 96-channel parallel independent trigger acquisition system according to claim 1, characterized in that: The trigger data is stored and the data before and after the trigger position can be collected as needed to ensure the integrity of the trigger signal for easy data analysis.

4. The 96-channel parallel independent trigger acquisition system according to claim 3, characterized in that: The method for triggering data to be stored comprises the following steps: 1) Before acquisition, set the data length L and trigger position X% to be acquired according to the system channel storage depth. X% indicates the trigger position as the boundary. L*X% is the pre-trigger data, and L*(1-%X) is the post-trigger data. The data stored in each channel is data[i][L-1] (i represents the channel number from 0 to 95). 2) To ensure the effectiveness of system-triggered analysis, data acquisition is performed as soon as the power is on. According to the storage length, the data is sequentially stored in the memory. Let the data increment during the storage process be j, that is, data[i][0], data[i][1], data[i][2]... data[i][j]... data[i][L - 1], and the trigger situation is judged in real time; 3) If no trigger occurs and the data fills the length L, the data storage starts from the 0th position of the memory in a loop; at the same time, the trigger situation and the trigger position are judged in real time; 4) When data triggering is detected, calculate the trigger position as j / L = A%; 41) If A% = X%, store the data after triggering, and the data length is L - j. The memory data is: the data before triggering data[i][j - 1] + the data after triggering data[i][j~L - 1]; 42) If A% < X%, store the data after triggering, and the data length is L*(1 - X%). The memory data is: the data before triggering data[i][j + L*(1 - X%)~L - 1] + data[i][j - 1] + the data after triggering data[i][j~j + L*(1 - X%)]; 43) If A% > X%, store the data after triggering, and the data length is L*(1 - X%). The memory data is: the data before triggering data[i][j - L*X%~j - 1] + the data after triggering data[i][j~L - 1] + data[i][j - L*X%]; 5) After the signal acquisition is completed, store the acquired data data[i][L] in the memories of each channel.

5. The 96-channel parallel trigger acquisition method of any one of claims 1 to 4, characterized in that: All channels simultaneously perform cyclic signal acquisition independently according to the trigger mode. Each channel is independent of each other and does not interfere with each other while acquiring; all channels continuously perform cyclic acquisition when there is no trigger signal. If a trigger signal arrives, a complete trigger signal acquisition of the current channel is performed according to the signal storage position, and the system is reported to complete the trigger acquisition of the current channel; the remaining untriggered channels continue to perform cyclic acquisition until all channels complete the trigger signal acquisition or the system stop instruction arrives, and the system acquisition task stops.

6. The 96-channel parallel independent trigger acquisition method according to claim 5, characterized in that: Store the trigger data. According to the requirements, the data before and after the trigger position can be acquired to ensure the integrity of the trigger signal for data analysis.

7. The 96-channel parallel independent trigger acquisition method according to claim 5, characterized in that: The method for storing trigger data includes the following steps: 1) Before acquisition, according to the storage depth of the system channels, set the required data length L and trigger position X% as needed. X% means that with the trigger position as the boundary, L*X% is the data before triggering and L*(1 - %X) is the data after triggering. The data stored in each channel is data[i][L - 1], where i represents the channel numbers from 0 to 95; 2) To ensure the effectiveness of system-triggered analysis, data acquisition is performed as soon as the power is on. According to the storage length, the data is sequentially stored in the memory. Let the data increment during the storage process be j, that is, data[i][0], data[i][1], data[i][2]... data[i][j]... data[i][L-1], and the triggering situation is judged in real time; 3) If no trigger occurs and the data fills the length L, the data storage starts from the 0th position of the memory in a loop; at the same time, the triggering situation and the triggering position are judged in real time; 4) When data triggering is detected, calculate the triggering position as j / L = A%; 41) If A% = X%, store the data after triggering, and the data length is L-j. The memory data is: the data before triggering data[i][j-1] + the data after triggering data[i][j~L-1]; 42) If A% < X%, store the data after triggering, and the data length is L*(1-X%). The memory data is: the data before triggering data[i][j+L*(1-X%)~L-1] + data[i][j-1] + the data after triggering data[i][j~j+L*(1-X%)]; 43) If A% > X%, store the data after triggering, and the data length is L*(1-X%). The memory data is: the data before triggering data[i][j-L*X%~j-1] + the data after triggering data[i][j~L-1] + data[i][j-L*X%]; 5) After the signal acquisition is completed, store the acquired data data[i][L] in the memories of each channel.

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