Embedded system reliability enhancement method, device, medium and product
By adopting differentiated configuration of memory controllers in heterogeneous multi-core architecture and real-time monitoring of the calling sequence of program instances in embedded systems, the problem of insufficient software reliability in existing technologies is solved, fine-grained detection of hardware failures and malicious attacks is achieved, and the reliability and fault tolerance of the system are improved.
Patent Information
- Application Number
- CN202510976953.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-16
- Publication Date
- 2025-09-16
- Estimated Expiration
- 2045-07-16
AI Technical Summary
Existing embedded system reliability enhancement technologies cannot effectively guarantee the correctness of results at the software level, and there are problems such as resource conflicts and difficulties in real-time anomaly detection. Especially under the multi-core processor architecture, existing technologies such as dynamic heterogeneous redundancy and triple-module redundancy cannot effectively improve system reliability.
The system adopts differentiated configuration of memory controller under heterogeneous multi-core architecture, obtains target program resources in learning mode, generates multiple program instances with isolated resources and different processor cores in running mode, and uses hook functions to monitor and compare the calling sequences and return values of program instances, triggering alarms to detect hardware failures, software errors or malicious attacks.
It enables fine-grained detection of hardware failures, software errors, and malicious attacks, improving the reliability and fault tolerance of embedded systems, especially in key areas such as automobiles and aircraft.
Smart Images
Figure CN120469827B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of reliability enhancement of computer equipment, and in particular to a method, device, medium and product for enhancing the reliability of an embedded system. Background Art
[0002] As semiconductor processes evolve toward higher integration and smaller feature sizes (e.g., processes below 10nm), an increasing number of chips are employing multi-core processors. In critical areas like automotive electronics (e.g., autonomous driving systems) and aerospace (e.g., flight control modules), system operational safety is directly linked to life safety and equipment stability, placing extreme demands on the reliability of multi-core processors. Software errors, which cause 80% to 90% of system failures, are the primary factor impacting the reliability of embedded real-time systems. Improving system reliability in multi-core architectures is crucial.
[0003] Existing reliability enhancement technologies include Dynamic Heterogeneous Redundancy (DHR) and Triple Modular Redundancy (TMR). DHR uses multiple different development languages to develop the same program. At runtime, three hardware platforms are randomly selected from multiple hardware platforms (including ARM, X86, LA, Alpha, and PPC). Three programs developed in multiple languages (including C, Go, Python, Perl, and Rust) are randomly selected and executed simultaneously. Correctness decisions are made based on the execution results. This technology requires multiple redundant devices and requires writing the same program in different languages, which wastes significant manpower and costs. Triple Modular Redundancy (TMR) uses three identical execution units (CPUs) to simultaneously process the same instruction. The results are output through a majority voter (choose two out of three). A single unit failure or error is masked by the correct results of the other two, ensuring correct execution. This technology only guarantees instruction success and does not guarantee the correctness of the results at the software's business layer. Summary of the Invention
[0004] Technical problem to be solved by the present invention: In response to the above-mentioned problems of the prior art, a method, device, medium and product for enhancing the reliability of an embedded system are provided. The present invention aims to achieve reliability enhancement at the software level, solve the problems of program execution reliability, resource conflict isolation, and real-time anomaly detection, and improve the system reliability in automobiles, aircraft, and production manufacturing scenarios in the embedded field.
[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:
[0006] A method for enhancing the reliability of an embedded system comprises the following steps:
[0007] S101, deploys a hardware platform that can differentiate memory controllers for different processor cores;
[0008] S102, running the target program in a learning mode to obtain resources required by the target program;
[0009] S103, run the target program in the running mode and generate multiple program instances for the target program with isolated resources and different processor cores in combination with the resources required by the target program, monitor and compare the calling sequence and return value of each program instance during the running process of the program instance, and trigger an alarm if the calling sequence or return value of any program instance is inconsistent with that of other program instances to realize the monitoring of hardware failures, software errors or malicious attacks during the running process of the target program.
[0010] Optionally, step S101 includes:
[0011] S201, a dual-memory controller embedded platform that supports ARM heterogeneous multi-core architecture features;
[0012] S202, installing an embedded operating system on a dual memory controller embedded platform;
[0013] S203 , allocating different memory controllers to the large-core CPU and the small-core CPU of the embedded platform in the embedded operating system so that the memory data of the large-core CPU and the small-core CPU are independent of each other.
[0014] Optionally, the dual memory controller embedded platform is a dual storage medium platform including a solid state drive (SSD) and an EMMC storage device. When installing an embedded operating system on the dual memory controller embedded platform in step S202, it includes installing the embedded operating system on the solid state drive (SSD) and configuring program data to be stored in the EMMC storage device.
[0015] Optionally, step S102 includes: running the target program in learning mode to obtain resources required by the target program, including configuration files, intermediate files and output file paths loaded when the target program is running, socket ports, pipe names, and shared memory identifiers created by the target program, generating a resource manifest file required for a program instance for the target program, and copying the configuration files, intermediate files and output file paths loaded when the target program Test is running to an EMMC storage device to generate multiple backups to ensure that each program instance can obtain the same configuration files, intermediate files and output file paths loaded when running.
[0016] Optionally, in step S103, running the target program in the running mode and generating multiple program instances for the target program with isolated resources and different processor cores in combination with the resources required by the target program include: executing the target program through a modified system execution function exec, and the modified system execution function exec calls the fork function once or multiple times when it detects that the name of the executed target program is the specified name, and binds the first program instance created by the system execution function exec to the large-core CPU of the dual-memory controller embedded platform to undertake the real business of the target program, and binds other program instances created by the fork function to the small-core CPU of the dual-memory controller embedded platform to serve as redundant verification program instances of the first program instance, and each program instance loads the configuration file, intermediate file and output file path loaded at runtime according to the required resource list file, and when creating the socket port, pipe name, and shared memory identifier, by adding a port number with a fixed different step length to the socket port, appending identifiers with different suffixes to the pipe name, and adding parameters of different sizes to the shared memory identifier, so as to achieve resource isolation of the socket port, pipe name, and shared memory identifier created by each program instance.
[0017] Optionally, the calling sequence or return value of any program instance being inconsistent with other program instances in step S103 includes: the calling sequence or return value of the first program instance being inconsistent with other program instances, or the calling sequence or return value of other program instances other than the first program instance being inconsistent.
[0018] Optionally, in step S103, when monitoring and comparing the call sequence and return value of each program instance during the running process of the program instance, monitoring the call sequence and return value of each program instance means using the hook function Hook to intercept key system calls in real time to monitor the call sequence and return value of each program instance.
[0019] In addition, the present invention also provides an embedded system reliability enhancement system, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the embedded system reliability enhancement method.
[0020] In addition, the present invention also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the embedded system reliability enhancement method through a processor.
[0021] In addition, the present invention also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the embedded system reliability enhancement method through a processor.
[0022] Compared with the prior art, the present invention can achieve the following beneficial effects: the method of the present invention includes deploying a hardware platform that can realize differentiated memory controllers for different processor cores; running a target program in a learning mode to obtain resources required by the target program; running the target program in a running mode and generating multiple program instances for the target program with mutually isolated resources and different processor cores based on the resources required by the target program; monitoring and comparing the call sequences and return values of each program instance during the running process; triggering an alarm if the call sequence or return value of any program instance is inconsistent with that of other program instances to realize the monitoring of hardware failures, software errors or malicious attacks during the running process. Through the "execution-verification-decision" model, the present invention realizes fine-grained detection of hardware failures, software errors and malicious attacks through the differentiated configuration of dual storage / memory controllers, dynamic resource collection during program running, three-instance multi-core running and periodic comparison of system call sequences, and can achieve software-level reliability enhancement, solve the problems of program execution reliability, resource conflict isolation, and real-time anomaly detection, and improve the fault tolerance and reliability of critical mission systems in embedded fields such as automobiles, aircraft, and manufacturing scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 Schematic diagram of the basic process of the method of the embodiment of the present invention.
[0024] Figure 2 Detailed flowchart of the method according to the embodiment of the present invention. DETAILED DESCRIPTION
[0025] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.
[0026] like Figure 1 As shown, the embedded system reliability enhancement method of this embodiment includes the following steps:
[0027] S101, deploys a hardware platform that can differentiate memory controllers for different processor cores;
[0028] S102, running the target program in a learning mode to obtain resources required by the target program;
[0029] S103, run the target program in the running mode and generate multiple program instances for the target program with isolated resources and different processor cores in combination with the resources required by the target program, monitor and compare the calling sequence and return value of each program instance during the running process of the program instance, and trigger an alarm if the calling sequence or return value of any program instance is inconsistent with that of other program instances to realize the monitoring of hardware failures, software errors or malicious attacks during the running process of the target program.
[0030] As an optional implementation, Figure 2 As shown, step S101 is Figure 2 The "Prepare Hardware" steps in the .
[0031] S201, prepares to support the dual memory controller embedded platform of ARM heterogeneous multi-core architecture features, such as Figure 2 As shown, the dual memory controller embedded platform in this embodiment specifically adopts the Rockchip RK3588 8G device, and this step S201 is recorded as the step of preparing the Rockchip RK3588 8G device;
[0032] S202, installing an embedded operating system on a dual memory controller embedded platform; Figure 2 As shown, the embedded operating system in this embodiment specifically adopts the Kylin embedded operating system. In addition, other embedded operating systems can also be used as needed;
[0033] S203: In the embedded operating system, separate memory controllers are allocated for the large-core CPU and small-core CPU of the embedded platform to ensure independent memory data. The Rockchip RK3588 8GB device has two memory controllers (referred to as memory controller 1 and memory controller 2 for clarity). Memory controller 1 is dedicated to the large-core CPU (Core0, Core1) operating area, ensuring high-performance core computing efficiency. Memory controller 2 is allocated to the small-core CPU (Core2, Core3) operating area, reducing redundant verification energy consumption.
[0034] The dual-memory controller embedded platform (Rockchip RK3588 8GB device) in this embodiment is a dual-storage platform (SSD+EMMC) consisting of a solid-state drive (SSD) and an EMMC storage device. In step S202, installing the embedded operating system on the dual-memory controller embedded platform involves installing the embedded operating system on the SSD and configuring the program data to be stored on the EMMC storage device. The system is installed on the SSD to increase operating speed, while program data, including configuration files, intermediate files, and output files, is stored on the EMMC storage device to ensure data persistence and stability.
[0035] like Figure 2 As shown, after the step of "prepare hardware", it is necessary to prepare the target program. For the sake of convenience, the target program is hereinafter referred to as "Test" in this embodiment. Figure 2 Indicated as "Prepare software Test".
[0036] like Figure 2 As shown, in this embodiment, step S102 is Figure 2 The step of "starting learning mode" is represented in the figure. The stage under "learning mode" is the first stage of running the target program Test, which is the learning and behavior collection stage, recording all isolated dynamic resource information when the program is running. Figure 2 Step S102 includes: running the target program Test in the learning mode to obtain resources required by the target program, including configuration files, intermediate files, and output file paths loaded when the target program runs, socket ports, pipe names, and shared memory identifiers created by the target program, generating a resource manifest file required for a program instance for the target program, and copying the configuration files, intermediate files, and output file paths loaded when the target program Test runs to an EMMC storage device to generate multiple backups to ensure that each program instance can obtain the same configuration files, intermediate files, and output file paths loaded when the program runs.
[0037] The "Run Mode" phase serves as the second stage of running the target program Test. When the system executes the specified program, the operating system automatically creates multiple (for example, three) instances of the same program, each running on a different CPU core. During the Run phase, all critical system calls are intercepted using hook technology. The call number and return value of each system call are recorded and stored in memory during program execution. The system call sequences of the three instances are compared at regular intervals. If the first program instance is inconsistent with both the second and third instances, an alarm is triggered, enabling real-time monitoring of hardware failures, software errors, or malicious attacks during program execution.
[0038] Specifically, in step S103 of this embodiment, running the target program in the running mode and generating multiple program instances with isolated resources and different processor cores for the target program in combination with the resources required by the target program include: executing the target program through the modified system execution function exec, and when the modified system execution function exec detects that the name of the executed target program is the specified name, calling the fork function fork once or multiple times, binding the first program instance (main execution instance, first instance) created by the system execution function exec executing the original target program to the large-core CPU of the dual-memory controller embedded platform to undertake the real business of the target program, and calling the fork function fork once or multiple times. Other program instances created by rk are bound to the small-core CPU of the dual-memory controller embedded platform as redundant verification program instances of the first program instance, and each program instance loads the configuration file, intermediate file, and output file path loaded at runtime according to the required resource list file. When creating the socket port, pipe name, and shared memory identifier, by adding a fixed port number with different step lengths to the socket port, appending identifiers with different suffixes to the pipe name, and adding parameters of different sizes to the shared memory identifier, the resource isolation of the socket port, pipe name, and shared memory identifier created by each program instance is achieved. Specifically, Figure 2 As shown,
[0039] In this embodiment, after executing the Test executable file, the modified system exec function detects that the executable file is Test, and calls fork twice additionally. When it is detected that the executable file is not Test, there is no need to call fork twice additionally. The fork function in the Exec function creates a Test execution instance, which is bound to the large core of RK3588, namely Core0, and its child process is also bound to Core0; the first additional fork called creates a Test_2 execution instance, which is bound to the small core of RK3588, namely Core2, and its child process is also bound to Core2; the first additional fork called creates a Test_3 execution instance, which is bound to the small core of RK3588, namely Core3, and its child process is also bound to Core3; among them, the Test execution instance undertakes the real business, and the Test_2 execution instance and the Test_3 execution instance are used for "double redundant verification", forming a three-mode architecture of "1 master core execution + 2 slave core verification", balancing performance and reliability. When the Test execution instance creates a socket, pipe, or shared memory, it can be executed directly. When the Test_2 execution instance creates a socket, the port number is incremented by 100. When creating a pipe, the name is suffixed with "_100". When creating shared memory, the first parameter is incremented by 100. When the Test_3 execution instance creates a socket, the port number is incremented by 200. When creating shared memory, the first parameter is incremented by 200. This ensures that multi-instance resources are completely isolated at the operating system level, avoiding program crashes caused by conflicts such as port occupation and pipe confusion.
[0040] In step S103 of this embodiment, the calling sequence or return value of any program instance being inconsistent with other program instances includes: the calling sequence or return value of the first program instance being inconsistent with other program instances, or the calling sequence or return value of other program instances other than the first program instance being inconsistent.
[0041] In step S103 of this embodiment, when monitoring and comparing the call sequence and return value of each program instance during the running process of the program instance, monitoring the call sequence and return value of each program instance means using the hook function Hook to intercept key system calls in real time to monitor the call sequence and return value of each program instance. Figure 2 As shown, this embodiment uses a hook function to intercept key system calls in real time to monitor the call sequence and return value of each program instance. It records the call number, return value, and execution time of each system call and stores this information in a shared memory buffer. The data in the shared memory buffer is compared every 5 seconds. If the call sequence or return value of any instance is inconsistent with other instances (i.e., a "three-module inconsistency" state), a UI pop-up alert is immediately triggered, indicating a potential hardware failure, software logic error, or security attack.
[0042] In summary, this embodiment proposes an embedded system reliability enhancement solution based on ARM's heterogeneous multi-processing (HMP). Leveraging the Rockchip RK3588 8G hardware platform, a lightweight triple-module redundant monitoring system is constructed to enhance software reliability. This embodiment combines the heterogeneous multi-core features of ARM HMP to create a lightweight triple-module redundant system. Through an "execution-verification-decision" model, this system addresses issues such as program execution reliability, resource conflict isolation, and real-time anomaly detection, thereby improving system reliability in embedded systems such as automotive, aircraft, and manufacturing. At the hardware level, a differentiated dual storage media (SSD + EMMC) and dual memory controller configuration are employed: Memory controller 1 is dedicated to the large core operating area to ensure high-performance computing efficiency, while controller 2 is allocated to the small core operating area to reduce redundant verification energy consumption. The system is deployed on SSDs to improve operation speed, and program data is stored in EMMCs to ensure persistence and stability. The technical implementation consists of two phases. In the first phase, a learning mode is used to collect dynamic resource information (including file paths, socket / pipe parameters, etc.) during program execution to form a baseline behavioral signature library. In the second phase, in production mode, the operating system automatically generates three instances during program execution, binding them to a large core (the main execution unit) and a small core (the redundant verification unit). Using hooking technology, the system intercepts key system calls in real time and records parameters such as call numbers and return values. The monitoring mechanism periodically compares the system call sequences of the three instances, triggering an alarm when the call behavior of the main execution instance (the first instance) and the two verification instances are inconsistent. This enables fine-grained detection of hardware faults, software logic errors, and malicious attacks. By leveraging heterogeneous multi-core division of labor, dynamic resource isolation, and system call-level comparison, this technology provides a low-cost, low-power anomaly detection solution for high-reliability embedded scenarios, effectively improving the fault tolerance and reliability of mission-critical systems. This embodiment is based on the ARM heterogeneous multi-core architecture and relies on the Rockchip RK3588 8G platform to enhance the reliability of lightweight triple-module redundant embedded systems. Through differentiated configuration of dual storage / memory controllers, dynamic resource collection during program execution, three-instance multi-core operation, and periodic comparison of system call sequences, it achieves fine-grained detection of hardware failures, software errors, and malicious attacks, thereby improving the fault tolerance and reliability of mission-critical systems.
[0043] In addition, this embodiment also provides an embedded system reliability enhancement system, including a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the embedded system reliability enhancement method.
[0044] In addition, this embodiment further provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the embedded system reliability enhancement method through a processor.
[0045] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the embedded system reliability enhancement method through a processor.
[0046] Those skilled in the art should understand that the technical solution provided by the present invention may be in the form of a method, a system, or a computer program product. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions described in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including the instruction device, which implements the function specified in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0047] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.
Claims
1. A method for enhancing the reliability of an embedded system, characterized in that: The steps include: S101, deploys a hardware platform that can differentiate memory controllers for different processor cores; S102, running the target program in a learning mode to obtain resources required by the target program; S103, running the target program in the run mode and generating multiple program instances for the target program with mutually isolated resources and different processor cores based on the resources required by the target program; monitoring and comparing the call sequences and return values of the various program instances during the running of the program instances; triggering an alarm if the call sequence or return value of any program instance is inconsistent with that of other program instances, thereby realizing the monitoring of hardware failures, software errors, or malicious attacks during the running of the target program; The method of running a target program in a running mode and generating multiple program instances with mutually isolated resources and different processor cores for the target program in combination with the resources required by the target program includes: executing the target program through a modified system execution function exec, and when the modified system execution function exec detects that the name of the executed target program is a specified name, calling the fork function once or multiple times, binding the first program instance created by the system execution function exec executing the original target program to the large-core CPU of the dual-memory controller embedded platform to undertake the real business of the target program, and binding other program instances created by the fork function to the small-core CPU of the dual-memory controller embedded platform to serve as redundant verification program instances of the first program instance, and each program instance loads the configuration file, intermediate file and output file path loaded at runtime according to the required resource list file, and when creating the socket port, pipe name, and shared memory identifier, by adding a port number with a fixed different step length to the socket port, appending identifiers with different suffixes to the pipe name, and adding parameters of different sizes to the shared memory identifier, so as to achieve resource isolation of the socket port, pipe name, and shared memory identifier created by each program instance.
2. The method for enhancing the reliability of an embedded system according to claim 1, wherein: Step S101 includes: S201, a dual-memory controller embedded platform that supports ARM heterogeneous multi-core architecture features; S202, installing an embedded operating system on a dual memory controller embedded platform; S203 , allocating different memory controllers to the large-core CPU and the small-core CPU of the embedded platform in the embedded operating system so that the memory data of the large-core CPU and the small-core CPU are independent of each other.
3. The method for enhancing the reliability of an embedded system according to claim 2, wherein: The dual memory controller embedded platform is a dual storage medium platform including a solid state drive (SSD) and an EMMC storage device. When installing an embedded operating system on the dual memory controller embedded platform in step S202, the embedded operating system is installed in the solid state drive (SSD) and the program data is configured to be stored in the EMMC storage device.
4. The method for enhancing the reliability of an embedded system according to claim 1, wherein: Step S102 includes: running the target program in the learning mode to obtain the resources required by the target program, including the configuration files, intermediate files and output file paths loaded when the target program is running, the socket ports, pipe names, and shared memory identifiers created by the target program, generating a resource list file required for the program instance for the target program, and copying the configuration files, intermediate files, and output file paths loaded when the target program Test is running to the EMMC storage device to generate multiple backups to ensure that each program instance can obtain the same configuration files, intermediate files, and output file paths loaded when running.
5. The method for enhancing the reliability of an embedded system according to claim 1, wherein: In step S103 , the calling sequence or return value of any program instance being inconsistent with other program instances includes: the calling sequence or return value of the first program instance being inconsistent with other program instances, or the calling sequence or return value of other program instances other than the first program instance being inconsistent.
6. The method for enhancing the reliability of an embedded system according to claim 1, wherein: In step S103, when monitoring and comparing the call sequence and return value of each program instance during the running process of the program instance, monitoring the call sequence and return value of each program instance means using the hook function Hook to intercept key system calls in real time to monitor the call sequence and return value of each program instance.
7. An embedded system reliability enhancement system, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the embedded system reliability enhancement method according to any one of claims 1 to 6.
8. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the embedded system reliability enhancement method according to any one of claims 1 to 6 through a processor.
9. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the embedded system reliability enhancement method according to any one of claims 1 to 6 through a processor.