A display method, an electronic device, and a readable storage medium

Abstract

This application relates to the display field and discloses a display method, an electronic device, and a readable storage medium. In this method, after an electronic device with a display screen detects a mode switching command in command mode, it can first determine the first moment when the first VSync signal of the video mode should be sent based on the refresh rate, and control the TE signal emitted by the display screen to switch to a high-level state at that first moment. Then, based on the detection of the TE signal switching to a high-level state at the first moment, it triggers the sending of the first VSync signal of the video mode at that first moment, indicating the start of the refresh cycle of the video mode. The sending time of the first VSync signal of the video mode can be equal to or later than the first moment. This ensures that the first VSync signal of the video mode is not sent prematurely, avoiding screen flicker caused by the difference in pixel illumination duration before and after the display mode switch due to the VSync signal being sent prematurely.

Description

Technical Field

[0001] This application relates to the field of displays, and more particularly to a display method, an electronic device, and a readable storage medium. Background Technology

[0002] Refresh rate indicates how many times a display refreshes a frame per second. For example, a refresh rate of 120Hz means the display refreshes 120 times per second, with a refresh cycle of 8.3ms (1000ms / 120 = 8.3ms). This means the display sends an external vertical sync (VSync) signal every 8.3ms to refresh one frame. To maintain consistent screen brightness, the transmitted signal (hereinafter referred to as the EM signal) is identical for each refresh cycle. The EM signal controls whether the pixels on the display are emitting light or turning off. For example, each 8.3ms refresh cycle may include three identical EM signals with a cycle of 2.7ms, and each EM signal corresponds to the same pixel illumination duration.

[0003] Furthermore, the display frame rate indicates the number of image frames rendered per second by the graphics processing unit (GPU). For example, a display frame rate of 120fps means that the GPU renders 120 frames of images per second, with a rendering cycle of 8.3ms. This means the GPU sends an internal vertical sync (VSync) signal every 8.3ms to indicate the completion of rendering one frame. It can be understood that the refresh rate and display frame rate are usually synchronized; that is, the external VSync signal sent by the display and the internal VSync signal sent by the GPU must be synchronized to ensure that each frame of image is displayed synchronously on the screen after rendering, thus providing a smoother viewing experience.

[0004] However, when the display switches from command mode (the display mode used to display static images or text) to video mode (the display mode used to display dynamic video) based on a mode switching command, the rendering speed of the image frames to be displayed in video mode is faster. This causes the start time of the first internal VSync signal in video mode to be earlier, meaning the first refresh cycle of video mode is earlier. Consequently, the end time of the last refresh cycle in command mode, which precedes the first refresh cycle of video mode, is also earlier. This results in differences between adjacent refresh cycles before and after the switch, and consequently, differences in pixel illumination time related to the refresh cycle, leading to screen flickering. Summary of the Invention

[0005] To address the aforementioned problems, this application provides a display method, an electronic device, and a readable storage medium.

[0006] In a first aspect, this application provides a display method applied to an electronic device, the electronic device including a display screen. The method includes: detecting a mode switching command during a first refresh cycle in a command mode, controlling a first TE signal to switch from a low level to a high level at a first moment, wherein the first TE signal is used to indicate that an image frame within the first refresh cycle has been displayed, the first moment is the end moment of the first refresh cycle, and the first moment is the start moment of a second refresh cycle corresponding to a video mode, the first moment being related to the screen refresh rate of the display screen; based on the first TE signal, sending a vertical synchronization signal at the first moment, the display screen switching from the command mode to the video mode, and displaying an image frame corresponding to the video mode during the second refresh cycle of the corresponding video mode.

[0007] It is understood that the first refresh cycle of the command mode can refer to the one mentioned in the embodiments of this application. Figure 7 The time intervals t0 to t1 are shown. The first time interval may refer to the time interval mentioned in the embodiments of this application. Figure 7 The time t1 shown. The second refresh period corresponding to the video mode can refer to the one mentioned in the embodiments of this application. Figure 7 The time intervals t1 to t2 are shown. Sending the vertical synchronization signal at the first time interval can refer to the internal Vsync signal sent at the first time interval mentioned in the embodiments of this application. The image frame corresponding to the video mode can refer to the one mentioned in the embodiments of this application. Figure 7 The image frame shown is N+1.

[0008] By using the above method, the first moment when the first VSync signal corresponding to the video mode should be sent is determined. This first moment is also the moment when the first refresh cycle of the command mode ends. Furthermore, the first TE signal emitted by the control display switches to a high-level state at this first moment, and the display can only switch from command mode to video mode at this first moment. This avoids the first VSync signal of the video mode being sent prematurely, thus preventing screen flickering caused by the difference in pixel illumination duration before and after the display mode switch due to the VSync signal being sent prematurely.

[0009] In one possible implementation of the first aspect above, before the display of the image frame corresponding to the video mode begins during the second refresh cycle of the corresponding video mode, the method further includes: switching the first TE signal from a high-level state to a low-level state.

[0010] It is understood that the second refresh cycle corresponding to the video mode may refer to the one mentioned in the embodiments of this application. Figure 7 The time intervals t1 to t2 shown correspond to the image frames displayed in the second refresh cycle of the video mode, which can refer to the frames mentioned in the embodiments of this application. Figure 7 The image frame shown is N+1.

[0011] Based on this, it is possible to control the situation at the first moment (e.g.) Figure 7 The first TE signal, which switches to a high level at time t1 (as shown in the diagram), is in... Figure 7 Before the image frame N+1 shown in the figure begins to be displayed, it switches from a high level state to a low level state.

[0012] In one possible implementation of the first aspect described above, the method further includes: detecting that a first buffer period of the command mode begins at a first time and ends at a second time, the first buffer period being less than or equal to a first refresh period, and the first refresh period being N times the first buffer period, where N ∈ positive integers; detecting that a second refresh period of the command mode begins at a second time and ends at a third time, corresponding to the detection of a mode switching command within the second refresh period of the command mode, and controlling a second TE signal to switch from a low level state to a high level state at the third time; wherein the second TE signal is used to indicate that the image frame within the second refresh period of the command mode has been displayed, the third time is the end time of the second refresh period of the command mode, and the third time is the start time of the third refresh period of the corresponding video mode; based on the second TE signal, sending a vertical synchronization signal at the third time, the display screen switching from the command mode to the video mode, and displaying the image frame corresponding to the video mode within the third refresh period of the corresponding video mode.

[0013] It is understood that the first refresh cycle may refer to the one mentioned in the embodiments of this application. Figure 8 The first buffer period, from time t0 to time t1, can refer to the period mentioned in the embodiments of this application. Figure 8 The time interval shown is from time t1 to time t1+2.7ms. The second time interval can refer to... Figure 8 The time shown as t1+2.7ms, the third time can refer to... Figure 8 The time interval shown is 2*t1+2.7ms. The second refresh cycle of the command mode can refer to the one mentioned in the embodiments of this application. Figure 8 The interval from t1+2.7ms to 2*t1+2.7ms is shown. This corresponds to the third refresh cycle of the video mode, as mentioned in the embodiments of this application. Figure 8 The time intervals shown are from 2*t1+2.7ms to 3*t1+2.7ms. The image frames corresponding to the video mode displayed within the third refresh cycle of the corresponding video mode can refer to those mentioned in the embodiments of this application. Figure 8 The image frame shown is N+2. Furthermore, the first refresh cycle is N times the first buffer cycle, where N ∈ positive integers, N = 1, 2, 3, etc., and is not limited here.

[0014] Based on this, by reserving a certain buffer time (i.e., the first buffer period) between adjacent refresh cycles in command mode, it is ensured that all commands have been processed and the system is fully ready to receive video data before switching to video mode, thus avoiding image frame loss or display errors when switching from command mode to video mode.

[0015] It is understood that in some other embodiments of this application, when switching from command mode to video mode, a certain buffer time can be reserved between adjacent refresh cycles in command mode. Furthermore, in the last refresh cycle of command mode (e.g., Figure 11 After the time interval from t1+2.7ms to 2*t1+2.7ms is completed, the image frame of the last refresh cycle of the command mode can be displayed again (e.g., ...). Figure 11 After the image frames (N+2) between 2*t1+2.7ms and 3*t1+2.7ms shown, the system switches to video mode. This process repeats, providing additional time to correct timing and ensure the stability and smoothness of the switching process.

[0016] In one possible implementation of the first aspect above, before displaying the image frame corresponding to the video mode within the third refresh cycle of the corresponding video mode, the method further includes: switching the second TE signal from a high-level state to a low-level state.

[0017] It is understood that the third refresh cycle corresponding to the video mode can refer to the one mentioned in the embodiments of this application. Figure 8 The intervals from 2*t1+2.7ms to 3*t1+2.7ms shown in the diagram represent the image frames displayed in the third refresh cycle of the corresponding video mode. These frames can refer to those mentioned in the embodiments of this application. Figure 8 The image frame shown is N+2.

[0018] Based on this, it can be controlled at the third moment (e.g.) Figure 8 The second TE signal, which switches to a high level at time 2*t1+2.7ms (as shown), Figure 8 Before the image frame N+2 shown in the figure begins to be displayed, it switches from a high level state to a low level state.

[0019] In one possible implementation of the first aspect above, the method further includes: detecting a first buffer period corresponding to the detected command mode starting at a first moment and ending at a second moment; detecting a second buffer period corresponding to the detected command mode starting at a first moment and ending at a fourth moment, the second buffer period being less than or equal to the first refresh period, and the first refresh period being N times the second buffer period, where N ∈ positive integers; detecting a mode switching command within the second buffer period; detecting the end of the second buffer period at the fourth moment, controlling a third TE signal to switch from a low level state to a high level state at the fourth moment, wherein the fourth moment is the end moment of the second buffer period of the command mode and the start moment of the second refresh period corresponding to the video mode; based on the third TE signal, sending a vertical synchronization signal at the fourth moment, the display screen switching from the command mode to the video mode, and displaying the image frame corresponding to the video mode within the second refresh period of the corresponding video mode.

[0020] It is understood that the second buffer cycle of the command mode can refer to the one mentioned in the embodiments of this application. Figure 9 The time interval shown is from time t1 to time t1+5.4ms. The fourth time interval may refer to the time interval mentioned in the embodiments of this application. Figure 9 The time interval t1+5.4ms shown. The second refresh cycle corresponding to the video mode can refer to the one mentioned in the embodiments of this application. Figure 9 The time interval from t1+5.4ms to 2*t1+5.4ms is shown. The image frames corresponding to the video mode displayed within the second refresh cycle of the corresponding video mode can refer to those mentioned in the embodiments of this application. Figure 9 The image frame shown is N+1.

[0021] Based on this, when switching from command mode to video mode, a buffer time can be reserved between adjacent refresh cycles in command mode, and the mode switching command in command mode can be issued during the buffer time reserved in the last refresh cycle of command mode.

[0022] In one possible implementation of the first aspect above, before displaying the image frame corresponding to the video mode within the second refresh cycle of the corresponding video mode, the method further includes: switching the third TE signal from a high-level state to a low-level state.

[0023] Based on this, it can be controlled at the fourth time (e.g.) Figure 9 The third TE signal, which switches to a high level at time t1+5.4ms, is shown in the figure. Figure 9 Before the image frame N+1 shown in the figure begins to be displayed, it switches from a high level state to a low level state.

[0024] In one possible implementation of the first aspect described above, the content displayed in command mode includes static or animated images, and the content displayed in video mode includes video.

[0025] In one possible implementation of the first aspect above, the method further includes: detecting a mode switching command during a first refresh cycle of the command mode, controlling the first TE signal to switch from a low level state to a high level state at a first moment; detecting that a second refresh cycle of the command mode starts at a first moment and ends at a fifth moment, controlling the first TE signal to switch from a low level state to a high level state at the fifth moment; and controlling the display screen to switch from the command mode to the video mode at the fifth moment based on the first TE signal.

[0026] It is understood that the first refresh cycle of the command mode can refer to the one mentioned in the embodiments of this application. Figure 10 The time intervals from t0 to t1 shown, where the first time interval can refer to the time interval mentioned in the embodiments of this application. Figure 10 The time t1 shown. The second refresh cycle of the command mode can refer to the one mentioned in the embodiments of this application. Figure 10 The time intervals t1 to t2 shown, with the fifth time referring to the time mentioned in the embodiments of this application. Figure 10 The time shown is t2.

[0027] Therefore, when switching from command mode to video mode, the refresh cycle in the last refresh cycle of command mode is as follows: Figure 10 After the second refresh cycle (from time t1 to time t2) of the command mode is completed, the image frame from the last refresh cycle of the command mode can be displayed again before switching to video mode. In this way, assuming an error is detected during the switching process, displaying a single image frame again provides additional time to correct the timing, ensuring the stability and continuity of the switching process.

[0028] In a second aspect, embodiments of this application provide an electronic device, including a memory for storing instructions and a processor for executing the instructions to implement the display method provided by the first aspect and various possible implementations of the first aspect.

[0029] Thirdly, embodiments of this application provide a readable storage medium storing instructions that, when executed on a terminal device, cause the electronic device to perform the display methods provided by the first aspect and various possible implementations of the first aspect.

[0030] Fourthly, embodiments of this application also provide a computer program product, including a computer program / instruction that, when executed by a processor, implements the display method provided by the first aspect and various possible implementations of the first aspect.

[0031] The beneficial effects of the second to fourth aspects mentioned above can be referred to the relevant descriptions in the first aspect and various possible implementations of the first aspect, which will not be repeated here. Attached Figure Description

[0032] Figure 1 (a) shows a schematic diagram of a mobile phone 10 displaying a static image interface 101 according to the method provided in the embodiments of this application;

[0033] Figure 1 (b) shows a schematic diagram of a mobile phone 10 displaying a video interface 102 according to the method provided in the embodiments of this application;

[0034] Figure 2A (a) illustrates a control process diagram corresponding to displaying a static screen in command mode, according to the method provided in the embodiments of this application.

[0035] Figure 2A (b) illustrates a control process diagram for displaying video images in video mode according to the method provided in the embodiments of this application.

[0036] Figure 2B According to the method provided in the embodiments of this application, a schematic diagram of a control process for displaying dynamic images in command mode is shown.

[0037] Figure 3 (a) illustrates a timing diagram of receiving a mode switching command in command mode according to the method provided in the embodiments of this application.

[0038] Figure 3 (b) illustrates another timing diagram of receiving a mode switching command in command mode according to the method provided in the embodiments of this application;

[0039] Figure 4 A timing diagram illustrating the switching from command mode to video mode is shown according to the method provided in the embodiments of this application.

[0040] Figure 5 A schematic diagram of a graphics processing system 00 for an electronic device is shown according to the method provided in the embodiments of this application;

[0041] Figure 6 A flowchart illustrating a display method is shown based on the method provided in the embodiments of this application.

[0042] Figure 7 According to the method provided in the embodiments of this application, a timing diagram 01 for switching from command mode to video mode is shown;

[0043] Figure 8 According to the method provided in the embodiments of this application, a timing diagram 02 is shown for switching from command mode to video mode;

[0044] Figure 9 According to the method provided in the embodiments of this application, a timing diagram 03 is shown for switching from command mode to video mode;

[0045] Figure 10 According to the method provided in the embodiments of this application, a timing diagram 04 is shown for switching from command mode to video mode;

[0046] Figure 11 According to the method provided in the embodiments of this application, a timing diagram 05 is shown for switching from command mode to video mode;

[0047] Figure 12 According to the method provided in the embodiments of this application, a timing diagram 06 is shown for switching from command mode to video mode;

[0048] Figure 13 According to the method provided in the embodiments of this application, a timing diagram 07 is shown for switching from video mode to command mode;

[0049] Figure 14 A schematic diagram of the structure of a terminal device 100 is shown according to the method provided in the embodiments of this application. Detailed Implementation

[0050] The illustrative embodiments of this application include, but are not limited to, a display method, a terminal device, and a readable storage medium.

[0051] It is understood that electronic devices applicable to this application may include mobile phones with displays, smart screens, wearable devices, tablets, laptops, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, terminal devices in industrial control, terminal devices in self-driving, terminal devices in remote medical surgery, terminal devices in smart grids, terminal devices in transportation safety, terminal devices in smart cities, terminal devices in smart homes, etc.

[0052] In a display system, the GPU sends an internal VSync signal to indicate that the image frame to be displayed has been rendered and is ready for display, while the display sends an external VSync signal to indicate that the display can begin displaying the image frame. When displaying image frames corresponding to static scenes, the display can begin displaying the image frame each time based on the external VSync signal. When displaying image frames corresponding to video, the GPU sends the rendered image frame to the display each time based on the internal VSync signal, and then the display shows the image frame based on the external VSync signal. Since the screen refresh rate and display frame rate are the same, the external VSync signal remains synchronized and is sent simultaneously.

[0053] Figure 1 A schematic diagram of a mode switching scenario is shown. For example... Figure 1 The static image display scene shown in (a) shows the static image interface 101 displayed on the mobile phone 10; as shown in (a). Figure 1 As shown in (b) of the diagram, mobile phone 10 displays video interface 102. When the display screen of mobile phone 10 switches from displaying static image interface 101 to displaying video interface 102, in order for mobile phone 10 to display the image frame corresponding to video interface 102, it needs to first send the first internal VSync signal in video mode through the GPU to indicate that the image frame has been rendered. However, if the GPU renders faster to meet the needs of video playback, the GPU may send the first internal VSync signal in video mode in advance. Based on this, in order for the display screen to synchronously display the image frame corresponding to the rendered video interface 102, it also needs to send the first external VSync signal in video mode in advance.

[0054] Thus, in command mode, the refresh cycle of the static image interface 101 is shorter than that of the video interface 102 in video mode. Furthermore, in command mode, the illumination duration of the relevant image frames displayed on the screen for the static image interface 101 is shorter than that of the relevant image frames displayed on the screen for the video interface 102 in video mode. This means the display brightness of the static image interface 101 differs from that of the video interface 102, causing screen flickering. Figure 1 The flashing line 1010 in Figure (a).

[0055] For ease of understanding, Figure 2A The diagram illustrates the control process of the control display screen and related image frames corresponding to the command mode and video mode.

[0056] like Figure 2AAs shown in (a), the control process for displaying a static image in command mode includes: After the GPU renders the image frame corresponding to the static image, it can store it in graphics random access memory (GRAM) for later display. When the display sends an external VSync signal according to the screen refresh rate, the display can directly retrieve the rendered image frame from the GRAM and display the image frame when the external VSync signal is sent, without waiting for the GPU to finish rendering and storing it in the GRAM before retrieving the image frame.

[0057] like Figure 2A As shown in (b), the control process for displaying video in video mode includes: after the GPU finishes rendering the image frame, the GPU sends the rendered image frame to the display screen for display based on the internal VSync signal sent according to the display frame rate. The display screen can then display the rendered image frame according to the external VSync signal synchronized with the internal VSync signal.

[0058] It's understandable that dynamic visuals can be displayed in the command mode described above. (See reference) Figure 2B The diagram shown illustrates the control process for displaying dynamic images in command mode. After the GPU completes the real-time rendering of the image frame, it sends the rendered image frame to the GRAM for storage based on the internal VSync signal sent according to the display frame rate. The display screen then retrieves the rendered image frame from the GRAM and displays it based on the external VSync signal synchronized with the internal VSync signal.

[0059] Regarding the above Figure 2A The timing relationship between the internal VSync signal and the external VSync signal in the control process shown below is explained in conjunction with... Figure 3 Please provide an explanation. (Reference) Figure 3 The diagram (a) shows the timing of receiving a mode switching command in command mode. When the display receives a mode switching command in command mode, it can send a TE signal after the image frame in command mode has been displayed. This TE signal indicates that the GPU's current display is ready to start displaying the next frame. The GPU can then send an internal VSync signal at any time when the TE signal is high to send the rendered new frame to the display for display. Figure 3As shown in (a), the refresh cycle in command mode is [t0, t1]. The TE signal is high in the interval [t03, t1], where t03 belongs to [t0, t1]. The GPU sends an internal VSync signal at time t1 when the TE signal is high. Time t1 is precisely the time when the internal VSync signal should be sent to indicate the start of the next refresh cycle based on the display frame rate. Thus, the display synchronizes the external and internal VSync signals at time t1 and displays the image frame to be displayed at time t1.

[0060] Continue to refer to Figure 3 In (a) of the diagram, if the VSync signal should be sent at time t1 corresponding to the display frame rate or refresh rate, then the first internal VSync signal and the first external VSync signal of the video mode are sent at time t1. Based on this, the refresh cycle before and after the display mode switch is 8.3ms, and each refresh cycle includes three 2.7ms EM signals. That is, the pixel emission time is the same before and after the display mode switch, which indicates that the display brightness remains unchanged.

[0061] It is understandable that a low level of each EM signal can represent the pixel's illuminated state, and a high level of each EM signal can represent the pixel's off state; this is not a limitation here. Therefore, Figure 3 In the refresh cycle of command mode and video mode (a) in the example, the complete cycle of each EM signal is 2.7ms, which means that the duration of each EM signal at low level is the same.

[0062] However, as Figure 3 (b) shows another timing diagram of receiving a mode switching command in command mode. When the display receives the mode switching command in command mode, it sends a TE signal after the image frame in command mode has been displayed. The TE signal is high at time t03. The GPU can send the internal VSync signal at any time when the TE signal is high. For example, the GPU sends the internal VSync signal at time t05 when the TE signal is high, which is earlier than... Figure 3 In (a), based on the display frame rate, at time t1 when the internal VSync signal should be sent, the GPU sends the image frame to be displayed to the display screen at time t05 according to the internal VSync signal sent at time t05. In order to synchronize with the internal VSync signal, the display screen also sends the external VSync signal in advance at time t05 and displays the image frame to be displayed.

[0063] pass Figure 3As can be seen from (b), the time when the VSync signal should be sent based on the display frame rate or refresh rate is time t1. However, the time interval corresponding to the high-level state of the TE signal sent in command mode is before time t1. If the current GPU rendering speed is fast, the GPU can send the internal VSync signal before time t1 after completing the fast rendering. For example, the GPU sends the internal VSync signal at time t05 and sends the image frame to be displayed to the display screen. Consequently, the display screen also sends the external VSync signal at time t05 to display the image frame in advance.

[0064] Continue to refer to Figure 3 In (b), the first internal VSync signal and the first external VSync signal in video mode are emitted at time t05, which is earlier than the time t1 when the VSync signal should be emitted based on the display frame rate or refresh rate. Therefore, the last refresh cycle in command mode is reduced and is less than the first refresh cycle in video mode (8.3ms). Consequently, the pixel emission duration corresponding to the last EM signal in the last refresh cycle of command mode is less than the pixel emission duration corresponding to the first EM signal in video mode.

[0065] As mentioned earlier, when the display switches from command mode to video mode based on a mode switching command, the rendering speed of the image frames to be displayed in video mode is faster. This causes the start time of the first internal VSync signal in video mode to be earlier, meaning the first refresh cycle of video mode is earlier. Consequently, the end time of the last refresh cycle in command mode, which precedes the first refresh cycle of video mode, is also earlier. This results in differences between adjacent refresh cycles before and after the switch, and consequently, differences in pixel emission times related to the refresh cycle, leading to screen flickering.

[0066] Therefore, to solve the above problems, this application provides a display method. In this method, after an electronic device with a display screen detects a mode switching command in command mode, it can first determine the time when the first internal VSync signal of the video mode should be sent as the first moment based on the matching display frame rate (e.g., 120fps) or screen refresh rate (e.g., 60Hz), and control the TE signal emitted by the display screen to switch to a high-level state at the first moment. This first moment is later than the time when the image frame is displayed in command mode. Furthermore, the GPU of the electronic device can trigger the sending of the first internal VSync signal of the video mode at the first moment based on the detection of the TE signal switching to a high-level state at the first moment, indicating the start of the refresh cycle of the video mode. The sending time of the first internal VSync signal of the video mode can be equal to or later than the first moment. Thus, if the first external VSync signal of the video mode is sent synchronously with the first internal VSync signal, it can be controlled so that the first external VSync signal of the video mode will not be sent before the first moment.

[0067] For example, when switching from command mode to video mode, assuming the last refresh cycle in command mode starts at 0ms and ends at 8.3ms based on the screen refresh rate, and the first refresh cycle in video mode starts at 8.3ms, if the image frame in command mode completes display at 6ms, then the control TE signal will not be issued at the earlier 6ms but at 8.3ms (i.e., the first moment), and the first internal VSync signal in video mode will also be issued at 8.3ms, and consequently, the first external VSync signal in video mode will also be issued at 8.3ms. Based on this, the first internal VSync signal and the first external VSync signal in video mode will not be issued earlier than the first moment (e.g., 6ms as mentioned above). Thus, the pixel illumination duration corresponding to the last EM signal in the last refresh cycle of command mode can remain the same as the pixel illumination duration corresponding to the first EM signal in video mode, i.e., there will be no screen flickering.

[0068] For example, suppose the last refresh cycle in command mode starts at 0ms and ends at 8.3ms. However, if the image frame in command mode is not displayed at the first moment (8.3ms) but needs to be displayed at (8.3ms + 2.7ms), the TE signal can be controlled to be issued later than the first moment (8.3ms), that is, at (8.3ms + 2.7ms). Based on this, the first internal VSync signal and the first external VSync signal in video mode will not be issued before (8.3ms + 2.7ms). In this way, the pixel illumination duration corresponding to the last EM signal in the last refresh cycle of command mode can remain the same as the pixel illumination duration corresponding to the first EM signal in video mode, that is, there will be no screen flickering.

[0069] The display method provided in this application embodiment can achieve a smooth transition of the electronic device's display screen from command mode to video mode, avoiding screen flickering.

[0070] It is understandable that the first VSync signal (including internal and external VSync signals) in video mode can be sent at the exact moment corresponding to the matching display frame rate or refresh rate, or later than the exact moment it should be sent. In other words, the first VSync signal in video mode will not be sent before the exact moment it should be sent. Furthermore, the pixel emission duration corresponding to the last EM signal in command mode is the same as the pixel emission duration corresponding to the first EM signal in video mode. This means the display brightness will not change before and after mode switching, thus preventing screen flickering.

[0071] For example, Figure 4 Based on the display method provided in the embodiments of this application, a timing diagram is shown when switching from command mode to video mode.

[0072] refer to Figure 4 Upon receiving a mode switching command in command mode, the system can determine, based on the matching display frame rate or refresh rate, that the first internal VSync signal in video mode should be sent at time t1. The display will then send the TE signal at time t1, as described above. Figure 3 In (b), the TE signal is initiated at time t05, which is different from the previous case. Furthermore, in video mode, the rising edge of the first internal VSync signal and the TE signal are synchronized at time t1, so the first external VSync signal in video mode is also initiated at time t1. That is, the first internal VSync signal and the first external VSync signal in video mode are synchronized and are both issued at time t1, which corresponds to when the VSync signal should be sent based on the display frame rate or refresh rate.

[0073] Based on this, before and after the display mode switch, the pixel emission duration corresponding to each EM signal in the refresh cycle of the command mode and video mode is the same, ensuring that the display brightness of the screen remains unchanged before and after the display mode switch, and avoiding screen flickering.

[0074] To facilitate understanding of the methods provided in the embodiments of this application, Figure 5 A schematic diagram of the graphics processing system of an electronic device is shown.

[0075] like Figure 5 As shown, the graphics processing system 00 of an electronic device may include a system on a chip (SoC), a display interface integrated circuit (DDIC), and a display panel, etc.

[0076] Specifically, a System-on-a-Chip (SoC) is an integrated circuit that may include an application processor (AP). The AP may integrate a central processing unit (CPU) and a graphics processing unit (GPU). The CPU handles application-related tasks, while the GPU handles graphics rendering tasks. Furthermore, the GPU can be integrated into the SoC or exist as a separate chip; this is not limited here. In the embodiments of this application, corresponding to command mode, the GPU can be used to send rendered image frames to GRAM for storage; corresponding to video mode, the GPU can send rendered image frames to the panel for display.

[0077] It is understandable that the AP may also include a display serial interface (DSI). Figure 5 (Not shown in the image), DSI is an interface used to connect the system on chip (SoC) and the display panel.

[0078] A DDIC is an integrated circuit directly connected to a display screen, responsible for processing and driving the display content. A DDIC may include GRAM, indicating that it possesses certain graphics processing capabilities and can store and process display data. In this embodiment, the display screen can send an external VSync signal based on the DDIC to indicate that it can begin displaying a new image frame. Furthermore, GRAM is memory used to store image data and can be called a frame buffer. GRAM stores image frames rendered by the GPU, allowing the panel to quickly access and display the images.

[0079] A panel refers to the physical panel that constitutes a display screen, including the screen that actually displays the image and the associated driving electronic components. In some embodiments, the panel can employ various technologies, such as liquid crystal display (LCD), organic light-emitting diode (OLED), etc., and is not limited thereto. In the embodiments of this application, the display screen can display image frames based on the panel.

[0080] In some embodiments of this application, ideally, the switching of the display mode from command mode to video mode can be instantaneous, that is, after the last refresh cycle of command mode ends, video signal reception begins and the display switches to video mode.

[0081] To facilitate understanding of the methods provided in the embodiments of this application, Figure 6 A flowchart illustrating a display method provided in this application is shown. It can be understood that... Figure 6 The execution entity in the flowchart shown can be the aforementioned mobile phone 10.

[0082] S601: A mode switching command was detected during the first refresh cycle of the command mode.

[0083] In some embodiments of this application, it is assumed that a mode switching command is detected during the first refresh cycle of the command mode, for example, in the above-mentioned Figure 4 A mode switching command was detected within the refresh cycle (t0, t1) of the command mode.

[0084] It can be understood that the mode switching command can be "set_dsi_mode param=1", where "set_dsi_mode" is a command used to configure the controller mode of the DSI, and "param=1" represents a specific operating mode, such as "video mode". Therefore, "set_dsi_mode param=1" can indicate switching the display mode from command mode to video mode. Furthermore, in this embodiment, using "param=1" to represent video mode is merely an illustrative example; in other embodiments, "param=2" can also represent video mode, which is not limited here.

[0085] S602: Based on the refresh rate, calculate the first moment of the start of the next refresh cycle, and control the first TE signal to switch from a low level to a high level at the first moment.

[0086] In some embodiments of this application, the first moment of the start of the next refresh cycle can be calculated based on the refresh rate, and the first TE signal can be controlled to switch from a low level state to a high level state at that first moment. For example, the above Figure 4 In the calculation, the first time point is determined to be time t1. Then, at time t1, the first TE signal can be controlled to switch from a low level to a high level, indicating that the image frame in the current command mode has been displayed. Furthermore, after detecting the first TE signal at time t1, an internal VSync signal can be synchronously emitted at time t1 to switch from command mode to video mode.

[0087] S603: Based on the first TE signal, it sends a vertical synchronization signal at the first moment to switch from command mode to video mode.

[0088] In some embodiments of this application, after detecting the first TE signal at time t1, an internal VSync signal and an external VSync signal can be simultaneously emitted at time t1. Corresponding to the internal VSync signal at time t1, the image frame to be displayed is sent to the display screen, and corresponding to the external VSync signal at time t1, the image frame to be displayed is displayed on the display screen. At this time, the display mode corresponding to the display screen is video mode.

[0089] The following is combined Figures 7 to 9 The timing diagrams shown illustrate the corresponding scenarios and processes.

[0090] It is understood that the processor's display frame rate of 120fps, the display refresh rate of 120Hz, and the corresponding refresh cycle of 8.3ms in the example embodiments of this application are merely illustrative examples. In other embodiments, the display frame rate, refresh rate, and refresh cycle of the display screen may be other values, which are not limited here.

[0091] As an example, Figure 7 A timing diagram 01 is shown for switching from command mode to video mode.

[0092] like Figure 7As shown in the timing diagram 01, in command mode, based on the external VSync signal at time t0, the refresh cycle of command mode is 8.3ms from time t0 to time t1, during which the display starts displaying image frame N output by the processor. When the display finishes displaying image frame N and receives the mode switching command, the display prepares to send a TE signal to indicate that the processor has finished displaying image frame N. In command mode, the display typically switches the TE signal from low to high at time t01, when the last image frame N in command mode has finished displaying. However, considering the need to switch the display from command mode to video mode, to avoid premature display of the new image frame corresponding to video mode (e.g., image frame N+1), the display control does not switch the TE signal from low to high at time t01. Instead, it calculates the time when the next external VSync signal should be sent based on the refresh rate, i.e., time t1, and controls the TE signal to switch from low to high at time t1.

[0093] Furthermore, after the processor detects that the TE signal switches from low to high at time t1, the processor sends the first internal VSync signal of the video mode at time t1, the display switches to video mode, and the processor prepares to send the first image frame of the video mode, i.e., image frame N+1, based on the first internal VSync signal.

[0094] It is understandable that after the first internal VSync signal is issued, there is a vertical backporch (VBP). VBP is a time period during which the processor prepares to output image frame N+1 and the display prepares to receive image frame N+1. When VBP ends, image frame N+1 is output to the display for display. It is also understandable that the TE signal can change from high to low during VBP. Furthermore, after the first internal VSync signal based on video mode is issued at time t1, the display can synchronously send the first external VSync signal of video mode at time t1, and the display shows image frame N+1. After switching to video mode, the second internal VSync signal and the second external VSync signal of video mode are issued at time t2, and the display then shows image frame N+2.

[0095] based on Figure 7As shown in the timing diagram 01 illustrating the mode switching, on one hand, the last refresh cycle of the display in the command mode before switching display modes is 8.3ms, and the three EM signals in this refresh cycle (t0, t1) each have the same period of 2.7ms. A low level for each EM signal indicates it is lit, and the EM duty cycle (EM duty) of each EM signal is the same. EM duty refers to the duration the EM signal is lit within the refresh cycle, i.e., the pixel illumination duration. On the other hand, the first refresh cycle (t1, t2) of the display in the video mode after switching is 8.3ms, and the three EM signals in this refresh cycle (t1, t2) each have the same period of 2.7ms, and the EM duty cycle (EM duty) of each EM signal is the same. Therefore, the EM duty of the last EM signal in the command mode and the EM duty of the first EM signal in the video mode are also the same. That is, before and after the display mode switching, the pixel illumination duration of the display is the same, and the corresponding display brightness is the same, meaning the display will not flicker.

[0096] It is understandable that, corresponding to the above Figure 7 In the VBP (Vertical Front Pole), after an image frame (e.g., image frame N+1) has been displayed, there is a corresponding vertical front porch (VFP). The VFP is a time interval, a short gap before the display prepares to receive and display the next image frame (e.g., image frame N+2). This time interval can be used to ensure the smooth transmission and processing of image frame N+1.

[0097] It's understandable that the mode switching command could be "set_dsi_mode param=1", where "set_dsi_mode" is a command used to configure the DSI controller mode, and "param=1" represents a specific operating mode, such as "video mode". Therefore, "set_dsi_mode param=1" can switch the display mode from command mode to video mode.

[0098] It is understood that the use of "param=1" to represent the video mode in this embodiment is merely an illustrative example. In other embodiments, "param=2" may also be used to represent the video mode, which is not limited here.

[0099] In some embodiments of this application, a certain buffer time can be reserved between adjacent refresh cycles in command mode to ensure that all commands have been processed and the system is fully ready to receive video data before switching to video mode, thus avoiding image frame loss or display errors during mode switching. Furthermore, the reserved buffer time can be a multiple of the refresh cycle; for example, if the refresh cycle is 8.3ms, the reserved buffer time could be 2.7ms, etc. That is, the refresh cycle can be N times the buffer cycle, where N ∈ positive integers, N = 1, 2, 3, etc., without limitation.

[0100] As another example Figure 8 Another timing diagram 02 shows the switching from command mode to video mode.

[0101] like Figure 8 As shown in the timing diagram 02, in command mode, based on the external VSync signal at time t0, the refresh cycle of command mode is 8.3ms from time t0 to time t1, during which the display starts showing image frame N output by the processor. When the display finishes displaying image frame N and is ready to display image frame N+1 in command mode, a certain buffer time is reserved, for example, 2.7ms based on the refresh cycle of 8.3ms, i.e., the time interval corresponding to the buffer time is (t1, t1+2.7ms). After the buffer time ends, the external VSync signal of command mode is sent at time (t1+2.7ms) so that the display can display image frame N+1. When the display finishes displaying image frame N+1, based on the display receiving the mode switching command, the display is ready to send a TE signal to indicate that the processor has finished displaying image frame N+1. In command mode, the display usually switches the TE signal from low to high at time t11, when the last image frame N+1 in command mode is displayed. However, considering the need to switch the display from command mode to video mode, to prevent the new image frame corresponding to video mode (e.g., image frame N+2) from being displayed prematurely, the display control does not switch the TE signal from low to high at time t11. Instead, it calculates the time when the next external VSync signal should be emitted based on the refresh rate, plus the buffer time, i.e., (2*t1+2.7ms). The TE signal is then controlled to switch from low to high at (2*t1+2.7ms).

[0102] Furthermore, after the processor detects that the TE signal switches from low to high at time (2*t1+2.7ms), the processor sends the first internal VSync signal of video mode at time (2*t1+2.7ms), the display switches to video mode, and the processor prepares to send the first image frame of video mode, i.e., image frame N+2, based on the first internal VSync signal.

[0103] based on Figure 8 As shown in the mode switching timing diagram 02, on the one hand, in the command mode before switching display modes, each refresh cycle of the display is 8.3ms, and the reserved buffer time is a multiple of the refresh cycle. That is, in the command mode, the period of each EM signal is the same, 2.7ms, and the low level of each EM signal indicates that it is lit, and the EM duty cycle of each EM signal is the same. On the other hand, in the video mode after switching, the first refresh cycle (2*t1+2.7ms, 3*t1+2.7ms) of the display is 8.3ms, and the period of each EM signal in this refresh cycle (2*t1+2.7ms, 3*t1+2.7ms) is the same, 2.7ms, and the EM duty cycle of each EM signal is the same. Therefore, the EM duty of the last EM signal in the command mode and the EM duty of the first EM signal in the video mode are also the same. That is, before and after the switch, the pixel illumination time of the display is the same, and the corresponding display brightness is the same, so the display will not flicker.

[0104] In some embodiments of this application, when switching from command mode to video mode, a buffer time can be reserved between adjacent refresh cycles in command mode, and the mode switching command in command mode can be issued during the buffer time reserved in the last refresh cycle of command mode.

[0105] As another example Figure 9 This illustrates yet another timing diagram for switching from command mode to video mode.

[0106] like Figure 9 As shown in the timing diagram 03, in command mode, based on the external VSync signal at time t0, the last refresh cycle of command mode starts from time t0 and ends at time t1, a total of 8.3ms. The display starts displaying the image frame N output by the processor. After the display finishes displaying image frame N, a certain buffer time is reserved. For example, based on the refresh cycle of 8.3ms, a buffer time of 2.7 + 2.7 = 5.4ms is reserved, that is, the time interval corresponding to the buffer time is (t1, t1 + 5.4ms). Within the buffer time interval (t1, t1 + 5.4ms), the display detects the mode switching command, and the display prepares to send a TE signal to indicate that the processor has finished displaying image frame N. First, the time when the next external VSync signal should be sent after the image frame N is displayed, based on the refresh rate, is calculated, plus the reserved buffer time, that is, time (t1 + 5.4ms), and the TE signal is controlled to switch from low level to high level at time (t1 + 5.4ms).

[0107] Furthermore, after the processor detects that the TE signal switches from low to high at (t1+5.4ms), it sends the first internal VSync signal for video mode at (t1+5.4ms). The display switches to video mode, and the processor prepares to send the first image frame of video mode, i.e., image frame N+1, based on the first internal VSync signal describing the video sent at (t1+5.4ms). In addition, after switching to video mode, the second internal VSync signal and the second external VSync signal for video mode are sent at (2t1+5.4ms), and the display then shows image frame N+2.

[0108] based on Figure 9 As shown in the mode switching timing diagram 03, on the one hand, in the command mode before switching display modes, each refresh cycle of the display is 8.3ms, and the reserved buffer time is a multiple of the refresh cycle. That is, in the command mode, the period of each EM signal is the same, 2.7ms, and the low level of each EM signal indicates that it is lit. The EM duty cycle of each EM signal is the same. On the other hand, in the video mode after switching, the first refresh cycle (t1+5.4ms, 2*t1+5.4ms) of the display is 8.3ms, and the period of each EM signal in this refresh cycle (t1+5.4ms, 2*t1+5.4ms) is the same, 2.7ms, and the EM duty cycle of each EM signal is the same. Therefore, the EM duty of the last EM signal in the command mode is the same as the EM duty of the first EM signal in the video mode. That is, before and after the switch, the pixel illumination time of the display is the same, and the corresponding display brightness is the same. Therefore, the display will not flicker.

[0109] pass Figures 7 to 9 As can be seen from the display method corresponding to the timing diagrams of each mode switching shown, in some embodiments, after receiving the mode switching command in command mode, the instantaneous switching from command mode to video mode can be realized, that is, the video mode has been switched in the next refresh cycle after the current refresh ends. The response speed to the mode switching command is fast and the mode switching is smooth.

[0110] Furthermore, based on Figures 7 to 9 As can be seen from the display method corresponding to the timing diagrams of each mode switching, before and after switching from command mode to video mode, the EM duty of the last EM signal in command mode and the EM duty of the first EM signal in video mode are the same. That is, before and after the switch, the pixel emission duration of the display screen is the same, and the corresponding display brightness is the same, so the display screen will not flicker.

[0111] In some embodiments of this application, in practical applications, due to software or hardware performance limitations, when switching from command mode to video mode, typically after the last refresh cycle of command mode ends, the image frame of the last refresh cycle of command mode can be displayed again before switching to video mode. For example, if an error is detected during the switching process, displaying a single image frame again can provide additional time to correct the timing, ensuring the stability and continuity of the switching process. The following is based on... Figures 10 to 11 The timing diagrams shown illustrate the corresponding scenarios and processes.

[0112] As an example, Figure 10 A timing diagram 04 illustrates a switch from command mode to video mode.

[0113] For example, Figure 10 A timing diagram 04 is shown for switching from command mode to example mode.

[0114] like Figure 10 As shown in the timing diagram 04, in command mode, based on the external VSync signal at time t0, the refresh cycle of command mode is 8.3ms from time t0 to time t1, during which the display starts displaying image frame N output by the processor. After the display finishes displaying image frame N, based on the display receiving the mode switching command, the display prepares to send a TE signal to indicate to the processor that image frame N has been displayed and is waiting to switch to video mode. Before this, to ensure the stability and continuity of the switching process, one image frame can be repeatedly displayed. The refresh cycle corresponding to the repeatedly displayed image frame N+1 is (t1, t2) and is 8.3ms. Furthermore, unlike the conventional method of switching the TE signal from low to high at time t01, when image frame N is displayed, within the refresh cycle (t0, t1) of command mode, this application controls the TE signal to switch from low to high at time t1 within the refresh cycle (t1, t2) corresponding to the repeatedly displayed image frame N+1.

[0115] Based on this, after the N+1 image frames repeatedly displayed in the refresh cycle (t1, t2) have finished displaying, the first internal VSync signal of the video mode, determined based on the refresh rate, is sent at time t2, which is also the time when the TE signal switches from low to high. After the processor detects that the TE signal switches from low to high at time t2, the processor sends the first internal VSync signal of the video mode at time t2, the display switches to video mode, and the processor prepares to send the first image frame of the video mode, i.e., image frame N+2, based on the first internal VSync signal.

[0116] based on Figure 10As shown in the mode switching timing diagram 04, on the one hand, the refresh cycle (t0, t1) and the repeated new cycle (t1, t2) of the command mode before the display mode switch are both 8.3ms. Furthermore, the period of each EM signal in both the refresh cycle (t0, t1) and the repeated new cycle (t1, t2) is the same, 2.7ms. A low level of each EM signal indicates illumination, and the EM duty cycle (EM duty) of each EM signal is the same. EM duty refers to the duration the EM signal is illuminated within the refresh cycle, i.e., the pixel illumination duration. On the other hand, the first refresh cycle (t2, t3) of the video mode after the switch is 8.3ms, and the period of each of the three EM signals in this refresh cycle (t2, t3) is the same, 2.7ms. The EM duty cycle (EM duty) of each EM signal is also the same. Therefore, the EM duty of the last EM signal in the command mode and the EM duty of the first EM signal in the video mode are also the same. This means that the pixel illumination time of the display is the same before and after the display mode is switched, and the corresponding display brightness is the same, so the display will not flicker.

[0117] In some embodiments of this application, when switching from command mode to video mode, a certain buffer time can be reserved between adjacent refresh cycles in command mode. Furthermore, after the last refresh cycle of command mode ends, the image frame from the last refresh cycle of command mode can be displayed again before switching to video mode. Displaying one image frame repeatedly provides additional time to correct timing, ensuring the stability and continuity of the switching process.

[0118] As another example Figure 11 Another timing diagram 05 shows the switching from command mode to video mode.

[0119] like Figure 11As shown in the timing diagram 05, in command mode, based on the external VSync signal at time t0, the refresh cycle of command mode is 8.3ms from time t0 to time t1, during which the display starts showing image frame N output by the processor. When the display finishes displaying image frame N and is ready to display image frame N+1 in command mode, a certain buffer time is reserved, for example, 2.7ms based on the refresh cycle of 8.3ms, i.e., the time interval corresponding to the buffer time is (t1, t1+2.7ms). After the buffer time ends, the external VSync signal of command mode is sent at time (t1+2.7ms) so that the display can display image frame N+1. When the display finishes displaying image frame N+1, the refresh cycle corresponding to image frame N+1 is (t1+2.7ms, 2*t1+2.7ms). Based on the display receiving the mode switching command within the refresh cycle of (t1+2.7ms, 2*t1+2.7ms), the display is ready to send a TE signal to indicate that the processor has finished displaying image frame N+1. Prior to this, to ensure the stability and continuity of the switching process, an image frame could be repeatedly displayed. The refresh period corresponding to the repeatedly displayed image frame N+2 was (2*t1+2.7ms, 3*t1+2.7ms), which was 8.3ms. In addition, unlike the conventional method of switching the TE signal from low to high level at time t11 when the image frame N+1 is displayed, which is based on the refresh period (t1+2.7ms, 2*t1+2.7ms) in the command mode, this application controls the TE signal to switch from low to high level at time (2*t1+2.7ms) in the refresh period (2*t1+2.7ms, 3*t1+2.7ms) corresponding to the repeatedly displayed image frame N+2.

[0120] Based on this, after the N+2 image frames that are repeatedly displayed in the refresh cycle (2*t1+2.7ms, 3*t1+2.7ms) are finished, the first internal VSync signal of the video mode determined based on the refresh rate is sent at (3*t1+2.7ms), which is also the moment when the TE signal switches from low to high. After the processor detects that the TE signal switches from low to high at (3*t1+2.7ms), the processor sends the first internal VSync signal of the video mode at (3*t1+2.7ms), the display screen switches to video mode, and the processor prepares to send the first image frame of the video mode, i.e., image frame N+3, based on the first internal VSync signal.

[0121] based on Figure 11As shown in the mode switching timing diagram 05, on the one hand, the refresh cycle of each command mode before the display screen switches the display mode is 8.3ms, and the reserved buffer time is a multiple of the refresh cycle. On the other hand, the refresh cycle (t0, t1), buffer time interval (t1, t1+2.7), refresh cycle (t1+2.7, 2*t1+2.7), and refresh cycle (2*t1+2.7, 3*t1+2.7) corresponding to the repeated display of image frame N+2 in the command mode are all the same with a cycle of 2.7ms. The low level of each EM signal indicates that it is lit, and the EM duty cycle of each EM signal is the same. On the other hand, the first refresh cycle (3*t1+2.7, 4*t1+2.7) of the display in the switched video mode is 8.3ms, and the period of each EM signal in this refresh cycle (3*t1+2.7, 4*t1+2.7) is the same at 2.7ms, and the EM duty cycle of each EM signal is the same. Therefore, the EM duty of the last EM signal in the command mode is the same as that of the first EM signal in the video mode. That is, before and after the switch, the pixel illumination time of the display is the same, and the corresponding display brightness is the same, meaning that the display will not flicker.

[0122] In some embodiments of this application, when switching from command mode to video mode, different buffer times can be reserved between adjacent refresh cycles in command mode, and the mode switching command in command mode can be issued within a buffer time reserved in the last refresh cycle of command mode. Furthermore, after the last refresh cycle of command mode ends, the image frame from the last refresh cycle of command mode can be displayed again before switching to video mode. Repeating the display of one image frame provides additional time to correct timing, ensuring the stability and continuity of the switching process.

[0123] As another example Figure 12 Another timing diagram 06 is shown, illustrating the switching from command mode to video mode.

[0124] like Figure 12As shown in the timing diagram 06, in command mode, based on the external VSync signal at time t0, the refresh cycle of command mode is 8.3ms from time t0 to time t1. The display starts displaying image frame N output by the processor. After the display finishes displaying image frame N, a certain buffer time is reserved, for example, based on the refresh cycle of 8.3ms, a buffer time of (5.4+2.7)ms is reserved, that is, the time interval corresponding to the buffer time is (t1, t1+5.4+2.7ms). During the buffer time interval (t1, t1+5.4ms), the display detects the mode switching command, and the display prepares to send a TE signal to indicate that the processor has finished displaying image frame N. Before this, in order to ensure the stability and continuity of the switching process, one image frame can be repeated. The refresh cycle corresponding to the repeated image frame N+1 is (t1+5.4+2.7ms). (2*t1+5.4+2.7ms) = 8.3ms. In addition, unlike the conventional method in the command mode refresh cycle (t1, t1+5.4ms) where the TE signal is switched from low to high at t12 when the image frame N+1 is displayed, based on the completion of the display of image frame N and the end of the buffer time, this application first calculates the time when the next external VSync signal should be issued after the completion of the display of image frame N+1 based on the refresh rate, plus the time after the buffer time, which is (2*t1+5.4+2.7ms), and controls the TE signal to switch from low to high at (2*t1+5.4+2.7ms).

[0125] Furthermore, after the processor detects that the TE signal switches from low to high at time (2*t1+5.4+2.7ms), the processor sends the first internal VSync signal of video mode at time (2*t1+5.4+2.7ms), the display switches to video mode, and the processor prepares to send the first image frame of video mode, i.e., image frame N+2, based on the first internal VSync signal of video description sent at time (2*t1+5.4+2.7ms).

[0126] based on Figure 12As shown in the mode switching timing diagram 06, on the one hand, the refresh cycle of each display in the command mode before switching display modes is 8.3ms, and the reserved buffer time is a multiple of the refresh cycle. Furthermore, the refresh cycle (t0, t1), buffer time interval (t1, t1+5.4+2.7), and refresh cycle (t1+5.4+2.7, 2*t1+5.4+2.7) corresponding to the N+1 repeated image frame in the command mode all have the same period of 2.7ms. A low level for each EM signal indicates illumination, and the EM duty cycle of each EM signal is the same. Therefore, the EM duty of the last EM signal in the command mode is the same as the EM duty of the first EM signal in the video mode. That is, before and after the switch, the pixel illumination time of the display is the same, and the corresponding display brightness is the same, meaning that the display will not flicker.

[0127] pass Figures 10 to 12 As can be seen from the display methods corresponding to the timing diagrams of each mode switching, in some embodiments, after receiving a mode switching command in command mode, the image frame of the last refresh cycle of command mode can be displayed again after the last refresh cycle of command mode ends, and then switched to video mode. Displaying one image frame again provides additional time to correct the timing, ensuring the stability and continuity of the switching process. Furthermore, based on... Figures 10 to 12 As can be seen from the display method corresponding to the timing diagrams of each mode switching, before and after switching from command mode to video mode, the EM duty of the last EM signal in command mode and the EM duty of the first EM signal in video mode are the same. That is, before and after the switch, the pixel emission duration of the display screen is the same, and the corresponding display brightness is the same, so the display screen will not flicker.

[0128] It is understood that, based on the display method provided in this application, when the display screen switches from video mode to command mode, there is usually no screen flickering problem.

[0129] As an example, Figure 13 A timing diagram 07 shows a display switching from video mode to command mode.

[0130] like Figure 13As shown in the timing diagram 07, in video mode, based on the internal and external VSync signals sent at time t0, the first refresh cycle of video mode lasts 8.3ms from time t0 to time t1, during which the display starts showing image frame N output by the processor. After the display finishes displaying image frame N, based on the internal and external VSync signals sent at time t1, the second refresh cycle of video mode lasts 8.3ms from time t1 to time t2, during which the display starts showing image frame N+1 output by the processor. After the display finishes displaying image frame N+1, based on the internal and external VSync signals sent at time t2, the third refresh cycle of video mode lasts 8.3ms from time t2 to time t3, during which the processor can output image frame N+2 to the GRAM, and the display shows image frame N+2 from the processor. Based on the mode switching command received during the refresh cycle (t1, t2) in video mode, the display can switch the TE signal from low to high at time t21, after the last image frame N+2 in video mode has been displayed. Furthermore, to ensure the stability and continuity of the switching process, one image frame N+2 can be displayed repeatedly. The refresh cycle corresponding to the repeated image frame N+2 is (t3, t4), which is 8.3ms. The TE signal in the refresh cycle (t3, t4) corresponding to the repeated image frame N+2 in video mode also switches from low to high after the repeated image frame N+2 has been displayed. After the display finishes displaying the repeated image frame N+2, the time when the first external VSync signal for command mode is sent is determined to be time t4 based on the refresh rate. After the processor detects that the TE signal is high at time t4, the processor sends the first external VSync signal for command mode at time t4, and the display switches to command mode. The processor then retrieves image N+3 from the GRAM based on the first external VSync signal corresponding to command mode at time t4 and displays image N+3.

[0131] based on Figure 13As shown in the timing diagram 07 illustrating the mode switching, when switching from video mode to command mode, firstly, in the video mode before the mode switch, each refresh cycle of the display is 8.3ms, and the refresh cycles (t0, t1), (t1, t2), (t2, t3) in video mode, as well as the refresh cycle (t3, t4) corresponding to the N+2 repeated image frames, each EM signal has the same period of 2.7ms. A low level for each EM signal indicates illumination, and the EM duty cycle of each EM signal is the same. Therefore, the EM duty of the last EM signal in command mode is also the same as that of the first EM signal in video mode. That is, before and after switching from video mode to command mode, the pixel illumination time of the display is the same, and the corresponding display brightness is the same, meaning that the display will not flicker.

[0132] Figure 14 A schematic diagram of the structure of a terminal device 100 is shown according to an embodiment of this application.

[0133] In this embodiment of the application, the terminal device 100 may be as described above. Figure 1 The various electronic devices in the scene shown are not limited here.

[0134] like Figure 14 As shown, the terminal device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, antenna A, antenna B, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, a display screen 194, a subscriber identification module (SIM) card interface 195, a communication device 196, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an accelerometer sensor 180E, a proximity sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, and a bone conduction sensor 180M, etc.

[0135] Processor 110 may include one or more processing units, such as application processors (APs), modem processors, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors.

[0136] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.

[0137] The processor 110 may also include a memory for storing instructions and data.

[0138] USB port 130 is a USB standard compliant interface, specifically a Mini USB port, Micro USB port, or USB Type-C port. USB port 130 can be used to connect a charger to charge terminal device 100, and can also be used for data transfer between terminal device 100 and peripheral devices. It can also be used to connect headphones for audio playback. This interface can also be used to connect other electronic devices, such as AR devices.

[0139] The charging management module 140 receives charging input from the charger. While charging the battery 142, the charging management module 140 can also supply power to the electronic device through the power management module 141.

[0140] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140 to power the processor 110, internal memory 121, display 194, camera 193, and wireless communication module 160, etc.

[0141] The wireless communication function of the terminal device 100 can be implemented through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor, and baseband processor. Antenna 1 and antenna 2 can be used to transmit and receive electromagnetic wave signals, that is, wireless carrier information.

[0142] The mobile communication module 150 can provide solutions for wireless communication, including 2G / 3G / 4G / 5G / 6G, applied to the terminal device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves via antenna 1, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via antenna 1.

[0143] The wireless communication module 160 can provide solutions for wireless communication applications on the mobile phone 10, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), and ultra-wideband (UWB). The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 can receive electromagnetic waves via antenna 2, filter and amplify the received electromagnetic waves, and transmit them to a modem processor for demodulation. The wireless communication module 160 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via antenna 2.

[0144] Terminal device 100 implements display functions through a GPU, display screen 194, and application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU performs mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information. In this embodiment, the GPU can send an internal VSync signal to indicate that the image frame to be displayed has been rendered and is ready for display. Furthermore, corresponding to command mode, the GPU can send the rendered image frame to be displayed to GRAM for storage; corresponding to video mode, the GPU can directly send the rendered image frame to the display screen for display, without further limitation.

[0145] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Mini-LED, a micro-LED, a Micro-OLED, a quantum dot light-emitting diode (QLED), etc. It is understood that the display method provided in this application embodiment can be applied to the display screen 194. In this application embodiment,

[0146] Camera 193 is used to capture still images or videos. An object passes through the lens, generating an optical image that is projected onto a photosensitive element. This photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, which is then passed to an ISP (Image Signal Processor) for conversion into a digital image signal. The ISP outputs the digital image signal to a DSP (Digital Signal Processor) for further processing. The DSP converts the digital image signal into standard RGB, YUV, or other image formats.

[0147] The external storage interface 120 can be used to connect an external storage card, such as a Micro SD card, to expand the storage capacity of the terminal device 100. The external storage card communicates with the processor 110 through the external storage interface 120 to perform data storage functions. For example, music, video, and other files can be saved on the external storage card.

[0148] Internal memory 121 can be used to store computer executable program code, including instructions, such as those in the aforementioned memory 103. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system, at least one application required for a function, etc. The data storage area may store data created during the use of the terminal device 100, such as control identifiers for security controls, screenshot redraw policy identifiers corresponding to security controls, and patterns, images, and text corresponding to screenshot redraw policies. Furthermore, internal memory 121 may include graphics random access memory (GRAM), high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory, universal flash storage (UFS), etc. Processor 110 executes various functional applications of the terminal device 100 by running instructions stored in internal memory 121 and / or instructions stored in memory located in processor 110. In some embodiments of this application, the GRAM may store image frames to be displayed after GPU rendering.

[0149] Terminal device 100 can implement audio functions through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.

[0150] The accelerometer 180E can detect the magnitude of acceleration of the terminal device 100 in various directions (typically three axes). When the terminal device 100 is stationary, it can detect the magnitude and direction of gravity. It can also be used to identify the attitude of the terminal device 100.

[0151] Touch sensor 180K, also known as a "touch device," can be located on display screen 194. The touch sensor 180K and display screen 194 together form a touchscreen, also known as a "touchscreen." Touch sensor 180K detects touch operations applied to or near it. The touch sensor can then transmit the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through display screen 194.

[0152] Motor 191 can generate vibration alerts.

[0153] Indicator 192 can be an indicator light, used to indicate charging status, power changes, or to indicate messages, missed calls, notifications, etc.

[0154] The SIM card interface 195 is used to connect the SIM card.

[0155] It is understood that the structure of the terminal device 100 shown in the embodiments of this application does not constitute a specific limitation on the terminal device 100. In other embodiments of this application, the terminal device 100 may include more or fewer components than shown, or combine some components, or split some components, or have different component arrangements. The components shown may be implemented in hardware, software, or a combination of software and hardware.

[0156] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0157] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0158] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0159] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or via other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, compact disc read-only memory (CD-ROMs), magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other forms of propagated signals. Therefore, machine-readable media includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0160] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0161] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0162] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0163] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A display method, characterized in that, Applied to an electronic device, the electronic device including a display screen, the method includes: If a mode switching command is detected during the first refresh cycle of the command mode, the first TE signal is controlled to switch from a low level to a high level at the first instant. The first TE signal is used to indicate that the image frame within the first refresh cycle has been displayed. The first moment is the end moment of the first refresh cycle and the first moment is the start moment of the second refresh cycle of the corresponding video mode. The first moment is related to the screen refresh rate of the display screen. Based on the first TE signal, a vertical synchronization signal is sent at the first moment, the display screen switches from command mode to video mode, and displays the image frame corresponding to the video mode within the second refresh cycle corresponding to the video mode.

2. The method according to claim 1, characterized in that, Before displaying the image frame corresponding to the video mode within the second refresh cycle corresponding to the video mode, the method further includes: Switch the first TE signal from a high level state to a low level state.

3. The method according to claim 1, characterized in that, The content displayed in the command mode includes static or animated images, while the content displayed in the video mode includes videos.

4. A display method, characterized in that, Applied to an electronic device, the electronic device including a display screen, the method includes: The first buffer period of the command mode is detected to start at a first moment and end at a second moment. The first moment is the end time of the first refresh period of the command mode. The first buffer period is less than or equal to the first refresh period, and the first refresh period is N times the first buffer period, where N ∈ positive integer. The second refresh cycle of the command mode is detected to start at the second time and end at the third time, which corresponds to the detection of a mode switching command within the second refresh cycle of the command mode. The second TE signal is controlled to switch from a low level state to a high level state at the third time. Wherein, the second TE signal is used to indicate that the image frame within the second refresh cycle of the command mode is completed and displayed, the third time is the end time of the second refresh cycle of the command mode, and the third time is the start time of the third refresh cycle of the corresponding video mode. Based on the second TE signal, a vertical synchronization signal is sent at the third moment, and the display screen switches from command mode to video mode, displaying the image frame corresponding to the video mode within the third refresh cycle corresponding to the video mode.

5. The method according to claim 4, characterized in that, Before displaying the image frame corresponding to the video mode within the third refresh cycle corresponding to the video mode, the method further includes: Switch the second TE signal from a high level state to a low level state.

6. A display method, characterized in that, Applied to an electronic device, the electronic device including a display screen, the method includes: The second buffer cycle of the command mode is detected to start at the first moment and end at the fourth moment. The first moment is the end moment of the first refresh cycle of the command mode. The second buffer cycle is less than or equal to the first refresh cycle, and the first refresh cycle and the second buffer cycle are multiples of each other. A mode switching command was detected during the second buffer period; When the end of the second buffer cycle is detected at the fourth time, the third TE signal is controlled to switch from a low level to a high level at the fourth time. The fourth time is the end time of the second buffer cycle of the command mode and the start time of the second refresh cycle of the corresponding video mode. Based on the third TE signal, a vertical synchronization signal is sent at the fourth moment, and the display screen switches from command mode to video mode, displaying the image frame corresponding to the video mode within the second refresh cycle corresponding to the video mode.

7. The method according to claim 6, characterized in that, Before displaying the image frame corresponding to the video mode within the second refresh cycle corresponding to the video mode, the method further includes: The third TE signal is switched from a high level state to a low level state.

8. A display method, characterized in that, Applied to an electronic device, the electronic device including a display screen, the method includes: If a mode switching command is detected during the first refresh cycle of the command mode, the first TE signal is controlled to switch from a low level to a high level at the first moment, which is the end time of the first refresh cycle of the command mode. If the second refresh cycle of the command mode is detected to start at the first moment and end at the fifth moment, the first TE signal is controlled to switch from a low level state to a high level state at the fifth moment. Based on the first TE signal, a vertical synchronization signal is sent at the fifth moment to control the display screen to switch from the command mode to the video mode at the fifth moment.

9. An electronic device, characterized in that, include: The processor and memory, the memory including physical memory and secondary memory, are used to store instructions executed by one or more processors of the electronic device; And a processor for executing the instructions to cause the electronic device to implement the display method of any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by the electronic device, causes the electronic device to implement the display method according to any one of claims 1 to 8.

11. A computer program product, characterized in that, Includes a computer program / instruction that, when the computer program product is run on an electronic device, causes the electronic device to perform the display method according to any one of claims 1 to 8.

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