A metal plug and a method of forming the same

Abstract

The application provides a metal plug and a forming method thereof, and the forming method comprises the following steps: forming an insulating medium layer on a substrate, the insulating medium layer comprises a first interlayer dielectric layer, a stop layer and a second interlayer dielectric layer from bottom to top in sequence, a filling layer is arranged in the insulating medium layer, the filling layer penetrates through the insulating medium layer and is in contact with the substrate, and the filling layer covers the surface of the insulating medium layer; first grinding is performed on the filling layer and grinding is stopped on the second interlayer dielectric layer; second grinding is performed on the filling layer, so that the surface of the filling layer is located between the upper surface of the second interlayer dielectric layer and the upper surface of the stop layer; the second interlayer dielectric layer is ground and grinding is stopped on the stop layer; third grinding is performed on the filling layer and a metal contact is formed, so that the surface of the metal contact is located below the lower surface of the stop layer, the polishing sequence is adjusted, one-time over-polishing is split into two times, the single grinding stress is reduced, the risk of metal contact center peeling is eliminated, and the yield loss is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a metal plug and a forming method thereof. BACKGROUND

[0002] In Damascene process in the field of semiconductor manufacturing, a via is formed by etching a dielectric layer, and a metal contact is formed by filling metal in the via, thereby avoiding the difficulty of directly etching metal to form a metal contact. However, when the metal contact is formed, there is a problem of CMP defect on the surface of the dielectric layer.

[0003] In order to solve the above problem, a deposition step of increasing the thickness of the dielectric layer is needed after the CMP of the dielectric layer is completed, but the problem that follows is that a deepened via is formed after etching the dielectric layer, and the metal contact peeling problem is prone to occur in the CMP process after the via is filled with metal. SUMMARY

[0004] The present application aims to provide a metal plug and a forming method thereof, which can solve the problem of metal contact peeling.

[0005] In order to solve the above technical problems, the present application provides a forming method of a metal plug, comprising the following steps:

[0006] An insulating dielectric layer is formed on a substrate, the insulating dielectric layer comprises a first interlayer dielectric layer, a stop layer and a second interlayer dielectric layer from bottom to top, a filling layer is arranged in the insulating dielectric layer, the filling layer penetrates through the insulating dielectric layer and is in contact with the substrate, and the filling layer covers the surface of the insulating dielectric layer;

[0007] The filling layer is ground for the first time, and the grinding is stopped on the second interlayer dielectric layer;

[0008] The filling layer is ground for the second time, so that the surface of the filling layer is located between the upper surface of the second interlayer dielectric layer and the upper surface of the stop layer;

[0009] The second interlayer dielectric layer is ground, and the grinding is stopped on the stop layer;

[0010] The filling layer is ground for the third time and a metal contact is formed, so that the surface of the metal contact is located below the lower surface of the stop layer.

[0011] Optionally, the specific method for forming the insulating dielectric layer comprises:

[0012] A substrate is provided, and a first interlayer dielectric layer is formed on the substrate;

[0013] planarizing the first interlayer dielectric layer;

[0014] forming a stop layer and a second interlayer dielectric layer on the first interlayer dielectric layer;

[0015] forming a plurality of contact holes through the second interlayer dielectric layer, the stop layer and the first interlayer dielectric layer, and exposing the device layer of the substrate;

[0016] forming a barrier layer on the inner wall of the contact hole, and forming a filling layer in the contact hole, the barrier layer covering the second interlayer dielectric layer outside the contact hole, and the filling layer covering the barrier layer outside the contact hole.

[0017] Further, the thickness of the first interlayer dielectric layer after planarization is 3200 Å ~ 4000 Å, the deposition thickness of the stop layer is 150 Å ~ 350 Å, and the deposition thickness of the second interlayer dielectric layer is 200 Å ~ 400 Å.

[0018] Further, the material of the first interlayer dielectric layer is TEOS, the material of the stop layer is silicon nitride, and the material of the second interlayer dielectric layer is TEOS.

[0019] Further, the specific method of first grinding of the filling layer is:

[0020] the filling layer and the barrier layer are ground by end-point stop polishing process, and the grinding stops on the second interlayer dielectric layer.

[0021] Further, the specific method of second grinding of the filling layer is:

[0022] the filling layer is over-grounded by over-polishing process.

[0023] Further, the specific method of grinding of the second interlayer dielectric layer is:

[0024] the second interlayer dielectric layer is ground by end-point stop polishing process, and the grinding stops on the stop layer.

[0025] Further, the specific method of third grinding of the filling layer and forming the metal contact is:

[0026] the filling layer is over-grounded by over-polishing process;

[0027] the stop layer is ground by end-point stop polishing process, and stops on the surface of the first interlayer dielectric layer, wherein the filling layer protrudes from the surface of the first interlayer dielectric layer.

[0028] Further, the grinding time of the second grinding and the third grinding of the over-polishing process is 5s-10s.

[0029] In another aspect, the application also provides a metal plug prepared by the forming method of the metal plug.

[0030] Compared with the prior art, the application has unexpected technical effects:

[0031] The application provides a metal plug and a forming method thereof, and the forming method comprises the following steps: forming an insulating medium layer on a substrate, the insulating medium layer comprises, from bottom to top, a first interlayer dielectric layer, a stop layer and a second interlayer dielectric layer in sequence, a filling layer is arranged in the insulating medium layer, the filling layer penetrates through the insulating medium layer and is in contact with the substrate, and the filling layer covers the surface of the insulating medium layer; performing first grinding on the filling layer and stopping grinding on the second interlayer dielectric layer; performing second grinding on the filling layer, so that the surface of the filling layer is located between the upper surface of the second interlayer dielectric layer and the upper surface of the stop layer; performing grinding on the second interlayer dielectric layer and stopping grinding on the stop layer; performing third grinding on the filling layer and forming a metal contact, so that the surface of the metal contact is located below the lower surface of the stop layer. By splitting the over-polishing process of long time (for example, greater than 45s) in the prior art into two over-polishing processes of short time (5s-10s), the application can significantly reduce single grinding stress, avoid that the filling layer 320 at the center position of the contact hole is excessively ground due to looseness, eliminate the risk of metal contact center peeling, reduce yield loss, shorten the over-polishing time to effectively reduce grinding time, greatly improve production throughput efficiency, and meet the demand of high productivity of semiconductor manufacturing. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is a structural schematic diagram of forming a medium layer on a provided substrate in the forming process of a metal plug.

[0033] Figure 2 It is a structural schematic diagram after the medium layer is subjected to CMP treatment.

[0034] Figure 3 It is a structural schematic diagram after a cap oxide layer is formed.

[0035] Figure 4 It is a structural schematic diagram after a filling layer is arranged in the contact hole.

[0036] Figure 5 It is a structural schematic diagram after the filling layer is subjected to CMP treatment.

[0037] Figure 6Structure diagram of the filled layer in the contact hole after over-polishing.

[0038] Figure 7 Structure diagram of the formed metal contact.

[0039] Figure 8 Flow diagram of the method for forming a metal plug according to an embodiment of the present application.

[0040] Figure 9 Structure diagram of the first interlayer dielectric layer formed on the substrate according to an embodiment of the present application.

[0041] Figure 10 Structure diagram after the first interlayer dielectric layer is planarized according to an embodiment of the present application.

[0042] Figure 11 Structure diagram after the second interlayer dielectric layer is formed according to an embodiment of the present application.

[0043] Figure 12 Structure diagram after the metal contact is initially formed according to an embodiment of the present application.

[0044] Figure 13 Structure diagram after the metal contact is ground for the first time according to an embodiment of the present application.

[0045] Figure 14 Structure diagram after the metal contact is ground for the second time according to an embodiment of the present application.

[0046] Figure 15 Structure diagram after the second interlayer dielectric layer is ground according to an embodiment of the present application.

[0047] Figure 16 Structure diagram after the metal contact is ground for the third time according to an embodiment of the present application.

[0048] Figure 17 Structure diagram after the stop layer is over-grounded according to an embodiment of the present application.

[0049] Legend of reference numerals:

[0050] Figures 1-7 10 - substrate; 21 - dielectric layer; 22 - cap oxide layer; 30 - filled layer; 31 - metal contact;

[0051] Figures 9-17 :

[0052] 100 - substrate; 110 - oxide layer; 120 - nitride layer; 210 - first interlayer dielectric layer; 220 - stop layer; 230 - second interlayer dielectric layer; 310 - barrier layer; 320 - filled layer. DETAILED DESCRIPTION

[0053] The following is a further detailed description of a metal plug and its formation method according to the present invention. The present invention will be described in more detail below with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art may modify the present invention described herein while still achieving the beneficial effects of the present invention. Therefore, the following description should be understood as a general guideline for those skilled in the art and is not intended to limit the present invention.

[0054] For the sake of clarity, not all features of actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would obscure the present invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as adapting from one embodiment to another to accommodate system or business constraints. Furthermore, it should be understood that such development work may be complex and time-consuming, but is nevertheless a routine undertaking for those skilled in the art.

[0055] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific embodiments of the present invention are further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0056] Currently, methods for forming metal contacts include:

[0057] like Figure 1 As shown, first, a dielectric layer 21 is formed on the substrate 10, and the thickness of the dielectric layer 21 is, for example, 6000Å;

[0058] like Figure 2 As shown, the dielectric layer 21 is subjected to CMP treatment. At this time, the thickness of the dielectric layer 21 is, for example, 3000 Å. This step is likely to cause surface defects in the dielectric layer 21.

[0059] like Figure 3 As shown, in order to improve the surface defect problem of the dielectric layer 21, a cap oxide layer 22 is formed on the dielectric layer. The thickness of the cap oxide layer 22 is, for example, 700 Å;

[0060] like Figure 4 As shown, a contact hole is formed, the contact hole penetrates the cap oxide layer 22 and the dielectric layer 21 and exposes the substrate 10; and a filling layer 30 is provided in the contact hole, and the filling layer 30 covers the cap oxide layer 22;

[0061] like Figure 5The fill layer 30 on the cap oxide layer 22 is removed by twice CMP processes, and the polishing is stopped on the cap oxide layer 22;

[0062] As shown in Figures 6-7 The fill layer 30 in the contact hole is over-polished to deepen the height difference between the contact hole opening and the fill layer 30 in the contact hole, and to form a metal contact 31. In this step, more polishing time, i.e. longer polishing time (for example, greater than 45s) is needed to deepen the height difference to the target depth, thereby increasing the process time, and the formed metal contact has a peeling problem due to the looseness of the fill layer at the central position of the contact hole compared to the fill layer at the sidewall of the contact hole.

[0063] To solve the above problems, the embodiment provides a metal plug forming method, comprising the following steps:

[0064] Step S1: forming an insulating medium layer on a substrate, the insulating medium layer comprises a first interlayer dielectric layer, a stop layer and a second interlayer dielectric layer from bottom to top in sequence, a fill layer is arranged in the insulating medium layer, the fill layer penetrates through the insulating medium layer and contacts the substrate, and covers the surface of the insulating medium layer;

[0065] Step S2: performing first polishing on the fill layer, and the polishing is stopped on the second interlayer dielectric layer;

[0066] Step S3: performing second polishing on the fill layer, so that the surface of the fill layer is located between the upper surface of the second interlayer dielectric layer and the upper surface of the stop layer;

[0067] Step S4: polishing the second interlayer dielectric layer, and the polishing is stopped on the stop layer;

[0068] Step S5: performing third polishing on the fill layer and forming a metal contact, so that the surface of the metal contact is located below the lower surface of the stop layer.

[0069] The following will be described in detail Figures 9-17 The metal plug forming method provided by the embodiment will be described in detail.

[0070] Please refer to Figures 9-12 , first, step S1 is performed, an insulating medium layer is formed on a substrate 100 in sequence, the insulating medium layer comprises a first interlayer dielectric layer 210, a stop layer 220 and a second interlayer dielectric layer 230 from bottom to top in sequence, a metal contact is arranged in the insulating medium layer, the metal contact penetrates through the insulating medium layer and contacts the substrate 100, and covers the surface of the insulating medium layer.

[0071] This step has the following steps:

[0072] As shown in Figure 9 , first, a substrate 100 is provided, and an oxide layer 110 and a nitride layer 120 are sequentially formed on the substrate 100, and a first interlayer dielectric layer 210 is formed on the nitride layer 120.

[0073] In an embodiment, the material of the substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, etc., and can also be silicon on insulator or germanium on insulator; or can also be other materials, such as III-V compound, for example, gallium arsenide. In the embodiment, the substrate 100 is a silicon substrate 100.

[0074] In an embodiment, an epitaxial layer is formed on the substrate 100, and a device layer is formed on the epitaxial layer. Any suitable method can be used to form various devices, such as transistors, capacitors, resistors, and similar elements, on the surface of the epitaxial layer. Of course, part of the devices can also be formed in the epitaxial layer. In the embodiment, a MOS transistor provided in the device layer is taken as an example for detailed introduction, wherein the MOS transistor includes a source region S, a drain region D, and a gate G.

[0075] In an embodiment, the oxide layer 110 serves as an isolation layer, which is used to prevent the subsequent metal interconnection from directly contacting the silicon material of the substrate 100, to avoid short circuit or carrier diffusion, and at the same time, serves as an etching stop layer 220 in the subsequent etching to form a contact hole, to protect the device layer from being damaged by excessive etching. The nitride layer 120 serves as a dense barrier layer, which is used to prevent metal ions (such as tungsten) from diffusing to the substrate 100, to avoid pollution or device failure, and also to inhibit the penetration of moisture and impurities, to improve the long-term reliability of the device; at the same time, in the etching of the contact hole, the high etching selectivity ratio (usually > 10:1) of SiN to SiO2 is used to achieve precise control of the etching depth, to prevent damage to the substrate 100.

[0076] In an embodiment, the material of the first interlayer dielectric layer 210 is TEOS, and the deposition thickness of the first interlayer dielectric layer 210 is 6000 Å ~ 8000 Å.

[0077] As shown in Figure 10 , then, the first interlayer dielectric layer 210 is planarized by a CMP process, and the thickness of the first interlayer dielectric layer 210 after the planarization (the thickness of the first interlayer dielectric layer 210 above the nitride layer 120 outside the gate) is 3200 Å ~ 4000 Å.

[0078] As shown in Figure 11 , then, a stop layer 220 and a second interlayer dielectric layer 230 are formed on the first interlayer dielectric layer 210 by a deposition process.

[0079] In one embodiment, the material of the stop layer 220 is silicon nitride, and the material of the second interlayer dielectric layer 230 is TEOS. The deposition thickness of the stop layer 220 is 150-350 A, and the deposition thickness of the second interlayer dielectric layer 230 is 200-400 A.

[0080] As shown in FIG. 2B, then, a plurality of contact holes are formed by an etching process, the contact holes penetrating through the second interlayer dielectric layer 230, the stop layer 220 and the first interlayer dielectric layer 210, and exposing the device layer. Figure 12

[0081] In one embodiment, the number of the contact holes is three, respectively exposing the source region S, the drain region D and the gate G of the MOS transistor.

[0082] Please refer to FIG. 2C, then, a barrier layer 310 is formed on the inner wall of the contact hole, and a filling layer 320 is arranged in the contact hole, the barrier layer 310 covering the second interlayer dielectric layer 230 outside the contact hole, and the filling layer 320 covering the barrier layer 310 outside the contact hole. Figure 12

[0083] In one embodiment, the barrier layer 310 can be selected from the group consisting of iron, cobalt, titanium nitride, tungsten nitride and other materials with good adhesion or barrier properties, and the material of the filling layer 320 can be a conductive metal or alloy with good step coverage and uniformity, such as tungsten. In addition to tungsten, the material of the filling layer 320 can also be aluminum, copper or an alloy of the above-mentioned metals.

[0084] Please refer to FIG. 2D, then, step S2 is performed, the first polishing of the filling layer 320 is performed, and the polishing is stopped on the second interlayer dielectric layer 230. Figure 13

[0085] In detail, the CMP process is used to polish the filling layer 320 and stop polishing on the second interlayer dielectric layer 230.

[0086] The CMP process includes an end-point stop polishing process and an over-polishing process. The purpose of the end-point stop polishing process is to quickly remove redundant materials and accurately stop at the specified interface layer to achieve preliminary planarization. The purpose of the over-polishing process is to intentionally extend the polishing time after stopping at the target layer to create a recess and improve electrical contact or eliminate residual defects.

[0087] In one embodiment, the end-point stop polishing process is used to polish the filling layer 320 and the barrier layer 310 and stop polishing on the second interlayer dielectric layer 230. At this time, only the filling layer 320 and the barrier layer 310 remain in the contact hole.

[0088] ​​​In one embodiment, the polishing liquid used in the endpoint stop polishing process of this step includes aluminum oxide (Al2O2) or manganese dioxide (MnO2) abrasive, an oxidizer (hydrogen peroxide, ferrous nitrate, or potassium chlorate), a pH adjuster (nitric acid or an organic acid), and deionized water (DIW); the polishing rate is 50 nm / min to 200 nm / min, the polishing pressure is 20 kPa to 41 kPa, and the polishing time is 30 s to 180 s.

[0089] See also Figure 14 Then, step S3 is performed to grind the filling layer 320 for the second time, so that the surface of the filling layer 320 is located between the upper surface of the second interlayer dielectric layer 230 and the upper surface of the stop layer 220 .

[0090] Specifically, the filling layer 320 is over-polished through an over-polishing process, so that a first height difference H1 exists between the opening surface of the contact hole and the surface of the filling layer 320, and the surface of the filling layer 320 is located above the stop layer 220. At this time, the barrier layer 310 still covers the entire sidewalls and bottom wall of the contact hole, and a portion of the barrier layer 310 is exposed at the opening of the contact hole.

[0091] In one embodiment, the polishing liquid used in the over-polishing process of this step includes aluminum oxide (Al2O2) or manganese dioxide (MnO2) abrasive, an oxidizing agent (hydrogen peroxide, ferrous nitrate, or potassium chlorate), a pH adjuster (nitric acid or an organic acid), and deionized water (DIW); the polishing rate is 200 nm / min to 500 nm / min, the polishing pressure is 28 kPa to 56 kPa, and the polishing time is 5 s to 10 s.

[0092] See also Figure 15 Then, step S4 is performed to grind the second interlayer dielectric layer 230 and stop the grinding on the stop layer 220 .

[0093] In detail, the second interlayer dielectric layer 230 is polished by an endpoint stop polishing process, and the polishing stops on the stop layer 220 , so that the surface of the filling layer 320 is slightly higher than the surface of the stop layer 220 .

[0094] In one embodiment, the polishing liquid used in the endpoint stop polishing process of this step includes silica abrasive, a pH adjuster (potassium hydroxide or ammonia water) and deionized water (DIW); the polishing rate is 100 nm / min to 500 nm / min, the polishing pressure is 20 kPa to 41 kPa, and the polishing time is 50 s to 300 s.

[0095] In this step, the core function of the stop layer 220 is to provide an accurate end point detection (EPD) of polishing, ensure the thickness uniformity of the ILD oxide layer 110, and protect the underlying structure from over-polishing, and reduce the device performance deviation caused by film thickness fluctuation.

[0096] Please refer to Figure 16 , then step S5 is performed to polish the filling layer 320 for the third time and form the metal contact, so that the surface of the metal contact is below the lower surface of the stop layer 220.

[0097] In detail, the filling layer 320 is over-polished by the over-polishing process, so that the second height difference H2 is formed between the opening surface of the contact hole and the surface of the filling layer 320, and the surface of the filling layer 320 is below the stop layer 220, wherein the sum of the first height difference H1 and the second height difference H2 is the target height. At this time, the barrier layer 310 still covers the entire sidewall and inner wall of the contact hole, and the filling layer 320 exposes a portion of the length of the barrier layer 310 at the opening of the contact hole.

[0098] In an embodiment, the polishing liquid used in the over-polishing process of this step includes aluminum oxide (Al2O2) or manganese dioxide (MnO2) abrasive, oxidizing agent (hydrogen peroxide, ferrous nitrate or potassium chlorate), PH adjuster (nitric acid or organic acid) and deionized water (DIW); the polishing rate is 200 nm / min ~ 500 nm / min, the polishing pressure is 28 kPa ~ 56 kPa, and the polishing time is 5s ~ 10s.

[0099] By splitting the existing long-time (e.g. greater than 45s) over-polishing process into two short-time (5s ~ 10s) over-polishing processes, this embodiment can significantly reduce the single polishing stress, avoid the over-polishing of the filling layer 320 at the center position of the contact hole, eliminate the risk of metal contact center peeling, reduce yield loss, shorten the over-polishing time to effectively reduce the polishing time, greatly improve the production throughput efficiency, and meet the demand for high productivity of semiconductor manufacturing.

[0100] As shown in Figure 17 , then the stop layer 220 is polished by the end-point stop polishing process, and is stopped at the surface of the first interlayer dielectric layer 210, while forming the final metal contact, and at this time the filling layer 320 protrudes from the first interlayer dielectric layer 210, and the surface of the filling layer 320 is 1 nm ~ 5nm higher than the height of the first interlayer dielectric layer 210.

[0101] In one embodiment, the polishing slurry used in the endpoint of the present step includes cerium oxide abrasive, oxidizing agent (hydrogen peroxide), pH adjuster (potassium hydroxide or ammonia water), and deionized water (DIW); the polishing rate is 100 nm / min ~ 300 nm / min, the polishing pressure is 7 kPa ~ 21 kPa, and the polishing time is 60 s ~ 180 s.

[0102] The present embodiment also provides a metal contact prepared by the above method.

[0103] In summary, the present application provides a metal plug and a forming method thereof, the forming method comprising the following steps: forming an insulating medium layer on a substrate, the insulating medium layer comprising, from bottom to top, a first interlayer dielectric layer, a stop layer, and a second interlayer dielectric layer, the insulating medium layer being provided with a filling layer, the filling layer penetrating through the insulating medium layer and being in contact with the substrate, and also covering the surface of the insulating medium layer; performing first polishing on the filling layer and stopping polishing on the second interlayer dielectric layer; performing second polishing on the filling layer so that the surface of the filling layer is between the upper surface of the second interlayer dielectric layer and the upper surface of the stop layer; performing polishing on the second interlayer dielectric layer and stopping polishing on the stop layer; performing third polishing on the filling layer and forming a metal contact so that the surface of the metal contact is below the lower surface of the stop layer. The present application can significantly reduce the single polishing stress by splitting the long-time (e.g., greater than 45 s) over-polishing process in the prior art into two short-time (5 s ~ 10 s) over-polishing processes, avoid the over-polishing of the filling layer 320 at the center position of the contact hole, eliminate the risk of metal contact center peeling, reduce yield loss, shorten the over-polishing time to effectively reduce the polishing time, greatly improve the production throughput efficiency, and meet the demand for high productivity in semiconductor manufacturing.

[0104] In addition, the core role of the stop layer 220 of the present application is to provide an accurate polishing endpoint detection (EPD), ensure the thickness uniformity of the ILD oxide layer 110, and also protect the underlying structure from over-polishing and reduce the device performance deviation caused by film thickness fluctuation; meanwhile, the formation of the stop layer 220 makes the polishing process only need to adjust the polishing step sequence and parameters (without adding new equipment), realizes efficient switching through the combined use of two polishing pads, and reduces the upgrade cost.

[0105] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first", "second" in the description are only used to distinguish the components, elements, steps, etc. in the description, and do not represent the logical relationship or sequence relationship between the components, elements, steps, etc.

[0106] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a metal plug, characterized in that: The following steps are involved: forming an insulating dielectric layer on a substrate, the insulating dielectric layer including, from bottom to top, a first interlayer dielectric layer, a stop layer, and a second interlayer dielectric layer; and providing a filling layer in the insulating dielectric layer, the filling layer penetrating the insulating dielectric layer and contacting the substrate, and also covering a surface of the insulating dielectric layer; performing a first grinding on the filling layer, and stopping the grinding on the second interlayer dielectric layer; performing a second grinding on the filling layer, wherein the second grinding is an over-polishing process and the grinding time is 5s to 10s, so that the surface of the filling layer is located between the upper surface of the second interlayer dielectric layer and the upper surface of the stop layer; grinding the second interlayer dielectric layer, and stopping the grinding on the stop layer; The filling layer is ground for a third time to form a metal contact, wherein the third grinding is an over-polishing process with a grinding time of 5s to 10s, so that the surface of the metal contact is located below the lower surface of the stop layer.

2. The method for forming a metal plug according to claim 1, wherein: The specific method of forming the insulating dielectric layer includes: Providing a substrate, on which a first interlayer dielectric layer is formed; planarizing the first interlayer dielectric layer; forming a stop layer and a second interlayer dielectric layer on the first interlayer dielectric layer; forming a plurality of contact holes by an etching process, wherein the contact holes penetrate the second interlayer dielectric layer, the stop layer and the first interlayer dielectric layer and expose the device layer of the substrate; A barrier layer is formed on the inner wall of the contact hole, and a filling layer is provided in the contact hole. The barrier layer covers the second interlayer dielectric layer outside the contact hole, and the filling layer covers the barrier layer outside the contact hole.

3. The method for forming a metal plug according to claim 2, wherein: The thickness of the first interlayer dielectric layer after planarization is 3200Å~4000Å, the deposition thickness of the stop layer is 150Å~350Å, and the deposition thickness of the second interlayer dielectric layer is 200Å~400Å.

4. The method for forming a metal plug according to claim 2, wherein: The material of the first interlayer dielectric layer is TEOS, the material of the stop layer is silicon nitride, and the material of the second interlayer dielectric layer is TEOS.

5. The method for forming a metal plug according to claim 2, wherein: The specific method for performing the first grinding on the filling layer is: The filling layer and the barrier layer are polished by an endpoint stop polishing process, and the polishing stops on the second interlayer dielectric layer.

6. The method for forming a metal plug according to claim 2, wherein: The specific method for grinding the second interlayer dielectric layer is: The second interlayer dielectric layer is polished by an endpoint stop polishing process, and the polishing stops on the stop layer.

7. The method for forming a metal plug according to claim 2, wherein: The specific method of grinding the filling layer for the third time and forming the metal contact is as follows: Over-grinding the filling layer through an over-polishing process; The stop layer is ground by an endpoint stop polishing process and stops at the surface of the first interlayer dielectric layer, wherein the filling layer protrudes from the surface of the first interlayer dielectric layer.

8. A metal plug, characterized in that: The metal plug is prepared by the method for forming the metal plug according to any one of claims 1 to 7.

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