Parallel energy storage charging and discharging system and charging and discharging device

Abstract

The invention discloses a parallel energy storage charging and discharging system and a charging and discharging device. The parallel energy storage charging and discharging system comprises a host and a plurality of battery modules, the plurality of battery modules are connected in parallel; the host and the battery module controllers connected in parallel are connected in series through a 485 line, that is, the host comprises a first interface and a second interface, the first interface is connected with the first battery module connected in parallel, and the second interface is connected with the last battery module connected in parallel. A communication mode that a host and a plurality of battery modules are connected in series in a hand-in-hand mode is adopted, address allocation is not needed, communication efficiency is improved, previous polling of the host and the slave is changed into annular communication, the problems of arbitration, address allocation and the like do not exist, cables are shortened, interference is not likely to happen, and the stability of the whole system is improved. The invention further provides a power supply activation detection circuit and a synchronous starting circuit which are used in cooperation with an original charging activation circuit. After charging is activated, all modules can be synchronously started to open a charging loop, and the problem that power distribution is not uniform in the initial charging stage is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of power systems, and in particular to a parallel energy storage charging and discharging system and a charging and discharging device. Background Art

[0002] In recent years, with the continuous advancement of lithium-ion battery technology and the continued decline in costs, more and more research has focused on improving the efficiency and safety of energy storage systems. 48V energy storage systems have been widely used in areas such as home energy storage, commercial backup power, and data center communication backup power due to their moderate voltage level and wide applicability. The fact that individual 48V battery packs have been developed for many years and the overall process, manufacturing, and technology are very mature, especially in terms of safety and stability. However, traditional single 48V battery packs often struggle to meet the high capacity and high power requirements of large-scale projects. While the total capacity can be increased by simply connecting multiple battery packs in parallel, this approach is prone to problems such as poor consistency between batteries, fault propagation, and communication issues, which can affect the stability and service life of the entire system. Summary of the Invention

[0003] The main purpose of the present invention is to propose a parallel energy storage charging and discharging system and charging and discharging device, which aims to solve the problems of abnormal communication delay, slow refresh speed, communication interference, and on-site address configuration when a large number of slaves communicate in parallel.

[0004] To achieve the above-mentioned purpose, the present invention proposes a parallel energy storage charging and discharging system, which includes: a host and multiple battery modules;

[0005] Multiple battery modules are connected in parallel;

[0006] The host includes a first interface and a second interface, the first interface is connected to the first battery module in parallel, the second interface is connected to the last battery module in parallel, and the host and the parallel battery modules are connected via a 485 serial line.

[0007] In one embodiment, the battery module includes: a battery pack and a slave device;

[0008] The battery pack is connected to the slave, and multiple slaves are connected together in series by hand-in-hand communication, the first slave in the communication series is connected to the first interface, and the last slave in the communication series is connected to the second interface;

[0009] The host is configured to send a plurality of registration commands to the slave connected to the first interface when the power is turned on or restarted;

[0010] The slave is configured to perform address coding in sequence according to the received registration command; and when the address coding is completed, output the coded registration command to the next connected slave.

[0011] In one embodiment, the slave connected to the second interface of the host is further configured to send the encoded registration command to the host after encoding is completed;

[0012] The host is used to check whether the number of address codes in each registration command is consistent. If the number of address codes is consistent, it is determined that the slave address registration is successful, and the number of slaves is counted.

[0013] In one embodiment, the host is configured to send an address set of the slave to each of the slaves;

[0014] The slave device is further configured to divide memory according to the address set, and each memory after the division is used to store data packets corresponding to the address;

[0015] The slave machine is further configured to output the stored data packet to the slave machine or host machine corresponding to the data packet.

[0016] In one embodiment, the host is configured to receive data packets sent by each of the slaves after the slave addresses are successfully registered, and feed back instructions corresponding to the data packets.

[0017] In one embodiment, the slave is used to receive an instruction output by the previous slave or host, and when it detects that the address of the instruction is consistent with its own address, parse and process the instruction; when it detects that the address of the data packet is inconsistent with its own address, output the instruction to the next slave or host.

[0018] In one embodiment, the battery module further comprises: a power activation detection circuit and a synchronous start-up circuit;

[0019] The power activation detection circuit is connected to the charging power supply and the synchronous start circuit, and the synchronous start circuit is connected to the slave device;

[0020] The power activation detection circuit is configured to send a start signal to the synchronous start circuit upon detecting a charging activation signal;

[0021] The synchronous starting circuit is used to control the battery packs in each battery module to connect to the charging power supply when receiving the start signal.

[0022] In one embodiment, a power activation detection circuit includes: a first resistor, a second resistor, a first transistor, and a first diode;

[0023] One end of the first resistor is connected to the negative electrode of the slave battery pack, the other end of the first resistor is connected to the base of the first transistor, the emitter of the first transistor is connected to the anode of the first diode, the cathode of the first diode is connected to the charging power supply, the emitter of the first transistor is connected to the second resistor, the other end of the second resistor is connected to the primary output end of the first optocoupler, and the primary input end of the first optocoupler is connected to the positive electrode of the charging power supply.

[0024] In one embodiment, the synchronous start-up circuit includes: a first optocoupler and a second optocoupler;

[0025] The secondary input and secondary output of the second optocoupler are connected to the slave device, the secondary input of the first optocoupler is connected to the primary output of the second optocoupler of the previous battery module or the positive electrode of the charging power supply, the secondary output of the first optocoupler is connected to the primary input of the second optocoupler, and the primary output of the second optocoupler is connected to the secondary input of the first optocoupler of the next battery module or the negative electrode of the charging power supply.

[0026] The present invention further provides a charging and discharging device, which includes the parallel energy storage charging and discharging system as described above.

[0027] The present invention discloses a parallel energy storage charging and discharging system and a charging and discharging device. The parallel energy storage charging and discharging system includes: a host and multiple battery modules; multiple battery modules are connected in parallel; the host and the parallel battery module controllers are connected in series via a 485 line, that is, the host includes a first interface and a second interface, the first interface is connected to the first battery module in parallel, and the second interface is connected to the last battery module in parallel. A communication method in which the host and multiple battery modules are connected hand in hand in series is adopted, which does not require address allocation and improves communication efficiency. The previous master-slave polling is changed to a ring communication, which eliminates the problems of arbitration, address allocation, etc. The cables are shortened and not easily interfered with, thereby improving the overall system stability. The power activation detection circuit and the synchronous start circuit are used in conjunction with the original charging activation circuit; after charging activation, all modules can be started synchronously to open the charging circuit, solving the problem of uneven power distribution in the initial charging stage, which in turn causes damage to some parallel modules, thereby improving the overall system consistency and long-term reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0029] Figure 1 A circuit diagram of the first embodiment of the parallel energy storage charging and discharging system provided by the present invention;

[0030] Figure 2 A schematic structural diagram of a first embodiment of a parallel energy storage charging and discharging system provided by the present invention;

[0031] Figure 3 A connection diagram of the first embodiment of the parallel energy storage charging and discharging system provided by the present invention;

[0032] Figure 4 A schematic flow chart of a second embodiment of the parallel energy storage charging and discharging system provided by the present invention;

[0033] Figure 5 Another flow chart of the second embodiment of the parallel energy storage charging and discharging system provided by the present invention;

[0034] Figure 6 A circuit diagram of a third embodiment of the parallel energy storage charging and discharging system provided by the present invention;

[0035] Figure 7 This is another circuit diagram of the third embodiment of the parallel energy storage charging and discharging system provided by the present invention.

[0036] Description of Figure Numbers:

[0037] Label name Label name R1~R2 First to second resistors Q1 The first transistor D1 First diode 1 First optocoupler 2 Second optocoupler

[0038] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0040] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0041] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of such features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0042] In recent years, with the continuous advancement of lithium-ion battery technology and the continued decline in costs, more and more research has focused on improving the efficiency and safety of energy storage systems. 48V energy storage systems have been widely used in areas such as home energy storage, commercial backup power, and data center communication backup power due to their moderate voltage level and wide applicability. The fact that individual 48V battery packs have been developed for many years and the overall process, manufacturing, and technology are very mature, especially in terms of safety and stability. However, traditional single 48V battery packs often struggle to meet the high capacity and high power requirements of large-scale projects. While the total capacity can be increased by simply connecting multiple battery packs in parallel, this approach is prone to problems such as poor consistency between batteries, fault propagation, and communication issues, which can affect the stability and service life of the entire system.

[0043] like Figure 1 As shown in the figure, the block diagrams of the two mainstream 48V large-parallel energy storage systems are generally composed of a high-power power supply, loads, and several 48V battery packs in parallel (usually 20 to 64). The communication management part uses 485 bus communication on the left and CAN communication on the right. Both of the above systems will encounter many problems in actual use, resulting in poor actual performance.

[0044] First, there are issues with communication stability. In typical RS485 bus multi-node communication networking applications, a single master node and multiple slave nodes, each with a unique ID, often employ a "question-and-answer" approach. The master node issues a query command to a slave node with a specific ID. The slave node verifies that the ID matches its own and responds. Other slave nodes on the bus remain silent until they receive a query command from the master with a matching ID. This communication method, due to polling and processing time, is very slow in large parallel systems. Furthermore, the large number of slaves puts a strain on the drive capability of all nodes on the bus, making it susceptible to interference and unstable communication. The CAN bus utilizes arbitration, with each node periodically uploading data. However, in large parallel systems with a large number of nodes, some nodes may be unable to connect during arbitration, leading to system-level communication instability. Furthermore, both communication methods require address allocation. For 64 nodes communicating, 64 addresses are required, posing challenges for both installation and after-sales service.

[0045] Second, there is the problem of high current surge from the power supply. Since there are too many parallel systems, the power they require and the power required by the load are both very high, which will cause two problems. First, when the system is turned on, the system power supply has not yet fully communicated with all the battery modules (the process usually takes about 1 minute). At this time, it will output current at full power, causing damage to all 48V modules in the system, resulting in uneven charging current input and causing overcurrent protection, triggering a chain reaction of overcurrent protection for all battery modules. If the system is large and the power output current briefly exceeds the pulse current limit of the protection board power MOS in each battery module, then the battery module may be damaged. Second, there is the problem of charging activation. The charger outputs voltage to activate each module, and it cannot activate dozens of modules at a time. Existing technology often results in several modules with low voltage being activated first, and then the bus voltage is pulled down, resulting in the inability to activate modules with slightly higher voltage, causing system waste. Over time, this leads to voltage and capacity imbalance between modules.

[0046] Third, configuration issues: The current architecture of the 485 bus and CAN bus requires address allocation, which requires adding dial switches to the circuit and on-site installation and configuration.

[0047] like Figure 2 As shown in FIG, this is a structural diagram of the first embodiment of the parallel energy storage charging and discharging system proposed in this embodiment.

[0048] The present invention discloses a parallel energy storage charging and discharging system and a charging and discharging device. The parallel energy storage charging and discharging system includes: a host and multiple battery modules; the multiple battery modules are connected in parallel; the host includes a first interface and a second interface, the first interface is connected to the first battery module in parallel, and the second interface is connected to the last battery module in parallel, and the host and the parallel battery modules are connected via a 485 serial line.

[0049] It is understandable that the present invention proposes a large parallel energy storage system framework, such as Figure 3 As shown in the figure, a new topology design for the communication 485 bus has been implemented on the original power main circuit system. Multiple battery modules are connected sequentially through the 485A and 485B ports to form a series battery module. When three battery modules are connected in series, the 485A port of module 1 is connected to the first port of the host computer, the 485B port of module 1 is connected to the 485A port of module 2, the 485B port of module 2 is connected to the 485A port of module 3, and the 485B port of module 3 is connected to the second port of the host computer.

[0050] It should be noted that the host's first interface is connected to the 485A interface of the first battery module in the parallel battery module, and the second interface is connected to the 485B interface of the last battery module in the parallel battery module. The communication topology adopts a 485 serial line, and the 485 serial line adopts a half-duplex communication protocol. The present invention adopts an end-to-end connection, which is suitable for industrial environments, has strong anti-interference capabilities, and is suitable for long-distance transmission. The host sends communication instructions through the 485 interface. Each serial communication slave recognizes the address and realizes the relay transmission of instructions or data, realizing polling or broadcasting instructions to each module and retrieving data from each module.

[0051] The battery module includes: a battery pack and a slave; the battery pack is connected to the slave, and multiple slaves are connected in series, the first slave in series is connected to the first interface, and the last slave in series is connected to the second interface.

[0052] It should be noted that the first interface is 485A and the second interface is 485B. Each battery module includes a battery pack and a slave MCU. Multiple slave MCUs are connected in sequence through the 485A and 485B interfaces to form a series battery module. When three battery modules are connected in series, the 485A of the slave MCU01 is connected to the first interface 485A of the master, the 485B of MCU01 is connected to the 485A of MCU02, the 485B of MCU02 is connected to the 485A of MCU03, and the 485B of MCU03 is connected to the second interface 485B of the master.

[0053] In this embodiment, the slave MCU adopts a hand-in-hand serial communication method, which does not require address allocation and improves communication efficiency. The previous master-slave polling is changed to a ring communication, which no longer has problems such as arbitration and address allocation. The cable is shortened and is less susceptible to interference, thereby improving the overall system stability.

[0054] like Figure 4 As shown, this is a flow chart of the second embodiment of the parallel energy storage charging and discharging system proposed in this embodiment.

[0055] Based on the above first embodiment, a second embodiment of the parallel energy storage charging and discharging system of the present invention is proposed.

[0056] The host is used to send multiple registration commands to the slave connected to the first interface when the power is turned on or restarted; the slave is used to perform address encoding in sequence according to the received registration commands; and when the address encoding is completed, output the encoded registration command to the next connected slave.

[0057] It is understood that the host is responsible for sending a registration command to the connected slave via the first interface 485A when the power is turned on or the system is restarted. The host sends multiple registration commands (such as frames containing specific instruction codes or initial addresses) in sequence. Each command may carry address allocation parameters to trigger the slave to enter the registration state.

[0058] It should be noted that the slaves perform address encoding in sequence according to the received registration command and pass the processed command to the next slave. After receiving the registration command, the slave generates a unique address according to preset rules (such as incremental, random, or based on the command content). After the encoding is completed, the modified command is forwarded to the next slave through the output interface, forming a chain transmission. The slaves are connected in series to form a linear topology. The command sent by the host passes through each slave in turn. Each slave continues to pass it on after processing until the last slave passes it back to the host. The slave can generate an address based on the parameters in the command (such as the initial address, node number) or its own hardware ID.

[0059] Specifically, each time the system is powered on or restarted, the host (PCU) will resend the registration command to request the slave to perform address encoding. The first interface 485A of the host will cyclically send instructions and count until the second interface 485B receives a response from the slave.

[0060] The slave connected to the second interface of the host is also used to send the encoded registration command to the host after the encoding is completed; the host is used to check whether the number of address codes of each registration command is consistent. When the number of address codes is consistent, it is determined that the slave address registration is successful and the number of slaves is counted.

[0061] It is understandable that the host's second interface 485A receives a response from the slave and checks whether the address code numbers are consistent. If they are consistent, all slave node addresses are successfully registered and the host informs the total number of slaves in the large parallel energy storage system.

[0062] It should be noted that the slave connected to the second interface of the host (the last slave MCU in the chain topology) sends the encoded registration command back to the host after the address encoding is completed. After completing its own address encoding, the slave sends the registration command containing its address information back to the host through the predetermined communication path 485 bus. The feedback content includes the slave's own address, encoding success status, and other relevant information (such as slave ID, hardware version, etc.). Because the host sends multiple registration commands, the host receives multiple registration command feedbacks fed back by the slave. The host checks whether the number of address codes in each registration command is consistent. When the host checks the number of address codes of each registration command received, it determines that the slave address registration is successful. After determining that the slave address registration is successful, the host counts the number of slaves actually connected and the address information of each slave for subsequent communication use.

[0063] The host is used to send the address set of the slave to each of the slaves; the slave is also used to divide the memory according to the address set, and each memory after the division is used to store data packets with corresponding addresses; the slave is also used to output the stored data packets to the slave or host corresponding to the data packets.

[0064] It can be understood that in order to enable the host to receive data from each slave very evenly, after the address encoding of each slave is completed at the software level, the host will send the number of all slaves in the system and the address set of each slave to each slave. In this way, each slave will reserve a memory block for each slave address in its own microcontroller memory, which is specifically used to store the data of the address. Then, each time data is sent through the 485B port, it will be packaged and sent out together.

[0065] It should be noted that after the address is successfully registered, the host sends an address set containing all slave addresses to each slave. The host generates an address set (such as a list or array) based on the previously counted slave address information. The host sends the address set to each slave through the first communication interface 485A. The slave divides the memory space according to the received address set to store data packets of the corresponding address. After receiving the address set, the slave parses the address information of all slaves and divides the memory space according to the number of addresses and specific rules (allocating a fixed-size buffer for each address). The divided memory space is used to temporarily store or process data packets related to the corresponding address. The slave stores the data packet in the corresponding memory space based on the address information in the data packet and forwards the data packet to the target slave or host as needed.

[0066] Specifically, when the 485A interface of the slave receives a data packet sent by the previous slave or host, it parses the target address information in the data packet and stores the data packet in the corresponding memory space previously allocated according to the target address. If the data packet needs to be forwarded to other slaves or hosts, the slave searches for the target address according to the address set and sends the data packet to the next connected slave through the communication interface 485B. The next slave continues to do so until the data packet is sent to the slave or host with the target address.

[0067] The host is configured to receive data packets sent by each of the slaves after the slave addresses are successfully registered, and to feed back instructions corresponding to the data packets.

[0068] It is understandable that if Figure 4 As shown, the host can send data from the 485A port at any time according to its own logic, without any restrictions on arbitration, time, speed, etc. The performance depends on the chip selected by the hardware. The host receives data packets from the 485B port at any time and feeds back the instructions corresponding to the data packets.

[0069] It should be noted that the host has completed slave address registration, counted the number of slaves, and sent a set of addresses to each slave. The system enters normal communication mode, and the slaves can begin sending data packets. The slaves generate data packets based on their own sensor data, status information, or execution results, and send them to the host. The host's 485B receives the data packets sent by the slaves and parses the packet contents, extracting information such as the data content, source address, and destination address. Based on the packet content or source address, the host determines whether the packet address corresponds to the host's address. If the packet address matches the host PCU address, it generates the corresponding instructions and feeds them back to the slave or performs the corresponding operation.

[0070] The slave is used to receive the instruction output by the previous slave or host, and when it detects that the address of the instruction is consistent with its own address, parse and process the instruction; when it detects that the address of the data packet is inconsistent with its own address, output the instruction to the next slave or host.

[0071] It is understandable that if Figure 5 As shown, each slave device constantly detects its own 485A port, receives all data packets, and detects whether the address of the data packet is consistent with its own. If it is consistent, it processes the relevant data; if it is inconsistent, it sends the original data packet out from the 485B port.

[0072] It should be noted that the slave receives instructions or data packets from the previous slave or host, and the slave listens and receives instructions or data packets through the communication interface 485B. The slave detects whether the address information in the received instruction or data packet is consistent with its own address, and the slave parses the received data, extracts the address information, compares the extracted address with the address of the slave itself, and when the detected address is consistent with the slave's own address, the slave parses and processes the content in the instruction or data packet. According to the instruction type (such as control instructions, query instructions, etc.), the corresponding operation (such as charging, discharging, returning power, etc.) is performed. When the detected address is inconsistent with the slave's own address, the slave forwards the instruction or data packet to the next slave or host. The slave copies the received instruction or data packet and then sends it to the next slave or host through the communication interface 485B to ensure data integrity and accuracy during the forwarding process.

[0073] In this embodiment, each time the system is powered on or restarted, the host (PCU) will re-register the command. The host will continue to send registration commands and count until 485B receives a response from the slave. The host will check whether the coded address numbers of each registration command are consistent. If they are consistent, all slave addresses are successfully registered. The host can send data from the 485A port at any time according to its own logic. Each slave detects its own 485A port, receives all data packets, and checks whether the data packet address is consistent with its own. If they are consistent, the relevant data is processed. If not, the original data packet is sent out from the 485B port. Data transmission is free of arbitration, time, speed, and other restrictions. This solves problems such as abnormal communication delays, slow refresh speeds, inconsistent communication interference, and on-site address configuration when communicating with many slaves in parallel.

[0074] like Figure 6 As shown in FIG, this is a structural diagram of the third embodiment of the parallel energy storage charging and discharging system proposed in this embodiment.

[0075] Based on the above-mentioned first embodiment and / or second embodiment, a third embodiment of the parallel energy storage charging and discharging system of the present invention is proposed.

[0076] The battery module also includes: a power activation detection circuit and a synchronous start-up circuit; the power activation detection circuit is connected to the charging power supply and the synchronous start-up circuit, and the synchronous start-up circuit is connected to the slave; the power activation detection circuit is used to send a start signal to the synchronous start-up circuit when a charging activation signal is detected; the synchronous start-up circuit is used to control the battery packs in each battery module to connect to the charging power supply when receiving the start signal.

[0077] It is understandable that the present invention is to solve the problem of the charger outputting voltage to activate the battery (depending on the voltage difference between the bus voltage and the battery pack, Figure 7As shown in the figure, some battery packs with low voltage are activated first, which lowers the bus voltage and causes other modules to be unable to be activated. The power activation detection circuit and the synchronous start circuit are introduced. The principle is that when the slave detects the charger activation signal of the power activation detection circuit, it will not activate the battery pack immediately, but send a start signal to the synchronous start circuit. After the power activation detection circuits of all battery modules send the charger activation signal, the synchronous start circuit controls the battery packs in each battery module to connect to the charging power supply together.

[0078] like Figure 6 As shown, the synchronous start-up circuit includes: a first optocoupler 1 and a second optocoupler 2; the secondary input and secondary output of the second optocoupler are connected to the slave, the secondary input of the first optocoupler is connected to the primary output of the second optocoupler of the previous battery module or the positive electrode of the charging power supply, the secondary output of the first optocoupler is connected to the primary input of the second optocoupler, and the primary output of the second optocoupler is connected to the secondary input of the first optocoupler of the next battery module or the negative electrode of the charging power supply.

[0079] It is understood that an optocoupler (optical coupler) is a device that converts electrical signals into optical signals through the photoelectric effect. It mainly consists of two parts: a light-emitting device (such as a light-emitting diode (LED)) and a light-receiving device (such as a phototransistor, photoresistor, etc.). These two parts are usually encapsulated in the same tube shell and optically coupled through transparent insulating materials (such as optical fiber, air, etc.). When an electrical signal is applied to the primary side of the optocoupler, the light-emitting device (such as an LED) will emit light and generate a light signal. After receiving the light signal, the light-receiving device will generate a corresponding electrical signal and output it to the secondary side of the optocoupler. The optical signal is not affected by electromagnetic interference during transmission, so the optocoupler has a strong anti-interference ability.

[0080] It should be noted that when the power activation detection circuit is connected to the charging power supply, the light-emitting device diode of the first optocoupler emits light, and the light receiver of the first optocoupler is turned on. When the power activation detection circuits of all battery modules are connected to the charging power supply, the light-emitting device diode of the first optocoupler emits light, and the light receiver of the first optocoupler is turned on. Because all the light receivers of the first optocouplers and the light-emitting devices of the second optocouplers are connected in series, the light-emitting device diode of the second optocoupler is turned on, and the light receiver of the second optocoupler is turned on, so that all the battery modules are activated together.

[0081] It is understandable that after the slave detects the charger activation signal from the power activation detection circuit, it will not activate the battery pack immediately, but will turn on the Figure 6 The first optocoupler 1 in the Figure 6 The second optocoupler 2 in the system detects that all power activation detection circuits in the system have detected Figure 7After the charger activation signal of the circuit is received, the secondaries of the first optocouplers 1 in all battery modules are turned on. Then, the secondaries of all the second optocouplers 2 will give a level signal to their respective battery modules. This level signal controls the activation of the battery pack without delay. That is, all battery modules in the parallel system can open the main circuit for charging at the same time, avoiding the problem of overcurrent protection caused by uneven current due to activation problems, which may lead to some modules not opening and further damage to the device.

[0082] like Figure 7 As shown, the power activation detection circuit includes: a first resistor R1, a second resistor R2, a first transistor Q1 and a first diode D1; one end of the first resistor is connected to the negative electrode of the slave battery pack, the other end of the first resistor is connected to the base of the first transistor, the emitter of the first transistor is connected to the anode of the first diode, the cathode of the first diode is connected to the charging power supply, the emitter of the first transistor is connected to the second resistor, the other end of the second resistor is connected to the primary output end of the first optocoupler, and the primary input end of the first optocoupler is connected to the positive electrode of the charging power supply.

[0083] It should be noted that P+ and P- are bus voltages, and the battery pack is the module voltage. When the charging power supply is connected, the primary of the first optocoupler is turned on.

[0084] In this embodiment, a new power activation detection circuit and synchronous start-up circuit are added to enable simultaneous charging, thus preventing the system from being impacted by high currents. The synchronous start-up circuit detects the synchronization signal of each slave module and can be activated simultaneously, preventing the charger from charging a single module at high power and also preventing individual modules from being inactivated. When all power activation detection circuits in the system send a charger activation signal, the secondary terminals of the first optocouplers 1 in all modules are turned on, and the primaries of all the second optocouplers 2 are also turned on. The second optocouplers 2 secondaries send a level signal to their respective battery packs. This level signal is triggered by an interrupt from the microcontroller of each battery module without any delay. This means that all battery modules in the large parallel system can simultaneously open the main circuit for charging, avoiding the problem of overcurrent protection caused by uneven current due to activation problems that may cause some modules to not turn on, thereby damaging the device.

[0085] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0086] The present invention also proposes a charging and discharging device, which includes a parallel energy storage charging and discharging system. The specific structure of the device refers to the above-mentioned embodiment. Since the maintenance auxiliary prompt device adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

[0087] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformation made by utilizing the contents of the present invention's description and drawings under the technical concept of the present invention, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A parallel energy storage charging and discharging system, characterized in that: The system includes: a host and multiple battery modules; Multiple battery modules are connected in parallel; The host includes a first interface and a second interface, the first interface is connected to the first battery module in parallel, the second interface is connected to the last battery module in parallel, and the host and the parallel battery modules are connected via a 485 serial line.

2. The parallel energy storage charging and discharging system according to claim 1, characterized in that: The battery module includes: a battery pack and a slave; The battery pack is connected to the slave device, and multiple slave devices are connected together in series by hand-in-hand communication, the first slave device in the series is connected to the first interface, and the last slave device in the series is connected to the second interface; The host is configured to send a plurality of registration commands to the slave connected to the first interface when the power is turned on or restarted; The slave is configured to perform address coding in sequence according to the received registration command; and when the address coding is completed, output the coded registration command to the next connected slave.

3. The parallel energy storage charging and discharging system according to claim 2, characterized in that: The slave connected to the second interface of the host is further configured to send the encoded registration command to the host after encoding is completed; The host is used to check whether the number of address codes in each registration command is consistent. If the number of address codes is consistent, it is determined that the slave address registration is successful, and the number of slaves is counted.

4. The parallel energy storage charging and discharging system according to claim 3, characterized in that: The host is configured to send the address set of the slaves to each of the slaves; The slave device is further configured to divide memory according to the address set, and each memory after the division is used to store data packets corresponding to the address; The slave machine is further configured to output the stored data packet to the slave machine or host machine corresponding to the data packet.

5. The parallel energy storage charging and discharging system according to claim 4, characterized in that: The host is configured to receive data packets sent by each of the slaves after the slave addresses are successfully registered, and to feed back instructions corresponding to the data packets.

6. The parallel energy storage charging and discharging system according to claim 5, characterized in that: The slave is used to receive the instruction output by the previous slave or host, and when it detects that the address of the instruction is consistent with its own address, parse and process the instruction; when it detects that the address of the data packet is inconsistent with its own address, output the instruction to the next slave or host.

7. The parallel energy storage charging and discharging system according to claim 2, characterized in that: The battery module further comprises: a power activation detection circuit and a synchronous start circuit; The power activation detection circuit is connected to the charging power supply and the synchronous start circuit, and the synchronous start circuit is connected to the slave device; The power activation detection circuit is configured to send a start signal to the synchronous start circuit upon detecting a charging activation signal; The synchronous starting circuit is used to control the battery packs in each battery module to connect to the charging power supply when receiving the start signal.

8. The parallel energy storage charging and discharging system according to claim 7, characterized in that: The power activation detection circuit includes: a first resistor, a second resistor, a first transistor and a first diode; One end of the first resistor is connected to the negative electrode of the slave battery pack, the other end of the first resistor is connected to the base of the first transistor, the emitter of the first transistor is connected to the anode of the first diode, the cathode of the first diode is connected to the charging power supply, the emitter of the first transistor is connected to the second resistor, the other end of the second resistor is connected to the primary output end of the first optocoupler, and the primary input end of the first optocoupler is connected to the positive electrode of the charging power supply.

9. The parallel energy storage charging and discharging system according to claim 8, characterized in that: The synchronous start-up circuit includes: a first optocoupler and a second optocoupler; The secondary input and secondary output of the second optocoupler are connected to the slave device, the secondary input of the first optocoupler is connected to the primary output of the second optocoupler of the previous battery module or the positive electrode of the charging power supply, the secondary output of the first optocoupler is connected to the primary input of the second optocoupler, and the primary output of the second optocoupler is connected to the secondary input of the first optocoupler of the next battery module or the negative electrode of the charging power supply.

10. A charging and discharging device, characterized in that: It comprises the parallel energy storage charging and discharging system as described in any one of claims 1 to 9.

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