Preparation method of back contact solar cell and back contact solar cell

Abstract

The invention discloses a preparation method of a back contact solar cell and the back contact solar cell, and relates to the technical field of solar cell manufacturing. The method specifically comprises the following steps: preparing a p-type carrier collection layer doped with p-type doping atoms in a first region of a first main surface of a silicon substrate, and preparing an n-type carrier collection layer doped with n-type doping atoms in a second region; preparing a passivation layer containing fixed negative charges on the outer side of the p-type carrier collection layer; and preparing a passivation antireflection layer on the outer sides of the passivation layer, the spacer region and the n-type carrier collection layer, wherein the passivation antireflection layer does not contain fixed negative charges. According to the embodiment, only the passivation layer containing the fixed negative charges is prepared on the outer side of the p-type carrier collection layer, and the passivation antireflection layer without the fixed negative charges is prepared on the outer side of the n-type carrier collection layer, so that carrier recombination of the n-type second region is reduced, and the overall passivation performance and the photoelectric conversion performance of the solar cell are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell manufacturing, and in particular to a method for preparing a back-contact solar cell and a back-contact solar cell. Background Art

[0002] The positive and negative electrodes of the back-contact solar cell are both arranged on its back, and there is no metal electrode blocking the front. Therefore, the light absorption efficiency of the front of the back-contact solar cell is improved, making the back-contact solar cell have a higher conversion efficiency.

[0003] An existing back-contact solar cell mainly includes: a silicon substrate, a first main surface of the silicon substrate having alternating p-type first regions and n-type second regions, and a spacing region located between adjacent first and second regions; a p-type carrier collection layer containing p-type dopant atoms arranged on the first region; an n-type carrier collection layer containing n-type dopant atoms arranged on the second region, and an aluminum oxide (Al2O3) passivation layer arranged on the surface of the p-type carrier collection layer, the spacing region, and the n-type carrier collection layer.

[0004] In the above-mentioned back-contact solar cell, carrier recombination easily occurs in the n-type second region. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a method for preparing a back-contact solar cell and a back-contact solar cell, in which a passivation layer containing fixed negative charges is prepared only on the outside of the p-type carrier collection layer, and the passivation anti-reflection layer on the outside of the n-type carrier collection layer does not contain fixed negative charges. This can reduce carrier recombination in the n-type second region, while ensuring the passivation effect and carrier transmission capacity of the p-type first region and the n-type second region in the back-contact solar cell.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a method for preparing a back-contact solar cell, comprising:

[0008] Step 1: providing a silicon substrate, wherein a first main surface of the silicon substrate includes first regions and second regions alternately arranged, and a spacing region between adjacent first regions and second regions;

[0009] Step 2: preparing a p-type carrier collection layer doped with p-type dopant atoms in the first region, and preparing an n-type carrier collection layer doped with n-type dopant atoms in the second region;

[0010] Step 3, preparing a passivation layer containing fixed negative charges outside the p-type carrier collection layer;

[0011] Step 4: preparing a passivation anti-reflection layer on the outside of the passivation layer, the spacer region, and the n-type carrier collection layer, wherein the passivation anti-reflection layer does not contain fixed negative charges.

[0012] Optionally, step 2 includes:

[0013] Step 21, forming a p-type carrier collection layer and a p-type silicon glass layer located on the p-type carrier collection layer in the first region of the silicon substrate, and forming an n-type carrier collection layer and an n-type silicon glass layer located on the n-type carrier collection layer in the second region of the silicon substrate;

[0014] Step 22, texturing the second main surface of the silicon substrate, or texturing the surface of the silicon substrate corresponding to the spacing region and the second main surface of the silicon substrate; the second main surface is opposite to the first main surface;

[0015] Step 23 : removing the p-type silicon glass layer on the first region and the n-type silicon glass layer on the second region.

[0016] Optionally, step 21 includes:

[0017] Step 21a, preparing a first tunnel passivation layer, a p-type doped polysilicon layer, and a p-type silicon glass layer by stacking from inside to outside on the first main surface of the silicon substrate;

[0018] Step 21b, removing portions of the first tunnel passivation layer, the p-type doped polysilicon layer, and the p-type silicon glass layer corresponding to the second region and the spacer region;

[0019] Step 21c, preparing a second tunnel passivation layer, an n-type doped polysilicon layer, and an n-type silicon glass layer by stacking from inside to outside on the first main surface of the silicon substrate;

[0020] Step 21d: removing portions of the second tunneling passivation layer, the n-type doped polysilicon layer, and the n-type silicon glass layer corresponding to the first region and the spacer region.

[0021] Optionally, step 21 includes:

[0022] Step 21a′, diffusing p-type dopant atoms into the first main surface of the silicon substrate to form a p-type diffusion layer and a p-type silicon glass layer;

[0023] Step 21b′, removing the portions of the p-type diffusion layer and the p-type silicon glass layer corresponding to the second region and the spacer region;

[0024] Step 21c′, preparing a second tunnel passivation layer, an n-type doped polysilicon layer, and an n-type silicon glass layer by stacking from the inside out on the first main surface of the silicon substrate;

[0025] Step 21d′: removing portions of the second tunneling passivation layer, the n-type doped polysilicon layer, and the n-type silicon glass layer corresponding to the first region and the spacer region.

[0026] Optionally, step 3 includes:

[0027] Step 31, forming an oxide layer on the outside of the n-type carrier collection layer and the spacer region by laser oxidation;

[0028] Step 32, treating the surface of the oxide layer with a silane capping agent to remove the surface activity of the oxide layer;

[0029] Step 33 : depositing a passivation layer on the first main surface using an atomic layer deposition process to obtain a passivation layer located outside the p-type carrier collection layer, wherein the passivation layer cannot be formed on the surface-deactivated oxide layer.

[0030] Optionally, in step 33 , an aluminum source and an oxygen source are introduced to form a passivation layer; and / or, in step 33 , a gallium source and an oxygen source are introduced to form a passivation layer.

[0031] Optionally, the region of the oxide layer corresponding to the n-type carrier collection layer is subjected to a high energy density of 1 J / cm 2 ~1.50J / cm 2 obtained by laser etching.

[0032] Optionally, the surface of the silicon substrate corresponding to the spacer region is a velvet surface, and the region of the oxide layer corresponding to the spacer region is heated by an energy density of 0.02 J / cm 2 ~1J / cm 2 obtained by laser etching.

[0033] Optionally, the surface of the silicon substrate corresponding to the spacer region is a polished surface, and the region of the oxide layer corresponding to the spacer region is subjected to an energy density of 1 J / cm 2 ~1.50J / cm 2 obtained by laser etching.

[0034] Optionally, after step 33 and before step 4, the method further includes:

[0035] Step 34, annealing the oxide layer to restore the surface activity of the oxide layer;

[0036] In step 35 , the oxide layer is removed by using a laser process.

[0037] Optionally, the laser oxidation in step 31 is performed using an ultraviolet femtosecond laser.

[0038] Optionally, the silane capping agent includes one or more of bis(dimethylamino)dimethylsilane, monochlorosilane, trimethylchlorosilane, and phenyldimethylchlorosilane.

[0039] Optionally, the proportion of tetravalent silicon oxide in the oxide layer is 90% to 100%.

[0040] Optionally, the annealing temperature in step 34 is 300° C. to 500° C.

[0041] Optionally, the annealing time in step 34 is 5 min to 15 min.

[0042] Optionally, in step 35 , an ultraviolet femtosecond laser is used to implement the laser process.

[0043] Optionally, the energy density of the laser in step 35 is 2 J / cm 2 ~5J / cm 2 .

[0044] In a second aspect, the present invention provides a back-contact solar cell comprising:

[0045] A back-contact solar cell, characterized in that it includes: a silicon substrate, a first main surface of the silicon substrate including first regions and second regions alternately arranged, and a spacing region located between adjacent first regions and second regions; a p-type carrier collection layer arranged on the first region; an n-type carrier collection layer arranged on the second region; a passivation layer containing fixed negative charges arranged on the p-type carrier collection layer; and a passivation anti-reflection layer containing no fixed negative charges arranged on the passivation layer, the spacing region, and the n-type carrier collection layer.

[0046] Optionally, the p-type carrier collection layer includes: a first tunneling passivation layer disposed on the surface of the first region, and a p-type doped polysilicon layer disposed on the first tunneling passivation layer.

[0047] Optionally, the p-type carrier collection layer includes: a p-type diffusion layer arranged inside the silicon substrate corresponding to the first region.

[0048] Optionally, the n-type carrier collection layer includes: a second tunneling passivation layer disposed on the surface of the second region, and an n-type doped polysilicon layer disposed on the second tunneling passivation layer.

[0049] Optionally, the n-type carrier collection layer includes: an n-type diffusion layer arranged inside the silicon substrate corresponding to the second region.

[0050] Optionally, the passivation layer is at least one of an aluminum oxide layer and a gallium oxide layer.

[0051] Optionally, the first tunnel passivation layer is a silicon oxide layer.

[0052] Optionally, the second tunneling passivation layer is a silicon oxide layer.

[0053] Optionally, the passivation anti-reflection layer is at least one of a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer.

[0054] Optionally, the passivation anti-reflection layers in the first region, the second region, and the spacer region are an integrated structure.

[0055] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects: a passivation layer containing fixed negative charges is prepared only on the outside of the p-type carrier collection layer, and the passivation anti-reflection layer on the outside of the n-type carrier collection layer does not contain fixed negative charges, which can reduce carrier recombination in the n-type region while ensuring the passivation effect and carrier transport capacity of the p-type first region and the n-type second region in the back-contact solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings are provided for a better understanding of the present invention and are not intended to limit the present invention.

[0057] Figure 1 is a schematic flow chart of a method for preparing a back-contact solar cell according to an embodiment of the present invention;

[0058] Figure 2 is a schematic cross-sectional structure diagram of a back-contact solar cell according to an embodiment of the present invention;

[0059] Figure 3 is a schematic flow chart of step S102 according to an embodiment of the present invention;

[0060] Figure 4 is a flowchart of an implementation method of step S301 according to an embodiment of the present invention;

[0061] Figure 5 is a schematic diagram of the cross-sectional structure of the silicon substrate prepared after step S402 according to an embodiment of the present invention;

[0062] Figure 6 is a schematic diagram of the cross-sectional structure of the silicon substrate prepared after step S404 according to an embodiment of the present invention;

[0063] Figure 7 is a flowchart of another implementation of step S301 according to an embodiment of the present invention;

[0064] Figure 8 is a schematic diagram of the cross-sectional structure of the silicon substrate prepared after step S302 according to an embodiment of the present invention;

[0065] Figure 9 is a schematic diagram of the cross-sectional structure of the silicon substrate prepared after step S303 according to an embodiment of the present invention;

[0066] Figure 10is a schematic diagram of a specific flow chart of step S103 according to an embodiment of the present invention;

[0067] Figure 11 is a schematic diagram of a cross-sectional structure of a silicon substrate with an oxide layer formed thereon according to an embodiment of the present invention;

[0068] Figure 12 is a schematic diagram of the cross-sectional structure of the silicon substrate prepared after step S1003 according to an embodiment of the present invention;

[0069] Figure 13 is a simplified schematic diagram of a cross-sectional structure of a silicon substrate having a p-type carrier collection layer and an n-type carrier collection layer according to an embodiment of the present invention;

[0070] Figure 14 is a simplified schematic cross-sectional view of a silicon substrate obtained after step 1001 according to an embodiment of the present invention;

[0071] Figure 15 is a simplified schematic cross-sectional view of a silicon substrate obtained after step 1002 according to an embodiment of the present invention;

[0072] Figure 16 is a simplified schematic cross-sectional view of a silicon substrate obtained after step 1003 according to an embodiment of the present invention;

[0073] Figure 17 FIG. 1 is a simplified schematic cross-sectional view of a silicon substrate obtained after step 1005 according to an embodiment of the present invention.

[0074] The reference numerals are as follows:

[0075] 1-silicon substrate; 11-first tunneling passivation layer; 12-p-type doped polysilicon layer; 13-p-type silicon glass layer; 2-p-type carrier collection layer; 21-second tunneling passivation layer; 22-n-type doped polysilicon layer; 23-n-type silicon glass layer; 3-n-type carrier collection layer; 4-passivation layer; 5-passivation anti-reflection layer; 6-oxide layer;

[0076] 100-first area; 200-second area; 300-interval area. DETAILED DESCRIPTION

[0077] For the purpose of conveniently and clearly describing the method for preparing a solar cell and the solar cell of the present invention, exemplary embodiments of the present invention are described below with reference to the accompanying drawings. Various details of the embodiments of the present invention are included to facilitate understanding, but these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present invention.

[0078] A back-contact solar cell is a type of solar cell in which both the positive and negative electrodes are placed on the backlit side. This design can reduce the shading of the electrodes on the front (light-receiving side) of the cell and increase the current of the solar cell.

[0079] Currently, a common back-contact solar cell mainly includes: a silicon substrate, a first main surface of the silicon substrate having alternating p-type first regions and n-type second regions, and a spacing region located between adjacent first and second regions; a p-type carrier collection layer containing p-type dopant atoms arranged on the first region; an n-type carrier collection layer containing n-type dopant atoms arranged on the second region, and an aluminum oxide (Al2O3) passivation layer arranged on the surface of the p-type carrier collection layer, the spacing region and the n-type carrier collection layer.

[0080] However, the back-contact solar cell structure described above is prone to carrier recombination in the n-type second region. Research and analysis revealed that the main reasons for carrier recombination in the n-type second region include: first, the aluminum oxide passivation layer contains fixed negative charges, which provides a good passivation effect for the p-type first region; however, for the n-type second region, the minority carriers in the n-type second region are holes (positive charges). Placing an aluminum oxide passivation layer containing fixed negative charges on the surface of the n-type second region is equivalent to introducing an additional minority carrier recombination path; second, placing an aluminum oxide passivation layer on the p-type carrier collection layer, the spacer region, and the n-type carrier collection layer causes a small amount of carriers to be transported laterally, leading to recombination of carriers of opposite polarity and resulting in leakage short circuits.

[0081] Based on the above, an embodiment of the present invention provides a method for preparing a back-contact solar cell and a corresponding back-contact solar cell, in which a passivation layer containing fixed negative charges is provided only on the p-type carrier collection layer, and the passivation anti-reflection layer located in the spacing region and the n-type carrier collection layer does not contain fixed negative charges, thereby solving the influence of the passivation layer containing fixed negative charges on the n-type second region.

[0082] In one embodiment of the present invention, Figure 1 As shown, this embodiment provides a method for preparing a back-contact solar cell, which may include the following steps:

[0083] Step S101 , providing a silicon substrate 1 , wherein a first main surface of the silicon substrate 1 includes first regions 100 and second regions 200 alternately arranged, and a spacing region 300 located between adjacent first regions 100 and second regions 200 ;

[0084] Step S102 , preparing a p-type carrier collection layer 2 doped with p-type dopant atoms in the first region 100 , and preparing an n-type carrier collection layer 3 doped with n-type dopant atoms in the second region 200 ;

[0085] Step S103, preparing a passivation layer 4 containing fixed negative charges on the outside of the p-type carrier collection layer 2;

[0086] Step S104 , forming a passivation anti-reflection layer 5 on the outside of the passivation layer 4 , the spacing region 300 , and the n-type carrier collection layer 3 , wherein the passivation anti-reflection layer 5 does not contain fixed negative charges.

[0087] For example, the cross-sectional structure of the back contact solar cell prepared after step S104 is as follows: Figure 2 As shown. Figure 1 and Figure 2 It can be seen that in the embodiment of the present invention, a passivation layer 4 containing fixed negative charges is only prepared on the outside of the p-type carrier collection layer 2, while the passivation anti-reflection layer 5 on the spacer region 300 and on the outside of the n-type carrier collection layer 3 is a passivation anti-reflection layer 5 that does not contain fixed negative charges. Compared to the prior art method of simultaneously preparing a passivation layer 4 containing fixed negative charges on the outside of the p-type carrier collection layer 2 and the n-type carrier collection layer 3, the back-contact solar cell obtained using the preparation method provided by the embodiment of the present invention not only avoids the short circuit problem caused by the lateral transmission of carriers of opposite polarity by the passivation layer 4 on the outside of the n-type carrier collection layer 3, but also reduces the carrier recombination path, thereby increasing the overall passivation performance and photoelectric conversion efficiency of the solar cell.

[0088] In the embodiment of the present invention, in step S101, the silicon substrate 1 can be a p-type single crystal silicon wafer or a polycrystalline silicon wafer. Alternatively, it can be an n-type single crystal silicon wafer or a polycrystalline silicon wafer. The silicon substrate 1 can be obtained by cleaning, texturing, double-sided polishing, etc. the silicon wafer.

[0089] In the embodiment of the present invention, Figure 3 As shown, step S102 may specifically include the following steps:

[0090] Step S301: forming a p-type carrier collection layer 2 and a p-type silicon glass layer 13 on the p-type carrier collection layer 2 in the first region 100 of the silicon substrate 1, and forming an n-type carrier collection layer 3 and an n-type silicon glass layer 23 on the n-type carrier collection layer 3 in the second region 200 of the silicon substrate 1;

[0091] Step S302 , texturing the second main surface of the silicon substrate 1 , or texturing the silicon substrate surface corresponding to the spacing region 300 and the second main surface of the silicon substrate 1 ; the second main surface is opposite to the first main surface;

[0092] Step S303 : removing the p-type silicon glass layer 13 on the first region 100 and the n-type silicon glass layer 23 on the second region 200 .

[0093] In an embodiment of the present invention, in step S301, the p-type carrier collection layer 2 and the p-type silicon glass layer 13 can be prepared first, and then the n-type carrier collection layer 3 and the n-type silicon glass layer 23 are prepared; or the n-type carrier collection layer 3 and the n-type silicon glass layer 23 can be prepared first, and then the p-type carrier collection layer 2 and the p-type silicon glass layer 13 are prepared.

[0094] Typically, a p-type carrier collection layer 2 is prepared on the first main surface of the silicon substrate 1 first and then the n-type carrier collection layer 3 is prepared. This is because the temperature required for the p-type carrier collection layer 2 during the preparation process is usually higher than the temperature required for the n-type carrier collection layer 3. If the n-type carrier collection layer 3 is prepared first, the high temperature process during the subsequent preparation of the p-type carrier collection layer 2 may damage the n-type carrier collection layer 3.

[0095] Currently, the common structures of the p-type carrier collection layer 2 may include the following two forms: one is as follows Figure 2 As shown, it includes a first tunnel passivation layer 11 disposed on the surface of the first region 100, and a p-type doped polysilicon layer 12 disposed on the first tunnel passivation layer 11; the other is a p-type diffusion layer (not shown) disposed inside the silicon substrate corresponding to the first region 100. The common structure of the n-type carrier collection layer 3 can also include the following two forms: one is as follows Figure 2 As shown, there is a second tunneling passivation layer 21 arranged on the surface of the second region 200, and an n-type doped polysilicon layer 22 arranged on the second tunneling passivation layer 21; the other is an n-type diffusion layer (not shown in the figure) arranged inside the silicon substrate corresponding to the second region 200.

[0096] Depending on the structure of the carrier collection layer, the above step 301 may include the following specific implementations.

[0097] In an optional embodiment, as Figure 4 As shown, step 301 specifically includes:

[0098] In step S401 , a first tunnel passivation layer 11 , a p-type doped polysilicon layer 12 and a p-type silicon glass layer 13 are stacked from the inside out on a first main surface of a silicon substrate 1 .

[0099] The first tunneling passivation layer 11 may be a silicon oxide layer or another film layer capable of achieving a carrier tunneling effect. The p-type doped polysilicon layer 12 may be formed by diffusing p-type dopant atoms from a pre-prepared intrinsic polysilicon layer. Because the diffusion process typically involves a high preparation temperature, an oxide layer containing p-type dopant atoms (i.e., a p-type silica glass layer 13) forms on the surface of the p-type doped polysilicon layer 12 in contact with air. In this case, the p-type silica glass layer 13 is formed simultaneously during the preparation of the p-type doped polysilicon layer 12. When the p-type dopant atom is boron, the p-type silica glass layer 13 is a borosilicate glass layer (BSG).

[0100] Step S402 : removing portions of the first tunneling passivation layer 11 , the p-type doped polysilicon layer 12 , and the p-type silicon glass layer 13 corresponding to the second region 200 and the spacer region 300 .

[0101] The cross-sectional structure of the silicon substrate obtained after the above steps S401 and S402 is as follows: Figure 5 As shown, since the stacked structure of the second region 200 and the spacer region 300 is removed, a structure in which only the first tunnel passivation layer 11 , the p-type doped polysilicon layer 12 and the p-type silicon glass layer 13 are stacked in the first region 100 is obtained.

[0102] In step S403 , a second tunnel passivation layer 21 , an n-type doped polysilicon layer 22 and an n-type silicon glass layer 23 are stacked on the first main surface of the silicon substrate 1 from the inside out.

[0103] The second tunneling passivation layer 21 can be a silicon oxide layer or other film layer capable of achieving a carrier tunneling effect. The n-type doped polysilicon layer 22 can also be obtained by diffusing n-type dopant atoms from a pre-prepared intrinsic polysilicon layer. Because the preparation temperature is typically high during the diffusion process, an oxide layer (i.e., n-type silica glass layer 23) forms on the surface of the n-type doped polysilicon layer 22 in contact with air. Therefore, the n-type silica glass layer 23 can also be formed simultaneously during the preparation of the n-type doped polysilicon layer 22. When the n-type dopant atom is phosphorus, the n-type silica glass layer 23 is a phosphorus silicate glass (PSG) layer.

[0104] Step S404 , removing portions of the second tunneling passivation layer 21 , the n-type doped polysilicon layer 22 , and the n-type silicon glass layer 23 corresponding to the first region 100 and the spacer region 300 .

[0105] The cross-sectional structure of the silicon substrate obtained after the above steps S403 and S404 is as follows: Figure 6 shown.

[0106] In an embodiment of the present invention, the process of removing the film structure on the second region 200 and the spacer region 300 in step S402 can be achieved by using a laser etching process combined with alkaline solution cleaning. Because the laser process can achieve regionalized removal, the p-type silica glass layer 13 corresponding to the second region 200 and the spacer region 300 can first be converted to a molten state by the laser process, and then cleaned with an alkaline solution (such as a sodium hydroxide solution or a potassium hydroxide solution) or an acid solution (such as a hydrofluoric acid solution) to achieve removal of the first tunneling passivation layer 11, the p-type doped polysilicon layer 12, and the p-type silica glass layer 13 in the second region 200 and the spacer region 300. Specifically, due to the high hardness of the p-type silicon glass layer 13, a high laser power is generally required to remove it. High-energy laser processes inevitably cause some damage to the structures stacked on the inner side of the p-type silicon glass layer 13. Therefore, in the embodiment of the present invention, the laser process preferably etches to a depth corresponding to the p-type doped polysilicon layer 12. This allows the p-type doped polysilicon layer 12 and the first tunneling passivation layer 11 to absorb the laser energy, thereby reducing the laser damage to the silicon substrate 1 itself. At the same time, subsequent cleaning with an alkaline solution can simultaneously remove the laser-damaged p-type doped polysilicon layer 12 and the first tunneling passivation layer 11.

[0107] In addition, when the first tunneling passivation layer 11, the p-type doped polysilicon layer 12 and the p-type silicon glass layer 13 are prepared on the first main surface of the silicon substrate 1, wrap-around plating will occur on the second main surface, that is, the first tunneling passivation layer 11, the p-type doped polysilicon layer 12 and the p-type silicon glass layer 13 will be simultaneously wrap-around plated onto the second main surface of the silicon substrate 1. Therefore, in an optional embodiment, before step S103, the wrap-around plating structure on the second main surface of the silicon substrate 1 can be removed by a single-sided chemical etching process to ensure that the second main surface of the silicon substrate 1 is still an exposed silicon substrate 1.

[0108] In step S404, a laser process is also required to remove the regionalized n-type silica glass layer 23. Specifically, similar to the aforementioned step of removing the p-type silica glass layer 13, a laser etching process can be used in conjunction with alkaline solution cleaning to remove the second tunneling passivation layer 21, the n-type doped polysilicon layer 22, and the n-type silica glass layer 23 in the first region 100 and the spacing region 300. For example, the n-type silica glass layer 23 corresponding to the first region 100 and the spacing region 300 is first converted to a molten state by a laser process, and then cleaned with an alkaline solution to remove the second tunneling passivation layer 21, the n-type doped polysilicon layer 22, and the n-type silica glass layer 23 in the first region 100 and the spacing region 300.

[0109] Similarly, when preparing the second tunneling passivation layer 21, the n-type doped polysilicon layer 22 and the n-type silicon glass layer 23 on the first main surface of the silicon substrate 1, wrap-around plating will also occur on the second main surface, that is, the second tunneling passivation layer 21, the n-type doped polysilicon layer 22 and the n-type silicon glass layer 23 will be simultaneously wrap-around plated onto the second main surface of the silicon substrate 1. Therefore, before step S302, the wrap-around plating structure on the second main surface of the silicon substrate 1 can also be removed by a single-sided chemical etching process to ensure that the second main surface of the silicon substrate 1 is still an exposed silicon substrate 1.

[0110] In another optional embodiment, as Figure 7 As shown, step S301 specifically includes:

[0111] Step S701 : diffusing p-type dopant atoms into the first main surface of the silicon substrate 1 to form a p-type diffusion layer and a p-type silicon glass layer 13 .

[0112] It can be understood that the p-type diffusion layer is formed inside the silicon substrate 1 .

[0113] Taking boron atom doping as an example, boron trichloride gas can be used as a boron source to diffuse boron atoms into the silicon substrate 1 in a tubular diffusion furnace, forming a p-type diffusion layer. Typically, while forming the p-type diffusion layer, a silicon oxide layer containing p-type dopant atoms, namely, a p-type silicon glass layer 13, is also formed on the p-type diffusion layer. For boron atom diffusion, the p-type silicon glass layer 13 is a borosilicate glass layer (BSG).

[0114] Step S702 : removing portions of the p-type diffusion layer and the p-type silicon glass layer 13 corresponding to the second region 200 and the spacer region 300 .

[0115] The p-type silicon glass layer 13 corresponding to the second region 200 and the spacer region 300 can be first transformed into a molten state by a laser process, and then cleaned with an acid solution or an alkaline solution to remove the p-type silicon glass layer 13 and the p-type diffusion layer corresponding to the second region 200 and the spacer region 300.

[0116] In step S701, p-type doping atoms can be performed on both the first main surface and the second main surface of the silicon substrate 1, and a p-type silicon glass layer 13 is formed on both sides of the silicon substrate 1. Then, the p-type silicon glass layer 13 corresponding to the second region 200 and the spacing region 300 is removed by laser, and then the p-type silicon glass layer on the second main surface is removed by acid solution. Thereafter, an alkaline solution is used to remove the p-type diffusion layer on the second main surface and the p-type diffusion layer corresponding to the second region 200 and the spacing region 300.

[0117] In step S703 , a second tunnel passivation layer 21 , an n-type doped polysilicon layer 22 and an n-type silicon glass layer 23 are stacked on the first main surface of the silicon substrate 1 from the inside out.

[0118] Step S704 , removing portions of the second tunneling passivation layer 21 , the n-type doped polysilicon layer 22 , and the n-type silicon glass layer 23 corresponding to the first region 100 and the spacer region 300 .

[0119] In an embodiment of the present invention, in step 301, ion implantation can be used to implant p-type dopant atoms into the silicon substrate corresponding to the first region 100 and n-type dopant atoms into the silicon substrate corresponding to the second region 200, and then high-temperature annealing is performed to activate the p-type dopant atoms and the n-type dopant atoms to form a p-type diffusion layer arranged inside the silicon substrate corresponding to the first region 100 and an n-type diffusion layer arranged inside the silicon substrate corresponding to the second region 200.

[0120] The back-contact solar cell obtained after the above-mentioned step S301 has a p-type carrier collection layer 2 and a p-type silicon glass layer 13 provided on the first region 100 of the first main surface of the silicon substrate 1, and an n-type carrier collection layer 3 and an n-type silicon glass layer 23 provided on the second region 200 of the first main surface of the silicon substrate 1; at the same time, the spacing region 300 of the first main surface of the silicon substrate 1 and the second main surface of the silicon substrate 1 are exposed silicon substrates. On this basis, step S302 is performed to perform a texturing treatment on the second main surface of the silicon substrate 1, or the spacing region 300 of the second main surface and the first main surface, using an alkaline solution. It can be understood that, in the embodiment of the present invention, the surface of the spacing region 300 can be a velvet surface or a polished surface. After texturing, step S303 is performed to remove the remaining p-type silicon glass layer 13 and n-type silicon glass layer 23 in the first region 100 and the second region 200.

[0121] For example, the cross-sectional structure of the silicon substrate obtained after the spacing region 300 and the second main surface are textured in step S302 is as follows: Figure 8 As shown, the cross-sectional structure of the silicon substrate obtained after step S303 is as follows Figure 9 As shown. Figure 8 It can be seen that after step S302, there are still n-type silicon glass layers 23 and p-type silicon glass layers 13 on the side of the p-type first region and n-type second region of the silicon substrate 1 that have not been cleared. Therefore, during the alkaline solution texturing process, the n-type silicon glass layer 23 and the p-type silicon glass layer 13 can effectively protect the carrier collection layer corresponding to the p-type first region and the n-type second region to prevent the carrier collection layer from reacting with the alkaline solution. Furthermore, in step S303, the remaining n-type silicon glass layer 23 and the p-type silicon glass layer 13 on the outside of the p-type doped polysilicon layer 12 and the n-type doped polysilicon layer 22 can be removed by a chemical etching process, thereby completing the preparation process of the basic structure of the p-type first region and the n-type second region of the silicon substrate 1.

[0122] The specific preparation method of the present invention for preparing the passivation layer 4 containing fixed negative charges only on the outside of the p-type carrier collection layer 2 in step S103 may include multiple methods. In an optional embodiment, for example, Figure 10 As shown, step S103 specifically includes:

[0123] Step S1001 , forming an oxide layer 6 on the outside of the n-type carrier collection layer 3 and the spacer region 300 by laser oxidation;

[0124] Step S1002, treating the surface of the oxide layer 6 with a silane capping agent to remove the surface activity of the oxide layer 6;

[0125] In step S1003 , a passivation layer 4 is deposited on the first main surface by an atomic layer deposition process to obtain a passivation layer 4 located outside the p-type carrier collection layer 2 . The passivation layer 4 cannot be formed on the surface-deactivated oxide layer 6 .

[0126] Among them, when the n-type carrier collection layer 3 includes an n-type doped polysilicon layer 22, the outermost layer of the n-type carrier collection layer 3 is the n-type doped polysilicon layer 22; when the n-type carrier collection layer 3 includes an n-type diffusion layer, the outermost layer of the n-type carrier collection layer 3 is the silicon substrate 1; at the same time, the surface of the spacing region 300 is the silicon substrate 1. It can be seen that the surface of the n-type carrier collection layer 3 and the surface of the spacing region 300 both have silicon atoms. Based on this step S1001, after laser oxidation, an oxide layer 6 can be effectively formed based on the existing silicon atoms and the introduced oxygen, as shown in FIG. Figure 11 As shown. Since there are multiple hydroxyl functional groups on the surface of the oxide layer 6, in order to prepare the passivation layer 4 only in the first p-type region, the embodiment of the present invention uses a silane capping agent to treat the hydroxyl functional groups on the surface of the oxide layer 6, so that the silane capping agent reacts chemically with the hydroxyl functional groups to form a uniform silane group covering layer on the surface of the oxide layer 6, thereby changing the surface properties of the oxide layer 6, making it impossible for the subsequent passivation layer 4 to adhere smoothly, that is, after step S1003, Figure 12 Schematic diagram of the cross-sectional structure of the silicon substrate shown.

[0127] In order to clearly illustrate the chemical changes between the silane capping agent and the oxide layer 6, the embodiment of the present invention further uses Figures 13 to 16 Steps S1001 to S1003 are described. Figure 13 This is a simplified schematic diagram of the cross-sectional structure of the silicon substrate having the p-type carrier collection layer 2 and the n-type carrier collection layer 3 obtained after completing step S101 and step S102. Figure 14 is a simplified schematic diagram of the cross section of the silicon substrate obtained after step 1001. Figure 15is a simplified schematic diagram of the cross section of the silicon substrate obtained after step 1002. Figure 16 FIG. 1 is a simplified schematic diagram of the cross section of the silicon substrate obtained after step 1003. Figures 14 to 16 It can be seen that the embodiment of the present invention uses a silane capping agent to chemically treat the surface of the oxide layer 6, so that the surface of the oxide layer 6 does not have the deposition conditions for depositing the passivation layer 4, thereby achieving the effect of depositing the passivation layer 4 only on the outside of the p-type carrier collection layer 2.

[0128] In an optional embodiment, laser oxidation is performed using an ultraviolet femtosecond laser with a wavelength of 300 nm to 400 nm, preferably 355 nm. The silane capping agent may include one or more of bis(dimethylamino)dimethylsilane, monochlorosilane, trimethylchlorosilane, and phenyldimethylchlorosilane.

[0129] It should be noted that, in the process of generating the oxide layer 6, by controlling different laser powers, coverage with different densities of hydroxyl functional groups can be achieved, thereby further controlling the adhesion effect of the passivation layer 4. For example, when the number of hydroxyl groups is large or the density is large, a relatively dense silane group coverage layer will be formed after the action of the silane capping agent, so that during the deposition process of the passivation layer 4, the deposition of the passivation layer 4 outside the n-type carrier collection layer 3 and outside the spacing region 300 can be effectively avoided. If the number of hydroxyl groups is small or the density is small, partial gaps may appear, so that part of the passivation layer 4 is still deposited outside the n-type carrier collection layer 3 and the spacing region 300. Therefore, the embodiment of the present invention specifically defines the morphology of the surface of the silicon substrate 1 corresponding to the n-type carrier collection layer 3 and the spacing region 300, that is, in an optional embodiment, the surface of the n-type carrier collection layer 3 is a polished surface, and the surface of the silicon substrate 1 corresponding to the spacing region 300 is a polished surface or a velvet surface. For different surface morphologies, the energy density of the laser oxidation used is also different. That is, in a further optional embodiment, the region of the oxide layer 6 corresponding to the n-type carrier collection layer 3 is oxidized by an energy density of 1 J / cm 2 ~1.50J / cm 2 Laser etching is obtained, for example, 1 J / cm 2 , 1.1 0J / cm 2 , 1.20J / cm 2 , 1.30J / cm 2 , 1.40J / cm 2 , 1.50J / cm 2 In the case where the surface of the silicon substrate 1 corresponding to the spacing region 300 is suede, the oxide layer 6 corresponding to the spacing region 300 passes through the energy density of 0.02 J / cm 2 ~1J / cm 2Laser etching is obtained, for example, 0.02 J / cm 2 , 0.04J / cm 2 , 0.051J / cm 2 , 0.061J / cm 2 , 0.081J / cm 2 , 0.1J / cm 2 , 0.2J / cm 2 , 0.4J / cm 2 , 0.5J / cm 2 , 0.6J / cm 2 , 0.8J / cm 2 , 1J / cm 2 In the case where the surface of the silicon substrate 1 corresponding to the spacing region 300 is a polished surface, the region of the oxide layer 6 corresponding to the spacing region 300 is heated by an energy density of 1 J / cm 2 ~1.50J / cm 2 Laser etching is obtained, for example, 1 J / cm 2 , 1.10 J / cm 2 , 1.20J / cm 2 , 1.30 J / cm 2 , 1.40J / cm 2 , 1.50J / cm 2 It is understandable that when the surface of the silicon substrate 1 corresponding to the spacing region 300 is a suede surface, excessive laser energy will affect the pyramidal morphology of the suede surface. Therefore, compared with the polished surface, the laser energy required for the pyramidal morphology of the suede surface is lower.

[0130] Specifically, the process of treating the oxide layer 6 with a silane capping agent in step S1002 of this embodiment of the present invention may specifically include: placing the silicon substrate prepared with the oxide layer 6 into a chamber, controlling the chamber temperature to 100°C to 150°C and the pressure to 1 Torr while introducing the silane capping agent, and reacting for 10 to 20 minutes. After hydroxyl functionalization, the chamber is purged with 600 sccm of high-purity N2 for 60 to 80 seconds to remove the silane capping agent and reaction byproducts physically adsorbed on the surface. The substrate is then exposed to dimethoxymethylsilane (DMMS) vapor at a chamber pressure of 1 Torr for 10 to 20 minutes, and purged with 600 sccm of high-purity N2 for 60 to 80 seconds. After the purge is complete, the chamber pressure is restored to ambient pressure, and the silicon substrate is removed from the chamber.

[0131] In an optional embodiment, the passivation layer 4 may be an aluminum oxide layer. The specific deposition process is as follows: a silicon substrate treated with a silane-terminated reagent is placed in an atomic layer deposition chamber, and an oxide layer is deposited while introducing an oxygen source (e.g., ozone), wherein the amount of ozone is 8000 sccm, the reaction temperature is 200°C, and the reaction time is 100 seconds. The chamber is then purged with N2 for 60 to 80 seconds, and an aluminum source and an oxygen source are alternately introduced into the chamber through multiple deposition cycles, maintaining the chamber temperature at a stable 260°C. The aluminum source is introduced for 4 seconds at a flow rate of 2000 sccm, and the oxygen source is introduced for 6 seconds at a flow rate of 10,000 sccm, ultimately resulting in a deposited aluminum oxide layer with a thickness of 5 nm.

[0132] The passivation layer 4 may also be a gallium oxide layer or a stacked structure of an aluminum oxide layer and a gallium oxide layer. In step 1003, an aluminum source and an oxygen source may be introduced to form a single aluminum oxide layer as the passivation layer 4, a gallium source and an oxygen source may be introduced to form a single gallium oxide layer as the passivation layer 4, or an aluminum source and a gallium source may be introduced separately to form an aluminum oxide / gallium oxide stacked structure as the passivation layer 4.

[0133] In a further optional embodiment, the ratio of silicon oxide to silicon atoms in the oxide layer 6 is 90% to 100%. Through the above process, the ratio of tetravalent silicon atoms in the oxide layer 6 can be effectively controlled, thereby achieving control over the number and density of hydroxyl functional groups.

[0134] It is understandable that after the passivation layer 4 is deposited, the oxide layer 6 on which the silane group covering layer is deposited needs to be removed. That is, in an optional embodiment, after step S1003 and before step S104, the following steps are further included:

[0135] Step S1004, annealing the oxide layer 6 to restore the surface activity of the oxide layer 6;

[0136] Step S1005 , removing the oxide layer 6 by using a laser process.

[0137] In an optional embodiment, the annealing temperature in step S1004 is 300°C to 500°C, such as 300°C, 400°C, 500°C, etc. The annealing time is 5min to 15min, such as 5min, 10min, 15min, etc. Through high temperature annealing, the silane capping agent will decompose, thereby restoring the surface activity of the oxide layer 6 and obtaining Figure 17 Schematic diagram of the cross-sectional structure of the silicon substrate shown.

[0138] In a further optional embodiment, an ultraviolet femtosecond laser is used to implement the laser process in step S1005, and the energy density of the laser is 2 J / cm 2 ~5J / cm2 , for example 2 J / cm 2 , 3 J / cm 2 , 4 J / cm 2 , 5 J / cm 2 wait.

[0139] In addition to the above-mentioned method of steps S1001 to S1005, in actual application, the purpose of regional preparation of the passivation layer 4 can also be achieved by preparing a mask. However, it requires multiple process flows such as mask preparation, passivation layer 4 deposition and mask removal, which is more complicated than the above-mentioned steps S1001 to S1005. Therefore, the process of steps S1001 to S1005 is a preferred embodiment of the present invention.

[0140] In an embodiment of the present invention, after the passivation layer 4 is prepared, a passivation anti-reflection layer 5 can be formed on the surface of the passivation layer 4, the surface of the spacer region 300, and the surface of the n-type carrier collection layer 3 by chemical vapor deposition (e.g., low-pressure chemical vapor deposition (PECVD)). The passivation anti-reflection layer 5 can be one or more of silicon nitride, silicon oxide, and silicon oxynitride. The passivation anti-reflection layer 5 can contain fixed positive charges to better passivate the n-type carrier collection layer 3. In an embodiment of the present invention, in step 1005, only the oxide layer 6 on the surface of the spacer region 300 can be removed, retaining the oxide layer on the surface of the n-type carrier collection layer 3 as part of the passivation anti-reflection layer 5.

[0141] In the embodiment of the present invention, the passivation anti-reflection layer 5 can be prepared on both main surfaces of the silicon substrate 1 at the same time.

[0142] After the passivation anti-reflection layer 5 is prepared, an electrode paste (such as silver paste) can be printed on the passivation anti-reflection layer 5 by screen printing, and then sintered at a high temperature to form metal electrodes that are in ohmic contact with the p-type carrier collection layer 2 and the n-type carrier collection layer 3 respectively.

[0143] In summary, the method for preparing a back-contact solar cell provided in an embodiment of the present invention only prepares a passivation layer 4 containing a fixed negative charge on the outside of the p-type carrier collection layer, and the passivation anti-reflection layer located in the spacing area and on the n-type carrier collection layer does not contain a fixed negative charge, thereby solving the influence of the passivation layer containing a fixed negative charge on the second n-type area, and improving the overall passivation performance and photoelectric conversion performance of the solar cell.

[0144] Below is still Figure 2The back-contact solar cell provided by the present invention is described by taking an example. Specifically, the solar cell provided by the present invention includes: a silicon substrate 1; wherein the first main surface of the silicon substrate 1 includes alternating first regions 100, second regions 200 and spacing regions 300 located between adjacent first regions 100 and second regions 200; a p-type carrier collection layer 2 provided on the first region 100; an n-type carrier collection layer 3 provided on the second region 200; a passivation layer 4 containing fixed negative charges provided on the p-type carrier collection layer 2; and a passivation anti-reflection layer 5 containing no fixed negative charges provided on the passivation layer 4, the spacing region 300 and the n-type carrier collection layer 3.

[0145] An n-type silicon wafer with a resistivity of 0.5-2Ω·m can be used as the silicon substrate 1. The first main surface of the silicon substrate 1 can be the back surface of the silicon substrate 1, and the second main surface can be the front surface of the silicon substrate 1.

[0146] In the embodiment of the present invention, the p-type carrier collection layer 2 may include: a first tunneling passivation layer 11 disposed on the surface of the first region 100, and a p-type doped polysilicon layer 12 disposed on the first tunneling passivation layer 11; or, it may include a p-type diffusion layer disposed within the silicon substrate corresponding to the first region 100. The n-type carrier collection layer 3 may include: a second tunneling passivation layer 21 disposed on the surface of the second region 200, and an n-type doped polysilicon layer 22 disposed on the second tunneling passivation layer 2; or, it may include an n-type diffusion layer disposed within the silicon substrate corresponding to the second region 200.

[0147] In an optional embodiment, the p-type carrier collection layer includes a first tunneling passivation layer 11 arranged on the surface of the first region 100, and a p-type doped polysilicon layer 12 arranged on the first tunneling passivation layer 11, and the n-type carrier collection layer 3 may include: a second tunneling passivation layer 21 arranged on the surface of the second region 200, and an n-type doped polysilicon layer 22 arranged on the second tunneling passivation layer 2.

[0148] In another optional embodiment, the p-type carrier collection layer includes a p-type diffusion layer arranged inside the silicon substrate corresponding to the first region 100, and the n-type carrier collection layer 3 may include: a second tunneling passivation layer 21 arranged on the surface of the second region 200, and an n-type doped polysilicon layer 22 arranged on the second tunneling passivation layer 2.

[0149] In another optional embodiment, the p-type carrier collection layer includes a p-type diffusion layer disposed inside the silicon substrate corresponding to the first region 100 , and the n-type carrier collection layer includes an n-type diffusion layer disposed inside the silicon substrate corresponding to the second region 200 .

[0150] In the embodiment of the present invention, the passivation layer 4 may be at least one of an aluminum oxide layer and a gallium oxide layer. It may be a single aluminum oxide layer, a single gallium oxide layer, or a stacked structure of aluminum oxide and gallium oxide layers. The thickness of the passivation layer 4 may be 3 nm to 6 nm, for example, 3 nm, 4 nm, 5 nm, 6 nm, etc.

[0151] The first tunnel passivation layer 11 may be a silicon oxide layer, and the second tunnel passivation layer 21 may be a silicon oxide layer.

[0152] The passivation anti-reflection layer 5 may contain fixed positive charges and may be at least one of silicon nitride, silicon oxynitride, and silicon oxide. The passivation anti-reflection layer 5 may have a thickness of 75 nm to 85 nm, such as 75 nm, 76 nm, 78 nm, 80 nm, 82 nm, 84 nm, and 85 nm.

[0153] The passivation anti-reflection layer 5 in the first region 100, the second region 200, and the spacer region 300 may be an integral structure, i.e., the passivation anti-reflection layers 5 corresponding to the three regions have no distinct interface. Different passivation anti-reflection layers may also be provided in different regions, for example, a stacked structure of a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layer is provided only on the outer surface of the n-type carrier collection layer 3.

[0154] In an optional embodiment, the surface of the silicon substrate 1 corresponding to the spacing region 300 is a polished surface or a velvet surface.

[0155] The back-contact solar cell provided by an embodiment of the present invention may further include: an electrode arranged on the passivation anti-reflection layer 5 corresponding to the first region 100 and in ohmic contact with the p-type carrier collection layer 2, and an electrode arranged on the passivation anti-reflection layer 5 corresponding to the second region 200 and in ohmic contact with the n-type carrier collection layer.

[0156] In summary, the back-contact solar cell provided by the embodiment of the present invention only has a passivation layer containing fixed negative charges outside the p-type carrier collection layer, which effectively solves the leakage problem of the n-type second region and improves the overall passivation performance of the solar cell.

[0157] Example 1

[0158] A method for preparing a back-contact solar cell, comprising:

[0159] (1) Using an n-type single crystal silicon wafer as the silicon substrate 1, pre-cleaning and texturing treatment are performed, and the first main surface (back surface) and the second main surface (front surface) of the silicon substrate 1 are double-sided polished using a tank polishing device;

[0160] (2) preparing a silicon oxide layer as a first tunneling passivation layer and an intrinsically doped polysilicon layer from the inside out on the first main surface of the silicon substrate 1;

[0161] (3) Boron is diffused into the first main surface of the silicon substrate 1 to obtain a p-type doped polysilicon layer and a borosilicate glass (BSG) layer;

[0162] (4) using a laser process in conjunction with an alkaline cleaning process to remove the first tunnel passivation layer, the p-type doped polysilicon layer, and the BSG layer corresponding to the second region 200 and the spacer region 300 of the first main surface of the silicon substrate 1, and also remove the BSG layer, the p-type doped polysilicon layer, and the first tunnel passivation layer plated around the second main surface of the silicon substrate;

[0163] (5) preparing a silicon oxide layer as a second tunneling passivation layer and an intrinsically doped polysilicon layer from the inside out on the first main surface of the silicon substrate 1;

[0164] (6) Phosphorus is diffused on the first main surface of the silicon substrate 1 to obtain an n-type doped polysilicon layer and a phosphorus silicon glass (PSG) layer;

[0165] (7) using a laser process in conjunction with an alkaline cleaning process to remove the second tunneling passivation layer, the n-type doped polysilicon layer, and the PSG layer corresponding to the first region 100 and the spacing region 300 of the first main surface, and to remove the PSG layer, the n-type doped polysilicon layer, and the second tunneling passivation layer deposited around the second main surface;

[0166] (8) performing alkali texturing treatment on the first main surface and the second main surface of the silicon substrate 1 to obtain a uniform pyramidal morphology;

[0167] (9) removing the remaining PSG layer and BSG layer on the first main surface of the silicon substrate 1;

[0168] (10) An oxide layer 6 is prepared on the outside of the n-type doped polysilicon layer and the outside of the silicon substrate 1 corresponding to the spacer region 300 by laser oxidation. The oxide layer corresponding to the n-type doped polysilicon layer is formed using an ultraviolet picosecond laser with a laser wavelength of 355 nm and an energy density of 1.0 to 1.50 J / cm 2 The oxide layer corresponding to the spacer region 300 is formed using a UV picosecond laser with a wavelength of 355 nm and an energy density of 0.02~1.0 J / cm 2 ;

[0169] (11) The silicon substrate 1 with the oxide layer 6 is placed in a gaseous bis(dimethylamino)dimethylsilane (BDMADMS) atmosphere, the chamber temperature is set to 150°C, the pressure is 1 Torr, and the reaction time is set to 10 minutes; after the surface of the oxide layer 6 is deactivated, the chamber is purged with 600 sccm of high-purity N2 for 60 seconds to remove the BDMADMS and reaction by-products physically adsorbed on the surface; after the purge is completed, the pressure in the chamber is slowly restored to normal pressure, and the silicon substrate 1 is taken out;

[0170] (12) The silicon substrate 1 was transferred to the ALD reaction chamber and deposited for 20 cycles to prepare Al2O3 with a thickness of 5 nm; wherein, in one cycle: first, N2 was introduced into the purge line, and then the oxygen source was introduced, the O3 flow rate was 8000 sccm, the reaction temperature was 200 °C, and the reaction time was 100 s; after the pipeline was purged with N2, the aluminum source and the oxygen source were alternately introduced into the chamber, and the temperature in the chamber was kept stable at 260 °C, wherein the aluminum source was introduced for 4 s at a flow rate of 2000 sccm, and after 3 s, the chamber was purged with N2 to remove the unreacted aluminum source; then the oxygen source was introduced for 6 s at a flow rate of 10000 sccm, and after 3 s, the chamber was purged with N2 to remove the unreacted oxygen source;

[0171] (13) Heating and annealing and removing the oxide layer 6 by laser process, wherein the annealing temperature is 400°C, the laser is a UV femtosecond laser, and the energy density is 2~5J / cm 2 ;

[0172] (14) The silicon substrate 1 is transferred to a PECVD device, and a SiNx film layer with a thickness of 75 nm is deposited on the first main surface and the second main surface of the silicon substrate 1;

[0173] (15) Silver paste is screen-printed on the first main surface of the silicon substrate 1 and then sintered to obtain a back-contact solar cell. The solar cell is tested using a steady-state IV tester.

[0174] Comparative Example 1

[0175] A method for preparing a back-contact solar cell, comprising:

[0176] (1) Using an n-type single crystal silicon wafer as the silicon substrate 1, pre-cleaning and texturing treatment are performed, and the first main surface (back surface) and the second main surface (front surface) of the silicon substrate 1 are double-sided polished using a tank polishing device;

[0177] (2) preparing a silicon oxide layer as a first tunneling passivation layer and an intrinsically doped polysilicon layer from the inside out on the first main surface of the silicon substrate 1;

[0178] (3) Boron is diffused into the first main surface of the silicon substrate 1 to obtain a p-type doped polysilicon layer and a borosilicate glass (BSG) layer;

[0179] (4) using a laser process in conjunction with an alkaline cleaning process to remove the first tunnel passivation layer, the p-type doped polysilicon layer, and the BSG layer corresponding to the second region 200 and the spacer region 300 of the first main surface of the silicon substrate 1, and also remove the BSG layer, the p-type doped polysilicon layer, and the first tunnel passivation layer plated around the second main surface of the silicon substrate;

[0180] (5) preparing a silicon oxide layer as a second tunneling passivation layer and an intrinsically doped polysilicon layer from the inside out on the first main surface of the silicon substrate 1;

[0181] (6) Phosphorus is diffused on the first main surface of the silicon substrate 1 to obtain an n-type doped polysilicon layer and a phosphorus silicon glass (PSG) layer;

[0182] (7) using a laser process in conjunction with an alkaline cleaning process to remove the second tunneling passivation layer, the n-type doped polysilicon layer, and the PSG layer corresponding to the first region 100 and the spacing region 300 of the first main surface, and to remove the PSG layer, the n-type doped polysilicon layer, and the second tunneling passivation layer deposited around the second main surface;

[0183] (8) performing alkali texturing treatment on the first main surface and the second main surface of the silicon substrate 1 to obtain a uniform pyramidal morphology;

[0184] (9) removing the remaining PSG layer and BSG layer on the first main surface of the silicon substrate 1;

[0185] (10) The silicon substrate 1 was transferred to the ALD reaction chamber and deposited for 20 cycles to prepare Al2O3 with a thickness of 5 nm; wherein, in one cycle: first, N2 was introduced into the purge line, and then the oxygen source was introduced, the O3 flow rate was 8000 sccm, the reaction temperature was 200 °C, and the reaction time was 100 s; after the pipeline was purged with N2, the aluminum source and the oxygen source were alternately introduced into the chamber to maintain the temperature in the chamber stable at 260 °C, wherein the aluminum source was introduced for 4 s at a flow rate of 2000 sccm, and after 3 s, the chamber was purged with N2 to remove the unreacted aluminum source; then the oxygen source was introduced for 6 s at a flow rate of 10000 sccm, and after 3 s, the chamber was purged with N2 to remove the unreacted oxygen source;

[0186] (11) The silicon substrate 1 is transferred to a PECVD device, and a SiNx film layer with a thickness of 75 nm is deposited on the first main surface and the second main surface of the silicon substrate 1;

[0187] (12) Silver paste is screen-printed on the first main surface of the silicon substrate 1 and then sintered to obtain a back-contact solar cell. The solar cell is tested using a steady-state IV tester.

[0188] The performance of the back-contact solar cells prepared in Example 1 and Comparative Example 1 was tested, and the test results are shown in the following table:

[0189]

[0190] It can be seen from the above test results that the back-contact solar cell prepared by the embodiment of the present invention has been improved in open circuit voltage (Voc), fill factor (FF) and photoelectric conversion efficiency (Eta), indicating that preparing a passivation layer 4 containing fixed negative charges only on the outside of the p-type carrier collection layer 2 can effectively improve the overall passivation performance and photoelectric conversion performance of the solar cell.

[0191] The above steps are merely provided to help understand the structure, method, and core concept of the present invention. It will be apparent to those skilled in the art that various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a back-contact solar cell, characterized in that: include: Step 1, providing a silicon substrate (1), wherein a first main surface of the silicon substrate (1) comprises first regions (100) and second regions (200) arranged alternately, and a spacing region (300) located between adjacent first regions (100) and second regions (200); Step 2, preparing a p-type carrier collection layer (2) doped with p-type dopant atoms in the first region (100), and preparing an n-type carrier collection layer (3) doped with n-type dopant atoms in the second region (200); Step 3, preparing a passivation layer (4) containing fixed negative charges on the outside of the p-type carrier collection layer (2); Step 4: preparing a passivation anti-reflection layer (5) outside the passivation layer (4), the spacing region (300), and the n-type carrier collection layer (3), wherein the passivation anti-reflection layer (5) does not contain fixed negative charges.

2. The method according to claim 1, characterized in that The step 2 includes: Step 21, forming the p-type carrier collection layer (2) and the p-type silicon glass layer (13) located on the p-type carrier collection layer (2) in the first region (100) of the silicon substrate (1), and forming the n-type carrier collection layer (3) and the n-type silicon glass layer (23) located on the n-type carrier collection layer (3) in the second region (200) of the silicon substrate (1); Step 22, texturing the second main surface of the silicon substrate (1), or texturing the silicon substrate surface corresponding to the spacing area (300) and the second main surface of the silicon substrate (1); the second main surface is opposite to the first main surface; Step 23: removing the p-type silicon glass layer (13) on the first region (100) and the n-type silicon glass layer (23) on the second region (200).

3. The method according to claim 2, characterized in that The step 21 includes: Step 21a, preparing a first tunnel passivation layer (11), a p-type doped polysilicon layer (12), and a p-type silicon glass layer (13) by stacking from the inside to the outside on the first main surface of the silicon substrate (1); Step 21b, removing portions of the first tunneling passivation layer (11), the p-type doped polysilicon layer (12), and the p-type silicon glass layer (13) corresponding to the second region (200) and the spacer region (300); Step 21c, preparing a second tunnel passivation layer (21), an n-type doped polysilicon layer (22), and an n-type silicon glass layer (23) by stacking from the inside to the outside on the first main surface of the silicon substrate (1); Step 21d, removing portions of the second tunneling passivation layer (21), the n-type doped polysilicon layer (22), and the n-type silicon glass layer (23) corresponding to the first region (100) and the spacer region (300); Alternatively, the step 21 includes: Step 21a′, diffusing p-type dopant atoms into the first main surface of the silicon substrate (1) to form a p-type diffusion layer and a p-type silicon glass layer (13); Step 21b′, removing portions of the p-type diffusion layer and the p-type silicon glass layer (13) corresponding to the second region (200) and the spacing region (300); Step 21c′, preparing a second tunnel passivation layer (21), an n-type doped polysilicon layer (22), and an n-type silicon glass layer (23) by stacking from the inside to the outside on the first main surface of the silicon substrate (1); Step 21d′, removing portions of the second tunneling passivation layer (21), the n-type doped polysilicon layer (22), and the n-type silicon glass layer (23) corresponding to the first region (100) and the spacer region (300).

4. The method according to claim 1, wherein The step 3 comprises: Step 31, preparing an oxide layer (6) on the outside of the n-type carrier collection layer (3) and the spacer region (300) by laser oxidation; Step 32, treating the surface of the oxide layer (6) with a silane capping agent to remove the surface activity of the oxide layer (6); Step 33, depositing the passivation layer (4) on the first main surface using an atomic layer deposition process to obtain the passivation layer (4) located outside the p-type carrier collection layer (2), wherein the passivation layer (4) cannot be formed on the surface-deactivated oxide layer (6).

5. The method according to claim 4, characterized in that In the step 33, an aluminum source and an oxygen source are introduced to form the passivation layer (4); and / or, In the step 33, a gallium source and an oxygen source are introduced to form the passivation layer (4).

6. The method according to claim 4, characterized in that The region of the oxide layer (6) corresponding to the n-type carrier collection layer (3) is heated by an energy density of 1 J / cm 2 ~1.50J / cm 2 obtained by laser etching.

7. The method according to claim 4, characterized in that The surface of the silicon substrate (1) corresponding to the spacing region (300) is velvet, and the region of the oxide layer (6) corresponding to the spacing region (300) is heated by an energy density of 0.02 J / cm 2 ~1J / cm 2 obtained by laser etching; or, The surface of the silicon substrate (1) corresponding to the spacing region (300) is a polished surface, and the region of the oxide layer (6) corresponding to the spacing region (300) is heated by an energy density of 1 J / cm 2 ~1.50J / cm 2 obtained by laser etching.

8. The method according to claim 4, characterized in that After step 33 and before step 4, the method further includes: Step 34, annealing the oxide layer (6) to restore the surface activity of the oxide layer (6); Step 35: removing the oxide layer (6) using a laser process.

9. The method according to claim 8, characterized in that The laser oxidation in step 31 is achieved using an ultraviolet femtosecond laser; and / or, The silane capping agent includes one or more of bis(dimethylamino)dimethylsilane, monochlorosilane, trimethylchlorosilane, and phenyldimethylchlorosilane; and / or, The proportion of tetravalent silicon oxide in the oxide layer (6) is 90% to 100%; and / or, The annealing temperature in step 34 is 300° C. to 500° C.; and / or, The annealing time in step 34 is 5 min to 15 min; and / or, In step 35, an ultraviolet femtosecond laser is used to implement the laser process; and / or, The energy density of the laser in step 35 is 2 J / cm 2 ~5J / cm 2 .

10. A back contact solar cell, characterized in that: include: A silicon substrate (1), wherein a first main surface of the silicon substrate (1) comprises first regions (100) and second regions (200) arranged alternately, and a spacing region (300) located between adjacent first regions (100) and second regions (200); a p-type carrier collection layer (2) disposed on the first region (100); an n-type carrier collection layer (3) disposed on the second region (200); a passivation layer (4) containing fixed negative charges disposed on the p-type carrier collection layer (2); and A passivation anti-reflection layer (5) free of fixed negative charges is provided on the passivation layer (4), the spacing region (300), and the n-type carrier collection layer (3).

11. The back contact solar cell according to claim 10, characterized in that The p-type carrier collection layer (2) comprises: a first tunneling passivation layer (11) arranged on the surface of the first region (100), and a p-type doped polysilicon layer (12) arranged on the first tunneling passivation layer (11); Alternatively, the p-type carrier collection layer (2) comprises: a p-type diffusion layer arranged inside the silicon substrate corresponding to the first region (100).

12. The back contact solar cell according to claim 11, characterized in that The n-type carrier collection layer (3) comprises: a second tunneling passivation layer (21) arranged on the surface of the second region (200), and an n-type doped polysilicon layer (22) arranged on the second tunneling passivation layer (21); Alternatively, the n-type carrier collection layer (3) comprises: an n-type diffusion layer arranged inside the silicon substrate corresponding to the second region (200).

13. The back contact solar cell according to claim 12, characterized in that The passivation layer (4) is at least one of an aluminum oxide layer and a gallium oxide layer; and / or, The first tunneling passivation layer (11) is a silicon oxide layer; and / or, The second tunneling passivation layer (21) is a silicon oxide layer; and / or, The passivation anti-reflection layer (5) is at least one of silicon nitride, silicon oxynitride layer and silicon oxide layer; and / or, The passivation anti-reflection layer (5) of the first region (100), the second region (200) and the spacer region (300) is an integrated structure.

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