Chip and generation method thereof
The integrated array of storage and computing was prepared by spin-coating ZnO nanoparticles, perovskite films and indium oxide layers on CMOS wafers, which solved the problems of high-cost and complex processes in the existing technology, and achieved low-cost and efficient neuromorphic calculations.
Patent Information
- Application Number
- CN202510559691.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2025-08-12
AI Technical Summary
The prior art has high cost and complex processes when preparing high-precision, high-performance storage and computing units, making it difficult to achieve large-scale production.
The chip was prepared by solution method, including spin-coating ZnO nanoparticles, perovskite films, K+ ion-doped indium oxide and aluminum oxide layers on the surface of CMOS wafers, and forming a computing-integrated array through multi-layer metal interconnection connection.
It reduces the production cost of storage and computing units, improves synaptic performance, is suitable for large-scale production, and improves the efficiency of neuromorphic computing.
Smart Images
Figure CN120475880A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chip and a method for generating the same. Background Art
[0002] In the existing technology, arrays made of integrated storage and computing devices are the mainstream choice for improving the computing power of neuromorphic networks today. Neuromorphic computing aims to imitate the working method of the human brain and achieve efficient computing through parallel processing and distributed storage, and integrated storage and computing technology just meets this demand. Most arrays use atomic layer deposition (ALD), magnetron sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD) and other technologies to complete the preparation of devices. These technologies play an important role in the preparation of high-precision, high-performance storage and computing units, but they also face challenges such as high cost and complex process. Summary of the Invention
[0003] In view of this, the main object of the present invention is to provide a chip and a method for generating the same.
[0004] In order to achieve one of the above-mentioned objects of the invention, an embodiment of the present invention provides a chip and a method for producing the same, comprising the following steps: a chip production method comprising the following steps: obtaining a CMOS wafer, removing the oxide on the target surface of the CMOS wafer and exposing a tungsten via, wherein the target surface of the CMOS wafer is provided with a Via hole structure; dissolving zinc acetate in an ethanol solution and stirring, then adding oleic acid, and heating the mixture to reflux; dissolving tetramethylammonium hydroxide in the ethanol solution; then injecting Zn(OAc)2 and oleic acid into the ethanol solution to obtain a mixed solution, and heating the mixed solution to reflux; then diluting the mixed solution with EtOH and cooling the mixed solution in an ice bath to produce a white precipitate of ZnO nanoparticles; The liquid is centrifuged and the supernatant is removed; the obtained oleic acid-capped ZnOQD is washed with ethanol for multiple times, and the ZnOQD is finally suspended in toluene; thereafter, the prepared precursor solution is ultrasonically treated and filtered through a polyethersulfone syringe to obtain a transparent solution, the transparent solution is spin-coated on the target surface of the CMOS wafer, and annealing is performed; a perovskite film is spin-coated on the target surface of the CMOS wafer to prepare a K+ ion-doped indium oxide precursor solution, the indium oxide precursor solution is spin-coated on the target surface of the CMOS wafer, and then annealing is performed; an aluminum oxide precursor solution is prepared, the aluminum oxide precursor solution is spin-coated on the target surface of the CMOS wafer, and then annealing is performed; and an aluminum source and drain are deposited on the target surface of the CMOS wafer.
[0005] As an improvement to an embodiment of the present invention, the step of "removing the oxide on the target surface of the CMOS wafer and exposing the tungsten vias" specifically includes: soaking the CMOS wafer in a hydrofluoric acid solution until the oxide on the target surface of the CMOS wafer is removed and the tungsten vias are exposed.
[0006] As an improvement of the embodiment of the present invention, the step of “dissolving zinc acetate in an ethanol solution and stirring” specifically includes: dissolving zinc acetate in an ethanol solution at a temperature below 50° C. and stirring.
[0007] As an improvement to an embodiment of the present invention, the step of “injecting Zn(OAc)2 and oleic acid into the ethanol solution to obtain a mixed solution, and heating the mixed solution to reflux” specifically includes: injecting Zn(OAc)2 and oleic acid into the ethanol solution to obtain a mixed solution, and heating the mixed solution to reflux for 2 to 3 minutes.
[0008] As an improvement to an embodiment of the present invention, the "centrifuging the mixed solution and removing the supernatant" specifically includes: centrifuging the mixed solution at a speed of 3000 to 5000 RPM for 10 to 20 minutes, and removing the supernatant.
[0009] As an improvement to an embodiment of the present invention, the step of “spin-coating the transparent solution on the target surface of the CMOS wafer and performing annealing treatment” specifically includes: ultrasonically treating the prepared precursor solution and filtering it through a polyethersulfone syringe to obtain a transparent solution, spin-coating the transparent solution on the target surface of the CMOS wafer at a spin coating speed of 2500 to 3500 RPM for 15 to 20 seconds, and annealing at 100 to 150°C for 10 to 15 minutes.
[0010] As an improvement to an embodiment of the present invention, the "spin coating a perovskite film on the target surface of the CMOS wafer" specifically includes: obtaining a mixed solvent containing DMF and DMSO, and dissolving PbI2, PbBr2, FAI and MABr in the mixed solvent; then, spin coating the target surface of the CMOS wafer at a speed of 1000-1500 RPM and continuing for 10 seconds, and then spin coating the target surface of the CMOS wafer at a speed of 4000-6000 RPM and continuing for 20 seconds; then, within 10 seconds, ethyl acetate is dropwise added to the target surface of the CMOS wafer; then, the CMOS wafer is annealed at a temperature of 100-150 degrees and continued for 20-30 minutes.
[0011] As an improvement of an embodiment of the present invention, the "preparation of a K+ ion-doped indium oxide precursor solution" specifically includes: dissolving indium nitrate hydrate in DI water, and adding potassium chloride to the DI water to obtain a K+ ion-doped indium oxide precursor solution.
[0012] As an improvement of the embodiment of the present invention, the “preparing an aluminum oxide precursor solution” specifically includes: dissolving aluminum nitrate nonahydrate in DI water to prepare an aluminum oxide precursor solution.
[0013] The embodiment of the present invention further provides a chip, comprising: a CMOS wafer, wherein the CMOS wafer comprises a source, a drain and a gate, and the CMOS wafer is connected by multi-layer metal interconnection, and a target surface of the CMOS wafer is provided with a via hole structure; on the target surface and in a direction away from the CMOS wafer, a ZnO layer, a perovskite layer, an InO layer, and a VIA layer are sequentially provided. x layer, AIO x layer and AI layer, wherein the InO x The layer is doped with K+.
[0014] Compared with the prior art, the technical effect of the present invention is that: the embodiment of the present invention discloses a chip production method, comprising the following steps: obtaining a CMOS wafer, dissolving tetramethylammonium hydroxide in an ethanol solution, injecting Zn(OAc)2 and oleic acid into the ethanol solution, diluting the mixed solution with EtOH, centrifuging the mixed solution, and removing the supernatant; washing the obtained oleic acid-capped ZnOQD with ethanol multiple times; then, ultrasonicating the prepared precursor solution and filtering it through a polyethersulfone syringe to obtain a transparent solution, and spin-coating the transparent solution on the target surface of the CMOS wafer; spin-coating an indium oxide precursor solution on the target surface of the CMOS wafer; spin-coating an aluminum oxide precursor solution on the target surface of the CMOS wafer, and then annealing; and depositing aluminum source and drain electrodes on the target surface of the CMOS wafer. The chip generated by this production method has the advantages of high synaptic performance, low cost, and suitability for large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A schematic diagram of the structure of a chip provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0016] The present invention will be described in detail below with reference to the embodiments shown in the accompanying drawings. However, the embodiments do not limit the present invention, and any structural, methodological, or functional changes made by those skilled in the art based on the embodiments are all within the scope of protection of the present invention.
[0017] The following description and accompanying drawings sufficiently illustrate the specific embodiments herein to enable those skilled in the art to practice them. Portions and features of some embodiments may be included in or substituted for portions and features of other embodiments. The scope of the embodiments herein includes the entire scope of the claims, including all available equivalents thereof. Herein, the terms "first," "second," and the like are used solely to distinguish one element from another and do not require or imply any actual relationship or order between these elements. In practice, the first element can also be referred to as the second element, and vice versa. Furthermore, the terms "comprise," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a structure, device, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such structure, device, or apparatus. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of other identical elements in the structure, device, or apparatus comprising the element. The various embodiments herein are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Similar or identical parts between the various embodiments can be referenced to each other.
[0018] The terms "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like used herein to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are intended only to facilitate the description of this document and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention. In the description herein, unless otherwise specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, they can be mechanical or electrical connections, or they can be internal connections between two elements, they can be directly connected, or they can be indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to the specific circumstances.
[0019] A first embodiment of the present invention provides a method for producing a wafer, comprising the following steps:
[0020] Step 1: obtaining a CMOS wafer, removing oxide from a target surface of the CMOS wafer and exposing tungsten vias, wherein the target surface of the CMOS wafer is provided with a via hole structure;
[0021] Here, the CMOS wafer includes a source, a drain and a gate, and the CMOS wafer is connected through multiple layers of metal interconnects.
[0022] Optionally, the CMOS wafer is manufactured using a 180 nm CMOS process on a 200 mm silicon wafer.
[0023] Here, CMOS stands for Complementary Metal Oxide Semiconductor. CMOS is a technology widely used in integrated circuit manufacturing, featuring low power consumption and high integration.
[0024] The CMOS wafer manufacturing process can be as follows: First, the silicon wafer is cleaned and pretreated to ensure a clean and contaminant-free surface. Subsequently, photolithography is used to define the transistor regions on the wafer, and the circuit pattern is transferred to the wafer surface using photoresist and a mask. Next, ion implantation or diffusion processes are used to form the transistor's source and drain regions, which are the input and output terminals for current flow in the transistor. Meanwhile, gate fabrication is a key step. Typically, a thin oxide layer (gate oxide) and polysilicon are deposited to form the gate structure, which controls the transistor's on / off state. After completing the basic transistor structure, the multilayer metal interconnect stage begins. First, a layer of insulating material (such as silicon dioxide) is deposited on the silicon wafer surface using chemical vapor deposition (CVD) or physical vapor deposition (PVD). Then, photolithography and etching processes are used to create holes in the insulating layer, forming contact holes and vias. These holes are then filled with metal (such as aluminum or copper) to form the transistor's electrode connections. Subsequently, the above steps are repeated, stacking metal interconnect layers layer by layer. Each layer is isolated by an insulating layer, and electrical connections are achieved between layers through through-holes. Ultimately, multi-layer metal interconnects connect transistors and other circuit components (such as resistors, capacitors, etc.) to form a complete CMOS integrated circuit. Throughout the manufacturing process, multiple cleaning, etching, deposition, and polishing steps are required to ensure the high performance and reliability of the circuit. Finally, it is tested and packaged.
[0025] Step 2: Dissolve zinc acetate in an ethanol solution and stir, then add oleic acid, and heat the mixture to reflux; dissolve tetramethylammonium hydroxide in the ethanol solution; then, inject Zn(OAc)2 and oleic acid into the ethanol solution to obtain a mixed solution, and heat the mixed solution to reflux; then, dilute the mixed solution with EtOH and cool the mixed solution using an ice bath, and a white precipitate of ZnO nanoparticles appears; the mixed solution is centrifuged and the supernatant is removed; the obtained oleic acid-capped ZnO QD is washed with ethanol several times, and the ZnO QD is finally suspended in toluene; then, the prepared precursor solution is ultrasonically treated and filtered through a polyethersulfone syringe to obtain a transparent solution, and the transparent solution is spin-coated on the target surface of the CMOS wafer and annealed;
[0026] Here, in the process of dissolving zinc acetate in the ethanol solution and stirring, vigorous stirring is required to ensure that the zinc acetate is evenly dispersed in the ethanol to avoid local excessive concentration or undissolved particles.
[0027] Here, after the zinc acetate is completely dissolved, oleic acid (an unsaturated fatty acid) is added. Oleic acid may react with the zinc acetate to form a complex or act as a surfactant. The mixture is then heated to reflux. Reflux occurs when a liquid is heated to boiling, the vapor is cooled through a condenser, and then flows back into the reaction vessel, maintaining a stable temperature and volume. This step may be used to accelerate the reaction or form a specific product.
[0028] Here, tetramethylammonium hydroxide (TMAH) is an organic base commonly used to adjust the pH of a reaction system or as a surfactant. TMAH is dissolved in refluxing ethanol. Refluxing ethanol means that ethanol is heated to boiling and refluxed through a condenser to maintain a stable temperature and volume of the reaction system. The purpose of this step is to prepare an ethanolic solution of TMAH.
[0029] Here, a TMAH solution in ethanol is rapidly injected into another flask containing zinc acetate (Zn(OAc)2) and oleic acid. Zinc acetate is a zinc precursor that provides Zn2+ ions, while oleic acid is a surfactant used to control the morphology and size of the nanoparticles. The rapid injection allows for rapid mixing of the reactants, promoting a uniform reaction.
[0030] Here, the mixed solution is heated to reflux. It can be understood that in this operation, zinc acetate is hydrolyzed under alkaline conditions (provided by TMAH) to generate zinc oxide (ZnO) nanoparticles.
[0031] In practice, a preset threshold can be set to cool the mixed solution to approximately 0°C. The reaction mixture is then diluted with ethanol (EtOH). The purpose of dilution is to reduce the concentration of the reaction system, slowing the reaction rate and facilitating subsequent processing. The mixture is then placed in an ice bath and cooled to approximately 0°C. Cooling further stabilizes the generated nanoparticles, preventing them from growing or agglomerating.
[0032] Here, after the mixed solution is cooled to a preset temperature, white precipitates appear, which are ZnO nanoparticles. Oleic acid acts as a surfactant and wraps around the surface of the ZnO nanoparticles, preventing the particles from agglomerating, thereby forming stable nanoparticles.
[0033] Here, ZnO quantum dots (QDs) are extremely small zinc oxide nanoparticles with quantum confinement effect (i.e., the size is small enough to affect its electronic structure and optical properties). Oleic acid capping means that oleic acid molecules are wrapped on the surface of ZnO quantum dots through chemical adsorption or physical adsorption. Oleic acid, as a surfactant, can prevent quantum dots from agglomerating and make them stably dispersed in organic solvents. The purpose of cleaning is to remove unreacted raw materials (such as zinc acetate, oleic acid, tetramethylammonium hydroxide, etc.) and by-products in the reaction. Ethanol is a polar solvent that can dissolve many impurities, but oleic acid-capped ZnO quantum dots do not dissolve in it because the oleic acid coating makes the surface of the quantum dots hydrophobic and difficult to disperse in polar solvents.
[0034] Ultrasonic treatment utilizes the high-frequency vibrations of ultrasound to create cavitation in liquids, thereby dispersing aggregated particles, promoting dissolution or mixing, or improving solution uniformity. Polyethersulfone (PES) is a polymer material commonly used in filter manufacturing. It offers chemical and high-temperature resistance and good mechanical strength. The purpose of filtration is to remove large particles, aggregates, and undissolved impurities from solutions, thereby obtaining a purer, more uniform solution.
[0035] Here, the procedure of "sonicating the prepared precursor solution and filtering it through a polyethersulfone syringe to obtain a transparent solution, spinning the transparent solution at a spin coating speed of 2500-3500 RPM for 15-20 seconds, and annealing it at 100-150 degrees Celsius for 10 to 15 minutes" can be understood as follows: First, the prepared precursor solution is ultrasonicated. The purpose of this step is to fully disperse the particles or agglomerates in the solution through the high-frequency vibration of ultrasound, thereby improving the uniformity and stability of the solution. The ultrasonication treatment typically lasts for several minutes, the specific duration of which depends on the properties of the solution and the desired dispersion effect.
[0036] The ultrasonically treated solution is then filtered through a polyethersulfone (PES) syringe filter. PES is a high-temperature and chemically resistant polymer material. Its filter effectively removes tiny particles and impurities from the solution, ensuring its purity. The filtered solution should be transparent, indicating that particles have been effectively removed and suitable for subsequent film preparation.
[0037] Next, the filtered, transparent solution is spin-coated to form a thin film. Spin coating is a commonly used thin-film preparation technique that involves dropping a solution onto the center of a substrate (such as a silicon wafer or glass) and then spinning the substrate at a preset speed for a period of time. During the high-speed rotation, the solution is evenly spread across the substrate surface under the action of centrifugal force, while the solvent rapidly evaporates, forming a uniform thin film. The choice of spin coating speed and time depends on the desired film thickness and uniformity.
[0038] Finally, the spin-coated film undergoes annealing. Annealing involves heating the film at a preset temperature for a period of several minutes. This process removes any residual solvent from the film and promotes densification and crystallization of the film's internal structure. The annealing temperature and duration must be optimized based on the film's thermal stability and target performance to ensure the film possesses good mechanical and electrical properties.
[0039] The mixed solution can be cooled to a preset temperature using an ice bath, where |preset temperature-0°C|≤preset threshold, and the preset threshold>0
[0040] Step 3: Spin-coating a perovskite film on the target surface of the CMOS wafer, preparing a K+ ion-doped indium oxide precursor solution, spin-coating the indium oxide precursor solution on the target surface of the CMOS wafer, and then performing an annealing process. Here, the annealing process can specifically include: annealing at a temperature of 200 to 300 degrees in an ambient atmosphere for 20 to 30 minutes;
[0041] The K+ ion-doped indium oxide precursor solution is evenly coated on the device surface by spin coating, and the spin coating speed is usually controlled at 2000 to 4000 rpm to ensure the uniformity and thickness consistency of the film. Subsequently, the coated device is placed in an ambient atmosphere (usually air or inert gas) and annealed in a temperature range of 200 to 300 degrees Celsius, and the annealing time is maintained at 20 to 30 minutes. During the annealing process, temperature control is crucial to ensure that K+ ions can be effectively doped into the indium oxide lattice, while promoting the complete decomposition and crystallization of the precursor solution, thereby forming a high-quality doped indium oxide film. After annealing is completed, the device should be slowly cooled to room temperature to avoid film cracking or defects caused by thermal stress.
[0042] Step 4: Prepare an aluminum oxide precursor solution, spin-coat the aluminum oxide precursor solution onto the target surface of the CMOS wafer, and then perform an annealing process. Here, the annealing process can specifically be performed at a temperature of 200-300° C. in an ambient atmosphere for 30-40 minutes.
[0043] Step 5: Depositing aluminum source and drain electrodes on the target surface of the CMOS wafer. Here, the aluminum source and drain electrodes may be deposited on the target surface of the CMOS wafer using a thermal evaporation technique.
[0044] Here, the K+ ion-doped indium oxide precursor solution is evenly coated on the device surface by spin coating, and the spin coating speed is usually controlled at 2000 to 4000 rpm to ensure the uniformity and thickness consistency of the film. Subsequently, the coated device is placed in an ambient atmosphere (usually air or inert gas) and annealed at a temperature range of 200 to 300 degrees Celsius. The annealing time is maintained at 20 to 30 minutes. During the annealing process, temperature control is crucial to ensure that K + The ions are effectively doped into the indium oxide lattice, while promoting the complete decomposition and crystallization of the precursor solution, thereby forming a high-quality doped indium oxide film. After annealing, the device should be slowly cooled to room temperature to avoid cracking or defects in the film caused by thermal stress.
[0045] The method described in this embodiment uses CMOS wafers and a solution-based manufacturing process to fabricate a memory-computing integrated array, a novel structure that improves synaptic performance. This method then uses a lower-cost solution-based manufacturing process, which can be mass-produced, thereby promoting the widespread application of memory-computing integrated technology.
[0046] Compared to traditional computer designs that separate computing and storage units, this invention uses a single unit for both storage and computing, which improves computing efficiency, especially in neuromorphic computing. The use of a solution-based manufacturing process reduces the cost of the storage and computing units and enables large-scale production.
[0047] In this embodiment, “removing oxide from the target surface of the CMOS wafer and exposing the tungsten vias” specifically includes: soaking the CMOS wafer in a hydrofluoric acid solution until the oxide from the target surface of the CMOS wafer is removed and the tungsten vias are exposed.
[0048] Here, you can soak the silicon wafer in a hydrofluoric acid solution for 1 to 2 minutes to remove the surface oxide and expose the tungsten vias. Hydrofluoric acid (HFA) is a clear, colorless, fuming, corrosive liquid containing hydrogen fluoride gas in water. It is a weak acid but extremely corrosive, capable of corroding metals, glass, and silicon-containing materials.
[0049] In this embodiment, the step of “dissolving zinc acetate in an ethanol solution and stirring” specifically includes: dissolving zinc acetate in an ethanol solution at a temperature below 50° C. and stirring.
[0050] Here, zinc acetate (zinc salt) is dissolved in ethanol (organic solvent). It is understood that temperature control is important because excessively high temperatures may cause zinc acetate to decompose or ethanol to volatilize. After long-term experiments, the inventors found that the optimal effect can be achieved at a temperature below 50°C.
[0051] In this embodiment, the step of “injecting Zn(OAc)2 and oleic acid into the ethanol solution to obtain a mixed solution, and heating the mixed solution to reflux” specifically includes: injecting Zn(OAc)2 and oleic acid into the ethanol solution to obtain a mixed solution, and heating the mixed solution to reflux for 2 to 3 minutes.
[0052] In this embodiment, the “centrifuging the mixed solution and removing the supernatant” specifically includes: centrifuging the mixed solution at a speed of 3000 to 5000 RPM for 10 to 20 minutes, and removing the supernatant.
[0053] In this embodiment, the step of “spin-coating the transparent solution on the target surface of the CMOS wafer and performing an annealing treatment” specifically includes: ultrasonically treating the prepared precursor solution and filtering it through a polyethersulfone syringe to obtain a transparent solution, spin-coating the transparent solution on the target surface of the CMOS wafer at a spin coating speed of 2500 to 3500 RPM for 15 to 20 seconds, and annealing at 100 to 150° C. for 10 to 15 minutes.
[0054] In this embodiment, the "spin coating the perovskite film on the target surface of the CMOS wafer" specifically includes: obtaining a mixed solvent containing DMF and DMSO, dissolving PbI2, PbBr2, FAI and MABr in the mixed solvent; then, spin coating the target surface of the CMOS wafer at a speed of 1000-1500RPM and continuing for 10 seconds, and then spin coating the target surface of the CMOS wafer at a speed of 4000-6000RPM and continuing for 20 seconds; then, within 10 seconds, ethyl acetate is added dropwise to the target surface of the CMOS wafer; then, the CMOS wafer is annealed at a temperature of 100-150 degrees and continued for 20-30 minutes.
[0055] This can, in practice, be done in a glove box.
[0056] PbI2 (lead iodide) and PbBr2 (lead bromide) provide the lead and halogens (iodine and bromine) in the perovskite. FAI (formamidinium iodide) and MABr (methylammonium bromide) provide the organic cations (formamidinium ion and methylammonium ion) and halogens (iodine and bromine). Use a mixed solvent of DMF (N,N-dimethylformamide) and DMSO (dimethyl sulfoxide). These two solvents effectively dissolve the above raw materials, and combining them optimizes solubility and solution stability. Stir until completely dissolved to form a uniform perovskite precursor solution.
[0057] Spin coating is a commonly used thin film preparation technology, widely used in the electronics industry and materials science. Its basic principle is to use the centrifugal force generated by the substrate during rotation to evenly distribute the liquid coating material on the surface of the substrate, and form a thin film through the volatilization of the solvent. The main equipment for spin coating is a spin coater. The basic steps of spin coating are: adding solution: using a pipette to drop the solution onto the rotating substrate. Substrate rotation: the substrate rotates at high speed on the spin coater, and the centrifugal force is used to spread the solution evenly on the surface of the substrate. Stop rotation: when the preset rotation time is reached, the rotation is stopped. Solvent volatilization: the solvent in the solution gradually evaporates to form a uniform thin film.
[0058] Ethyl acetate is an organic solvent commonly used in the anti-solvent treatment of perovskite films. During the preparation of perovskite films, the addition of ethyl acetate can quickly remove excess solvent from the precursor solution, thereby promoting the rapid crystallization of perovskite crystals and the formation of thin films. Ethyl acetate will mix with the solvent in the film, but due to its high volatility, it will quickly remove the excess solvent, causing the perovskite crystals to precipitate from the solution and form a dense film. Effects: 1. Ethyl acetate treatment can improve the crystallization quality of perovskite films, making them more uniform and dense, and reducing defects. 2. This treatment can also enhance the optoelectronic properties of perovskite films, such as improving light absorption efficiency and charge transport properties.
[0059] In this embodiment, the “preparing a K+ ion-doped indium oxide precursor solution” specifically includes: dissolving indium nitrate hydrate in DI water, and adding potassium chloride to the DI water, thereby obtaining a K+ ion-doped indium oxide precursor solution.
[0060] Here, DI water (deionized water) is an extremely pure water made by removing all cations and anions in water. It is colorless, odorless, and lacks ions, that is, water with extremely low electrical conductivity.
[0061] Indium nitrate hydrate is the primary raw material for the preparation of indium oxide, providing the element indium (In). The hydrate form means it contains water of crystallization, which is released upon dissolution.
[0062] Potassium chloride is a potassium ion (K + ) source, used to dope into indium oxide. + The electrical properties of indium oxide (such as conductivity, carrier concentration, etc.) can be adjusted. Deionized water is a solvent used to dissolve indium nitrate hydrate and potassium chloride to ensure that there is no interference from impurity ions in the solution.
[0063] Preparation process: 1. Dissolve indium nitrate hydrate: Add indium nitrate hydrate to deionized water and stir until completely dissolved to form an indium nitrate solution. Indium nitrate dissociates into indium ions and nitrate ions in water. 2. Add potassium chloride: Add potassium chloride (KCl) to the indium nitrate solution and stir until completely dissolved; potassium chloride dissociates into potassium ions (K+) and chloride ions (Cl-) in water. 3. Form a precursor solution: The final product is a precursor solution containing In. 3+ and K + The mixed solution, K + Ion-doped indium oxide precursor solution; the solution can be used for subsequent thin film preparation (such as spin coating, spray coating, etc.) or heat treatment (such as annealing) to generate K+-doped indium oxide thin film.
[0064] In this embodiment, the “preparing an aluminum oxide precursor solution” specifically includes: dissolving aluminum nitrate nonahydrate in DI water to prepare an aluminum oxide precursor solution.
[0065] Aluminum nitrate nonahydrate (Al(NO3)39H2O): Aluminum nitrate nonahydrate is the main raw material for the preparation of alumina, providing aluminum (Al). It is a hydrate containing 9 crystal water molecules (9H2O) that are released when dissolved. After dissolving in water, aluminum nitrate nonahydrate dissociates into aluminum ions (Al 3+ ) and nitrate ions (NO3 - ).
[0066] Deionized water (DI water): Deionized water is the solvent used to dissolve aluminum nitrate nonahydrate. Using deionized water can avoid interference from impurity ions and ensure the purity of the solution.
[0067] Preparation process: Step 1, dissolve aluminum nitrate nonahydrate: add aluminum nitrate nonahydrate into deionized water and stir until completely dissolved; Step 2, during the dissolution process, aluminum nitrate nonahydrate will dissociate into Al 3+ and NO3 - , forming a uniform aluminum nitrate solution. The final result is an aluminum oxide precursor solution containing Al 3+ ion.
[0068] The second embodiment of the present invention provides a chip, such as Figure 1 Shown, including:
[0069] A CMOS wafer 101, wherein the CMOS wafer 101 includes a source, a drain, and a gate, and the CMOS wafer 101 is connected by multiple layers of metal interconnects, and a via hole structure is provided on the target surface of the CMOS wafer 101;
[0070] On the target surface and in the direction away from the CMOS wafer 101, a ZnO layer 102, a perovskite layer 103, an InOx Layer 104, AIO x layer 105 and Al layer 106, wherein the InO x The layer is doped with K+.
[0071] Here, the CMOS wafer 101 also includes: a transistor layer 101A,
[0072] a first signal transmission layer 1011 , a second signal transmission layer 1012 , a third signal transmission layer 1013 , a fourth signal transmission layer 1014 and a fifth signal transmission layer 1015 .
[0073] The transistor layer 101A serves as a switch for the entire chip, and is used to control the output of current.
[0074] The first signal transmission layer 1011 is used for the transmission of signals or currents, which can greatly avoid signal interference; the second signal transmission layer 1012 is used for the transmission of signals or currents, which can expand other circuits outward and can also be used to detect signals. The third signal transmission layer 1013 is used for the transmission of signals or currents, which can greatly avoid signal interference. The fourth signal transmission layer 1014 is used to connect the upper synaptic transistor and the traditional transistor below, and also transmits the signal of the synaptic transistor; it is respectively connected to the source and drain of the synaptic transistor and the source of the traditional transistor. The fifth signal transmission layer 1015 is used for the transmission of signals or currents, which can greatly avoid signal interference.
[0075] The ZnO layer 102 is a passivation layer that can avoid reactions between materials; the perovskite layer 103 is a photosensitive layer that can sense light signals; x Layer 104 is a semiconductor layer that can serve as a conduction channel to connect the input (presynaptic) and output (postsynaptic) signals of the device; x Layer 105 is a dielectric layer that can isolate the metal electrode from the semiconductor layer so that an external voltage can regulate the conductivity state of the semiconductor layer; AI layer 106 is a metal layer that can be used for signal or current transmission.
[0076] It should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation method can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.
[0077] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.
Claims
1. A method for producing a chip, characterized in that: The following steps are involved: Obtaining a CMOS wafer, removing oxide from a target surface of the CMOS wafer and exposing tungsten vias, wherein the target surface of the CMOS wafer is provided with a via hole structure; Zinc acetate is dissolved in an ethanol solution and stirred, and then oleic acid is added, and the mixture is heated to reflux; tetramethylammonium hydroxide is dissolved in the ethanol solution; then, Zn(OAc)2 and oleic acid are injected into the ethanol solution to obtain a mixed solution, and the mixed solution is heated to reflux; then, the mixed solution is diluted with EtOH and cooled using an ice bath, and a white precipitate of ZnO nanoparticles appears; the mixed solution is centrifuged and the supernatant is removed; the obtained oleic acid-capped ZnO QD is washed with ethanol for multiple times, and the ZnO QD is finally suspended in toluene; then, the prepared precursor solution is ultrasonically treated and filtered through a polyethersulfone syringe to obtain a transparent solution, and the transparent solution is spin-coated on the target surface of the CMOS wafer and annealed; Spin-coating a perovskite film on the target surface of the CMOS wafer, preparing a K+ ion-doped indium oxide precursor solution, spin-coating the indium oxide precursor solution on the target surface of the CMOS wafer, and then performing an annealing process; preparing an aluminum oxide precursor solution, spin-coating the aluminum oxide precursor solution onto a target surface of the CMOS wafer, and then performing an annealing process; Aluminum source and drain electrodes are deposited on the target surface of the CMOS wafer.
2. The production method according to claim 1, characterized in that The “removing oxide from the target surface of the CMOS wafer and exposing the tungsten vias” specifically includes: The CMOS wafer is immersed in a hydrofluoric acid solution until the oxide on the target surface of the CMOS wafer is removed and the tungsten vias are exposed.
3. The production method according to claim 1, characterized in that The step of “dissolving zinc acetate in an ethanol solution and stirring” specifically includes: Dissolve zinc acetate in ethanol solution at a temperature below 50°C and stir.
4. The production method according to claim 1, characterized in that The step of “injecting Zn(OAc) 2 and oleic acid into the ethanol solution to obtain a mixed solution, and heating the mixed solution to reflux” specifically includes: Zn(OAc)2 and oleic acid were injected into the ethanol solution to obtain a mixed solution, and the mixed solution was heated to reflux for 2 to 3 minutes.
5. The production method according to claim 1, characterized in that The “centrifuging the mixed solution and removing the supernatant” specifically includes: The mixed solution is centrifuged at a speed of 3000-5000 RPM for 10-20 minutes, and the supernatant is removed.
6. The production method according to claim 1, characterized in that The process of "spin coating the transparent solution on the target surface of the CMOS wafer and performing an annealing treatment" specifically includes: subjecting the prepared precursor solution to ultrasonic treatment and filtering it through a polyethersulfone syringe to obtain a transparent solution, spin coating the transparent solution on the target surface of the CMOS wafer at a spin coating speed of 2500 to 3500 RPM for 15 to 20 seconds, and annealing at 100 to 150°C for 10 to 15 minutes.
7. The production method according to claim 1, characterized in that The “spin coating a perovskite film on a target surface of the CMOS wafer” specifically includes: Obtain a mixed solvent containing DMF and DMSO, and dissolve PbI2, PbBr2, FAI and MABr in the mixed solvent; then, spin-coat the target surface of the CMOS wafer at a speed of 1000-1500 RPM for 10 seconds, and then spin-coat the target surface of the CMOS wafer at a speed of 4000-6000 RPM for 20 seconds; then, within 10 seconds, dropwise add ethyl acetate to the target surface of the CMOS wafer; then, anneal the CMOS wafer at a temperature of 100-150 degrees for 20-30 minutes.
8. The production method according to claim 1, characterized in that The “preparation of a K+ ion-doped indium oxide precursor solution” specifically includes: Indium nitrate hydrate is dissolved in DI water, and potassium chloride is added to the DI water to obtain a K+ ion-doped indium oxide precursor solution.
9. The production method according to claim 1, characterized in that The "preparation of an aluminum oxide precursor solution" specifically includes: Aluminum nitrate nonahydrate was dissolved in DI water to prepare an aluminum oxide precursor solution.
10. A chip, characterized in that: include: A CMOS wafer (101), the CMOS wafer (101) comprising a source, a drain and a gate, the CMOS wafer (101) being connected via multiple layers of metal interconnects, and a target surface of the CMOS wafer (101) being provided with a via hole structure; On the target surface and in a direction away from the CMOS wafer (101), a ZnO layer (102), a perovskite layer (103), an InO x Layer (104), AIO x layer (105) and Al layer (106), wherein the InO x The layer is doped with K+.