Manufacturing method of biological chip

Abstract

The invention discloses a manufacturing method of a biological chip. The method comprises the following steps: preparing a conductive substrate; array conductive salient points are processed on the surface of the substrate to form a conductive salient point layer; the screen plate is assisted by ultrasonic vibration to permeate and coat the insulating layer, and gradient curing is carried out; and performing high-precision polishing on the insulating layer based on the three-dimensional scanning data to expose the top surfaces of the salient points. The conductive bump layer is integrally formed on the conductive substrate, so that the traditional multilayer structure process is simplified, the interface contact resistance is eliminated, the adhesive force of the insulating layer is enhanced by combining vibration coating and gradient curing, and the coating is prevented from cracking. A dual process of rough grinding and then three-dimensional scanning guided fine grinding is adopted, so that the flatness deviation of the top surface of the salient point is ensured, and the distribution uniformity of an electric field is improved. The preparation method solves the problems of large energy loss and poor targeting of the traditional electroporation technology, has the characteristics of simple process, low cost and high electrode stability, and is suitable for the fields of transdermal drug delivery and skin treatment.

Description

Technical Field

[0001] The present invention relates to the technical field of biochips, and in particular to a method for manufacturing a biochip. Background Art

[0002] Electroporation is a unique physical phenomenon in cells. When exposed to an electric field, especially when the field strength exceeds a certain threshold, the dense structure of keratinocytes and the intercellular lipid layer physically rearranges, forming transient pores that enable efficient transdermal delivery of drugs / ingredients. With the development of the drill-and-wall theory of skin electroporation and its continued research, electroporation technology has become widely used in applications such as transdermal drug delivery and skin beauty.

[0003] However, traditional monopolar / bipolar electroporation technology still faces the following technical bottlenecks in practical applications:

[0004] 1. Inefficient energy utilization

[0005] Existing bipolar electroporation systems rely on voltage gradients exceeding 100V to generate effective electric field strength, but only 10%-20% of this energy actually reaches the target tissue. This significant amount of energy is wasted as heat or nonspecific ionization, resulting in high device power consumption and poor battery life. Furthermore, sustained high voltage output can pose safety risks, such as skin burns.

[0006] 2. Insufficient spatial targeting

[0007] Conventional electrode configurations use single-point or bipolar planar arrangements, and their electric field distribution exhibits diffuse characteristics. Non-target areas (such as subcutaneous nerves and blood vessels) are easily exposed to high-intensity electric fields, resulting in a narrow therapeutic window. Experimental data show that conventional dual-electrode systems have a high-intensity electric field at 1.5 J / cm 2 At this energy density, the electric field strength on the skin surface is only 30V / cm, and the field strength attenuation is exponentially related to the tissue depth.

[0008] 3. Limited penetration depth

[0009] Limited by the law of electric field attenuation, the field strength retention rate of monopolar electroporation in the dermis (at a frequency of 1Hz) is less than 20%. When the electric field penetrates to a depth of 4mm below the skin, the field strength has decayed to below 10V / cm, which is difficult to meet the treatment needs of deep lesions (such as scar tissue and hair follicle units).

[0010] Chinese Patent Publication No. CN115637225A discloses a microelectrode structure and its preparation method, comprising: a substrate layer; a transition layer located on one side of the substrate layer, and a groove extending through the transition layer; an electrode layer located on the side of the transition layer facing away from the substrate layer, the electrode layer covering the bottom and sidewalls of the groove and the surface of the transition layer facing away from the substrate layer; an insulating layer located within the groove and on the side of the electrode layer facing away from the substrate layer, the insulating layer exposing a portion of the electrode layer located on the side of the transition layer facing away from the substrate layer to form a plurality of microelectrode units; and an array arrangement of the plurality of microelectrode units. The microelectrode structure is based on a high-density regular array arrangement of multiple small-sized microelectrode units, resulting in a large number of microelectrodes per unit area. The micronization and regular arrangement of the electrodes can make the electric field distribution more uniform, and the micronized electric field can effectively focus the electric field to act on cells. Furthermore, the multi-layer composite microelectrode structure has the advantages of strong inertness, good stability, and good biocompatibility. While electroporation technology also utilizes multiple microelectrode units, it utilizes a complex multilayer structure (including a substrate layer, transition layer, electrode layer, and insulating layer), resulting in a cumbersome manufacturing process and high costs. Furthermore, the interfaces of these multilayer materials can suffer from poor adhesion or stress concentration, impacting long-term stability and, consequently, the lifespan of products using this structure.

[0011] Therefore, how to overcome the above-mentioned defects has become an important issue to be solved urgently by those skilled in the art. Summary of the Invention

[0012] The purpose of this application is to provide a method for manufacturing a biochip, which has the advantages of simple structure, simplified preparation process, reduced cost, and effective improvement of interface adhesion and long-term stability. A method for manufacturing a biochip comprises the following steps:

[0013] S1. Prepare a conductive substrate;

[0014] S2, processing a plurality of conductive bumps on one surface of the conductive substrate to form a conductive bump layer with conductive bumps;

[0015] S3, covering one surface of the conductive substrate with an insulating layer to cover the conductive bump layer;

[0016] S4. Grind the corresponding positions of the conductive bumps in the insulating layer to expose the top surfaces of the conductive bumps.

[0017] Preferably, step S2 includes:

[0018] S21, customized fixtures;

[0019] S22, fixing the conductive substrate on the surface of the fixture by vacuum adsorption;

[0020] S23. Array bumps are manufactured on one side of the corrected substrate by electrochemical etching or laser engraving.

[0021] Preferably, the fixture is provided with a plane correction plate; mesh holes are provided in the plane correction plate, and the mesh holes are integrally vacuumed to make the surface of the conductive substrate close to the plane correction plate, so as to correct the uneven conductive substrate.

[0022] Preferably, step S3 includes:

[0023] S31, fixing the conductive substrate using a fixture;

[0024] S32, covering the conductive substrate with a mesh sheet that is easy to penetrate the insulating coating;

[0025] S33, applying an insulating coating through a stencil, and uniformly distributing the insulating coating to a side of the conductive substrate with the conductive bump layer by ultrasonic vibration;

[0026] S34. Bake in an oven to set the shape.

[0027] Preferably, step S3 further includes:

[0028] Before covering the insulating layer, the conductive bump layer is cleaned in three stages;

[0029] After the insulation layer is applied, the coating adhesion is enhanced by step-by-step high-temperature baking.

[0030] Preferably, after step S2, the method further includes:

[0031] The top surface of the conductive bumps of the conductive bump layer is firstly rough ground.

[0032] Preferably, step S4 includes:

[0033] S41, scanning the surface height of the conductive bumps by a laser sensor, generating a three-dimensional image and programming and controlling the polishing path;

[0034] S42. Use a high-precision grinder for grinding and polishing, control the grinding depth and flatness deviation, and finely grind the top surface of the conductive bump.

[0035] Preferably, the grinding depth in step S4 is 80-120 μm.

[0036] Preferably, after step S4, the method further includes:

[0037] S5. Cover the exposed conductive bumps with a gold plating layer, and adhere the gold to the exposed conductive bumps by electroplating.

[0038] Preferably, the plurality of conductive bumps are distributed in a circular array; and the surface of a portion of the conductive bumps that is exposed is a plane.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. This invention, through the design of steps S1 to S4, produces a biochip structure comprising a conductive substrate, a conductive bump layer, and an insulating layer. Compared to existing technologies, this approach reduces the number of preparation steps and process steps, not only lowering manufacturing complexity and costs but also mitigating stress concentration issues caused by multi-layer stacking. The conductive bumps are formed directly on the conductive substrate, achieving integrated molding. This eliminates the interfacial contact resistance of traditional multi-layer structures, lowering overall impedance, improving current transmission efficiency, and reducing ineffective energy loss during transmission. By directly forming an array of conductive bumps on the conductive substrate, the biochip is able to focus the electric field on localized, tiny electrode points, achieving electric field focusing. Compared to existing large, planar electrodes, this approach offers higher current density and reduces operating voltage requirements. This allows for a stronger electric field strength even at lower operating voltages. While it can open the stratum corneum for electroporation, ensuring delivery of active ingredients, it also reduces voltage, preventing user discomfort such as skin irritation and erythema, thereby improving the user experience. Furthermore, electric field focusing reduces energy diffusion losses to non-target areas, thereby reducing overall thermal effects and preventing inactivation of active substances in the human body due to excessive heat.

[0041] 2. This case achieved one-time uniform coverage of the insulating layer through vibration-assisted coating and screen penetration, effectively reducing coating pores and interface defects, while avoiding the stress concentration risk caused by multi-layer material stacking, improving the long-term stability and preparation efficiency of the biochip, and further solving the problems of complex preparation process and poor interface adhesion of traditional multi-layer electrode structures.

[0042] 3. This solution optimizes the pretreatment and post-curing processes for the conductive substrate to enhance coating adhesion and avoid interface defects caused by stacked insulating layers. Traditional insulating coating processes rely solely on a single high-temperature cure, which can easily cause coating cracking. This solution, by adjusting the temperature gradient, releases internal stress in the material, thereby resolving the problem of coating shedding caused by poor interfacial adhesion in multilayer structures. This eliminates the microgaps between the insulating layer and the conductive bumps, allowing the biochip to maintain stable electrical performance during long-term contact with biological fluids. This also simplifies the fabrication process and reduces material costs. Furthermore, this solution further enhances the bonding strength between the insulating layer and the substrate through the aforementioned ultrasonic vibration-assisted infiltration and gradient curing process.

[0043] 4. This solution uses three-dimensional scanning and adaptive path planning to accurately match the actual shape of each bump. Combined with the closed-loop control capabilities of a high-precision grinder, it significantly improves grinding accuracy and efficiency. This solves the problem of uneven top surface exposure caused by inconsistent conductive bump height or substrate deformation during the grinding process, ensuring that all conductive bump top surfaces are fully exposed and meet the predetermined flatness requirements after the insulating layer is removed, thereby improving the contact reliability of biochip electrodes and signal transmission stability. In addition, this solution is combined with the above-mentioned step S2 to implement a process of coarse grinding followed by fine grinding. The rough grinding stage initially corrects the height differences of the conductive bumps formed, and then the fine grinding is combined with the three-dimensional scanning data to dynamically adjust the path. This dual process ensures further precise control of the flatness of the final bump top surface, solving the problem of surface flatness control in biochip electrode preparation. The biochip conductive bumps produced using this method are smoother, improving the user experience when using the biochip. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a flow chart of the method for manufacturing a biochip in Example 1 of this case.

[0045] Figure 2 Schematic diagram of the structure of the biochip in Example 1.

[0046] Figure 3 yes Figure 2 A magnified schematic diagram of .

[0047] Figure 4 yes Figure 2 Schematic diagram of the structure under the AA section view.

[0048] Figure 5 yes Figure 3 Enlarged schematic diagram of point B.

[0049] Figure 6 This is the second embodiment of the present case Figure 5 Schematic diagram of adding gold plating to the foundation.

[0050] Figure 7 This is a flow chart of the method for manufacturing a biochip in Example 2 of this case. DETAILED DESCRIPTION

[0051] The technical solutions of this application will be described clearly and completely below, in conjunction with the accompanying drawings. It should be understood that the described embodiments represent only a portion of the embodiments of this application, and not all of them. The components of this application, generally described and illustrated in the drawings herein, may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of this application. All other embodiments derived by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. Furthermore, in the description of this application, the terms "first," "second," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0052] In existing technologies, electroporation technology is limited in its application effectiveness due to problems such as low energy utilization, diffuse electric field distribution, and insufficient deep penetration. Traditional electrode systems rely on multi-layer composite structures to realize microelectrode arrays. The preparation process involves multiple steps such as substrate material, transition layer etching, and insulation layer filling, which leads to interfacial stress concentration and increased process complexity. When applied to transdermal drug delivery devices, the multi-layer stacking structure can easily lead to a decrease in coating adhesion. During long-term contact with biological tissue, interfacial delamination may occur, affecting the stability of the electric field output.

[0053] In order to solve the above problems, those skilled in the art have focused on simplifying the electrode structure and improving the manufacturing accuracy.

[0054] The following examples further illustrate the features of the present invention and other related features to facilitate understanding by those skilled in the art:

[0055] Example 1

[0056] like Figures 1 to 5 As shown, the present application proposes a method for manufacturing a biochip, comprising:

[0057] S1, prepare a conductive substrate 1;

[0058] S2, processing a plurality of arrays of conductive bumps 21 on one side surface of the conductive substrate 1 to form a conductive bump layer 2 with conductive bumps;

[0059] S3, covering the surface of one side of the conductive substrate with an insulating layer 3 to cover the conductive bump layer 2;

[0060] S4. Polishing the corresponding position of the conductive bump 21 in the insulating layer 3 to expose the top surface of the conductive bump 21.

[0061] Among them, the conductive substrate refers to the base material that supports the conductive structure. Specifically, it can be a thin plate made of conductive metal or a thin plate made of semiconductor material. Its function is to provide physical support and electrical connection basis for subsequent conductive bumps. The conductive bump layer refers to the raised conductive units distributed on the surface of the conductive substrate. Specifically, it can be formed by electrochemical corrosion or laser engraving process, and is used to establish a local high-density electric field. The insulating layer refers to the non-conductive medium covering the outside of the conductive bump. Specifically, it can be achieved by epoxy resin or polyimide coating. The electric field is spatially confined by completely wrapping the non-target area. The polishing process refers to the selective removal of the insulating layer. Specifically, mechanical grinding or laser ablation can be used to accurately expose the top surface of the conductive bump to form an effective electrical contact.

[0062] As described above, the present invention utilizes steps S1 through S4 to create a biochip structure comprising a conductive substrate, a conductive bump layer, and an insulating layer. This reduces the number of preparation steps and process steps compared to existing technologies, not only reducing manufacturing complexity and costs but also mitigating stress concentration issues caused by multi-layer stacking. The conductive bumps are formed directly on the conductive substrate, achieving integrated molding. This eliminates the interfacial contact resistance of traditional multi-layer structures, lowering overall impedance, improving current transmission efficiency, and reducing ineffective energy loss during transmission. By directly forming an array of conductive bumps on the conductive substrate, the biochip is able to focus the electric field on localized, tiny electrode points, achieving electric field focusing. Compared to existing large, planar electrodes, this provides higher current density and reduces operating voltage requirements. This allows for a stronger electric field strength even at lower operating voltages. While it can open the stratum corneum for electroporation, ensuring delivery of active ingredients, it also reduces voltage, preventing user discomfort such as skin irritation and erythema, thereby improving user experience. Furthermore, electric field focusing reduces energy diffusion losses to non-target areas, thereby reducing overall thermal effects and preventing active substances in the human body from being inactivated by excessive heat.

[0063] As a preferred embodiment, since the conductive substrate may be uneven during the manufacturing process, resulting in uneven corrosion bumps, step S2 of the present application includes:

[0064] S21. Customized fixtures; wherein, the fixture refers to a positioning device used to fix the conductive substrate, which can be specifically implemented by a fixture with a vacuum adsorption function, and its function is to ensure that the conductive substrate remains stable during the processing.

[0065] S22. Use vacuum adsorption to fix the conductive substrate on the surface of the fixture; vacuum adsorption refers to a fixing method that causes the substrate to adhere to the fixture surface through the action of negative pressure.

[0066] S23. An array of bumps is produced on one side of the corrected substrate by electrochemical etching or laser engraving. Electrochemical etching refers to a processing method in which an electric current is applied to selectively remove material in an electrolyte. Specifically, this method can be achieved using an acidic electrolyte in conjunction with a mask process. Its purpose is to form a micron-scale array structure. Laser engraving refers to a processing method in which a high-energy laser beam is used to ablate the material. Specifically, this method can be achieved using an ultraviolet laser in conjunction with a galvanometer system. Its purpose is to quickly generate a high-precision bump array.

[0067] As described above, the present application uses the combination of fixtures and vacuum adsorption to firmly fix the conductive substrate, eliminating the impact of substrate warping or offset on subsequent processing. The substrate is electrochemically corroded or laser engraved in a flat state, which can accurately control the geometric size and spatial distribution of the array bumps, thereby improving the position accuracy of the conductive bumps. Moreover, the present solution realizes the bump array by directly processing a single-layer conductive substrate, reducing the number of material interfaces; compared with the existing technology, the present solution can complete the array forming through a single-step processing of electrochemical corrosion or laser engraving, which simplifies the process flow compared with the existing technology, avoids the adhesion problem caused by the interface of multi-layer materials, and enhances the structural integrity by adopting the method of direct processing of a single-layer substrate, thereby improving the long-term use reliability of the biochip. In addition, electrochemical corrosion can realize the formation of bumps of different depths by adjusting the current density and corrosion time; laser engraving can form a highly consistent surface morphology by precisely controlling the spot size and energy density.

[0068] As a preferred embodiment, the present application further proposes a fixture equipped with a flatness correction plate; the flatness correction plate is provided with mesh holes, and vacuum is applied through the mesh holes to force the surface of the conductive substrate into close contact with the flatness correction plate, thereby correcting uneven conductive substrates. The flatness correction plate refers to a rigid plate that functions as a reference plane. Specifically, it can be implemented as a surface-polished metal plate or ceramic substrate. Its high flatness provides a physical reference for morphological correction of the conductive substrate. The mesh holes refer to an array of through-holes distributed on the surface of the flatness correction plate, which are connected to a vacuum adsorption device to generate a negative pressure adsorption effect. The overall vacuuming refers to applying a negative pressure to the entire area covered by the mesh holes. Specifically, this can be achieved using a multi-channel vacuum pump assembly in conjunction with a sealed chamber structure. Local deformation of the conductive substrate is eliminated through a uniformly distributed adsorption force. In a specific implementation, during the fixing process of the conductive substrate, the conductive substrate is placed on the flatness correction plate. The vacuum adsorption system generates a uniformly distributed negative pressure through the mesh holes, forcibly stretching the uneven areas of the conductive substrate until they are completely in contact with the flatness correction plate. This eliminates deformations such as bending and warping of the substrate caused by production or storage, ensuring the positional accuracy and high consistency of the conductive bumps in subsequent processing steps. Furthermore, through the synergistic effect of the flat correction plate and vacuum adsorption, physical correction, uniform fixation, and stress dispersion are used to address substrate deformation at the source, reducing initial deformation. This not only simplifies the process (eliminating complex calibration steps), but also improves the adhesion reliability of multi-layer materials by suppressing interfacial stress, making it suitable for high-precision manufacturing.

[0069] As a preferred embodiment, step S3 of the present application includes the following steps:

[0070] S31, fixing the conductive substrate using a fixture;

[0071] S32, covering the conductive substrate with a mesh sheet that is easy to penetrate the insulating coating;

[0072] S33, applying an insulating coating through a stencil, and uniformly and tightly distributing the insulating coating to a side of the conductive substrate with the conductive bump layer by ultrasonic vibration;

[0073] S34. Bake in an oven to set the shape.

[0074] The fixture is a clamping device used to secure the conductive substrate. Specifically, it can be implemented using a vacuum clamp or a mechanical snap-on clamp, or it can share the fixture used in step S2. Its function is to ensure the positional stability of the conductive substrate during processing and prevent deviation that could lead to uneven coating coverage. The stencil is a template with a perforated structure. Specifically, it can be implemented using a metal etched stencil or a polymer laser-engraved stencil. Its function is to control the penetration path and distribution range of the insulating coating, preventing excessive accumulation of coating in the gaps between the conductive bumps. Ultrasonic vibration is used to promote the insulating coating to fully fill the gaps between the conductive bumps at a microscopic scale through cavitation, eliminating bubbles and improving the coating's density. Oven baking is a thermal curing process performed on the insulating material to form a solid insulating layer that is tightly bonded to the conductive substrate. In practice, after the conductive bumps are processed on the conductive substrate, the substrate is first securely secured using a fixture, and then the stencil is applied to the substrate surface. The insulating coating penetrates the stencil's pores and reaches the substrate surface. At this point, ultrasonic vibration is applied, forcing the coating to spread evenly under the action of surface tension, fully filling the recessed areas between the bumps. Finally, the coating is cured in an oven, forming an insulating layer that completely covers the conductive bump layer. This solution achieves efficient insulation coverage through a single coating combined with a vibration-assisted molding process, significantly simplifying the process.

[0075] As mentioned above, the production process may result in uneven insulation or areas of missing coverage. Therefore, this case achieves uniform, one-time coverage of the insulation layer through vibration-assisted coating and stencil penetration, effectively reducing coating porosity and interface defects. This also avoids the stress concentration risks associated with multi-layer material stacking, improves the long-term stability and production efficiency of the biochip, and further addresses the complex production process and poor interface adhesion issues of traditional multi-layer electrode structures.

[0076] As a preferred embodiment, the method further comprises the following steps:

[0077] Before covering the insulating layer, the conductive bump layer is subjected to a three-stage cleaning step to make the surface of the conductive substrate reach a clean level;

[0078] After the insulating layer is applied, a step-by-step high-temperature baking process is performed to make the coating highly adhere to the surface of the conductive substrate, thereby enhancing the coating adhesion through step-by-step high-temperature baking.

[0079] Three-stage cleaning refers to the phased removal of contaminants from the surface of the conductive substrate. This can be achieved through a combination of ultrasonic cleaning with an alkaline solution to remove grease, soaking with an acidic solution to remove oxides, and rinsing with deionized water to remove residual ions. This step-by-step cleaning process enhances the surface activity of the substrate. Step-by-step high-temperature baking refers to the phased heating and curing of the insulating layer. This can be achieved through a gradient heating mode, for example, gradually increasing the temperature from 80°C to 160°C and maintaining a constant temperature for multiple stages. This gradual temperature change reduces internal stress in the coating and promotes the orderly arrangement of molecular chains. In practice, before being coated with the insulating coating, the conductive bump layer is subjected to ultrasonic vibration with an alkaline solution to strip away organic residue from the surface. Subsequently, the metal oxide layer is etched with an acidic solution, and finally, ionic contamination is eliminated through high-frequency rinsing with deionized water. After the insulating coating is applied, the substrate is placed in a segmented temperature-controlled oven. The initial low-temperature stage allows the coating to initially crosslink to form a continuous film layer. The subsequent gradual increase in temperature promotes complete polymerization of the polymer material, thereby eliminating the risk of interface delamination.

[0080] As mentioned above, during the process of forming the insulating layer on a biochip, the insulating layer is prone to falling off, resulting in defective products. This solution optimizes the pretreatment and post-curing processes of the conductive substrate to enhance the coating adhesion and avoid interface defects caused by the stacking of the insulating layers. Furthermore, the traditional insulating coating process only uses a single high-temperature cure, which can easily cause the coating to crack. This solution achieves internal stress release in the material by adjusting the temperature gradient, thereby solving the problem of coating shedding caused by poor interface adhesion of the multilayer structure and eliminating the micro-gap between the insulating layer and the conductive bumps. This allows the biochip to maintain stable electrical performance during long-term contact with biological fluids, while simplifying the preparation process and reducing material costs. Furthermore, this solution further enhances the bonding strength between the insulating layer and the substrate through the aforementioned ultrasonic vibration-assisted infiltration and gradient curing process.

[0081] As a preferred embodiment, the present application further proposes that after step S2, the top surface of the conductive bump of the conductive bump layer is rough ground. Rough grinding refers to a preliminary grinding process of the top surface of the conductive bump, which can be achieved by using a grinding wheel or a grinder to remove surface burrs and irregular protrusions through mechanical contact, so that the top surface of the conductive bump forms a uniform preparatory surface. This step can eliminate the microscopic unevenness generated during the conductive bump forming process, provide a reference surface for the subsequent fine grinding process, and thus reduce the complexity of grinding path planning.

[0082] This solution solves the problem of uneven electric field distribution caused by surface unevenness in biochip fabrication. The rough grinding process pre-qualifies the top surface of the conductive bumps to a uniform reference surface, ensuring the precision and consistency of the subsequent insulation layer coating and fine grinding processes, thereby improving the electric field focusing capability and energy utilization efficiency of the electrode array.

[0083] As a preferred embodiment, the present application further proposes that step S4 includes:

[0084] S41. Scan the height of the surface of the conductive bump using a laser sensor to generate a three-dimensional image and program the polishing path. Specifically, scanning the height of the surface of the conductive bump using a laser sensor refers to obtaining geometric information about the top of the bump using a non-contact optical measuring device. This can be achieved using the principle of laser triangulation, by emitting a laser beam and receiving a reflected light signal to calculate the surface height difference. This method can avoid deformation of the bump caused by physical contact while establishing accurate three-dimensional coordinate data. Generating a three-dimensional image and programmatically controlling the polishing path refers to converting the height data into a three-dimensional model and generating the optimal polishing trajectory through an algorithm. This can be achieved using computer-aided manufacturing software, such as using point cloud data processing technology to automatically plan the motion trajectory of the grinding head. This method ensures that the polishing path accurately matches the actual shape of the bump, eliminating manual operation errors.

[0085] S42. Use a high-precision grinder for grinding and polishing, control the grinding depth and flatness deviation, and fine-grind the top surface of the conductive bumps. Grinding and polishing with a high-precision grinder refers to the use of a CNC machine tool with micron-level positioning accuracy to perform surface treatment. Specifically, it can be achieved by using an air-bearing spindle with a diamond grinding head, and the grinding parameters are adjusted in real time through a closed-loop feedback system. This method can accurately control the amount of material removed and maintain the consistency of the flatness of the top surface of each bump. In specific implementation, after completing the rough grinding of the conductive bumps, the laser sensor scans the entire surface of the bump array to generate three-dimensional point cloud data containing the height distribution of each bump. Based on this data, the control system automatically generates a grinding path program that matches the actual position and height of each bump. According to the program instructions, the high-precision grinder drives the grinding head to move along a predetermined trajectory through multi-axis linkage. During the polishing process, the grinding pressure and depth are monitored in real time, and the feed speed and grinding head speed are dynamically adjusted, ultimately making the top surface of all conductive bumps meet the predetermined flatness requirements.

[0086] As mentioned above, during the polishing process of the top surface of the conductive bump, the polishing tool may not be flat enough, resulting in poor bump polishing consistency, causing over-polishing or under-polishing of the electrode bump, and thus causing electrode defects. This solution uses three-dimensional scanning and adaptive path planning to accurately match the actual shape of each bump. Combined with the closed-loop control capabilities of the high-precision grinder, it significantly improves polishing accuracy and efficiency. This solves the problem of uneven top surface exposure caused by inconsistent conductive bump height or substrate deformation during the polishing process, ensuring that after the insulating layer is removed, the top surface of all conductive bumps can be fully exposed and meet the predetermined flatness requirements, thereby improving the contact reliability of biochip electrodes and the stability of signal transmission. In addition, this case is combined with the rough grinding process of the top surface of the conductive bump after the above-mentioned step S2 to realize the process coordination of rough grinding first and then fine grinding. The height difference of the conductive bumps formed is preliminarily corrected in the rough grinding stage, and then the path is dynamically adjusted through fine grinding combined with three-dimensional scanning data. The dual process ensures further precise control of the flatness of the top surface of the final bump, solves the problem of surface flatness control in the preparation of biochip electrodes, and makes the conductive bumps of the biochip produced by the method of this case smoother, thereby improving the user contact experience when using the biochip.

[0087] As a preferred embodiment, the present application further proposes that the grinding depth range in step S4 is 80-120um, preferably 100um, and cannot exceed the height of the conductive bump itself. Among them, the grinding depth refers to the material removal thickness between the surface of the insulating layer and the top surface of the conductive bump. In specific implementation, after the insulating layer is covered, the top surface of the conductive bump is precisely processed by a preset grinding program. The grinding path planning is based on the three-dimensional distribution data of the conductive bump, and a closed-loop control system is used to dynamically adjust the grinding pressure and feed speed. During the grinding process, the sensor continuously monitors the amount of material removed and automatically stops processing when the target depth is reached. By setting 100 microns, the effective exposure requirement of the conductive bump is met. In this way, by quantifying the grinding depth, the effective effective area of each conductive bump is ensured to be consistent, thereby improving the uniformity of the electric field distribution. The parameter setting of 80-120um can ensure the effective exposure of the conductive bump while avoiding excessive grinding that causes damage to the insulating layer or insufficient height of the conductive bump.

[0088] During the biochip production process, we tried different polishing depths and found that it was difficult to polish at too high a depth, and the polished surface was not smooth enough. Therefore, this case used a gradient experiment to verify the comprehensive performance differences of different polishing depths, and formed the following comparative data table:

[0089]

[0090] As can be seen from the above table, at a depth of 80-120um, the surface roughness can be guaranteed to be less than 50nm, the insulating layer can be guaranteed to be intact, and the yield rate can be greater than 95%. Therefore, in order to ensure that the surface of the conductive bump is smooth, the insulating layer is not damaged, and the yield rate of the biochip is guaranteed, this case limits the polishing depth range to 80-120um, with 100um being preferred.

[0091] like Figure 2 As shown, as a preferred embodiment, the plurality of conductive bumps 2 are distributed in a circular array; the exposed surface of the conductive bumps 2 is a flat surface. The exposed surface of the conductive bumps serves as an electrode point that contacts the human body. The spacing between two adjacent conductive bumps 2 is 1-999 μm, the height of each conductive bump 2 ranges from 10-200 μm, and the exposed surface of each conductive bump serves as an electrode point, with a diameter ranging from 10-500 μm.

[0092] In this way, the design of the circular array distribution of multiple conductive bumps in this case makes the electric field superposition area of adjacent conductive bumps distributed in a ring-shaped symmetrical manner, optimizing the electric field focusing effect and avoiding the generation of local hot spots. The electrode points exposed by the conductive bumps through the polishing process are planar structures, and the pressure is evenly distributed when in contact with the skin, avoiding local current concentration. By limiting the distance between two adjacent conductive bumps and the electrode point diameter (that is, the top diameter of the conductive bump exposed), it is possible to integrate a number of conductive bumps far exceeding the large electrodes in the existing technology within the same unit area. When the same voltage or current is applied, the current can be more evenly distributed on each conductive bump, effectively improving the current density. The design of the size range of 1-999um, 10-200um, and 10-500um can flexibly adapt to different cell sizes or experimental requirements.

[0093] In specific implementation, the entire production process of Example 1 of this case is as follows: First, a conductive substrate with a flatness that meets the standard is selected as the base layer to be processed in this application. After the conductive substrate is placed on a fixture, a vacuum adsorption device is used to fix and adsorb the conductive substrate; then, a regularly arranged conductive bump array is formed at a preset position through electrochemical corrosion or laser engraving technology to form a conductive bump layer on the surface of one side of the conductive substrate. Subsequently, the liquid insulating material is evenly applied to the surface of the substrate, and ultrasonic vibration and the screen are used to promote the penetration of the coating into the surface of the conductive bump layer to ensure complete isolation between the conductive bumps. The solidified insulating layer is positioned by three-dimensional scanning, and the top area of the conductive bump is finely ground using a CNC grinder, and the removal depth is precisely controlled to ensure that the conductive surface is completely exposed.

[0094] Example 2

[0095] like Figure 6 and Figure 7As shown, the second embodiment further proposes the following on the basis of the first embodiment:

[0096] After step S4, the method further includes:

[0097] S5. Cover the exposed conductive bumps 2 with a gold plating layer 4, allowing the gold to automatically adhere to the exposed conductive bumps through electroplating. This automatically adheres to the exposed bumps, increasing the electrode surface's antioxidant capacity, improving electrode safety, and improving the biochip's compatibility with skin.

[0098] In summary, through the above technical solutions, this application solves the problems of diffuse electric field distribution and insufficient penetration depth in traditional electroporation technology. The circular array arrangement increases the electric field density per unit area, concentrating the energy on the target cell area; the flat surface reduces contact impedance and reduces energy loss in non-target tissues, thereby improving energy utilization efficiency at the same input voltage and reducing the risk of skin burns.

[0099] As mentioned above, this case protects a method for manufacturing a biochip, and all technical solutions that are identical or similar to this case should be deemed to fall within the scope of protection of this case.

Claims

1. A method for making a biochip, characterized in that: The following steps are involved: S1. Prepare a conductive substrate; S2, processing a plurality of conductive bumps on one surface of the conductive substrate to form a conductive bump layer with conductive bumps; S3, covering one surface of the conductive substrate with an insulating layer to cover the conductive bump layer; S4. Grind the corresponding positions of the conductive bumps in the insulating layer to expose the top surfaces of the conductive bumps.

2. The method for producing a biochip according to claim 1, wherein: Step S2 includes: S21, customized fixtures; S22, fixing the conductive substrate on the surface of the fixture by vacuum adsorption; S23. Array bumps are manufactured on one side of the corrected substrate by electrochemical etching or laser engraving.

3. The method for producing a biochip according to claim 2, wherein: The fixture is provided with a plane correction plate; mesh holes are arranged in the plane correction plate, and the mesh holes are used to vacuum the surface of the conductive substrate so as to make the surface of the conductive substrate close to the plane correction plate to correct the uneven conductive substrate.

4. The method for producing a biochip according to any one of claims 1 to 3, characterized in that: Step S3 includes: S31, fixing the conductive substrate using a fixture; S32, covering the conductive substrate with a mesh sheet that is easy to penetrate the insulating coating; S33, applying an insulating coating through a stencil, and uniformly distributing the insulating coating to a side of the conductive substrate with the conductive bump layer by ultrasonic vibration; S34. Bake in an oven to set the shape.

5. The method for producing a biochip according to claim 4, wherein: Step S3 further includes: Before covering the insulating layer, the conductive bump layer is cleaned in three stages; After the insulation layer is applied, the coating adhesion is enhanced by step-by-step high-temperature baking.

6. The method for producing a biochip according to claim 1, wherein: After step S2, the method further includes: The top surface of the conductive bumps of the conductive bump layer is firstly rough ground.

7. The method for producing a biochip according to claim 1 or 6, wherein: Step S4 includes: S41, scanning the surface height of the conductive bumps by a laser sensor, generating a three-dimensional image and programming and controlling the polishing path; S42. Use a high-precision grinder for grinding and polishing, control the grinding depth and flatness deviation, and finely grind the top surface of the conductive bump.

8. The method for producing a biochip according to claim 7, wherein: The grinding depth in step S4 is 80-120 μm.

9. The method for producing a biochip according to claim 1, wherein: After step S4, the method further includes: S5. Cover the exposed conductive bumps with a gold plating layer, and adhere the gold to the exposed conductive bumps by electroplating.

10. The method for producing a biochip according to claim 1, wherein: The plurality of conductive bumps are distributed in a circular array; and the surface of a portion of the conductive bumps that is exposed is a plane.

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