Direct current detection circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of electronic circuits, in particular to a direct current detection circuit, a chip and electronic equipment. The direct current detection circuit is used for detecting a direct current signal in the differential amplification circuit. The DC detection circuit comprises a switch module and an amplification processing module. And the differential amplification circuit is sequentially connected with the switch module, the amplification processing module and the switch module. When the switch module is in the first state, the switch module can conduct the first output end of the differential amplification circuit and the first input end of the amplification processing module, so that the amplification processing module outputs a first signal. And when the switch module is in the second state, the switch module can be in short circuit with the first input end and the second input end of the amplification processing module, so that the amplification processing module outputs a second signal. According to the direct current detection circuit in the embodiment of the invention, the direct current offset voltage of the differential amplification circuit can be effectively eliminated.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a DC detection circuit, a chip, and an electronic device. Background Art

[0002] Speakers in audio devices typically amplify audio signals using Class-D differential amplifiers. The output signal from a Class-D differential amplifier typically includes a DC offset voltage, a voltage inherent in the amplifier's output. In some scenarios, this DC offset voltage can cause popping noise in the audio signal during gain switching, a type of noise.

[0003] In order to ensure the normal use of the speaker and avoid noise signals, DC offset voltage detection is required to accurately measure the DC offset voltage in the output signal of the Class D differential amplifier circuit to eliminate the DC offset voltage.

[0004] In some solutions, the DC offset voltage is detected by adding a capacitor to a Class D differential amplifier. Specifically, the charge and discharge voltages of the capacitor are compared with a reference voltage, and a corresponding level is output to indicate the presence or absence of a DC offset voltage. However, the specific value of the DC offset voltage cannot be determined, and the measurement accuracy is low. In other solutions, the DC offset voltage is measured using a high-precision machine, but this method has a high measurement cost. Summary of the Invention

[0005] The illustrative embodiments of the present application provide a direct current detection circuit, a chip, and an electronic device.

[0006] In a first aspect, the present application provides a DC detection circuit for detecting a DC signal in a differential amplifier circuit; the DC detection circuit includes: a switch module for connecting to the differential amplifier circuit; an amplification processing module connected to the switch module; the switch module can switch between a first state and a second state, and when the switch module is in the first state, the switch module can connect the first output end of the differential amplifier circuit and the first input end of the amplification processing module, and connect the second output end of the differential amplifier circuit and the second input end of the amplification processing module, so that the amplification processing module outputs a first signal; when the switch module is in the second state, the switch module can short-circuit the first input end and the second input end of the amplification processing module, so that the amplification processing module outputs a second signal.

[0007] In an embodiment of the present application, a switch module in a DC detection circuit can switch between a first state and a second state. The output signal of the DC detection circuit is detected in the first and second states of the switch module. When the switch module is in the first state, the output signal of the DC detection circuit may be a first signal. When the switch module is in the second state, the output signal of the DC detection circuit may be a second signal. The first and second signals are analog signals.

[0008] Based on the above-described DC detection circuit, the first signal is a signal obtained by first amplifying the DC offset voltage of the differential amplifier circuit and the DC offset voltage of the amplification processing module, and the second signal is a signal obtained by first amplifying the DC offset voltage of the amplification processing module. Since the difference between the first signal and the second signal lies primarily in that the first signal includes the DC offset voltage of the differential amplifier circuit, while the second signal does not, the DC offset voltage of the differential amplifier circuit can be accurately obtained by processing the result obtained by performing a subtraction operation based on the two detection results, thereby effectively eliminating the DC offset voltage of the differential amplifier circuit.

[0009] In a possible implementation of the first aspect above, the switch module includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube; the first end of the first switch tube is used to be connected to the first output end of the differential amplifier circuit, and the second end of the first switch tube is connected to the first input end of the amplification processing module; the first end of the second switch tube is used to be connected to the first output end of the differential amplifier circuit, and the second end of the second switch tube is connected to the second input end of the amplification processing module; the first end of the third switch tube is used to be connected to the second output end of the differential amplifier circuit, and the second end of the third switch tube is connected to the first input end of the amplification processing module; the first end of the fourth switch tube is used to be connected to the second output end of the differential amplifier circuit, and the second end of the fourth switch tube is connected to the second input end of the amplification processing module.

[0010] In a possible implementation of the first aspect above, when the first switch tube and the fourth switch tube are closed and the second switch tube and the third switch tube are disconnected, the switch module is in the first state; or when the first switch tube and the fourth switch tube are disconnected and the second switch tube and the third switch tube are closed, the switch module is in the first state.

[0011] In a possible implementation of the first aspect above, when the first switch tube and the second switch tube are closed and the third switch tube and the fourth switch tube are disconnected, the switch module is in the second state; or when the first switch tube and the second switch tube are disconnected and the third switch tube and the fourth switch tube are closed, the switch module is in the second state.

[0012] In a possible implementation of the first aspect, the DC detection circuit includes a low-pass filter, and the switch module is connected to the differential amplifier circuit through the low-pass filter.

[0013] In the embodiment of the present application, the low-pass filter can filter out high-frequency signals in the output signals of the two output terminals of the differential amplifier circuit.

[0014] In a possible implementation of the first aspect above, the first input end of the low-pass filter is used to connect to the first output end of the differential amplifier circuit, and the second input end of the low-pass filter is used to connect to the second output end of the differential amplifier circuit; the first output end of the low-pass filter is used to connect to the first end of the first switching tube and the first end of the second switching tube in the switching module, respectively, and the second output end of the low-pass filter is used to connect to the first end of the third switching tube and the first end of the fourth switching tube in the switching module, respectively.

[0015] In a possible implementation of the first aspect above, the first signal and the second signal are analog signals; the DC detection circuit also includes an analog-to-digital conversion module, and the input end of the analog-to-digital conversion module is connected to the output end of the amplification and processing module; when the switch module is in a first state, the analog-to-digital conversion module converts the first signal and the DC offset voltage of the analog-to-digital conversion module into a first digital signal; when the switch module is in a second state, the analog-to-digital conversion module converts the second signal and the DC offset voltage of the analog-to-digital conversion module into a second digital signal.

[0016] It can be understood that the first digital signal may refer to DC_OUT1 mentioned in the embodiment of the present application, and the second digital signal may refer to DC_OUT2 mentioned in the embodiment of the present application.

[0017] In a possible implementation of the first aspect above, the DC detection circuit also includes an operation module, which is connected to the output end of the analog-to-digital conversion module; the operation module is used to perform a subtraction operation on the first digital signal and the second digital signal to obtain a DC offset voltage of the differential amplifier circuit.

[0018] In a possible implementation of the first aspect above, the amplification processing module includes a first amplifier, a first resistor, a second amplifier, a second resistor, a third amplifier, a third resistor, and a fourth resistor, wherein the first resistor and the second resistor are equal, and the third resistor and the fourth resistor are equal; a positive-phase input terminal of the first amplifier is connected to the first input terminal of the amplification processing module, a negative-phase input terminal of the first amplifier is connected to the output terminal of the first amplifier and the first terminal of the first resistor, a second terminal of the first resistor is connected to the first terminal of the fourth resistor and the positive-phase input terminal of the third amplifier, a second terminal of the fourth resistor is connected to the reference voltage terminal, and the output terminal of the first amplifier is connected to the negative-phase input terminal of the first amplifier and the first terminal of the first resistor; a positive-phase input terminal of the second amplifier is connected to the second input terminal of the amplification processing module, a negative-phase input terminal of the second amplifier is connected to the output terminal of the second amplifier and the first terminal of the second resistor, a second terminal of the second resistor is connected to the first terminal of the third resistor and the negative-phase input terminal of the third amplifier; a positive-phase input terminal of the third amplifier is connected to the second terminal of the first resistor and the first terminal of the fourth resistor, a negative-phase input terminal of the third amplifier is connected to the second terminal of the second resistor and the first terminal of the third resistor, and an output terminal of the third amplifier is connected to the second terminal of the third resistor and the input terminal of the analog-to-digital conversion module.

[0019] In a possible implementation of the first aspect above, the amplification processing module includes a first amplifier, a first resistor, a second amplifier, a second resistor, a third amplifier, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor, wherein the first resistor and the second resistor are equal, the third resistor and the fourth resistor are equal, and the fifth resistor and the seventh resistor are equal; the positive phase input terminal of the first amplifier is connected to the first input terminal of the amplification processing module, the negative phase input terminal of the first amplifier is connected to the second end of the fifth resistor and the first end of the sixth resistor, the second end of the fifth resistor is connected to the output terminal of the first amplifier and the first end of the first resistor, the second end of the sixth resistor is connected to the negative phase input terminal of the second amplifier and the first end of the seventh resistor, and the output terminal of the first amplifier is connected to the fifth resistor. The second end of the resistor is connected to the first end of the sixth resistor; the positive phase input end of the second amplifier is connected to the second input end of the amplification processing module, the negative phase input end of the second amplifier is connected to the second end of the fifth resistor, the first end of the sixth resistor and the first end of the seventh resistor, the second end of the seventh resistor is connected to the output end of the second amplifier, and the output end of the second amplifier is connected to the second end of the seventh resistor and the first end of the second resistor; the positive phase input end of the third amplifier is connected to the second end of the first resistor and the first end of the fourth resistor, the second end of the fourth resistor is connected to the reference voltage end, the negative phase input end of the third amplifier is connected to the second end of the second resistor and the first end of the third resistor, and the second end of the third resistor is connected to the output end of the third amplifier and the input end of the analog-to-digital conversion module.

[0020] In a second aspect, the present application provides a chip, which includes the DC detection circuit provided by the first aspect and various possible implementations of the first aspect.

[0021] In a third aspect, the present application provides an electronic device comprising the chip provided in the second aspect.

[0022] The beneficial effects of the second to third aspects mentioned above can be found in the relevant descriptions of the first aspect and various possible implementations of the first aspect, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 According to some embodiments of the present application, a circuit schematic diagram of a DC detection circuit 10 is shown;

[0024] Figure 2 According to some embodiments of the present application, a circuit diagram of another DC detection circuit 10 is shown;

[0025] Figure 3 According to some embodiments of the present application, a structural schematic diagram of the amplification processing module 104 is shown;

[0026] Figure 4 According to some embodiments of the present application, a schematic structural diagram of another amplification processing module 104 is shown. DETAILED DESCRIPTION

[0027] Illustrative embodiments of the present application include, but are not limited to, a DC detection circuit, a chip, and an electronic device.

[0028] The specific implementation process of the technical solution provided by the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0029] It can be understood that the DC detection circuit of the embodiment of the present application can be applied to any electronic device that requires a DC detection circuit, such as mobile phones, tablet computers, headphones, smart wearable devices and smart home devices, etc., without limitation here.

[0030] As mentioned above, in some solutions, the DC offset voltage of the Class D differential amplifier is detected by adding a capacitor to the Class D differential amplifier, but the measurement accuracy is low; in other solutions, the DC offset voltage of the Class D differential amplifier is detected by adding a high-precision machine to the Class D differential amplifier, but the measurement cost is high.

[0031] To address the above-mentioned issues, an embodiment of the present application provides a DC detection circuit for detecting a DC signal in a differential amplifier circuit. The DC detection circuit includes a switch module and an amplification processing module. The switch module is connected to the differential amplifier circuit, and the amplification processing module is connected to the switch module. Furthermore, the switch module is capable of switching between a first state and a second state. When the switch module is in the first state, the switch module is capable of connecting the first output terminal of the differential amplifier circuit to the first input terminal of the amplification processing module, and connecting the second output terminal of the differential amplifier circuit to the second input terminal of the amplification processing module, so that the amplification processing module outputs a first signal S1. When the switch module is in the second state, the switch module is capable of short-circuiting the first input terminal and the second input terminal of the amplification processing module, so that the amplification processing module outputs a second signal S2. The first signal S1 is a signal obtained by first amplifying the DC offset voltage Vc of the differential amplifier circuit and the DC offset voltage Vos1 of the amplification processing module, and the second signal S2 is a signal obtained by first amplifying the DC offset voltage Vos1 of the amplification processing module.

[0032] Based on the above scheme, when the switch module is in the first state, the amplification processing module can output a first signal S1 = G × (Vc + Vos1); when the switch module is in the second state, the amplification processing module can output a second signal S2 = Vos1 * G. Here, G is the amplification factor of the amplification processing module. It can be understood that the difference between the first signal S1 and the second signal S2 is Vc * G. By dividing this difference by G, the DC offset voltage Vc of the differential amplifier circuit can be obtained.

[0033] That is to say, by switching the state of the switch circuit, the DC offset voltage of the differential amplifier circuit itself can be effectively eliminated, thereby obtaining an accurate DC offset voltage of the differential amplifier circuit.

[0034] The DC detection circuit mentioned in this application is introduced in detail below.

[0035] For example, Figure 1 A DC detection circuit 10 is shown. Figure 1 The DC detection circuit 10 is connected to the differential amplifier circuit 101. The DC detection circuit 10 includes a switch module 103 and an amplifier processing module 104. The differential amplifier circuit 101 is connected to the switch module 103 and the amplifier processing module 104.

[0036] The differential amplifier circuit 101 includes a first output terminal VOP and a second output terminal VON. The first output terminal VOP of the differential amplifier circuit 101 is connected to the first input terminal of the switch module 103, and the second output terminal VON of the differential amplifier circuit 101 is connected to the second input terminal of the switch module 103. It can be understood that the differential amplifier circuit 101 can be a class D differential amplifier circuit. The differential amplifier circuit 101 can be used to amplify a low-power input signal (such as an audio signal) of the differential amplifier circuit 101 into a high-power signal to drive a load (such as driving a speaker to produce sound). In the embodiment of the present application, the circuit structure of the differential amplifier circuit 101 is not specifically limited.

[0037] The switch module 103 may include a first switch transistor k1, a second switch transistor k2, a third switch transistor k3, and a fourth switch transistor k4. The first end of the first switch transistor k1 is connected to the first output terminal VOP of the differential amplifier circuit 101, and the second end of the first switch transistor k1 is connected to the first input terminal of the amplification processing module 103. The first end of the second switch transistor k2 is connected to the first output terminal VOP of the differential amplifier circuit 101, and the second end of the second switch transistor k2 is connected to the second input terminal of the amplification processing module 103. The first end of the third switch transistor k3 is connected to the second output terminal VON of the differential amplifier circuit 101, and the second end of the third switch transistor k3 is connected to the first input terminal of the amplification processing module 103. The first end of the fourth switch transistor k4 is connected to the second output terminal VON of the differential amplifier circuit 101, and the second end of the fourth switch transistor k4 is connected to the second input terminal of the amplification processing module 101.

[0038] In some embodiments of the present application, when the first switch tube k1 and the fourth switch tube k4 are closed, and the second switch tube k2 and the third switch tube k3 are open, it can be determined that the switch module 103 is in the first state. Alternatively, when the first switch tube k1 and the fourth switch tube k4 are open, and the second switch tube k2 and the third switch tube k3 are closed, it can be determined that the switch module 103 is in the first state.

[0039] In some embodiments of the present application, when the first switch tube k1 and the second switch tube k2 are closed, and the third switch tube k3 and the fourth switch tube k4 are open, it can be determined that the switch module 103 is in the second state. Alternatively, when the first switch tube k1 and the second switch tube k2 are open, and the third switch tube k3 and the fourth switch tube k4 are closed, the switch module 103 is in the second state.

[0040] exist Figure 1In the illustrated DC detection circuit 10, the switch module 103 can switch between a first state and a second state. When the switch module is in the first state, the switch module 103 can connect the first output terminal of the differential amplifier circuit 101 to the first input terminal of the amplification processing module 104, and connect the second output terminal of the differential amplifier circuit 101 to the second input terminal of the amplification processing module 104, so that the amplification processing module 104 outputs a first signal. When the switch module 103 is in the second state, the switch module 103 can short-circuit the first input terminal and the second input terminal of the amplification processing module 104, so that the amplification processing module 104 outputs a second signal. The first signal is a signal obtained by first amplifying the DC offset voltage of the differential amplifier circuit 101 and the amplification processing module 104, and the second signal is a signal obtained by first amplifying the DC offset voltage of the amplification processing module.

[0041] I understand. Figure 1 Vos1 in the figure can represent the DC offset voltage of the amplifying and processing module 104. When the switch module 103 is in the first state, Figure 1 The output signal OUT of the DC detection circuit 10 may be a first signal. When the switch module 103 is in the second state, Figure 1 The output signal OUT of the DC detection circuit 10 may be a second signal, wherein the first signal and the second signal are analog signals.

[0042] based on Figure 1 In the DC detection circuit 10 shown, when the switch module 103 is in the first state, the amplification processing module 104 can output a first signal S1 = (Vc + Vos1); when the switch module 103 is in the second state, the amplification processing module 104 can output a second signal S2 = Vos1. Here, G is the amplification factor of the amplification processing module 104. It can be understood that the difference between the first signal S1 and the second signal S2 is Vc*G. Dividing this difference by G yields the DC offset voltage Vc of the differential amplifier circuit.

[0043] That is, by switching the state of the switch circuit 103 , the DC offset voltage Vc of the differential amplifier circuit 101 itself can be effectively eliminated, thereby obtaining an accurate DC offset voltage Vc of the differential amplifier circuit.

[0044] In other embodiments of the present application, Figure 1 The DC detection circuit 10 shown may further include a low-pass filter, an analog-to-digital conversion module, and an operation module.

[0045] Among them, the low-pass filter can be used to filter out high-frequency signals in the differential amplifier circuit, the analog-to-digital conversion module is used to convert analog signals into digital signals, and the operation module is used to calculate the DC offset voltage of the differential amplifier circuit.

[0046] For example, Figure 2 FIG2 shows a circuit diagram of another DC detection circuit 10 . The DC detection circuit 10 is connected to a differential amplifier circuit 101 .

[0047] refer to Figure 2 The DC detection circuit 10 includes a low-pass filter 102, a switch module 103, an amplification processing module 104, an analog-to-digital conversion module 105, and an operation module 106. The differential amplifier circuit 101 is sequentially connected to the low-pass filter 102, the switch module 103, the amplification processing module 104, the analog-to-digital conversion module 105, and the operation module 106.

[0048] The first input terminal of the low-pass filter 102 is connected to the first output terminal VOP of the differential amplifier circuit 101, and the second input terminal of the low-pass filter 102 is connected to the second output terminal VON of the differential amplifier circuit 101. The first output terminal of the low-pass filter 102 is connected to the first terminal of the first switch tube k1 and the first terminal of the second switch tube k2 in the switch module 103, respectively. The second output terminal of the low-pass filter 102 is connected to the first terminal of the third switch tube k3 and the first terminal of the fourth switch tube k4 in the switch module 103, respectively.

[0049] It can be understood that the low-pass filter 102 is an electronic filter that allows low-frequency signals to pass through while attenuating or blocking high-frequency signals. In the embodiment of the present application, the two input terminals of the low-pass filter 102 can be used to receive the output signal of the first output terminal VOP of the differential amplifier circuit 101 and the output signal of the first output terminal VOP of the differential amplifier circuit 101, respectively, and filter out high-frequency signals from the output signals of the two output terminals of the differential amplifier circuit 101.

[0050] It can be understood that, since the DC detection circuit 10 includes the low-pass filter 102 , the switch module 103 can be connected to the differential amplifier circuit 101 through the low-pass filter 102 .

[0051] The switch module may include a first switch transistor k1, a second switch transistor k2, a third switch transistor k3, and a fourth switch transistor k4. The first end of the first switch transistor k1 is connected to the first output end of the low-pass filter 102, and the second end of the first switch transistor k1 is connected to the first input end of the amplification processing module 103. The first end of the second switch transistor k2 is connected to the first output end of the low-pass filter 102, and the second end of the second switch transistor k2 is connected to the second input end of the amplification processing module 103. The first end of the third switch transistor k3 is connected to the second output end of the low-pass filter 102, and the second end of the third switch transistor k3 is connected to the first input end of the amplification processing module 103. The first end of the fourth switch transistor k4 is connected to the second output end of the low-pass filter 102, and the second end of the fourth switch transistor k4 is connected to the second input end of the amplification processing module 101.

[0052] In some embodiments of the present application, when the first switch tube k1 and the fourth switch tube k4 are closed, and the second switch tube k2 and the third switch tube k3 are open, it can be determined that the switch module 103 is in the first state. Alternatively, when the first switch tube k1 and the fourth switch tube k4 are open, and the second switch tube k2 and the third switch tube k3 are closed, it can be determined that the switch module 103 is in the first state.

[0053] In some embodiments of the present application, when the first switch tube k1 and the second switch tube k2 are closed, and the third switch tube k3 and the fourth switch tube k4 are open, it can be determined that the switch module 103 is in the second state. Alternatively, when the first switch tube k1 and the second switch tube k2 are open, and the third switch tube k3 and the fourth switch tube k4 are closed, the switch module 103 is in the second state.

[0054] The first input end of the amplification processing module 104 is respectively used to connect to the first end of the first switching tube k1 and the first end of the third switching tube k3. The second input end of the amplification processing module 104 is respectively used to connect to the first end of the second switching tube k2 and the first end of the fourth switching tube k4. The output end of the amplification processing module 104 is connected to the input end of the analog-to-digital conversion module 105.

[0055] It is understood that when the switch module 103 is in the first state, the output signal of the amplification processing module 104 may be a first signal S1. When the switch module 103 is in the second state, the output signal of the amplification processing module 104 may be a second signal S2. The first and second signals are analog signals. The first signal S1 may include the DC offset voltage of the differential amplifier circuit 101 and the DC offset voltage of the amplification processing module 104. The second signal S2 may include the DC offset voltage of the amplification processing module 104.

[0056] The input end of the analog-to-digital conversion module 105 is connected to the output end of the amplification processing module 104. When the switch module 103 is in the first state, the analog-to-digital conversion module 105 is configured to convert the first signal S1 and the DC offset voltage of the analog-to-digital conversion module 105 into a first digital signal. When the switch module 103 is in the second state, the analog-to-digital conversion module 105 is configured to convert the second signal S2 and the DC offset voltage of the analog-to-digital conversion module 105 into a second digital signal.

[0057] Operation module 106. Operation module 106 is connected to the output terminal of analog-to-digital conversion module 105. Operation module 106 can be used to perform a subtraction operation on the first digital signal and the second digital signal output by analog-to-digital conversion module 105 to obtain a DC offset voltage of differential amplifier circuit 101.

[0058] In some embodiments of the present application, the output signal of the amplification processing module 104 may be different when the corresponding switch module 103 is in different states.

[0059] For example, when the switch module 103 is in the first state, the first switch tube k1 and the fourth switch tube k4 are closed, and the second switch tube k2 and the third switch tube k3 are opened. Based on this, the first switch tube k1 and the fourth switch tube k4 can conduct electricity between the first output terminal of the differential amplifier circuit 101 and the first input terminal of the amplification processing module 104, and conduct electricity between the second output terminal of the differential amplifier circuit 101 and the second input terminal of the amplification processing module 104, so that the amplification processing module 104 outputs a first signal S1. It can be understood that the first signal S1 is an analog signal, and the first signal S1 includes the DC offset voltage corresponding to the differential amplifier circuit 101 and the DC offset voltage corresponding to the amplification processing module 104.

[0060] For another example, when the switch module 103 is in the second state, the first switch transistor k1 and the second switch transistor k2 are closed, and the third switch transistor k3 and the fourth switch transistor k4 are open. Therefore, the first switch transistor k1 and the second switch transistor k2 can short-circuit the first input terminal and the second input terminal of the amplification processing module 104, so that the amplification processing module 104 can output the second signal S2. It can be understood that the second signal S2 is an analog signal and includes the DC offset voltage corresponding to the amplification processing module 104, but does not include the DC offset voltage corresponding to the differential amplifier circuit 101.

[0061] In some embodiments of the present application, since the first signal S1 and the second signal S2 output by the amplification processing module 104 are analog signals, the first signal S1 and the second signal S2 need to be converted into a first digital signal and a second digital signal respectively by the analog-to-digital conversion module 105. Due to the offset (Offset) of the analog-to-digital conversion module 102 itself, the analog-to-digital conversion module 105 will generate a corresponding DC offset voltage. In order to more accurately measure the DC offset voltage of the differential amplifier circuit 101, the analog-to-digital conversion module 105 needs to convert the first signal S1 and the DC offset voltage of the analog-to-digital conversion module 105 together when performing analog-to-digital conversion to obtain a first digital signal. Similarly, the second signal S2 needs to be converted together with the DC offset voltage of the analog-to-digital conversion module 105 to obtain a second digital signal. In this way, the operation module 106 can calculate the accurate DC offset voltage of the differential amplifier circuit 101 based on the first digital signal and the second digital signal, specifically:

[0062] When the switch module 103 is in the first state, the switch module 103 can conduct the first output terminal (second output terminal) of the differential amplifier circuit 101 and the first input terminal (second input terminal) of the amplification processing module 104. Based on the switch module 103 being in the first state, the operation module 106 can calculate the DC offset voltage DC_OUT1 detected by the DC detection circuit 10 in this case based on the first signal S1 output by the amplification processing module 104 and the DC offset voltage Vos2 of the analog-to-digital conversion module 105 using formula (1). DC_OUT1 includes the DC offset voltage of the differential amplifier circuit 101, as well as the DC offset voltages of the amplification processing module 104 and the analog-to-digital conversion module 105.

[0063] DC_OUT1=[(Vc+Vos1)*G+Vos2] / VFS (1)

[0064] In formula (1), DC_OUT1 may represent the DC offset voltage detected by the DC detection circuit 10 when the switch module 103 is in the first state; Vc may represent the DC offset voltage of the differential amplifier circuit 101; Vos1 may represent the DC offset voltage of the amplification processing module 104; Vos2 may represent the DC offset voltage of the analog-to-digital conversion module 105. G may represent the amplification factor of the amplification processing module 104, and VFS may represent the full-scale voltage of the analog-to-digital conversion module 105.

[0065] The DC offset voltage Vos1 generated by the amplification processing module 104 is superimposed on the DC offset voltage Vc of the differential amplifier circuit 101. Therefore, the first signal S1 output by the amplification processing module 104 includes a DC offset voltage "(Vc+Vos1)*G". Since the analog-to-digital conversion module 105 has a DC offset voltage (Vos2), the analog-to-digital conversion module 105 needs to consider Vos2 when performing the analog-to-digital conversion on the first signal. That is, the analog-to-digital conversion module 105 needs to convert the first signal and Vos2 into a first digital signal. Therefore, the DC offset voltage DC_OUT1 determined by the operation module 106 based on the first digital signal is [(Vc+Vos1)*G+Vos2]. In order to normalize the output value of the analog-to-digital conversion module 105 to its full-scale range (VFS), it needs to be divided by VFS. Therefore, when the switch module 103 is in the first state, the DC offset voltage DC_OUT1 detected by the DC detection circuit 10 is [(Vc+Vos1)*G+Vos2] / VFS.

[0066] When the switch module 103 is in the second state, the switch module 103 can short-circuit the first input terminal and the second input terminal of the amplification processing module 104. Based on the switch module 103 being in the second state, the operation module 106 can calculate the DC offset voltage DC_OUT2 detected by the DC detection circuit 10 in this case based on the second signal S2 output by the amplification processing module 104 and the DC offset voltage Vos2 of the analog-to-digital conversion module 105 using formula (2). DC_OUT2 includes the DC offset voltage of the amplification processing module 104 and the DC offset voltage of the analog-to-digital conversion module 105, but does not include the DC offset voltage of the differential amplifier circuit 101.

[0067] DC_OUT2=[Vos1*G+Vos2] / VFS (2)

[0068] In formula (2), DC_OUT2 may represent the DC offset voltage detected by the DC detection circuit 10 when the switch module 103 is in the second state; Vos1 may represent the DC offset voltage of the amplification processing module 101; Vos2 may represent the DC offset voltage of the analog-to-digital conversion module 105. G may represent the amplification factor of the amplification processing module 104, and VFS may represent the full-scale voltage of the analog-to-digital conversion module 105.

[0069] When the first and second input terminals of amplification processing module 104 are short-circuited, the output signal of differential amplifier circuit 101 does not reach amplification processing module 104. Therefore, second signal S2 output by amplification processing module 101 includes the DC offset voltage "Vos1*G" of amplification processing module 104. Because the analog-to-digital conversion module 105 has a DC offset voltage (Vos2), the analog-to-digital conversion module 105 needs to convert the second signal S2 and Vos2 into a second digital signal. Therefore, the DC offset voltage calculated by operation module 106 based on the second digital signal is [(Vos1)*G+Vos2]. To normalize the output value of analog-to-digital conversion module 105 to its full-scale range (VFS), it needs to be divided by VFS. Therefore, when switch module 103 is in the second state, DC_OUT2 is [(Vos1)*G+Vos2] / VFS.

[0070] It can be understood that, based on the above formula (1), when the switch module 103 is in the first state, the DC offset voltage DC_OUT1 detected by the DC detection circuit 10 includes the DC offset voltage of the differential amplifier circuit 101, the DC offset voltages of the amplification processing module 104, and the DC offset voltages of the analog-to-digital conversion module 105. Based on the above formula (2), when the switch module 103 is in the second state, the DC offset voltage DC_OUT2 detected by the DC detection circuit 10 includes the DC offset voltage of the amplification processing module 104 and the DC offset voltage of the analog-to-digital conversion module 105. Therefore, the operation module 106 can perform a subtraction operation based on DC_OUT1 and DC_OUT2 based on formula (3) to obtain the difference ΔDC_OUT between DC_OUT1 and DC_OUT2, and further calculate the DC offset voltage Vc of the differential amplifier circuit 101 based on the difference ΔDC_OUT.

[0071] ΔDC_OUT=DC_OUT1-DC_OUT2=(Vc*G) / VFS (3)

[0072] In formula (3), ΔDC_OUT represents the difference between DC_OUT1 and DC_OUT2. Since the difference between DC_OUT1 and DC_OUT2 lies in that DC_OUT1 includes the DC offset voltage of the differential amplifier circuit 101, while DC_OUT2 does not, DC_OUT1 is subtracted from DC_OUT2 to obtain the difference ΔDC_OUT = (Vc*G) / VFS. This difference is then multiplied by VFS and divided by G to obtain the accurate DC offset voltage Vc of the differential amplifier circuit 101, thereby effectively eliminating the DC offset voltage Vc of the differential amplifier circuit.

[0073] based on Figure 2In the DC detection circuit 10 shown, when the switch module 103 is in the first state, the amplification processing module 104 can output a first signal S1 = G × (Vc + Vos1). Based on the first signal S1 and Vos2, the analog-to-digital conversion module 105 can convert the first signal S1 into a first digital signal DC_OUT1 = [(Vc + Vos1) * G + Vos2] / VFS. When the switch module 103 is in the second state, the amplification processing module 104 can output a second signal S2 = (G × Vos1) + Vos2. Based on the second signal S2 and Vos2, the analog-to-digital conversion module 105 can convert the second signal S2 into a second digital signal [(Vos1 * G) + Vos2] / VFS. G is the amplification factor of the amplification processing module 104. It can be understood that the difference between the first digital signal S1 and the second digital signal S2 is (Vc * G) / VFS. Multiplying this difference by VFS and dividing it by G yields the DC offset voltage Vc of the differential amplifier circuit.

[0074] That is, by switching the state of the switch circuit 103 , the DC offset voltage Vc of the differential amplifier circuit 101 itself can be effectively eliminated, thereby obtaining an accurate DC offset voltage Vc of the differential amplifier circuit.

[0075] In some embodiments of the present application, when measuring the DC offset voltage of the differential amplifier circuit 101, the DC offset voltage of the differential amplifier circuit 101 is relatively weak and needs to be amplified by the amplification processing module 104 and then sent to the analog-to-digital conversion module 105 for quantization. Taking into account that the two output terminals of the differential amplifier circuit 101 are respectively at the two ends of the output load, in order to avoid the influence of the load effect, a pre-buffer (Buffer) can be set in the amplification processing module 104 to avoid the influence of the load effect. It can be understood that the input impedance of the pre-buffer is high and the output impedance is low, which can isolate the input signal from the subsequent circuit and prevent the load effect from being fed back to the signal source. The pre-buffer (Buffer) is usually composed of an operational amplifier. Specifically:

[0076] For example, Figure 3 A structural schematic diagram of an amplifying and processing module 104 is shown. The amplifying and processing module 104 is connected to the switch module 103 and the analog-to-digital conversion module 104 respectively.

[0077] In some embodiments of the present application, reference is made to Figure 3The amplification processing module 104 may include a first amplifier A1, a first resistor R1, a second amplifier A2, a second resistor R2, a third amplifier A3, a third resistor R3 and a fourth resistor R4, wherein the first resistor R1 and the second resistor R2 are equal, and the third resistor R3 and the fourth resistor R4 are equal; the positive phase input terminal of the first amplifier A1 is connected to the first input terminal of the amplification processing module 104, the negative phase input terminal of the first amplifier A1 is connected to the output terminal of the first amplifier A1 and the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the fourth resistor R4 and the positive phase input terminal of the third amplifier A3, the second end of the fourth resistor R4 is connected to the reference voltage terminal VREF, the output terminal of the first amplifier A1 is connected to the first The negative phase input terminal of the amplifier A1 is connected to the first end of the first resistor R1; the positive phase input terminal of the second amplifier A2 is connected to the second input terminal of the amplification processing module 104, the negative phase input terminal of the second amplifier A2 is connected to the output terminal of the second amplifier A2 and the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the third resistor R3 and the negative phase input terminal of the third amplifier A3; the positive phase input terminal of the third amplifier A3 is connected to the second end of the first resistor R1 and the first end of the fourth resistor R4, the negative phase input terminal of the third amplifier A3 is connected to the second end of the second resistor R2 and the first end of the third resistor R3, and the output terminal of the third amplifier A3 is connected to the second end of the third resistor R3 and the input terminal of the analog-to-digital conversion module 105.

[0078] It can be understood that the first amplifier A1 and the second amplifier A2 are a type of pre-buffer. They are used to isolate and buffer the output signals of the two output terminals of the differential amplifier circuit 101, ensuring that the output signals of the two output terminals of the differential amplifier circuit 101 are not affected by load effects during transmission. The third amplifier A3 is a differential amplifier that compares and amplifies the output signals of the first amplifier A1 and the second amplifier A2, with an amplification factor G = R2 / R1. Finally, the output of the third amplifier A3 is sent to the analog-to-digital conversion module 103 for analog-to-digital conversion.

[0079] For example, Figure 4 1 shows a structural diagram of another amplification processing module 104 , in which the amplification processing module 104 is connected to the switch module 103 and the analog-to-digital conversion module 104 respectively.

[0080] In some embodiments of the present application, reference is made to Figure 4The amplification processing module includes a first amplifier A1, a first resistor R1, a second amplifier A2, a second resistor R2, a third amplifier A3, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, wherein the first resistor R1 and the second resistor R2 are equal, the third resistor R3 and the fourth resistor R4 are equal, and the fifth resistor R5 and the seventh resistor R7 are equal; a positive input terminal of the first amplifier A1 is connected to a first input terminal of the amplification processing module 104, a negative input terminal of the first amplifier A1 is connected to a second end of the fifth resistor R5 and a first end of the sixth resistor R6, a second end of the fifth resistor R5 is connected to an output terminal of the first amplifier A1 and a first end of the first resistor R1, a second end of the sixth resistor R6 is connected to a negative input terminal of the second amplifier A2 and a first end of the seventh resistor R7, and an output terminal of the first amplifier A1 is connected to the fifth resistor R55 and the first end of the sixth resistor R6; the positive phase input terminal of the second amplifier A2 is connected to the second input terminal of the amplification processing module 104, the negative phase input terminal of the second amplifier A2 is connected to the second end of the fifth resistor R5, the first end of the sixth resistor R6 and the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected to the output terminal of the second amplifier A2, and the output terminal of the second amplifier A2 is connected to the second end of the seventh resistor R7 and the first end of the second resistor R2; the positive phase input terminal of the third amplifier A3 is connected to the second end of the first resistor R1 and the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the reference voltage terminal VREF, the negative phase input terminal of the third amplifier A3 is connected to the second end of the second resistor R2 and the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the output terminal of the third amplifier A3 and the input terminal of the analog-to-digital conversion module 105.

[0081] The present application provides a chip, which may include the DC detection circuit 10 in the above embodiment.

[0082] The present application provides an electronic device, which may include the above-mentioned chip.

[0083] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to floppy disks, optical disks, optical discs, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Therefore, a machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0084] In the accompanying drawings, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order may not be required. In some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not imply that such features are required in all embodiments, and these features may not be included or may be combined with other features.

[0085] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems raised by this application. In addition, in order to highlight the innovative part of this application, the above-mentioned device embodiments of this application do not introduce units / modules that are not closely related to solving the technical problems raised by this application. This does not mean that other units / modules do not exist in the above-mentioned device embodiments.

[0086] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a" do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0087] Although the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims

1. A DC detection circuit, characterized in that: Used to detect a DC signal in a differential amplifier circuit; the DC detection circuit comprises: A switch module, configured to be connected to the differential amplifier circuit; an amplification processing module connected to the switch module; The switch module is capable of switching between a first state and a second state. When the switch module is in the first state, the switch module is capable of conducting between the first output terminal of the differential amplifier circuit and the first input terminal of the amplification processing module, and conducting between the second output terminal of the differential amplifier circuit and the second input terminal of the amplification processing module, so that the amplification processing module outputs a first signal. When the switch module is in the second state, the switch module can short-circuit the first input terminal and the second input terminal of the amplifying and processing module, so that the amplifying and processing module outputs a second signal.

2. The DC detection circuit according to claim 1, characterized in that: The switch module includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube; The first end of the first switch tube is used to be connected to the first output end of the differential amplifier circuit, and the second end of the first switch tube is connected to the first input end of the amplification processing module; The first end of the second switch tube is used to be connected to the first output end of the differential amplifier circuit, and the second end of the second switch tube is connected to the second input end of the amplification processing module; The first end of the third switch tube is used to be connected to the second output end of the differential amplifier circuit, and the second end of the third switch tube is connected to the first input end of the amplification processing module; The first end of the fourth switch tube is used to be connected to the second output end of the differential amplifier circuit, and the second end of the fourth switch tube is connected to the second input end of the amplification processing module.

3. The DC detection circuit according to claim 2, characterized in that: When the first switch tube and the fourth switch tube are closed, and the second switch tube and the third switch tube are open, the switch module is in the first state; or, When the first switch tube and the fourth switch tube are disconnected, and the second switch tube and the third switch tube are closed, the switch module is in the first state.

4. The DC detection circuit according to claim 2, characterized in that: When the first switch tube and the second switch tube are closed, and the third switch tube and the fourth switch tube are open, the switch module is in the second state; or, When the first switch tube and the second switch tube are disconnected, and the third switch tube and the fourth switch tube are closed, the switch module is in the second state.

5. The DC detection circuit according to claim 1 or 2, characterized in that: The DC detection circuit includes a low-pass filter, and the switch module is connected to the differential amplifier circuit through the low-pass filter.

6. The DC detection circuit according to claim 5, characterized in that: The first input end of the low-pass filter is used to be connected to the first output end of the differential amplifier circuit, and the second input end of the low-pass filter is used to be connected to the second output end of the differential amplifier circuit; The first output end of the low-pass filter is used to be connected to the first end of the first switching tube and the first end of the second switching tube in the switching module respectively, and the second output end of the low-pass filter is used to be connected to the first end of the third switching tube and the first end of the fourth switching tube in the switching module respectively.

7. The DC detection circuit according to claim 1, characterized in that: The first signal and the second signal are analog signals; The DC detection circuit further includes an analog-to-digital conversion module, wherein an input end of the analog-to-digital conversion module is connected to an output end of the amplification processing module; When the switch module is in the first state, the analog-to-digital conversion module converts the first signal and the DC offset voltage of the analog-to-digital conversion module into a first digital signal; When the switch module is in the second state, the analog-to-digital conversion module converts the second signal and the DC offset voltage of the analog-to-digital conversion module into a second digital signal.

8. The DC detection circuit according to claim 7, characterized in that: The DC detection circuit further includes a calculation module, which is connected to the output end of the analog-to-digital conversion module; The operation module is used to perform a subtraction operation on the first digital signal and the second digital signal to obtain a DC offset voltage of the differential amplifier circuit.

9. The DC detection circuit according to claim 1, characterized in that: The amplification processing module includes a first amplifier, a first resistor, a second amplifier, a second resistor, a third amplifier, a third resistor and a fourth resistor, wherein the first resistor is equal to the second resistor, and the third resistor is equal to the fourth resistor; The positive phase input terminal of the first amplifier is connected to the first input terminal of the amplification processing module, the negative phase input terminal of the first amplifier is connected to the output terminal of the first amplifier and the first end of the first resistor, the second end of the first resistor is connected to the first end of the fourth resistor and the positive phase input terminal of the third amplifier, the second end of the fourth resistor is connected to the reference voltage terminal, and the output terminal of the first amplifier is connected to the negative phase input terminal of the first amplifier and the first end of the first resistor; The positive phase input terminal of the second amplifier is connected to the second input terminal of the amplification processing module, the negative phase input terminal of the second amplifier is connected to the output terminal of the second amplifier and the first terminal of the second resistor, and the second terminal of the second resistor is connected to the first terminal of the third resistor and the negative phase input terminal of the third amplifier; The positive phase input terminal of the third amplifier is connected to the second end of the first resistor and the first end of the four resistors, the negative phase input terminal of the third amplifier is connected to the second end of the second resistor and the first end of the third resistor, and the output terminal of the third amplifier is connected to the second end of the third resistor and the input terminal of the analog-to-digital conversion module.

10. The DC detection circuit according to claim 1, characterized in that: The amplification processing module includes a first amplifier, a first resistor, a second amplifier, a second resistor, a third amplifier, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor, wherein the first resistor is equal to the second resistor, the third resistor is equal to the fourth resistor, and the fifth resistor is equal to the seventh resistor; The positive phase input terminal of the first amplifier is connected to the first input terminal of the amplification processing module, the negative phase input terminal of the first amplifier is connected to the second end of the fifth resistor and the first end of the sixth resistor, the second end of the fifth resistor is connected to the output terminal of the first amplifier and the first end of the first resistor, the second end of the sixth resistor is connected to the negative phase input terminal of the second amplifier and the first end of the seventh resistor, and the output terminal of the first amplifier is connected to the second end of the fifth resistor and the first end of the sixth resistor; a positive-phase input terminal of the second amplifier connected to the second input terminal of the amplification processing module, a negative-phase input terminal of the second amplifier connected to the second end of the fifth resistor, the first end of the sixth resistor, and the first end of the seventh resistor, a second end of the seventh resistor connected to the output terminal of the second amplifier, and an output terminal of the second amplifier connected to the second end of the seventh resistor and the first end of the second resistor; The positive phase input terminal of the third amplifier is connected to the second end of the first resistor and the first end of the fourth resistor, the second end of the fourth resistor is connected to the reference voltage terminal, the negative phase input terminal of the third amplifier is connected to the second end of the second resistor and the first end of the third resistor, and the second end of the third resistor is connected to the output terminal of the third amplifier and the input terminal of the analog-to-digital conversion module.

11. A chip, characterized in that: The chip includes the DC detection circuit according to any one of claims 1 to 10.

12. An electronic device, characterized in that: The electronic device comprises the chip according to claim 11.

Images