Memory management method and related equipment

Abstract

The invention provides a memory management method and related equipment, and relates to the technical field of cloud computers. The method is applied to an aggregation host, and the aggregation host comprises a plurality of computing nodes; the method comprises the following steps: in response to starting an aggregation host, reserving a local memory for each computing node; after the aggregation host is started, creating a kernel thread for each computing node; and in response to starting the load in the aggregation host, copying a memory page table corresponding to the load from a computing fast link (CXL) memory to a local memory reserved by each computing node through a kernel thread of each computing node. According to the method and the device, the local memory is reserved for the computing node, the memory page table is copied to the local, the dependence on a CXL memory is reduced, and the reserved local memory is closer to the computing node, so that the access speed is higher, the memory access speed and efficiency can be improved, and the problem that the performance is limited when a super aggregation host runs a service with a high requirement on the memory is solved.

Description

Technical Field

[0001] The present disclosure relates to the field of cloud computing technology, and in particular to a memory management method and related devices. Background Art

[0002] Super-converged hosts integrate the resources of multiple compute nodes. The physical CPUs of their client operating systems come from different nodes, that is, from different hardware units. Compute Express Link (CXL) memory enables shared access by all compute nodes through high-speed interconnect technology. In this way, in a super-converged host environment, CXL memory helps CPUs from different hardware units efficiently access shared resources, optimizing overall performance.

[0003] In the hyper-aggregated architecture based on CXL shared memory, considering that the CPUs of different hosts need to have a consistent view of the operating system memory, the operating system memory and business memory resources of the aggregated hosts are all allocated to the CXL memory pool, forming a large virtual machine that flexibly aggregates separate resources.

[0004] However, since CXL memory is connected to the CPU via a high-speed interconnect protocol, data needs to go through more physical links and protocol conversions during transmission, and CXL memory needs to be processed by additional memory controllers and cache layers. Therefore, super aggregation based on CXL shared memory has limited performance when running some memory access performance-sensitive businesses, and it is difficult to meet the needs of business scenarios with extremely high requirements for memory access speed and efficiency.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0006] The present disclosure provides a memory management method and related devices, which can improve the memory access performance of a load.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0008] According to one aspect of the present disclosure, a memory management method is provided for an aggregation host, the aggregation host including multiple compute nodes. The method comprises: in response to starting the aggregation host, reserving local memory for each compute node; when the aggregation host is started, creating a kernel thread for each compute node; and in response to starting a load in the aggregation host, copying the memory page table corresponding to the load from a compute fast link (CXL) memory to the local memory reserved for each compute node via the kernel thread of each compute node.

[0009] In some embodiments, a fast emulation program Qemu process is deployed on each computing node, and reserving local memory for each computing node includes: reserving local memory for each computing node using the Qemu process deployed on each computing node.

[0010] In some embodiments, the method of reserving local memory for each computing node using the Qemu process deployed on each computing node includes: constructing a memory mapping function for each computing node using the Qemu process deployed on each computing node; reserving memory for each computing node according to the memory mapping function on each computing node; and allocating the reserved memory to the local memory of each computing node.

[0011] In some embodiments, after creating a kernel thread for each computing node, the method further includes: binding the kernel thread of each computing node to a central processing unit of each computing node.

[0012] In some embodiments, copying the memory page table corresponding to the load from the CXL memory to the local memory reserved for each compute node through the kernel thread of each compute node includes: identifying the memory page table information corresponding to the load in the CXL memory through the kernel thread of each compute node; establishing a mapping relationship with the local memory based on the memory page table information corresponding to the load in the CXL memory; and reading the memory page table information corresponding to the load from the CXL memory according to the page table data block into the local memory reserved for each compute node based on the mapping relationship.

[0013] In some embodiments, the memory page table corresponding to the load includes M-level page tables, where M is a positive integer. Copying the memory page table corresponding to the load from the CXL memory to the local memory reserved for each computing node through the kernel thread of each computing node includes: copying the first N-level page tables corresponding to the load from the CXL memory to the local memory reserved for each computing node through the kernel thread of each computing node, where N is a positive integer and N is less than M; the method also includes: each computing node sharing the page tables in the M-level page tables except the first N-level page tables with the CXL memory.

[0014] In some embodiments, the multiple computing nodes include a first computing node and a second computing node, and the method further includes: performing a memory management operation in response to a load running on the first computing node, updating page table information in the CXL memory, and updating page table information in the local memory of the first computing node based on the updated page table information in the CXL memory; when the load running on the first computing node is transferred to the second computing node, in response to a page fault being triggered by the load running on the second computing node, synchronizing data between the local memory of the second computing node and the CXL memory.

[0015] In some embodiments, the memory management operation includes at least one of the following: memory access, memory permission change, and memory release.

[0016] According to another aspect of the present disclosure, a memory management device is also provided, which is applied to an aggregation host, wherein the aggregation host includes multiple computing nodes; the device includes: a reservation module, which is used to reserve local memory for each computing node in response to starting the aggregation host; a creation module, which is used to create a kernel thread for each computing node after the aggregation host is started; and a copy module, which is used to copy the memory page table corresponding to the load from the computing fast link CXL memory to the local memory reserved for each computing node through the kernel thread of each computing node in response to starting the load in the aggregation host.

[0017] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute any one of the above-mentioned memory management methods by executing the executable instructions.

[0018] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the memory management method described above is implemented.

[0019] According to another aspect of the present disclosure, a computer program product is provided, including: a computer program or instructions, wherein when the computer program or instructions are executed by a processor, any one of the above memory management methods is implemented.

[0020] Embodiments of the present disclosure provide a memory management method and related devices for use with a clustered host comprising multiple compute nodes. The method comprises: in response to starting the clustered host, reserving local memory for each compute node; after the clustered host is started, creating a kernel thread for each compute node; and in response to starting a load in the clustered host, copying the memory page table corresponding to the load from the compute express link (CXL) memory to the local memory reserved for each compute node via the kernel thread of each compute node. The present disclosure reserves local memory for the compute nodes and copies the memory page table locally, reducing reliance on CXL memory. Since the reserved local memory is closer to the compute nodes, it is accessed faster, improving memory access speed and efficiency, and resolving the performance limitations of super-converged hosts when running memory-intensive services.

[0021] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0023] Figure 1 A schematic diagram of a memory management system architecture according to an embodiment of the present disclosure is shown;

[0024] Figure 2 A flow chart of a memory management method according to an embodiment of the present disclosure is shown;

[0025] Figure 3 A flow chart of a method for reserving local memory for each computing node according to an embodiment of the present disclosure is shown;

[0026] Figure 4 A flow chart of a method for copying a page table according to an embodiment of the present disclosure is shown;

[0027] Figure 5 A schematic diagram showing an embodiment of the present disclosure in which an aggregation host utilizes local memory to cache page tables is shown;

[0028] Figure 6 A flow chart of another memory management method according to an embodiment of the present disclosure is shown;

[0029] Figure 7 A specific method flow chart of a memory management method according to an embodiment of the present disclosure is shown;

[0030] Figure 8 A schematic diagram of a memory management device according to an embodiment of the present disclosure is shown;

[0031] Figure 9 A structural block diagram of an electronic device in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0033] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0034] For ease of understanding, before introducing the embodiments of the present disclosure, several terms involved in the embodiments of the present disclosure are first explained as follows:

[0035] The central processing unit (CPU) is primarily composed of an arithmetic unit (APU), a controller, and a register bank. The APU performs arithmetic and logical operations, such as addition, subtraction, multiplication, division, and comparisons. The controller orchestrates the various computer components, fetching, analyzing, and executing instructions in sequence. The register bank temporarily stores instructions, data, addresses, and other information. CPU performance impacts the overall speed of the computer. Performance indicators include the main frequency (which determines computing speed), the number of cores (multiple cores can process tasks in parallel for improved efficiency), and the cache (which speeds up data access).

[0036] Dynamic Random Access Memory (DRAM): A type of semiconductor memory. It's a type of random access memory, capable of random read and write operations to memory cells at high speeds. Its "dynamic" nature stems from the fact that its memory cells require constant refreshing to retain data. DRAM is relatively low-cost and highly integrated, making it a common component used in computers' main memory. It's a crucial component for temporarily storing data while computers run programs and process data. However, stored data is lost if power is lost.

[0037] Compute Express Link (CXL): Compute Express Link (CXL) is a high-speed, low-latency, open interconnect technology standard. It is primarily used in servers and data centers to enable efficient communication and resource sharing between processors, accelerators, and memory. By providing a high-bandwidth, low-latency data transmission channel, CXL significantly improves the collaborative work efficiency of various components within the data center.

[0038] Hybrid Memory Management: By establishing a hierarchical architecture between storage media of different speeds and capacities, more efficient and flexible memory resource management is achieved. Hybrid memory management can represent a mix of local DRAM and persistent memory, a mix of local DRAM and CXL memory pools, or a mix of different non-uniform memory access and dynamic random access memories within the same physical machine. Among them, non-uniform memory access (NUMA) is a computer memory design architecture. In this architecture, processors and memory are organized into multiple nodes, each node has its own local memory, and nodes communicate through the internet.

[0039] Distributed Shared Memory Pool: A physically distant dedicated memory pool built through CXL and shared by multiple physical machines. Each physical compute node can access the memory pool data through CXL technology.

[0040] Hyper Aggregated Host: It is a fusion computing architecture based on virtualization and distributed technology. It builds a unified logical resource pool by integrating the hardware capabilities of multiple physical computing nodes (such as servers, storage devices, network resources, etc.). Its core is to abstract the scattered CPU, GPU, memory, storage and other resources into elastically allocated computing units through the virtualization layer (such as KVM, container engine) and intelligent scheduling system, and support the hybrid deployment of virtual machines, containers and loads. The system relies on dynamic load balancing, cross-node redundancy, heterogeneous hardware pooling and other capabilities to achieve on-demand resource expansion, fault self-healing and high-efficiency scheduling. It is suitable for cloud-native applications, AI training, edge computing and other scenarios. It aims to break through the performance bottleneck of a single node and maximize global resource utilization and business agility.

[0041] Super Large Memory Host: A virtual machine with super-large memory resources that exceeds the memory capacity of a physical machine by leveraging CXL memory resources. Its CPU resources are allocated to a single physical host, and its memory resources include both local memory and remote CXL memory resources.

[0042] Page table: A data structure used to manage memory mapping in a virtual memory system. It maintains the translation from virtual addresses to physical addresses. Each application has its own independent page table, which is maintained by the operating system and is typically implemented using a radix tree data structure with four or five levels.

[0043] Translation Lookaside Buffer (TLB): It is a component of the Memory Management Unit (MMU). In a computer, programs use virtual addresses, but physical addresses are required to actually access memory, which requires converting virtual addresses into physical addresses. The page table stores the mapping relationship between virtual addresses and physical addresses, but accessing the page table to query the mapping relationship is time-consuming. The role of the TLB is to cache these mapping relationships. When the MMU wants to convert a virtual address, it first checks whether there is a corresponding mapping in the TLB. If so, it uses it directly without accessing the page table. This greatly speeds up address conversion, avoids the performance loss caused by repeated page table queries, and improves the operating efficiency of the entire system.

[0044] Memory Management Unit (MMU): It is a hardware device in the computer that is specifically responsible for processing the CPU's memory access requests. Its main function is to perform address translation, that is, to convert the virtual address issued by the CPU into the actual address of the physical memory. When the MMU receives a memory access request, it will first quickly query the mapping relationship through the TLB. If the query fails, a cache miss occurs, that is, a TLB miss, and the MMU needs to traverse the page table in the memory to find the correct address mapping. After finding it, the MMU will update the TLB so that the address translation can be completed faster next time. In short, the MMU relies on the TLB to speed up address translation, and when a TLB miss occurs, it searches and updates the TLB through the page table.

[0045] Memory Paging Technology: Currently, memory paging technology (paging) essentially uses a coordinated set of software and hardware logic to translate process virtual addresses into actual physical memory addresses. Taking the X86-64 platform as an example, the memory paging mechanism divides the virtual address space and physical memory into fixed-size blocks, called pages and page frames, and uses a page table to manage the mapping between them. Each process has an independent virtual address space, divided into pages of equal size (for example, 4KB), while physical memory is also divided into page frames of equal size. The page table records the physical page frame address corresponding to each virtual page. When a process accesses a virtual address, the CPU checks the TLB in the MMU to see if there is a cache linking the virtual address to the physical address, thereby translating the virtual address into a physical address. If the TLB lookup fails, the MMU performs a page table walk by accessing memory and caches the mapping in the TLB. The page table walk breaks the virtual address into a page number and an offset within the page. The page number is used to locate the corresponding entry in the page table, while the offset within the page is used to calculate the specific physical address. If the accessed virtual address is not yet mapped to physical memory, a page fault interrupt will be triggered. The operating system must handle this interrupt by allocating a new page frame and updating the page table to ensure that the virtual address is correctly mapped to the physical address. A multi-level page table structure is often used to reduce page table size and management overhead, mapping virtual addresses to physical addresses in a hierarchical manner. Furthermore, the paging mechanism supports memory protection. Each page table entry contains permission bits, ensuring that a process can only access its own memory and preventing unauthorized access. The paging mechanism also supports memory sharing. The page tables of different processes can point to the same physical page frame, enabling shared memory areas such as shared libraries or memory-mapped files. In summary, the memory paging mechanism achieves efficient memory management through technologies such as page and page frame mapping, page fault interrupt handling, multi-level page tables, memory protection and sharing, and virtual memory. This supports inter-process isolation and resource sharing, ensuring stable and efficient system operation.

[0046] The specific implementation of the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0047] Figure 1 FIG. 1 shows a schematic diagram of a memory management system architecture according to an embodiment of the present disclosure. Figure 1 As shown, the system architecture 10 may include: a memory 103 and multiple processors 101 . The memory 103 and the processors 101 are connected, for example, via a bus 102 .

[0048] The memory 103 stores one or more application programs, which are suitable for being executed by the multiple processors 101 to implement the memory management method described in the method embodiment. This disclosure uses two examples as an example. In actual application, this disclosure does not limit the number of processors.

[0049] Processor 101 may be a CPU, a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the present disclosure. Processor 101 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0050] Bus 102 may include a path for transmitting information between the aforementioned components. Bus 102 may be a PCI bus or an EISA bus, for example. Bus 102 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, the figure shows only one thick line, but this does not indicate that there is only one bus or only one type of bus.

[0051] The memory 103 may be a ROM or other type of static storage device that can store static information and instructions, a RAM or other type of dynamic storage device that can store information and instructions, or an EEPROM, a CD-ROM or other optical disk storage, an optical disc storage (including a compact disc, a laser disc, an optical disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

[0052] Figure 2 A flow chart of a memory management method according to an embodiment of the present disclosure is shown, which is applied to an aggregation host including multiple computing nodes. Figure 2 As shown, the memory management method provided in the embodiment of the present disclosure includes the following steps:

[0053] S202 : In response to starting the aggregation host, reserve local memory for each computing node.

[0054] In this embodiment, an aggregation host is a host that integrates the resources of multiple compute nodes. A compute node is a single computing unit in a distributed system or cluster that performs data processing tasks. Reserved local memory means pre-allocating and reserving a portion of memory space on each compute node, unavailable for other uses, to ensure sufficient memory resources are available for specific tasks or applications.

[0055] Specifically, during the aggregation host startup process, a portion of memory is reserved for each compute node for custom page table management using the Linux kernel startup parameter memmap. memmap is a parameter used during Linux kernel startup to specify specific memory mapping areas. In short, memmap explicitly indicates to the kernel which memory areas are reserved for local memory, preventing the kernel from using these areas.

[0056] For example, assume the aggregation host includes compute nodes 1 and 2. For compute node 1, 1GB of memory is reserved starting at the 4GB address. That is, during system initialization, the 4GB to 5GB portion of memory is allocated exclusively to compute node 1 for subsequent specific operations, such as custom page table management. For compute node 2, 1GB of memory is reserved starting at the 8GB address. This also establishes a dedicated memory area for this node at system startup, facilitating operations such as custom page table management.

[0057] In some embodiments, a fast emulation program Qemu process is deployed on each computing node, and local memory is reserved for each computing node, including: using the Qemu process deployed on each computing node to reserve local memory for each computing node.

[0058] Qemu process: Qemu is an open-source simulator and virtualization technology that can simulate a variety of hardware devices. In this embodiment, the Qemu process runs on each compute node as a process to simulate or virtualize a specific computing environment. Local memory reservation: This pre-allocates a portion of memory resources on each compute node to ensure sufficient memory availability when running the Qemu process or other applications, thereby improving system performance and stability.

[0059] Specifically, each computing node is used to start the Qemu process of the aggregation host and perform local memory allocation binding on the configured reserved memory interval through the mbind system startup, and physical memory allocation is performed in advance. mbind is a system call in the Linux system, which is used to bind the memory area in the virtual address space of the process to a specific physical memory node or memory page. Here, the reserved local memory is operated. In this embodiment, local memory binding is to associate the memory requirements of the Qemu process with the local memory of the computing node. The purpose of physical memory allocation is to allocate physical memory before the process officially uses a large amount of memory, so as to avoid insufficient memory or performance fluctuations during runtime.

[0060] S204: After the aggregation host is started, a kernel thread is created for each computing node.

[0061] In this embodiment, kernel threads are execution units at the operating system kernel level, managed and scheduled directly by the operating system kernel. Unlike user-level threads, kernel thread creation, destruction, and switching are all handled by the kernel, resulting in higher permissions and lower overhead. Specifically, when the aggregation host starts, to effectively manage and allocate tasks to each compute node, the system creates a kernel thread for each compute node. These threads are responsible for communicating with the corresponding compute node, scheduling tasks, and processing the results returned by the node, thereby ensuring the efficient operation of the entire aggregation host system.

[0062] In some embodiments, after creating a kernel thread for each computing node, the method further includes: binding the kernel thread of each computing node to a central processing unit of each computing node.

[0063] Exemplarily, the aggregation host includes computing node A and computing node B. After the aggregation host is started, the CPUs of different computing nodes respectively initialize the reserved local memory and manage the page table pages of the local memory according to a preset granularity (such as 4KB). Specifically, the client operating system starts two kernel threads TA and TB. TA is bound to the CPU of computing node A, and TB is bound to the CPU of computing node B. TA and TB are respectively responsible for tasks related to their respective computing nodes. Among them, the client operating system is an operating system running in a virtual machine. It manages the resources within the virtual machine, just like managing hardware resources in a physical machine. Here, it needs to perform some specific operations. Kernel threads TA and TB are threads in the client operating system, and kernel threads are managed by the operating system kernel.

[0064] In some embodiments, TA and TB can be initialized separately and used to allocate local page table pages for the local memory reserved for the two computing nodes. That is, each computing node has its own independent address space management, and the page table is used to map virtual addresses to physical addresses. The initialized TA and TB are respectively used to allocate local page table pages for the local memory reserved for their respective computing nodes (A and B). That is, TA is responsible for the page table page allocation operations for the local memory reserved for computing node A, and TB is responsible for node B, in order to manage the use of memory space.

[0065] In some embodiments, when the allocated memory size is fixed at 4KB, a bitmap can be used for local page table page management. A bitmap is a data structure that uses a bit to represent a certain state (such as whether a page is used). In local page table page management, the usage of the page table page can be efficiently marked through the bit state of the bitmap. Specifically, each bit in the bitmap can represent the usage status (allocated or unallocated) of a memory page (4KB corresponds to one page), and the allocation of memory pages can be conveniently managed by operating the bitmap. In this embodiment, the bitmap intuitively reflects the usage status of the memory page in a concise binary manner, thereby optimizing the speed and accuracy of memory management.

[0066] S206 , in response to starting the load in the aggregation host, copying the memory page table corresponding to the load from the compute fast link CXL memory to the local memory reserved by each compute node through the kernel thread of each compute node.

[0067] In this embodiment, starting a load in the aggregation host means starting a computing task or program. Compute Express Link (CXL) memory is a new high-speed interconnect memory technology. Page tables are used to manage operations such as memory address mapping.

[0068] It's important to note that in the aggregation host, both page tables and business data are stored in CXL memory. Although each compute node can share access to CXL memory, CXL memory has certain limitations. Specifically, when a large number of page tables and business data are shared, access conflicts and latency increase. For example, frequent page table lookups can interfere with the fast access of business data, resulting in poor overall performance and inability to fully utilize the high speed of CXL memory. This results in low efficiency for these workloads when using CXL memory alone.

[0069] For example, when workloads run on a clustered host, the hardware's TLB capacity is insufficient to cover the workload's memory address mapping requirements in large memory scenarios, resulting in common TLB misses. These misses require the MMU to perform page table walks involving multiple memory accesses. Furthermore, the clustered host's page tables are stored in CXL memory, which holds a large number of page tables shared by multiple compute nodes. This time-consuming page table walks can lead to poor workload performance.

[0070] In some embodiments, the memory page table corresponding to the load is copied from the CXL memory to the local memory reserved for each compute node through the kernel thread of each compute node, including: identifying the memory page table information corresponding to the load in the CXL memory through the kernel thread of each compute node; establishing a mapping relationship with the local memory based on the memory page table information corresponding to the load in the CXL memory; and reading the memory page table information corresponding to the load from the CXL memory according to the page table data block into the local memory reserved for each compute node based on the mapping relationship.

[0071] Therefore, in this embodiment, local memory is reserved for each computing node, which makes local memory access faster. The load-related memory page table is copied from the CXL memory to the local memory reserved by the computing node, reducing the waiting and conflicts when multiple nodes access the CXL memory at the same time. This can reduce the dependence on the CXL memory, reduce access conflicts and delays, and improve overall operating performance.

[0072] Figure 3 A flowchart of a method for reserving local memory for each computing node provided by an embodiment of the present disclosure is shown. Figure 3 As shown, this embodiment uses the Qemu process deployed on each computing node to reserve local memory for each computing node, including the following steps:

[0073] S302: Construct a memory mapping function for each computing node using the Qemu process deployed on each computing node.

[0074] In this embodiment, a memory mapping function is a function that establishes a correspondence between a memory address space and a specific data structure or storage area. Using the Qemu process to construct a memory mapping function leverages Qemu's capabilities on each compute node to create a mapping relationship based on the node's memory layout and other conditions. This may be intended to achieve efficient memory management.

[0075] For example, assume that the CPU resources of two compute nodes, compute node A and compute node B, collectively constitute the CPU of the client operating system of the aggregated computing host. Each node provides two physical CPU cores, referred to as ACPU and BCPU, respectively, allocated to the aggregated computing host. The Qemu processes deployed on the two compute nodes that boot the aggregated computing host are QA and QB, respectively. During the boot process of the aggregated computing host, QA sets memmap=1G$4G in its startup parameters; similarly, QB sets memmap=1G$5G in its startup parameters.

[0076] S304: Reserve memory for each computing node according to the memory mapping function on each computing node.

[0077] In this example, when QA starts up, it constructs memmap=1G$4G, which reserves 1GB of memory address space starting from the 4GB starting address as the aggregate host's reserved memory RA. Similarly, QB uses memmap=1G$5G to reserve 1GB of memory address space starting from the 5GB starting address as reserved memory RB. Here, QA and QB are different compute nodes, each reserving memory in a specific memory address range based on its own needs.

[0078] S306: Allocate the reserved memory to the local memory of each computing node.

[0079] In this embodiment, Non-Uniform Memory Access (NUMA) is a computer memory design architecture. In this architecture, memory access times may vary depending on the physical distance between the processor and the memory. When QA starts, the reserved memory RA is NUMA-bounded to the local memory of compute node A using the mbind system call. This allows QA to access the RA memory more efficiently when running on node A. Similarly, the reserved memory RB is NUMA-bounded to the local memory of compute node B using the mbind system call. This allows QA to access the RB memory efficiently when running on node B.

[0080] In this embodiment, since local memory access is faster, by reserving local memory for each computing node, the flexibility and efficiency of memory management are improved, so that each computing node can effectively utilize local memory resources to meet its own operating needs and improve overall operating performance.

[0081] In some embodiments, the memory page table corresponding to the load includes an M-level page table, where M is a positive integer. Figure 4 A flow chart of a method for copying a page table provided by an embodiment of the present disclosure is shown. Figure 4 As shown, this embodiment copies the memory page table corresponding to the load from the CXL memory to the local memory reserved by each computing node through the kernel thread of each computing node, including the following steps:

[0082] S402 , copying the first N levels of page tables corresponding to the load from the CXL memory to the local memory reserved by each computing node through the kernel thread of each computing node, where N is a positive integer and N is less than M.

[0083] In some embodiments, each compute node shares page tables except the first N levels of page tables in the M levels of page tables with the CXL memory.

[0084] In this embodiment, the M-level page table represents the total number of page table levels (e.g., M = 4 in a four-level page table). The N-level page table represents the first N levels of page tables that need to be copied to local memory (e.g., N = 3). The sharing rule is that the first N levels are localized, and the remaining (MN) levels (e.g., the last level of page tables) are retained in CXL memory for global sharing.

[0085] It should be noted that the page table hierarchy is a mechanism used in operating systems to manage the mapping of virtual memory to physical memory. To effectively manage large memory spaces, a multi-level page table is used. Understandably, if a single-level page table covers the entire virtual address space, it would occupy a large amount of memory. A multi-level page table divides the page table into multiple levels. For example, in a common two-level page table, each entry in the first-level page table (page directory) points to a second-level page table (page table), and the entries in the second-level page table actually point to physical page frames. This hierarchical structure allows specific portions of the page table to be loaded into memory only when needed, reducing memory usage. Page tables at different levels work together to gradually convert a process's virtual addresses into physical addresses, implementing virtual memory management and improving system memory utilization and performance.

[0086] Taking x86_64 as an example, it includes a four-layer page table structure, specifically including: PGD (Page Global Directory): top-level page table, indexing the highest bit of the virtual address; PUD (Page Upper Directory): sub-top-level page table, dividing large pages or next-level directories; PMD (Page Middle Directory): intermediate page table, managing medium-granularity memory areas; PTE (Page Table Entry): the lowest-level page table entry, also called the last-level page table, directly mapping the physical page frame.

[0087] Specifically, when workload W starts, the aggregation host's kernel triggers the page table synchronization process: Continuing with the above example, kernel thread TA is bound to compute node A, and kernel thread TB is bound to compute node B. TA and TB copy the page table of workload W from CXL global memory to the local memory (RA and RB) of compute nodes A and B, respectively. This copy process only involves the top three levels of the page table structure—the PGD (global page directory), the PUD (upper page directory), and the PMD (middle page directory). The bottom-level PTEs (page table entries) are directly shared with CXL memory. Figure 5 A schematic diagram of an aggregation host using local memory to cache page tables provided in an embodiment of the present disclosure, combined with Figure 5As shown in the figure, in a typical four-level page table architecture (M=4), if N=3, the first three levels of page tables (PGD / PUD / PMD) are completely copied locally, while the fourth level PTEs remain globally shared in CXL memory. When workload W is assigned by the client operating system's scheduler to the CPU of compute node A (ACPU), the CPU's page table base address register (such as CR3 on x86) will point to the PGD start address copied from RA. If the workload is migrated to the CPU of node B (BCPU), the base address switches to the PGD address in RB.

[0088] In this embodiment, this design enables the query of the first three levels of page tables to be completed entirely through local memory during the address translation process, and only triggers a remote read of the CXL memory once when the PTE is finally accessed, thereby significantly reducing latency.

[0089] It should be noted that sharing the last-level page table (e.g., PTE) is only an example solution; actual systems can flexibly adjust the sharing level based on needs. For example, in some scenarios, the system may choose to share the middle-level page table (e.g., PMD) and the lowest-level PTE, replicating only the PGD and PUD; or share the next-highest-level page table (PUD), the middle-level page table (PMD), and PTE, replicating only the PGD. However, from a comprehensive perspective of performance and resource overhead, sharing the last-level page table is generally the most effective.

[0090] Understandably, the number of last-level page tables (PTEs) is enormous (for example, a 4KB page corresponds to 1,048,576 PTEs). Fully replicating these to every node would consume a significant amount of local memory. Higher-level page tables (such as PGD / PUD) have fewer entries (typically hundreds to thousands), making the memory overhead of local replication negligible. Furthermore, PTEs are directly associated with physical page frame mappings, and the shared design naturally relies on CXL's consistency protocols (such as directory-based cache coherence) to maintain global synchronization of cross-node mappings, avoiding complex synchronization issues in multi-replica scenarios. For example, with a four-level page table, replicating the first three levels (PGD / PUD / PMD) and sharing PTEs, a single process's local memory usage is only a few KB (assuming PGD / PUD / PMD each occupies one page). Global PTE sharing within CXL eliminates the need for redundant storage of multi-gigabyte memory mappings. This hierarchical strategy reduces address translation latency while preventing the massive last-level page tables from encroaching on local memory.

[0091] In this embodiment, the compute node's local memory is used to aggregate the host's additional management space for page tables. A copy of the process page table in CXL memory is cached in local memory. When a process switches, its MMU page table base address is changed, and if local memory becomes unavailable, it can flexibly switch back to CXL memory. Furthermore, the process's page table location is relocated as needed to minimize memory access latency.

[0092] In some embodiments, for page table page management with local cache, the disclosed embodiments also provide specific methods required for memory access, memory permission change, and memory release scenarios corresponding to the creation, modification, and release operations of load page table pages (entries). Figure 6 A flow chart of another memory management method according to the embodiment of the present disclosure is shown. Figure 6 As shown, the memory management method provided in this embodiment also includes the following steps:

[0093] S602 : In response to a memory management operation performed by a load running on the first computing node, page table information is updated in the CXL memory, and page table information of a local memory in the first computing node is updated according to the updated page table information in the CXL memory.

[0094] In some embodiments, the memory management operation includes at least one of: memory access, memory permission change, and memory release.

[0095] Specifically, it is assumed that the first computing node is computing node A, the second computing node is computing node B, the physical CPU of computing node A is ACPU, and the physical CPU of computing node B is BCPU.

[0096] Taking memory access as an example, when a load first requests memory through the memory allocation function (malloc), this operation may occur on any physical CPU of the compute node (ACPU or BCPU). Assuming the operation is triggered by ACPU, ACPU first updates the page table information in CXL, then updates the page table information of ACPU's reserved local memory area RA (i.e., compute node A's local memory), linking the PMD table entry in the area to the newly allocated PTE entry in CXL. This allows the compute node to correctly access resources in CXL memory, and the local memory page table information is also updated according to the update in CXL. Similarly, when the operation is triggered by BCPU, BCPU first updates the page table information in CXL, then updates the page table information of BCPU's reserved local memory area RB (i.e., compute node B's local memory), linking the PMD table entry in the area to the newly allocated PTE entry in CXL. This allows the compute node to correctly access resources in CXL memory, and the local memory page table information is also updated according to the update in CXL.

[0097] Taking memory permission changes as an example, when the load performs memory permission changes on ACPU, the page table information in CXL is also changed first, including all page table entries in the permission modification range. The change process requires copying the page table entry information related to the permission change in CXL and synchronizing the information to RA, and triggering the TLB shootdown operation to mark the page table cache of BCPU invalid. It should be noted that TLB shootdown is the fast table invalidation process. When certain situations occur in the system, such as the mapping relationship of the original process in the TLB is no longer applicable, a TLB shootdown operation is required to invalidate the relevant entries in the TLB. If the old mapping relationship continues to be used, it will cause incorrect address translation. The purpose is to ensure that the content in the TLB is consistent with the page table of the current process, thereby ensuring the accuracy of the address translation and maintaining the normal operation of the system. The operation of computing node B is similar and will not be repeated here.

[0098] Taking memory release as an example, when the load releases the relevant memory pages on the ACPU, the page table information of the CXL memory is also changed, including recycling the relevant page table entries, triggering the TLB shootdown operation to mark the page table cache of the BCPU invalid.

[0099] S602 : When the load running on the first computing node is transferred to the second computing node, in response to the load running on the second computing node triggering a page fault, the local memory of the second computing node synchronizes data with the CXL memory.

[0100] In this embodiment, when a workload first requests memory through the memory allocation function (malloc) during memory access, if it is executed on compute node A, the local memory RB area of compute node B does not yet contain the data update of the newly created page table entry. Due to the newly added entry, when the workload migrates to CPU B, if it accesses the corresponding memory or other operations that trigger a page fault, it first synchronizes data with the latest page table information of CXL before performing physical memory access.

[0101] When memory permissions are changed, compute node A triggers a TLB shootdown operation, marking BCPU's page table cache invalid. Therefore, when the load running on the first compute node is transferred to the second compute node, BCPU re-traverses the page table in RB when performing relevant memory accesses, and triggers a synchronous update of the page table through a page fault, that is, the local memory of compute node B synchronizes data with the CXL memory.

[0102] When memory is released, compute node A also triggers a TLB shootdown operation, marking the BCPU's page table cache invalid. Since some PTE pages will be deleted, BCPU will also cause page faults when traversing page table entries, which also triggers a synchronous update of the page table. That is, the local memory of compute node B and the CXL memory synchronize data.

[0103] In this embodiment, when page table modifications occur on CPUs of different compute nodes, the page tables of CPUs on other compute nodes need to be updated synchronously to avoid data access permission disruptions. Considering that the CPUs of other compute nodes cannot be directly accessed and modified by the local CPU, the present invention synchronizes page table modifications by sharing the CXL layer's four-level page table (PTE page table page) between page table replicas. This allows for lazy page table synchronization by causing other compute nodes to generate page faults when corresponding data accesses occur.

[0104] Figure 7 The following is a flow chart showing a specific method of providing a memory management method according to an embodiment of the present disclosure. Figure 7 As shown, the memory management method provided by the embodiment of the present disclosure includes the following steps:

[0105] S701: The guest operating system kernel starts the reserved memory.

[0106] S702, Qemu binds the memory allocation policy of the reserved memory address space to the local memory of the computing node.

[0107] S703: Check whether the load has enabled local page table cache. If so, go to S704; if not, go to S708.

[0108] S704 , synchronously load the CXL page table memory to the reserved space of the local memory of the computing node, and share the last-level page table entry.

[0109] S705 : Any CPU of any computing node that modifies the CXL page table will also modify the local page table cache simultaneously.

[0110] S706 , other CPU nodes trigger synchronous update of local page tables and CXL page tables through Page fault.

[0111] S707, whether the load stops, if so, go to S708, if not, go to S703.

[0112] S708, clear the local memory page table cache and CXL page table.

[0113] Based on the same inventive concept, the present disclosure also provides a memory management device, as described in the following embodiments. Since the principle of solving the problem in the device embodiment is similar to that in the above method embodiment, the implementation of the device embodiment can refer to the implementation of the above method embodiment, and the repeated parts will not be repeated.

[0114] Figure 8 A schematic diagram of a memory management device according to an embodiment of the present disclosure is shown, which is applied to an aggregation host comprising multiple computing nodes. Figure 8 As shown, the device includes: a reservation module 81, a creation module 82 and a copy module 83;

[0115] The reservation module 81 is used to reserve local memory for each computing node in response to starting the aggregation host; the creation module 82 is used to create a kernel thread for each computing node when the aggregation host is started; the copy module 83 is used to copy the memory page table corresponding to the load from the computing fast link CXL memory to the local memory reserved for each computing node through the kernel thread of each computing node in response to starting the load in the aggregation host.

[0116] In some embodiments, the reservation module 81 is specifically used to reserve local memory for each computing node using the Qemu process deployed on each computing node.

[0117] In some embodiments, the reservation module 81 is specifically used to: construct a memory mapping function for each computing node using the Qemu process deployed on each computing node; reserve memory for each computing node according to the memory mapping function on each computing node; and allocate the reserved memory to the local memory of each computing node.

[0118] In some embodiments, the reservation module 81 is further specifically configured to bind the kernel thread of each computing node to the central processing unit of each computing node.

[0119] In some embodiments, the copy module 83 is specifically used to: identify memory page table information corresponding to the load in the CXL memory through the kernel thread of each computing node; establish a mapping relationship with the local memory based on the memory page table information corresponding to the load in the CXL memory; and read the memory page table information corresponding to the load from the CXL memory according to the page table data block into the local memory reserved for each computing node based on the mapping relationship.

[0120] In some embodiments, the memory page table corresponding to the load includes M-level page tables, where M is a positive integer. The copy module 83 is specifically used to: copy the first N-level page tables corresponding to the load from the CXL memory to the local memory reserved for each computing node through the kernel thread of each computing node, where N is a positive integer and N is less than M; the method also includes: each computing node shares the page tables in the M-level page tables except the first N-level page tables with the CXL memory.

[0121] In some embodiments, the multiple computing nodes include a first computing node and a second computing node, and the device further includes a management module for: performing memory management operations in response to a load running on the first computing node, updating page table information in the CXL memory, and updating page table information in the local memory of the first computing node based on the updated page table information in the CXL memory; when the load running on the first computing node is transferred to the second computing node, in response to a page fault being triggered by the load running on the second computing node, synchronizing data between the local memory of the second computing node and the CXL memory.

[0122] In some embodiments, the memory management operation includes at least one of the following: memory access, memory permission change, and memory release.

[0123] It should be noted that the examples and application scenarios implemented by the modules in the above-mentioned apparatus embodiment are the same as those implemented by the corresponding steps in the method embodiment, but are not limited to the contents disclosed in the above-mentioned method embodiment. It should be noted that the above-mentioned modules, as part of the apparatus, can be executed in a computer system, such as a set of computer-executable instructions.

[0124] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation that combines hardware and software aspects, which may be collectively referred to herein as a "circuit," "module," or "system."

[0125] Based on the same inventive concept, an embodiment of the present disclosure further provides an electronic device, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute any one of the aforementioned memory management methods by executing the executable instructions. Since the principles for solving the problem in this electronic device embodiment are similar to those in the aforementioned method embodiment, the implementation of this electronic device embodiment can refer to the implementation of the aforementioned method embodiment, and any repetitive details will not be repeated.

[0126] Refer to the following Figure 9 1 and 2 to describe the electronic device 900 according to this embodiment of the present disclosure. Figure 9The electronic device 900 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0127] like Figure 9 As shown, electronic device 900 is implemented as a general-purpose computing device. Components of electronic device 900 may include, but are not limited to, at least one processing unit 910, at least one storage unit 920, and a bus 930 connecting various system components (including storage unit 920 and processing unit 910).

[0128] The storage unit stores program code, which can be executed by the processing unit 910, so that the processing unit 910 performs the steps described in the "Exemplary Method" section of this specification according to various exemplary embodiments of the present disclosure. For example, the processing unit 910 can perform the following steps of the above-mentioned method embodiment: in response to starting the aggregation host, reserving local memory for each computing node; when the aggregation host is started, creating a kernel thread for each computing node; in response to starting a load in the aggregation host, copying the memory page table corresponding to the load from the compute fast link CXL memory to the local memory reserved for each computing node through the kernel thread of each computing node.

[0129] The storage unit 920 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 9201 and / or a cache memory unit 9202 , and may further include a read-only memory unit (ROM) 9203 .

[0130] The storage unit 920 may also include a program / utility 9204 having a set (at least one) of program modules 9205, such program modules 9205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0131] Bus 930 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0132] The electronic device 900 can also communicate with one or more external devices 940 (e.g., a keyboard, a pointing device, a Bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 900, and / or any device that enables the electronic device 900 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication can occur via an input / output (I / O) interface 950. Furthermore, the electronic device 900 can communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter 960. As shown, the network adapter 960 communicates with other modules of the electronic device 900 via a bus 930. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 900, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0133] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0134] Based on the same inventive concept, embodiments of the present disclosure also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements any of the aforementioned memory management methods. Because the principles underlying the problems solved by this computer-readable storage medium embodiment are similar to those of the aforementioned method embodiment, the implementation of this computer-readable storage medium embodiment can be referenced to the implementation of the aforementioned method embodiment, and any repetitions will not be repeated.

[0135] More specific examples of computer-readable storage media in the present disclosure may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0136] In the present disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0137] Alternatively, the program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.

[0138] In a specific implementation, the program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, and the like, as well as conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a standalone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0139] Based on the same inventive concept, embodiments of the present disclosure further provide a computer program product, including a computer program or instructions, which, when executed by a processor, implements the memory management method of any one of the aforementioned method embodiments. Because the principles for solving the problems in this computer program product embodiment are similar to those in the aforementioned method embodiment, the implementation of this computer program product embodiment can refer to the implementation of the aforementioned method embodiment, and any repetitions will not be repeated.

[0140] It should be noted that although several modules or units of the device for action execution are mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0141] Furthermore, although the steps of the method of the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in this particular order, or that all steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0142] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0143] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A memory management method, characterized in that: Applied to an aggregation host, the aggregation host includes multiple computing nodes; the method includes: In response to starting the aggregation host, reserving local memory for each computing node; When the aggregation host starts, a kernel thread is created for each compute node; In response to starting a load in the aggregation host, a memory page table corresponding to the load is copied from a compute fast link CXL memory to a local memory reserved by each compute node through a kernel thread of each compute node.

2. The memory management method according to claim 1, wherein: A fast simulation program Qemu process is deployed on each computing node, and local memory is reserved for each computing node, including: The local memory is reserved for each computing node using the Qemu process deployed on each computing node.

3. The memory management method according to claim 2, wherein: The method of reserving local memory for each computing node by using the Qemu process deployed on each computing node includes: Use the Qemu process deployed on each computing node to construct a memory mapping function for each computing node; Reserving memory for each computing node according to the memory mapping function on each computing node; Allocate the reserved memory to the local memory of each compute node.

4. The memory management method according to claim 1, wherein: After creating a kernel thread for each computing node, the method further includes: binding the kernel thread of each computing node to a central processing unit of each computing node.

5. The memory management method according to claim 1, wherein: The step of copying the memory page table corresponding to the load from the CXL memory to the local memory reserved by each computing node through the kernel thread of each computing node includes: Identify the memory page table information corresponding to the load in CXL memory through the kernel thread of each compute node; Establishing a mapping relationship with the local memory based on the memory page table information corresponding to the load in the CXL memory; According to the mapping relationship, the memory page table information corresponding to the load is read from the CXL memory according to the page table data block into the local memory reserved by each computing node.

6. The memory management method according to claim 1, wherein: The memory page table corresponding to the load includes an M-level page table, where M is a positive integer. The step of copying the memory page table corresponding to the load from the CXL memory to the local memory reserved by each computing node through the kernel thread of each computing node includes: Copying the first N levels of page tables corresponding to the load from the CXL memory to the local memory reserved by each computing node through the kernel thread of each computing node, where N is a positive integer and is less than M; The method further comprises: Each computing node and the CXL memory share page tables in the M-level page tables except the first N-level page tables.

7. The memory management method according to claim 6, wherein: The plurality of computing nodes include a first computing node and a second computing node, and the method further includes: In response to a memory management operation performed by a load running on the first compute node, updating page table information in the CXL memory, and updating page table information in a local memory in the first compute node based on the updated page table information in the CXL memory; When the workload running on the first computing node is transferred to the second computing node, in response to a page fault being triggered by the workload running on the second computing node, the local memory of the second computing node synchronizes data with the CXL memory.

8. The memory management method according to claim 7, wherein: The memory management operation includes at least one of the following: memory access, memory permission change, and memory release.

9. A memory management device, characterized in that: Applied to an aggregation host, the aggregation host includes multiple computing nodes; the device includes: a reservation module, configured to reserve local memory for each computing node in response to starting the aggregation host; A creation module is used to create kernel threads for each computing node when the aggregation host is started; The copy module is used for copying the memory page table corresponding to the load from the computing fast link CXL memory to the local memory reserved by each computing node through the kernel thread of each computing node in response to starting the load in the aggregation host.

10. An electronic device, characterized in that: include: processor; as well as a memory for storing executable instructions of the processor; The processor is configured to execute the memory management method according to any one of claims 1 to 8 by executing the executable instructions.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the memory management method according to any one of claims 1 to 8 is implemented.

12. A computer program product comprising: A computer program or instruction, characterized in that when the computer program or instruction is executed by a processor, it implements the memory management method according to any one of claims 1 to 8.

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