A method for optimizing analog circuit parameters in view of process deviation

Abstract

The present invention discloses a method for optimizing analog circuit parameters for process variation, comprising the following steps: S1. For a given analog circuit, multi-objective optimization is performed under nominal process conditions. Based on the optimization results, design regions with poor performance are identified and eliminated. These remaining high-quality regions are then divided into a number of initial trust regions through cluster analysis; S2. Finite Monte Carlo simulation data within the initial trust regions are modeled using a heteroscedastic Gaussian process model to capture the average level and variation trend of circuit performance and predict circuit behavior under process variation; S3. While optimizing performance, the required yield is maintained, and a value at risk (VAR) is used to provide a probabilistic guarantee for performance values. During the optimization phase that considers process variation, multiple iterations are performed to ultimately obtain an optimized set of design points and a corresponding Pareto optimal solution set. The present invention finds a high-quality Pareto optimal solution set that satisfies yield constraints under process variation with unknown distributions, thereby optimizing the size of the analog circuit.

Description

Technical Field

[0001] The present invention relates to analog circuit optimization, and in particular to an analog circuit parameter optimization method oriented to process deviation. Background Art

[0002] As process scale continues to advance, integrated circuit (IC) design becomes increasingly complex and challenging. To achieve higher density, enhanced functionality, and higher production yields in smaller form factors, more advanced technologies and methodologies must be employed. While digital circuit design has become highly automated, analog circuit design still relies primarily on manual processes. However, given the growing demand for high performance and high yield, coupled with the pressure to achieve rapid time to market, manual analog circuit design is becoming increasingly impractical. Consequently, there is a pressing need for automated tools in the analog circuit design field.

[0003] In analog circuit design automation tools, sizing is a key step, with the primary goal of maximizing performance by optimizing device design parameters. This task can be formulated as a multi-objective optimization problem, aiming to find the optimal solution corresponding to the maximum performance metric (FoM) or the Pareto optimality set. The FoM is the weighted sum of all objectives, but improving one performance metric often comes at the expense of another. The Pareto optimal solution set represents a set of solutions that provide the best trade-off between all objectives and cannot be simultaneously surpassed by other solutions in the feasible solution space. The optimal design parameter vector lies on the Pareto optimal solution set.

[0004] Existing analog circuit sizing methods fall primarily into two categories: model-based and simulation-based. Model-based methods require the development of analytical models linking device design parameters to performance, but accurately deriving such performance models is often challenging. Consequently, many approaches have turned to simulation-based approaches, in which performance is represented by black-box functions (i.e., surrogate models), such as Gaussian processes. These models are constructed and optimized through real-time simulation, leveraging techniques such as evolutionary algorithms, Bayesian optimization, and reinforcement learning to identify Pareto-optimal solutions and the optimal solution corresponding to the maximum FoM. However, these traditional methods often fail to fully account for the impact of process variations, potentially leading to low yield. To improve yield, existing methods attempt to maximize yield by fine-tuning device design parameters, but these methods often require extensive simulations to achieve the desired results. While methods combining surrogate models with importance sampling can reduce simulation times, optimizing solely for yield can compromise circuit performance. In addition, some existing methods attempt to optimize circuit performance at process, voltage, and temperature (PVT) corners to enhance design robustness. However, these methods typically rely on PVT corner simulations and fail to consider all process variations. Therefore, they may not always meet yield requirements, especially in analog circuits that are more sensitive to process variations. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide an analog circuit parameter optimization method oriented to process deviation, so as to find a high-quality Pareto optimal solution set that meets the yield constraint under process variations with unknown distribution, and optimize the analog circuit size.

[0006] The object of the present invention is achieved through the following technical solution: a method for optimizing analog circuit parameters for process deviation, comprising the following steps:

[0007] S1. For a given analog circuit, perform multi-objective optimization under nominal process conditions. Based on the optimization results, identify and eliminate design regions with poor performance. Then, use cluster analysis to partition these remaining high-quality regions into several initial trust regions.

[0008] S2. Use a heteroscedastic Gaussian process model to model the finite Monte Carlo simulation data within the initial trust region, capturing the average level and variation trend of circuit performance and predicting circuit behavior under process variations.

[0009] S3. Maintain the required yield while optimizing performance, using value at risk to provide a probabilistic guarantee on performance values. During the optimization phase that takes process variations into account, through multiple iterations, we ultimately obtain the optimized set of design points and the corresponding Pareto optimal solution set.

[0010] The beneficial effect of the present invention is that the present invention can find a high-quality Pareto optimal solution set that meets the yield constraint under process variations with unknown distribution, and optimize the size of the analog circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the principle of the present invention; DETAILED DESCRIPTION

[0012] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0013] like Figure 1 As shown, a method for optimizing analog circuit parameters for process deviation includes the following steps:

[0014] S1. Initialization Phase: For a given circuit, we first perform multi-objective optimization under nominal process conditions. Using the optimization results, we identify and eliminate design regions with poor performance, retaining those with potential. Then, through cluster analysis, we group these remaining high-quality regions into several initial trust regions, laying the foundation for further exploration.

[0015] The core idea of ​​this phase is that designs that perform well under nominal process conditions generally maintain relatively good performance under process variations, although the specific performance ranking may change. Based on this observation, we propose a space pruning strategy that gradually narrows the search scope while retaining promising designs to ensure the efficiency and effectiveness of the subsequent optimization process.

[0016] For a given circuit, a series of design points are given to characterize the circuit parameters. Each design point contains various circuit parameters, such as the aspect ratio of transistors, the values ​​of resistors and capacitors, etc. These parameters serve as input variables for the optimization algorithm. Ignoring the impact of process variations, the design solution with the best performance under nominal conditions is found:

[0017] First, we perform multi-objective optimization on a given circuit under typical process conditions. In this process, we do not consider the impact of process variations, but instead focus on finding the design with the best performance under nominal conditions. Specifically, we use the Bayesian optimization method to predict the value of the objective function by constructing a Gaussian process (GP) as a proxy model. The Gaussian process can provide uncertainty estimates for each prediction point, which is crucial for the optimization process. We use the acquisition function to select new sampling points, thereby gradually approaching the optimal solution with a limited number of evaluations. After multiple iterations, we generate a series of evaluation points and their performance data, which constitute the optimization history. The specific process is summarized as follows:

[0018] S101. Perform multi-objective optimization on a given circuit under typical process conditions:

[0019] For a given analog circuit, assume that the components and their connections are fixed. Given a design space, the design space contains several different design points, each of which is a design solution containing the parameters of each component in the analog circuit. The multi-objective optimization process is as follows:

[0020] A1. Initialize and select multiple design points from the design space as existing design points;

[0021] A2. Simulate each existing design point to obtain actual performance data of the existing design point;

[0022] A3. Use each existing design point and its corresponding actual performance data to train a Gaussian model and establish a mapping relationship between the design point and the performance data;

[0023] A4. Use the Gaussian model to predict the performance data of each design point in the design space;

[0024] A5. Based on the performance prediction results of each design point in the design space, the sampling function in the Bayesian optimization method is used to select multiple design points to be evaluated from the design space. Simulations are performed on each of the design points to obtain the actual performance data of the design points to be evaluated. The Gaussian model is then trained and updated.

[0025] A6. Based on the updated Gaussian model, repeat steps A4 to A5, continuously iterating the sampling of the design points to be evaluated and the updating of the Gaussian model until the set number of iterations is reached.

[0026] A7. After multiple iterations, the initial point and its performance data, together with all the design points to be evaluated and their performance data selected by the sampling function during the iteration, constitute the optimization history record;

[0027] S102. Extract the Pareto optimal solution set and its related design points from the design points included in the historical records as evaluation points. Perform Monte Carlo simulation on these evaluation points under process variation conditions to obtain the performance of the design solution corresponding to the evaluation point under process variation and determine a performance lower limit.

[0028] Based on the performance lower limit as the dividing line, the evaluation points are divided into two groups: the first group is the points whose performance is greater than the performance lower limit, which are recorded as good performance points, and the points whose performance is not greater than the performance lower limit, which are recorded as poor performance points;

[0029] By analyzing the distribution of points in the design space, the design space is divided into multiple regions. In each region, the ratio of points with poor performance to points with good performance is calculated. If the ratio is greater than a preset threshold, the region is removed to narrow the search range.

[0030] Among the remaining design points, if the distance between two points is less than the set threshold, one of the points is removed to maintain diversity; the remaining point will be used as the initial point for the subsequent optimization stage;

[0031] S103. Divide the input parameter space into several initial trust regions using k-means clustering.

[0032] S2. Process Variation-Aware Optimization Phase: In this phase, we focus on the high-quality regions identified during the initialization phase. We use the Heteroskedastic Gaussian Process (HGP) model to model the finite Monte Carlo (MC) simulation data within these regions. This model captures both the average level and variation trends of circuit performance, thereby predicting circuit behavior under process variations.

[0033] The specific process is summarized as follows:

[0034] S201. In the process of analog circuit processing based on the design point, process changes will affect the performance of the design point, thereby introducing noise variance of the performance. The design point is calculated based on the logarithm of the noise variance. x Performance modeling, denoted as :

[0035]

[0036] in, represents the noise variance caused by process variation, The mean is 0 and the variance is Gaussian distribution of Indicates the design point x performance at the

[0037] S202. Construct two Gaussian processes. The first Gaussian process is used to infer the design point. x Performance at , recorded as f Process, the model parameters of the first Gaussian process are recorded as ;

[0038] The second Gaussian process is used to model the logarithm of the noise variance, which is used to capture the difference between the noise variance and the design point x The relationship is recorded as:

[0039]

[0040] The model parameters of the second Gaussian process are recorded as ;

[0041] S203. For each initial trust region, since it contains multiple design points;

[0042] S2031. Given multiple process change conditions, for any design point x ,Through the simulation process under each process change condition, the simulation results under different ,process change conditions are obtained, forming a real performance distribution, and ,according to the real performance distribution, the real performance mean and ,performance variance are calculated;

[0043] At the same time, the two Gaussian processes constructed in step S202 are used to predict the design point x The distribution of performance at and the distribution of the logarithm of the noise variance;

[0044] Take the average of the predicted performance distribution to obtain the predicted performance mean;

[0045] The distribution of the predicted noise variance logarithm is averaged to obtain the predicted noise variance logarithm, and the predicted noise variance logarithm is processed by exponential processing to restore it to the noise variance, that is, the predicted performance variance;

[0046] S2032. For any sampled design point in the trust region, repeat step S3021 to obtain the true performance mean, performance variance, and predicted performance mean and performance variance at each design point;

[0047] S2033. Based on the actual performance mean and the predicted performance mean at each design point, the model parameters of the first Gaussian process are optimized by the gradient descent method using the maximization log-likelihood criterion. Conduct training updates;

[0048] Based on the actual noise variance and the predicted noise variance at each design point, the model parameters of the second Gaussian process are optimized by the gradient descent method using the maximization log-likelihood criterion. Conduct training updates;

[0049] S2034. For each trust region, repeat steps S3022 to S3023 to train and update the two Gaussian process models;

[0050] S2035. After the training is completed, for any design point, the mean of the performance distribution is predicted by the first Gaussian process, the logarithm of the noise variance is predicted by the second Gaussian process, and after converting back to the noise variance, the performance function in step S201 is used. The design point is obtained by modeling x The performance distribution prediction at , the entire model is recorded as HGP model.

[0051] In a multi-objective scenario, there are different indicators for the performance of the analog circuit. For different performance indicators, steps S1 to S2 are repeated to obtain the performance distribution prediction model under each performance indicator. Assuming that there are M performance indicators in total, the distribution prediction model of the 1st to Mth performance indicators is recorded as ;

[0052] S3. While optimizing performance and maintaining the required yield, we use Value at Risk to provide a probabilistic guarantee on performance. During the optimization phase, which considers process variations, we perform multiple iterations to ultimately obtain the optimal set of design points and the corresponding Pareto optimal solution set.

[0053] To ensure yield requirements are met, we select promising design points based on model predictions using an acquisition function based on Thompson sampling, balancing the need to explore uncertain regions with the need to exploit promising areas. The goal of this phase is to maximize circuit performance while meeting yield requirements.

[0054] S301. Robust prediction through model:

[0055] In order to optimize performance while maintaining the required yield, we use Value at Risk (VaR), which provides a probabilistic guarantee on the performance value. , at the design point x The yield requirement is α∈ [0 , 1], VaR is defined as:

[0056]

[0057] Intuitively, VaR defines the x Meeting yield requirements α The best performance that can be achieved under the circumstances. Multivariate Value-at-Risk (MVaR) extends the VaR concept to the multi-objective scenario. Due to the existence of multiple objectives, the single maximum value is replaced by the Pareto optimal solution set. For a given point x and yield requirements α∈ [0 , 1], MVaR is defined as:

[0058]

[0059] Similar to VaR, MVaR can be interpreted as satisfying Performance vector Due to yield requirementsα Typically high, MVaR essentially represents the worst performance vector under process variation. In this high yield scenario ( α≈ 1) The joint probability is subject to the constraints of a single performance, which allows MVaR to be effectively approximated by the VaR of a single performance indicator:

[0060]

[0061] Acquisition Function: Based on the definition given above, the goal of this stage can be expressed as optimizing a robust Pareto-optimal solution set formed by MVaR values, where each solution inherently meets the yield requirement. By maximizing the hypervolume (HV) of this solution set, we can improve solution quality while maintaining robustness to process variations. To efficiently select new design points most likely to increase HV, we propose an acquisition function based on Thompson sampling (TS). TS achieves a balance between exploration and exploitation by randomly sampling from the posterior distribution of the generalized regression model and generating new query points based on these samples. This approach naturally supports batch selection.

[0062] The sampling point selection strategy is:

[0063] S3021. First, select multiple design points from the trust region, perform performance prediction according to step S2, and add the selected design points to the optimized set of design points;

[0064] S3022. For each design point in the design point set, evaluate it separately according to step S301, construct a set of MVaR values ​​for each design point in the design point optimization set, and calculate the hypervolume of the set;

[0065] S3023. Construct an acquisition function based on Thompson sampling and select multiple new design points as candidate points from the trust region;

[0066] For each candidate point, its predicted MVaR value is combined with the MVaR value of the selected point to form a new set. The excess volume improvement brought by the candidate point is calculated, and the candidate point with the largest excess volume improvement is selected to be added to the batch, that is, the candidate point is added to the optimized set of design points.

[0067] S3024. Repeat step S3022, and finally obtain the optimized set of design points and the corresponding Pareto optimal solution set through iterative optimization.

[0068] The foregoing description shows and describes a preferred embodiment of the present invention. However, as previously stated, it should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Instead, the present invention is applicable to various other combinations, modifications, and environments and is capable of modification within the scope of the inventive concept described herein, through the teachings above, or through techniques or knowledge in the relevant art. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be within the scope of the appended claims.

Claims

1. A method for optimizing analog circuit parameters for process deviation, characterized by: The following steps are involved: S1. For a given analog circuit, perform multi-objective optimization under nominal process conditions. Based on the optimization results, identify and eliminate design regions with poor performance. Then, use cluster analysis to partition these remaining high-quality regions into several initial trust regions. S2. Use a heteroscedastic Gaussian process model to model the finite Monte Carlo simulation data within the initial trust region, capturing the average level and variation trend of circuit performance and predicting circuit behavior under process variations. The step S2 comprises: S201. In the process of analog circuit processing based on the design point, process changes will affect the performance of the design point, thereby introducing noise variance of the performance. The design point is calculated based on the logarithm of the noise variance. x Performance modeling, denoted as : in, represents the noise variance caused by process variation, The mean is 0 and the variance is Gaussian distribution of Indicates the design point x performance at the S202. Construct two Gaussian processes. The first Gaussian process is used to infer the design point. x Performance at , recorded as f Process, the model parameters of the first Gaussian process are recorded as ; The second Gaussian process is used to model the logarithm of the noise variance, which is used to capture the difference between the noise variance and the design point x The relationship is recorded as: The model parameters of the second Gaussian process are recorded as ; S203. For each initial trust region, since it contains multiple design points; S2031. Given multiple process change conditions, for any design point x ,Through the simulation process under each process change condition, the simulation results under different ,process change conditions are obtained, forming a real performance distribution, and ,according to the real performance distribution, the real performance mean and ,performance variance are calculated; At the same time, the two Gaussian processes constructed in step S202 are used to predict the design point x The distribution of performance at and the distribution of the logarithm of the noise variance; Take the average of the predicted performance distribution to obtain the predicted performance mean; The distribution of the predicted noise variance logarithm is averaged to obtain the predicted noise variance logarithm, and the predicted noise variance logarithm is processed by exponential processing to restore it to the noise variance, that is, the predicted performance variance; S2032. For any sampled design point in the trust region, repeat step S2031 to obtain the true performance mean, performance variance, and predicted performance mean and performance variance at each design point; S2033. Based on the actual performance mean and the predicted performance mean at each design point, the model parameters of the first Gaussian process are optimized by the gradient descent method using the maximization log-likelihood criterion. Perform training updates; Based on the actual noise variance and the predicted noise variance at each design point, the model parameters of the second Gaussian process are optimized by the gradient descent method using the maximization log-likelihood criterion. Perform training updates; S2034. For each trust region, repeat steps S2032 to S2033 to train and update the two Gaussian process models; S2035. After the training is completed, for any design point, the mean of the performance distribution is predicted by the first Gaussian process, the logarithm of the noise variance is predicted by the second Gaussian process, and after converting back to the noise variance, the performance function in step S201 is used. The design point is obtained by modeling x The performance distribution prediction at , the entire model is recorded as HGP model; S3. Maintain the required yield while optimizing performance, use value at risk to provide a probabilistic guarantee on the performance value, and in the optimization phase considering process variations, through multiple iterations, ultimately obtain the optimized set of design points and the corresponding Pareto optimal solution set.

2. The method for optimizing analog circuit parameters for process deviation according to claim 1, wherein: The step S1 comprises: S101. Perform multi-objective optimization on a given circuit under typical process conditions: For a given analog circuit, assume that the components and their connections are fixed. Given a design space, the design space contains several different design points, each of which is a design solution containing the parameters of each component in the analog circuit. The multi-objective optimization process is as follows: A1. Initialize and select multiple design points from the design space as existing design points; A2. Simulate each existing design point to obtain actual performance data of the existing design point; A3. Use each existing design point and its corresponding actual performance data to train a Gaussian model and establish a mapping relationship between the design point and the performance data; A4. Use the Gaussian model to predict the performance data of each design point in the design space; A5. Based on the performance prediction results of each design point in the design space, the sampling function in the Bayesian optimization method is used to select multiple design points to be evaluated from the design space. Simulations are performed on each of the design points to obtain the actual performance data of the design points to be evaluated. The Gaussian model is then trained and updated. A6. Based on the updated Gaussian model, repeat steps A4 to A5, continuously iterating the sampling of the design points to be evaluated and the updating of the Gaussian model until the set number of iterations is reached. A7. After multiple iterations, the initial point and its performance data, together with all the design points to be evaluated and their performance data selected by the sampling function during the iteration, constitute the optimization history record; S102. Extract the Pareto optimal solution set and its related design points from the design points included in the historical records as evaluation points. Perform Monte Carlo simulation on these evaluation points under process variation conditions to obtain the performance of the design solution corresponding to the evaluation point under process variation and determine a performance lower limit. Based on the performance lower limit as the dividing line, the evaluation points are divided into two groups: the first group is the points whose performance is greater than the performance lower limit, which are recorded as good performance points, and the points whose performance is not greater than the performance lower limit, which are recorded as poor performance points; By analyzing the distribution of points in the design space, the design space is divided into multiple regions. In each region, the ratio of points with poor performance to points with good performance is calculated. If the ratio is greater than a preset threshold, the region is removed to narrow the search range. Among the remaining design points, if the distance between two points is less than the set threshold, one of the points is removed to maintain diversity; the remaining point will be used as the initial point for the subsequent optimization stage; S103. Divide the input parameter space into several initial trust regions using k-means clustering.

3. The method for optimizing analog circuit parameters for process deviation according to claim 1, wherein: In a multi-objective scenario, there are different indicators for the performance of the analog circuit. For different performance indicators, steps S1 to S2 are repeated to obtain the performance distribution prediction model under each performance indicator. Assuming that there are M performance indicators in total, the distribution prediction model of the 1st to Mth performance indicators is recorded as .

4. The method for optimizing analog circuit parameters for process deviation according to claim 3, wherein: The step S3 comprises: S301: Circuit robustness prediction; Case 1: For a single-target scenario, that is, when there is only one performance indicator, the VaR is used to provide a probability guarantee for the performance value. x Performance function affected by process fluctuations , under the yield requirement α, VaR is defined as: satisfying performance greater than or equal to When the probability of is not less than α, find The maximum value of is: in, is the performance value that meets the yield requirement in a single-target scenario. There are multiple solutions for the performance value that meets the yield requirement in a single-target scenario, and the maximum value is , represents a real number; Case 2: For multi-objective scenarios, that is, when there are M performance indicators, the multivariate risk value MVaR is used to represent the performance vector under the yield requirement α, which is recorded as: in, is the performance vector that meets the yield requirement in a multi-objective scenario. The performance vector that meets the yield requirement has several solutions, which constitute the solution set of the performance vector. Each solution contains the performance values ​​corresponding to various performance indicators. It means finding the Pareto optimal solution for the solution set of performance vector; Among them, MVaR is obtained by approximating the VaR of each performance indicator: in, Indicates the design point x At , VaR of the 1st to Mth performance indicators; S302: Sampling point selection strategy: S3021. First, select multiple design points from the trust region, perform performance prediction according to step S2, and add the selected design points to the optimized set of design points; S3022. For each design point in the design point set, evaluate it separately according to step S301, construct a set of MVaR values ​​for each design point in the design point optimization set, and calculate the hypervolume of the set; S3023. Construct an acquisition function based on Thompson sampling and select multiple new design points as candidate points from the trust region; For each candidate point, its predicted MVaR value is combined with the MVaR value of the selected point to form a new set. The excess volume improvement brought by the candidate point is calculated, and the candidate point with the largest excess volume improvement is selected to be added to the batch, that is, the candidate point is added to the optimized set of design points. S3024. Repeat step S3022, and finally obtain the optimized set of design points and the corresponding Pareto optimal solution set through iterative optimization.

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