Elastic neural network

Abstract

A spiking neural network is disclosed comprising spiking neurons and a synaptic element connected to the spiking neurons wherein the synaptic element comprises a first receptor and a second receptor adapted to receive a synaptic input signal wherein the first receptor and the second receptor generate a first receptor signal and a second receptor signal, respectively, based on the synaptic input signal, the synaptic element applies a weight to the first recipient signal to generate a synaptic output signal, the synaptic element being configurable to adjust the weight applied by the synaptic element based at least on the second recipient signal, and wherein the spiking neuron is adapted to receive the synaptic output signal from the synaptic element, and generate a spatio-temporal pulse sequence output signal in response to at least the received synaptic output signal.

Description

[0001] This application is a divisional application of the invention patent application with the application date of November 18, 2019, the entry date of the Chinese national phase on June 21, 2021, the application number 201980084907.1, and the invention name "Elastic Neural Network". Technical Field

[0002] The present disclosure relates generally to automatic signal recognition techniques, and more particularly, to systems and methods for hardware-resilient deep learning inference accelerators using spiking neurons. Background Art

[0003] Automatic signal recognition (ASR) refers to the process of identifying a signal by recognizing its constituent features. ASR is leveraged in a range of applications, such as recognizing a speaker's voice and spoken words in speech / voice recognition systems, identifying cardiac arrhythmias in an electrocardiogram (ECG), and determining the shape of gestures in motion-controlled systems. ASR is typically performed by characterizing the patterns present in short samples of the input signal, and accurate pattern recognition is therefore crucial for an effective ASR system.

[0004] Measuring some physical quantity to derive input signals for an ASR system may require fusing data from multiple types of sensors. For example, recognizing gestures using a handheld input device may require fusing data from an accelerometer (for measuring motion) and a gyroscope (for measuring orientation). Combining the data from these two sensors enables the detection of gestures in three-dimensional space.

[0005] In general, data fusion refers to the integration of data collected from different and potentially heterogeneous sources in order to reduce the uncertainty in the interpretation of the data from those individual sources. It is important that during the fusion process, the essential features in the different input signals are fully reflected in the fused signal.

[0006] Pattern recognition and fusion are typically performed using microprocessors and / or digital signal processors, both of which implement a stored program architecture. This architecture is inherently inefficient for analyzing streaming data. On a single processor, patterns are extracted and recognized sequentially. This is because pattern extraction and recognition are implemented based on common, simple instruction sets (such as RISC or CISC instruction sets), resulting in long execution sequences for each pattern in the signal sample. Complex patterns in the input signal require the use of more complex signal processing algorithms, which in turn requires higher clock frequencies for the processor in systems that require real-time responses from the pattern recognition engine. This is not feasible in power-constrained devices (such as portable electronic devices, wearable devices, etc.). In addition, due to the sequential execution paradigm, the latency and power consumption of pattern recognition operations on microprocessors increase significantly with the complexity of the pattern and the library. The presence of noise in the input signal further increases the complexity of the analysis and adversely affects performance and efficiency.

[0007] Data fusion is a non-native operation for microprocessors. This means that before input signals or data streams can be fused, their information content must first be extracted and then combined with corresponding content from other streams. Therefore, in microprocessor implementations, each input signal / data source for fusion is processed separately by a separate pattern recognition pipeline, and the different pattern recognition results are then combined by a rule-based framework. This approach requires multiple calls to the pattern recognition infrastructure for each input signal or data stream, resulting in increased power consumption. Furthermore, the limitations of load-store architecture microprocessors and digital signal processors (DSPs) used for pattern recognition mean that as pattern complexity increases, the power consumption and latency costs of recognizing these patterns also increase. While latency costs can be reduced by increasing clock frequency, this comes at the expense of further increased power consumption. Similarly, the quality of fusion is limited by the complexity of the processing and ASR performed on the input signals, the number of signals being fused, and the computational power of the microprocessor or DSP. The sequential nature of processing reduces the throughput of fusion-based ASR, and therefore, as the complexity of the signal patterns increases, the number of input signals that can be fused using a microprocessor or DSP decreases.

[0008] Artificial neural networks in the form of deep neural networks (DNNs) have been proposed as an alternative to microprocessor implementations. DNNs form the basis of a large number of machine learning applications; starting with speech and image recognition, the number of applications utilizing DNNs has grown exponentially, but these applications have inherent limitations, primarily in processing large amounts of data or adapting quickly to changing environments.

[0009] Initially, hardware deep network accelerators have been implemented on standard synchronous digital logic. The high-level parallelism of neural networks cannot be replicated in the (typically) serial and time-division multiplexed processing of digital systems; instead, the computational primitives of hardware DNN emulators implemented as analog compute nodes (where memory and processing elements are co-located) offer significant improvements in speed, size, and power consumption.

[0010] In biological neural network models, individual neurons communicate asynchronously and through sparse events, or spikes. In such event-based spiking neural networks (SNNs), only neurons that change state generate spikes, potentially triggering signal processing in subsequent layers, thus conserving computational resources. SNNs are a promising approach to implementing automatic sequence recognition (ASR) for many different applications.

[0011] SNNs encode information in the form of one or more precisely timed (voltage) pulses rather than integer or real-valued vectors. Computations for inference (i.e., inferring the presence of a feature in the input signal) are efficiently performed in the analog and time domains. Therefore, SNNs are typically implemented in hardware as fully customized mixed-signal integrated circuits. In addition to having a smaller network size, this enables them to perform inference functions with energy consumption orders of magnitude lower than their artificial neural network counterparts.

[0012] SNNs consist of a network of spiking neurons interconnected by synapses, which indicate the strength of the connections between spiking neurons. This strength is represented as a weight that mitigates the influence of the output of the presynaptic neuron on the input of the postsynaptic neuron. Typically, these weights are set during a training process that involves exposing the network to a large amount of labeled input data and then gradually adjusting the weights of the synapses until the desired network output is achieved.

[0013] Relying on the principle that the amplitude, time, and frequency domain features in the input signal can be encoded into a unique spatially and temporally encoded pulse sequence, SNN can be directly applied to pattern recognition and sensor data fusion.

[0014] The generation of these sequences relies on the use of one or more ensembles of spiking neurons, which are cooperative groups of neurons. Each ensemble performs a specific signal processing function, i.e., feature encoding, conditioning, filtering, data fusion, classification, for example. Each ensemble consists of one or more interconnected layers of spiking neurons, with the connectivity between and within these layers following a specific topology. The size of each ensemble (the number of neurons), its connectivity (topology and number of synapses), and its configuration (weights and number of layers) depend on the characteristics of the input signal, such as the dynamic range, bandwidth, time scale, or complexity of the features in the input signal. Therefore, the ensemble used in the case of a speech pattern matching system may be different from the ensemble used in a handwriting recognition system.

[0015] In general, as the complexity of the features to be identified in the input signal increases, the size of the ensemble required to process them also increases. Spiking neural network hardware can utilize configurable arrays of spiking neurons and synapses, which are connected using a programmable interconnect structure, facilitating the implementation of any arbitrary connection topology. However, in order to achieve larger ensembles, the underlying SNN hardware must have at least the required number of neurons and synapses.

[0016] While the fundamental operations required for SNNs are implemented very efficiently using analog electronic circuits, the inevitable variations in microelectronic circuits due to the fabrication process can cause distortions in their functional characteristics, such as resistance, capacitance, gain, and time response. Particularly at smaller fabrication geometries and lower operating currents, these circuits are increasingly susceptible to quantum effects and external noise, effectively degrading the signal-to-noise ratio and limiting processing performance. These undesirable effects are exacerbated in large arrays where driver, bias, and encoder / decoder circuits are shared by a larger number of devices over longer interconnects. Summary of the Invention

[0017] To address the shortcomings of the prior art discussed above, according to a first aspect of the present disclosure, a spiking neural network for classifying input signals is provided. The spiking neural network includes a plurality of spiking neurons and a plurality of synaptic elements interconnecting the spiking neurons to form a network, wherein each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, and the synaptic element is configurable to adjust the weight applied by each synaptic element. Each of the spiking neurons is adapted to receive one or more synaptic output signals from one or more synaptic elements and generate a spatiotemporal spike train output signal in response to the received one or more synaptic output signals. The network is divided into a plurality of sub-networks, wherein each sub-network includes a subset of spiking neurons connected to receive synaptic output signals from a subset of synaptic elements. The sub-network is adapted to generate a sub-network output pattern signal in response to a sub-network input pattern signal applied to the sub-network. Furthermore, each sub-network forms part of one or more cores in a core array, each core comprising a programmable network of spiking neurons implemented in hardware or a combination of hardware and software, and communication between the cores in the core array is arranged via a programmable interconnect structure.

[0018] In an embodiment, the programmable interconnect structure includes a switchable matrix.

[0019] In an embodiment, the switchable matrix includes a plurality of routers adapted to route a plurality of output signals from a first core in the core array to a plurality of inputs of a second core in the core array.

[0020] In an embodiment, a programmable interconnect structure forms a packet-switched network between cores in a core array. In an embodiment, the programmable interconnect structure uses address event representation. In an embodiment, the programmable interconnect structure uses synchronous or asynchronous communication. In an embodiment, the core array is implemented in an integrated circuit, and the programmable interconnect structure includes an on-chip network.

[0021] In an embodiment, the network on chip is configurable in real time.

[0022] In an embodiment, a learning rule, weight storage mechanism, or communication protocol for a synaptic element is applied heterogeneously to a single core of a core array. In an embodiment, a learning rule, weight storage mechanism, or communication protocol for a synaptic element is applied heterogeneously to multiple cores in a core array. In an embodiment, a learning rule block is used to implement the learning rule configuration for one or more cores in a core array. In an embodiment, cores using the same learning rule use a common learning rule block that implements the learning rule.

[0023] In an embodiment, the distribution of learning rules within each core and / or across cores in a core array is dynamically configurable at runtime.

[0024] In an embodiment, one of the sub-networks is part of a classifier for classifying an input signal of the sub-network.

[0025] In an embodiment, one of the sub-networks is part of a set of classifiers for classifying an input signal of said sub-network.In an embodiment, the weights of the synaptic elements are configured using stochastic weight updates.

[0026] In an embodiment, the weight of a synaptic element is bound by a binding value, wherein the binding value is a random value.

[0027] According to a second aspect of the present disclosure, an integrated circuit is disclosed, which includes a spiking neural network implemented in the core array of the first aspect of the present disclosure.

[0028] According to a third aspect of the present disclosure, a method for partitioning and mapping a spiking neural network onto a core array is disclosed. Here, the spiking neural network includes a plurality of spiking neurons, and a plurality of synaptic elements interconnecting the spiking neurons to form a network, wherein each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, the synaptic element being configurable to adjust the weight applied by each synaptic element, and wherein each of the spiking neurons is adapted to receive one or more synaptic output signals from one or more synaptic elements, and to generate a spatiotemporal spike train output signal in response to the received one or more synaptic output signals. Furthermore, the core array includes a plurality of cores, wherein each core is comprised of a programmable network of spiking neurons implemented in hardware or a combination of hardware and software, and wherein communication between the cores in the core array is arranged via a programmable interconnect structure. Here, the method includes partitioning the network into a plurality of subnetworks, wherein each subnetwork includes a subset of spiking neurons connected to receive synaptic output signals from a subset of synaptic elements. The sub-networks are adapted to generate sub-network output pattern signals from a subset of spiking neurons in response to sub-network input pattern signals applied to a subset of synaptic elements, wherein each sub-network is mapped onto one or more cores.

[0029] In an embodiment, partitioning a spiking neural network into subnetworks implemented in one or more cores is determined by a mapping method. The mapping method includes constraint-driven partitioning. The constraints are performance indicators of functions linked to each corresponding subnetwork.

[0030] According to a fourth aspect of the present disclosure, a spiking neural network is disclosed. The spiking neural network includes a plurality of spiking neurons implemented in hardware or a combination of hardware and software, and a plurality of synaptic elements interconnecting the spiking neurons to form a network, wherein each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, the synaptic element being configurable to adjust the weight applied by each synaptic element, and wherein each of the spiking neurons is adapted to receive one or more synaptic output signals from one or more synaptic elements and generate a spatiotemporal pulse train output signal in response to the received one or more synaptic output signals. In addition, learning rules, weight storage mechanisms, and / or communication protocols are heterogeneously applied to neurons and / or synaptic elements in the spiking neural network.

[0031] According to a fifth aspect of the present disclosure, a spiking neural network is disclosed, comprising a spiking neuron and a synaptic element connected to the spiking neuron. Here, the synaptic element comprises a first and a second receptor adapted to receive a synaptic input signal, wherein the first and the second receptors generate a first and a second receptor signal, respectively, based on the synaptic input signal. The synaptic element applies a weight to the first receptor signal to generate a synaptic output signal, and the synaptic element may be configured to adjust the weight applied by the synaptic element based at least on the second receptor signal. The spiking neuron is adapted to receive a synaptic output signal from the synaptic element and to generate a spatiotemporal pulse train output signal in response to at least the received synaptic output signal.

[0032] In an embodiment, the neuron emits a control signal, wherein the control signal, together with the second receptor signal, modulates a weight applied by the synaptic element.

[0033] In an embodiment, the control signal is a reverse propagating signal.

[0034] In an embodiment, the neuron comprises dendrites, an axon and a soma, wherein the control signal originates from the dendrites and / or axon and / or soma of the neuron.

[0035] In an embodiment, the control signal comprises one or more pulses generated by an action potential in the neuron. In an embodiment, the decay time of the first receptor is faster than the decay time of the second receptor. In an embodiment, the first receptor generates a current source or sink for the spiking neuron.

[0036] In an embodiment, the first receptor comprises a low-pass filter. In an embodiment, the second receptor forms a voltage-gated receptor. In an embodiment, the second receptor comprises a low-pass filter, a band-pass filter, a high-pass filter, and / or an amplifier. In an embodiment, the first receptor is an AMPA receptor, or a GABA receptor, or an NMDA receptor.

[0037] According to a sixth aspect of the present disclosure, a method for adjusting the weight of a synaptic element in a spiking neural network is disclosed, the spiking neural network comprising a spiking neuron connected to the synaptic element. The synaptic element comprises a first and a second receptor adapted to receive a synaptic input signal, wherein the first and second receptors receive the synaptic input signal and generate a first and a second receptor signal, respectively, based on the synaptic input signal. The synaptic element applies a weight to the first receptor signal to generate a synaptic output signal. Based at least on the second receptor signal, the weight of the synaptic element is adjusted, and the spiking neuron receives the synaptic output signal from the synaptic element and generates a spatiotemporal pulse train output signal in response to at least the received synaptic output signal.

[0038] In an embodiment, the neuron emits a control signal, wherein the control signal, together with the second receptor signal, modulates a weight applied by the synaptic element.

[0039] In an embodiment, the control signal is a reverse propagating signal.

[0040] In an embodiment, the neuron comprises dendrites, an axon and a soma, wherein the control signal originates from the dendrites and / or axon and / or soma of the neuron.

[0041] In an embodiment, the control signal comprises one or more pulses generated by an action potential in the neuron. In an embodiment, the decay time of the first receptor is faster than the decay time of the second receptor. In an embodiment, the first receptor generates a current source or sink for the spiking neuron.

[0042] In an embodiment, the first receptor comprises a low-pass filter. In an embodiment, the second receptor forms a voltage-gated receptor. In an embodiment, the second receptor comprises a low-pass filter, a band-pass filter, a high-pass filter, and / or an amplifier. In an embodiment, the first receptor is an AMPA receptor, or a GABA receptor, or an NMDA receptor.

[0043] According to a seventh aspect of the present disclosure, an integrated circuit comprising the pulse neural network of the fifth aspect of the present disclosure is disclosed.

[0044] According to an eighth aspect of the present disclosure, a method for configuring a spiking neural network to reduce the effects of noise in the spiking neural network is disclosed. The spiking neural network includes a plurality of spiking neurons implemented in hardware or a combination of hardware and software, and a plurality of synaptic elements that interconnect the spiking neurons to form a network. Each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, and the synaptic element can be configured to adjust the weight applied by each synaptic element. Each of the spiking neurons is adapted to receive one or more synaptic output signals from one or more synaptic elements and generate a spatiotemporal pulse train output signal in response to the received one or more synaptic output signals. The synaptic drive Γ of one of the spiking neurons i in the spiking neural networki is a time-dependent function that describes the total transfer function of all synaptic elements connected to the neuron. The method involves obtaining the synaptic drive Γ i The variance of each synaptic drive in is given by an expression that depends on the control parameters. i The variance of each synaptic drive in can be adjusted by adjusting the control parameter. Adjust the control parameter so that the synaptic drive Γ i The variance of each synaptic drive in is lower than the predetermined value, so that the synaptic drive Γ of each neuron in the spiking neural network is i The synaptic drive Γ is minimized at its noise impact i The equilibrium point Γ i * Bind around.

[0045] In an embodiment, the synaptic drive Γ of a spiking neuron i in a spiking neural network is i It can be written in vector form for all neurons in the spiking neural network as Γ=(Γ1,…,Γ n ) T , where n is the number of neurons in the spiking neural network, and where Γ satisfies the following formula:

[0046] dΓ=N(Γ(t))dt+σ(Γ(t))dω(t),

[0047] where N(Γ(t)) is the nominal matrix part and σ(Γ) is the state-dependent noise matrix of the Gaussian white noise process dω(t), where ω is the Wiener process describing the noise in the spiking neural network, where the expression for dΓ can be rewritten in terms of the variance-covariance matrix K(t) of Γ(t) that satisfies the following continuous-time algebraic Lyapunov equation:

[0048] N(Γ(t))K(t)+K(t)[N(Γ(t))] T +σ(Γ(t))[σ(Γ(t))] T =0,

[0049] Where, the synaptic drive Γ is obtained i The step of obtaining an expression for the variance of the drive of each synapse in t includes determining the diagonal values of the variance-covariance matrix K(t).

[0050] In an embodiment, the synaptic driver Γ i The equilibrium point Γ i * can be written in vector form for all neurons in a spiking neural network as The noise matrix σ is zero, that is, σ(Γ * )=0.

[0051] In an embodiment, the control parameters are adjusted with the aid of computer simulation.

[0052] According to a ninth aspect of the present disclosure, a spiking neural network is disclosed, comprising a plurality of spiking neurons implemented in hardware or a combination of hardware and software, and a plurality of synaptic elements interconnecting the spiking neurons to form a network. Each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, and the synaptic element can be configured to adjust the weight applied by each synaptic element. Each of the spiking neurons is adapted to receive one or more synaptic output signals from one or more synaptic elements and generate a spatiotemporal pulse train output signal in response to the received one or more synaptic output signals. The synaptic drive Γ of one of the spiking neurons i in the spiking neural network is i is a time-dependent function that describes the total transfer function of all synaptic elements connected to the neuron. i The variance of each synaptic drive in is lower than a predetermined value, so that the synaptic drive Γ of each neuron in the spiking neural network is i The synaptic drive Γ is minimized by noise i The equilibrium point Γ i * Bind around. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Embodiments will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference numerals indicate corresponding parts, and in which:

[0054] Figure 1 shows an exemplary neural network composed of neurons and synaptic elements;

[0055] Figure 2 schematically illustrates a spiking neural network within a microcontroller integrated circuit;

[0056] Figure 3 shows the high-level architecture of a learning system with an array of neuromorphic cores;

[0057] Figure 4 A graphical representation showing the enhancement algorithm within a single core;

[0058] Figure 5 A graphical representation showing the combination of multiple collective systems within a single core;

[0059] Figure 6 A graphical representation showing combining multiple collective systems on multiple cores in a multi-core implementation;

[0060] Figure 7A A conceptual diagram showing the structure of a synapse;

[0061] Figure 7B A conceptual diagram showing the structure of a neural synapse;

[0062] Figure 8 Shows the net activity of the unbound network; and

[0063] Figure 9 Shows the net activity of the bonded network.

[0064] The drawings are for illustrative purposes only and are not intended to limit the scope or protection provided by the claims. DETAILED DESCRIPTION

[0065] Hereinafter, some embodiments will be described in more detail. However, it should be understood that these embodiments cannot be interpreted as limiting the scope of protection of the present disclosure.

[0066] Figure 1 is a simplified diagram of a neural network 100. Neurons 1 are connected to each other via synaptic elements 2. In order not to clutter the drawing, only a small number of neurons and synaptic elements are shown (and only some have reference numerals attached to them). Figure 1 The connection topology shown (the manner in which synaptic elements 2 and neurons 1 are connected to each other) is merely an example, and many other topologies can be employed. Each synaptic element 2 can send a signal to the input of a neuron 1, and each neuron 1 that receives a signal can process the signal and then generate an output, which is sent to other neurons 1 via another synaptic element 2. Each synaptic element 2 has a certain weight assigned to it, which is applied to each synaptic input signal received and transmitted by the synaptic element to produce a weighted synaptic output signal. Thus, the weight of a synaptic element is a measure of the type of causal relationship between two neurons 1 connected by a synaptic element 2. The relationship can be causal (positive weight), anti-causal (negative weight), or non-existent (zero weight).

[0067] Neurons 1 and synaptic elements 2 can be implemented in hardware, for example using analog circuit elements or digital hardwired logic circuits. They can also be implemented partially in hardware, partially in software, or entirely in software. Preferably, they are implemented in hardware, or at least partially in hardware, i.e., hardware circuits or elements are used to perform the functions of individual neurons, rather than using a large processor to execute software, where the software mimics individual neurons. These (partial) hardware implementations can enable faster processing, for example, faster pattern recognition and event-driven processing, where blocks of neurons and synaptic elements are activated only when needed.

[0068] The neural network 100 can be a spiking neural network. Then, neuron 1 is a spiking neuron that generates a neuronal output signal in the form of one or more pulses or neuron-generated events. The spiking neuron 1 can be configured to trigger (i.e., generate an output pulse) only when the membrane potential (e.g., energy potential, or voltage or current level) within the neuron reaches a predetermined threshold. The membrane potential of the spiking neuron changes due to the input signal received, that is, the synaptic output signal received by the neuron from the synaptic element is accumulated, integrated, or otherwise processed to change the membrane potential. When the weight of the synaptic element 2 is positive, the synaptic output signal received from the synaptic element excites the spiking neuron 1 receiving the signal, thereby increasing its membrane potential. When the weight of the synaptic element 2 is negative, the synaptic output signal received from the synaptic element inhibits the synaptic neuron 1 receiving the signal, thereby reducing its membrane potential. When the weight of the synaptic element 2 is zero, the synaptic output signal received from the synaptic element has no effect on the synaptic neuron 1 receiving the signal.

[0069] When the membrane potential of a spiking neuron 1 reaches a threshold, the neuron fires, generating a pulse upon firing, and the membrane potential decreases as a result of the firing. If the membrane potential subsequently reaches the threshold again, the neuron will fire again, generating a second pulse. Thus, each spiking neuron 1 is configured to generate one or more pulses in response to an input signal received from a connected synaptic element 2, the pulses forming a spatiotemporal pulse train. Since a spiking neuron 1 fires only when its membrane potential reaches a predetermined threshold, the encoding and processing of temporal information is incorporated into the neural network 100. In this way, spatiotemporal pulse trains are generated in the spiking neural network 100, which are time series of pulses generated by the spiking neurons 1 of the network 100.

[0070] The temporal properties of a spike train encode the amplitude and frequency characteristics of the input signal. These properties include: the latency between the onset of a stimulus (e.g., an input signal from a synaptic element) and the generation of a spike at the neuron's output; the latency between consecutive spikes from the same neuron; and the number of spikes the neuron fires during the duration of the applied input stimulus.

[0071] Synaptic elements 2 can be configurable, such that, for example, their respective weights can be changed by training neural network 100. Neurons 1 can be configured in a manner that responds to signals from synaptic elements. For example, in the case of a spiking neural network, neurons 1 can be configured in a manner that increases or decreases certain signals: membrane potential, the time it takes for the membrane potential to naturally decay to the resting potential, the value of the resting potential, or the threshold that triggers a spike in neuron 1. The configuration of neurons 1 can, for example, remain constant during training, or be variable and set when neural network 100 is trained on a specific training set.

[0072] The input signal 11 is, for example, a plurality of different sampled input signals or a temporal and spatial pulse sequence. The input can be the analog-to-digital converted value of the signal sample, or, for example, the digital value of the sample in the case of an analog or digital integrator, or the analog value of the sample in the case of an analog integrator.

[0073] The output signal 12 of the neural network 100 is, for example, a spatiotemporal pulse train, which can be read out from the output neuron 1 and further classified and converted by an output conversion stage into a set of digital values corresponding to the output code type selected by the user.

[0074] Figure 2 An embodiment of a high-level architecture of a microcontroller integrated circuit 100 is shown that includes a spiking neural network 110. In this case, the microcontroller 110 is an economical means of data collection, sensing, pattern recognition, and actuation of physical signals.

[0075] Spiking neural network 110 is connected to one or more streaming input data ports 111, which provide input to spiking neural network 110, which is converted into a spatiotemporal spike train. Spiking neural network 110 is connected to one or more output ports 112. A memory-mapped control and configuration interface 113 controls configuration parameters of spiking neural network 110, such as synaptic weights and / or neuron configurations, and may further include peripheral devices (e.g., A / D converters, D / A converters, band gaps, PLLs) and circuits for controlling and regulating neurons, synapses, and plasticity (learning) circuits. Interface 113 reads memory device 102, where settings for spiking neural network 110 are stored, and sends signals to spiking neural network 110 to configure the hardware accordingly. Interface 113 can send analog signals to spiking neural network 110. Settings may include configuration parameters for each neuron 1 or synaptic element 2 of spiking neural network 110, or the network topology.

[0076] Each neuron 1 can have a set of configuration parameters that control the precise triggering behavior of that neuron 1. For example, a neuron can be designed to have a trigger threshold, which represents a threshold of voltage, energy, or other variable that accumulates in the neuron as a result of receiving input, and when the accumulated variable meets or exceeds the trigger threshold, the neuron generates an output peak (e.g., a voltage, current, or energy peak). The neuron can implement an integration function that integrates the neuron's input to determine the regulation of the accumulated variable. In addition, the neuron can also be designed with: (a) a leakage rate, which represents the rate at which the accumulated variable in the neuron decays over time; (b) a resting value of the accumulated variable, which represents the value to which the accumulated variable will decay over time in the absence of any input signal to the neuron; (c) an integration time constant, which represents the time over which the input signal is integrated to determine any increase in the accumulated variable in the neuron; (d) a refractory level, which represents the value of the accumulated variable in the neuron immediately after the neuron is triggered; and (e) a refractory period, which represents the time period required for the accumulated variable in the neuron to rise to the resting value after the neuron is triggered. These parameters can be predetermined and / or configurable and / or adjustable for each neuron. By adjusting, for example, the neuron's firing threshold, leak rate, integration time constant, and refractory period, as well as the neuron's refractory period to match the energy content of a key input signal characteristic, when neuron 1 is stimulated by an input signal containing that characteristic, it will generate one or more precisely timed pulses.

[0077] The configuration parameters of synaptic element 2 include the weight and gain of synaptic element 2. The weight of synaptic element 2 is generally used to regulate synaptic element 2, while the gain of synaptic element 2 is used for signal amplification in hardware and is generally related to the implementation of a low-pass filter. Generally, the gain is fixed when network 110 is initialized, while the weight can change based on the evolution / training of spiking neural network 110.

[0078] The microcontroller integrated circuit 100 further includes a microprocessor core 101 to perform computations and control of the integrated circuit 100. For example, the microprocessor core 101 may oversee communications between the memory mapped control and configuration interface 113 and the memory device 102.

[0079] Memory device 102 can be any computer-readable storage medium. Memory device 102 can be a non-transitory storage medium. Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media on which information can be permanently stored (e.g., a read-only memory device within a computer, such as a CD-ROM disk readable by a CD-ROM drive, a ROM chip, or any type of solid-state non-volatile semiconductor memory); and (ii) writable storage media on which variable information can be stored, such as a hard drive or any type of solid-state random access semiconductor memory, flash memory.

[0080] An external bus 104 is connected to one or more sensors or other data sources 103. The microcontroller integrated circuit 100 may also be directly attached to a sensor 105. The sensor may first pass through an analog-to-digital converter 106. One or more serial input / output ports 107 and general-purpose input / output ports 108 may be present on the microcontroller integrated circuit 100. Direct access of external devices to the memory of the microcontroller integrated circuit 100 may be arranged through direct memory access (DMA) 109.

[0081] Figure 3 A high-level architecture for a learning system is shown having a plurality of neurosynaptic cores 210 arranged in a core array 200. Each core 210 comprises a network of neurons 1 implemented in hardware, with the neurons interconnected by synaptic elements 2. A single core 210 can implement a complete spiking neural network, or a portion of a spiking neural network forming a separate sub-network. In this way, a large spiking neural network can be divided into multiple smaller sub-networks, each implemented in one of the cores 210 of the array 200. In one embodiment, a core 210 can implement Figure 2 A spiking neural network 110 is shown in FIG. 1 with associated input data ports 111 , output ports 112 and / or control and configuration interface 113 .

[0082] By partitioning the large spiking neural network 110 into smaller sub-networks and implementing each sub-network on one or more cores 210, each core having its own essential circuitry, some of the non-idealities in the circuitry are eliminated to operate at smaller processing geometries and at lower operating currents, especially for large arrays. Thus, the core-based implementation reduces the impact of physical non-idealities.

[0083] The sub-networks or neuron sets forming a cooperative group may, for example, form a classifier, an ensemble of classifiers, a neuron set handling data transformation, feature encoding or only classification, and the like.

[0084] In such cases, a large collective network is partitioned and mapped onto an array of cores, each containing a programmable network of spiking neurons. Thus, each core implements a single collective, multiple small collectives (related to the number of neurons and synapses in the core), or, in the case of a large collective, only a portion of a single collective, with the remaining portions implemented on other cores in the array. The method by which the collective is partitioned and mapped onto the cores is determined by the mapping method. The mapping method can include constraint-driven partitioning. The constraint can be a performance metric of the functionality linked to each corresponding sub-network. The performance metric can depend on power area constraints, memory structure, memory access, time constants, skew, technology limitations, resilience, acceptable mismatch levels, and network or physical artifacts.

[0085] The periphery of the array 200 includes rows of synaptic circuits that mimic the action of the soma and axon hillock of a biological neuron. In addition, each neurosynaptic core 210 in the array 200 has a local router 202 that communicates with the routers 202 of other cores 210 within a dedicated real-time reconfigurable network-on-chip.

[0086] Local routers 202 and their connections 201 form a programmable interconnect fabric between cores 210 of core array 200. Cores 210 are connected via a switchable matrix. Different cores 210 of core array 200 are thus connected via the programmable interconnect fabric. Specifically, different parts of the spiking neural network implemented on different cores 210 of core array 200 are interconnected via the programmable interconnect fabric. This allows quantum effects and external noise to act only on each core individually, rather than on the entire network. Consequently, these effects are mitigated.

[0087] The spiking neural network 110 implemented on the core array 200 can have high modularity in the sense that the spiking neural network 110 has dense connections between neurons within a core 210 but sparse connections between different cores 210. In this way, noise and quantum effects between cores can be reduced even further while still allowing the sub-networks to increase, for example, classification accuracy by allowing a high degree of complexity.

[0088] The programmable interconnect fabric can form a packet-switched network between cores 210 in core array 200. For example, local routers 202 can group data into packets and then send them via connections 201. These connections 201 can form a digital network. A packet can consist of a header and a payload. The data in the header is used by local routers 202 to direct the packet to its destination core 210, where the payload within the packet is extracted and used. The data can, for example, be the output of one of the subnetworks of a spiking neural network partitioned and implemented on one or more cores 210 of core array 200. Data can also be input from a sensor or another external device.

[0089] The programmable interconnect fabric can also use address event representation, where the addresses of the neurons to be connected are sent to the different cores.

[0090] Furthermore, synchronous or asynchronous communication may be used. An example of synchronous communication is any clock-based communication, while an example of asynchronous communication is e.g. a handshake protocol.

[0091] The cores in the core array may form a network-on-chip on the microcontroller integrated circuit 100. The network-on-chip improves the scalability and power efficiency of the microcontroller integrated circuit 100.

[0092] The topology of the on-chip network is selected based on the system's parameters, such as a mesh, torus, tree, ring, or star. The routing algorithm used depends on the topology and characteristics of the network 110. The complexity of the routing algorithm can be increased by, for example, considering multiple shortest paths to the destination and then randomly selecting one of these paths for each migration (resulting in better network load). Additional efficiency can be achieved by using heuristics and information about the network load at any given time. Other types of routing methods exist, including static routing tables or source-based routing.

[0093] The network on chip can be reconfigurable in real time or statically defined during the production phase. When the network on chip is reconfigurable in real time, the configuration of the cores 210 in the core array 200 and their interconnection structure can be changed. For example, such changes can be made based on changes in the inputs or outputs of the microcontroller integrated circuit, different requirements for classification accuracy or stability, network development based on its learning rules, and changes in communication protocols.

[0094] The present invention contemplates that the neurosynaptic core 210 can apply uniform learning rules, weight storage types, and / or communication protocols to the synaptic matrix. In other words, the same learning rules, weight storage types, and / or communication protocols can be set within a core.

[0095] The entire spiking neural network 110 can be implemented as a single entity within one core 210 (e.g., as a cross-section of neurons 1 and synapses 2, with all feedback connections in place to implement any recurrent neural network structure, or a simple feed-forward network without any feedback signals). Alternatively, the entire spiking neural network 110 can be distributed across multiple cores 210, with each core 210 implementing a specific layer or portion of a layer, for example, in the context of a deep neural network. The decision on how to completely split the network is entirely based on the application case (e.g., radar, lidar, imaging, ultrasound, biopotential sensing).

[0096] In an embodiment, all neurosynaptic cores 210 may apply the same learning rules, weight storage type, and / or communication protocol to each of their synaptic matrices.

[0097] In an embodiment, the neurosynaptic core 210 may apply different learning rules, weight storage types, and / or communication protocols to each of their synaptic matrices.

[0098] In an embodiment, the entire spiking neural network 110 synaptic array may be organized into a single core 210 implementing heterogeneous learning rules depending on the optimal performance-power-area tradeoff.

[0099] In another embodiment, different regions of the synaptic matrix within core 210 can be configured with the same learning rules, which can be achieved by a common learning rule block driven by the same configuration registers. The size of this region of the synaptic matrix within core 210 can be configured at design time to create dedicated circuits, or dynamically configured at runtime, where the synaptic matrix within core 210 will have heterogeneous clusters of synaptic circuits, each cluster implementing a different learning rule. This heterogeneous clustering may require a special mapping or synthesis algorithm to map each neuronal unit to a cluster of the synaptic matrix determined within core 210 based on the applied learning rule.

[0100] The learning rules block may be implemented for each synaptic element, each synaptic element group, or each core 210 of the core array 200. The learning rules block may be composed of circuitry implemented in the configuration interface 113, for example.

[0101] In another embodiment, different groups of one or more cores 210 within the core array 200 can be configured with the same learning rules, which can be achieved by a common learning rule block driven by the same configuration registers. The size of the group of cores 210 within the core array 200 can be configured at design time to create a dedicated group of cores 210, or dynamically configured at runtime, where the core array 200 will have a heterogeneous cluster of cores 210, each cluster implementing a different learning rule. This heterogeneous clustering may also require a special mapping or synthesis algorithm to map each neuron unit to a specific cluster of cores 210 based on the applied learning rule.

[0102] Different / heterogeneous learning rules may also be implemented within a single core 210 and not just across cores 210 .

[0103] Because different groups of cores 210 in core array 200, as well as different regions of the synaptic matrix within cores 210, can implement different learning rules, the design is more flexible. Furthermore, by applying different learning rules, specific inputs will have different effects on specific regions of core array 200. In this way, different regions implementing different learning rules can be optimized, resulting in better operation of the entire network 110. Finally, different learning rules may work better for different input signals, allowing the network to be customized based on which parts of the network require the learning rules.

[0104] Furthermore, in an embodiment, each region of the synaptic matrix within a core 210 or each region of a group of one or more cores 210 within the core array 200 may also implement a different weight storage mechanism, such as digital memory, capacitive storage, or a bi-directional-stable mechanism, where each region will have different power requirements.

[0105] A group of cores 210 within core array 200 can implement different communication protocols. This allows for greater design flexibility. Thus, cores 210 of core array 200 allow for a practical and flexible implementation of spiking neural network 110 in hardware, particularly because they allow for the application of the same or different learning rules, weight storage types, and / or communication protocols to each of their synaptic matrices.

[0106] The brain's cognitive abilities arise from joint forms of computational or collective neuronal activity, i.e., collaborative groups of neurons (subnetworks or ensembles) produce functional neural states that trigger learning and enhance integrated perceptual abilities and compensate for impaired sensory modalities, where the joint activity of groups of neurons overcomes the unreliable stochastic nature of individual neuron firing.

[0107] Subsequently, numerous architectures can be used that attempt to reflect aspects of biology: multiple (parallel) classifiers operating on the same stimulus or parts or features of the stimulus to remedy various machine learning complexities such as feature selection, confidence estimation, missing features, incremental learning, error correction, etc. Multiple classifiers can be used to partition the feature space of the input signal. Ensembles of similarly configured neural networks can be used to improve classification performance. Through boosting procedures, powerful classifiers (with low error on binary classification problems) can be constructed from an ensemble of classifiers; the error of any of these ensemble classifiers is only slightly better than random guessing.

[0108] Thus, based on (i) the selection of training data for individual classifiers, (ii) specific procedures for generating ensemble members, and / or (iii) combination rules for obtaining ensemble decisions, a variety of ensemble systems can be designed, including, for example, bagging, random forests (ensembles of decision trees), composite classifier systems, mixtures of experts (MoE), stacked induction, consensus aggregation, combinations of multiple classifiers, dynamic classifier selection, classifier fusions, neural network committees, and classifier ensembles.

[0109] Figure 4 A graphical representation of the boosting algorithm within a single core 210 of the core array 200 is shown. Figure 4 , a plurality of classifiers 300 are shown implemented within a single core 210 of a core array 200 . The classifiers 300 form a collection of classifiers 300 .

[0110] Ensemble 300 of classifiers is an example of a subnetwork of spiking neural network 110 , which may be implemented on a single core 210 of core array 200 .

[0111] Assume that a classifier 300 has a set of output neurons (one for each class), each of which triggers an event (spike) according to its firing probability distribution. A particular classifier 300 may include different layers 301, 302, 303 of neurons 1 (or neurons 1 and synaptic elements 2) connected via synaptic elements 2. Each layer may have a different function; for example, layer 301 may perform data conversion, layer 302 may perform feature encoding, and layer 303 may perform classification. An output layer may also be present in each classifier 300. This output layer may be connected to a local router 202 of a particular core 210 of the core array 200. Using connections 201 between local routers 202, the output of a particular classifier 300 or a collection of classifiers 300 may be directed to other cores 210 in the core array 200, and in this way to other subnetworks of the spiking neural network 110.

[0112] Figure 5 A graphical representation of combining multiple ensemble classifier systems within a single core 210 of the core array 200 is shown.

[0113] First, a set 401 of classifiers 300 implemented using a boosting algorithm receives input 404 and then sends its output to a second set 402 implemented using a mixture of experts algorithm. The synaptic elements 410 between layers can be trained using triplet-based spike-timing-dependent plasticity (T-STDP) as a learning rule. When using STDP, if, on average, an input spike to neuron 1 tends to occur immediately before its output spike, that particular input is made stronger. If, on average, an input spike tends to occur immediately after its output spike, that particular input can be weakened by adjusting its weight. Thus, by increasing the weight of a particular synaptic element 2, inputs that are likely responsible for the postsynaptic neuron 1's firing are made more likely to contribute in the future, while inputs that are not responsible for the postsynaptic spike are made less likely to contribute in the future by decreasing the weight of that particular synaptic element 2. This STDP method is pair-based because it uses a pair of spikes. T-STDP differs from standard STDP in that it uses triplets.

[0114] Using a gating network 408, data partitioning is established between the experts during training, and the outputs are combined. The gating network 408 can serve as a so-called "golden reference" during training, defining the filter or transfer function used to aggregate the results of the different experts and acting as a teacher signal. The experts compete to learn the training pattern, and the gating network 408 coordinates the competition. The aggregation and combination system 409 aggregates and combines the outputs of all the different experts into a single output 406, and outputs the output 406 of the mixture-of-experts layer as input to the third set 403 of the classifier 300 implemented based on the boosting algorithm. The output 407 of the third set 403 can be output to the local router 202 of the core 210 and can be sent via the interconnect 201 to other cores 210 of the core array 200 or to the output port 112 of the spiking neural network 110.

[0115] Figure 6 A graphical representation showing combining multiple collective systems across multiple cores in a multi-core implementation.

[0116] First, in the first core 510A, the set 401 of classifiers 300 implemented based on the boosting algorithm receives input 404 and then sends its output to the second set 402, which is implemented based on the mixture of experts algorithm. The aggregation and combination system 409 of the second set 402 outputs its output to the first local router 502A of the first core 510A, which then sends the output to the second local router 502B of the second core 510B via the interconnects 501A, 501B. This data is then used as input to the third set 403 present on the second core 510B. Therefore, this system is different from Figure 5 The system shown in is that the spiking neural network 110 is partitioned in some way and mapped differently onto the core array 200. That is, in this embodiment, the set is divided into two different cores 510A, 510B; each with its own necessary circuitry.

[0117] A dynamic model is designed that represents the subsequent merging of classifier outputs, forcing a scheme for assigning each unique unlabeled pattern to the best-fitting classifier. Classifiers are defined as stochastic winner-take-all, where only a single neuron can spike for any data presented as input. A trainable combiner can determine which classifiers are accurate in which part of the feature space and can then be combined accordingly.

[0118] Without loss of generality, the equality of weak and strong probably approximately correct (PAC) learning models is a prerequisite for the boosting algorithm, i.e., different distributions are generated when training different subhypotheses. PAC learning is a mathematical analysis framework in computational learning theory in machine learning. Here, the learner receives samples and must select a generalization function from a class of possible functions. The goal is to select a function with high probability (the "likely" part) and low generalization error (the "approximately correct" part).

[0119] In contrast, adaptive mixture of experts achieves enhanced performance by assigning different subtasks to different learners.Most ensemble learning algorithms (eg, stacking) first train the base predictors and then try to tune the combined model.

[0120] Mixtures of experts and boosting are designed for different classes of problems, resulting in different advantages and disadvantages. For boosting, the distribution is primarily specified to enable individual classifiers to become experts in data patterns that the previous classifier was incorrect or disagreed with. However, with mixtures of experts, the data patterns are divided into essential but consistent subsets; the subsequent learning process required for each subset is not as complex as for the original data patterns.

[0121] Both use the same gating function to set the data partition between experts during training and combine the outputs. Gated networks are typically trained using the Expectation-Maximization (EM) algorithm on the original training data.

[0122] Each set or combination of sets may be implemented in one or more cores 210 .

[0123] exist Figure 7A In the embodiment shown in FIG, a hardware implementation of a synaptic matrix having synaptic elements 652A-D within core 210 is shown. Synaptic elements 652A-D each have a corresponding weight 653A-D attributed to them. The first weight 653A may be written as 2,1 , write w for the second weight 653B 1,1 , write w for the third weight 653C 2,2 , and write w for the fourth weight 653D 1,2 .

[0124] The input signal 650A to synaptic elements 652A, 652B can be written as X1, while the input signal 650B to synaptic elements 652C, 652D can be written as X2. This can be a voltage spike as part of a sequence of spatiotemporal spikes. In each synaptic element 652A, 652B, the input signal 650A is multiplied by the corresponding weight 653A, 653B. In each synaptic element 652C, 652D, the input signal 650B is multiplied by the corresponding weight 653C, 653D. The output signal 651A can then be written as ∑ i w 1,i X i , and the output signal 651B can be written as ∑ i w 2,i X i These output signals 651A, 651B may be sent to one or more neurons.

[0125] The weights 653A-D of the synaptic elements 652A-D can be set using one or more enable lines 654 and error lines 655. The enable lines 654 implement the weights 653A-D and set the correct values known to the system, while the error lines 655 update the weights 653A-D based on the perceived errors in the weight settings. These signals can be analog or digital.

[0126] In another embodiment, each of the synapse sets can be implemented as a combination of multiple (synaptic) receptors with dendrites (inputs) and axonal soma (outputs) of a biological neuron. Figure 7B Shown in.

[0127] Figure 7B One or more synaptic elements 602 are shown. A pulse 606 portion of a spatiotemporal pulse train enters the synaptic element 602. At the input of the computational element, three receptors are accessible: NMDA receptors (rNMDA) 607A provide activity-dependent modifications to the synaptic weight w, while AMPA receptors (rAMPA) 607B facilitate fast synaptic currents to drive the soma, and finally, GABA receptors (rGABA) 607C can facilitate fast or slower inhibitory synaptic currents to sink currents, depending on whether GABAA or GABAB receptors are used. The outputs of rAMPA 607A and / or rGABA 607C can serve as inputs to amplifier 608.

[0128] In this embodiment, rNMDA 607A and rAMPA 607B or rGABA 607C may also be present. Importantly, receptors 607A-C with different temporal components may be used. rAMPA 607B and rGABA 607C may be implemented as low-pass filters. Meanwhile, rNMDA 607A may be implemented as a voltage-gated receptor with both amplification and filtering capabilities, connected to the presynaptic circuitry of the implemented learning rule. This filtering may consist of bandpass, low-pass, and high-pass filters.

[0129] The output of amplifier 608 is sent to dendrite 601A, which forms part of the neuron connected to synaptic element 602. The output from all synaptic elements 602 is then integrated over time by integrator 609. The integrated signal is sent via receptor 610 to the neuron's axon soma 601B, which consists of an axon 603 and a soma 604. Signals from other clusters 605 and 606 of synaptic elements may also enter axon soma 601B at this time. A different integrator 611 may be placed in axon soma 601B. When axon 603 releases a pulse, generating an action potential, it leaves axon soma 601B and can be sent to other synaptic elements, for example, as a pulse in a spatiotemporal pulse train.

[0130] Receptors 612 and 613 receive the back-propagating signals from dendrite 601A and axon soma 601B, respectively, and add them to, for example, the synaptic element, performing a time derivative 614, and multiplying the resulting signal with the rNMDA 607A signal to modify amplifier 608 and thereby modify the weight of each synaptic element 602.

[0131] This increase in size allows for more states and transitions (and time constants), providing greater flexibility for the implementation of homeostatic plasticity and metaplastic interactions, i.e., providing mechanisms for adaptation to environmental changes and, therefore, providing a means to achieve and maintain robust neural computation.

[0132] In engineering terms, homeostatic plasticity is a form of back-propagating signal control that balances the effects of drifts in neuronal activity or internal connectivity due to altered external conditions or temperature changes.

[0133] Although this concept plays a crucial role in the hardware design of spiking neural networks 110 as it provides robustness to changes in operating conditions, the limited number of previous implementations is mainly due to the technological constraints involved in realizing long-term constants in silicon, thereby including steady-state plasticity.

[0134] The implemented synaptic element 602 allows for a variety of computational capabilities, such as a wide range of receptor time constants and conductance values g m, axonal and dendritic delays, and optimal synaptic transfer function.

[0135] Activity-dependent plasticity of synaptic transmission, which underlies learning and memory, has been primarily attributed to postsynaptic changes in the biophysical properties of receptors.

[0136] In order to regulate the flow of synaptic current, each receptor is referred to as a multi-(trans)conduction channel, which models nonlinear characteristics, such as the multi-binding synergy of neurotransmitters and receptors. The synaptic current mediated by NMDA receptor 607A is regulated by synaptic activity. Through the formation, stability, morphology and density of synaptic contacts, the rapid change of the number of receptors on the synaptic element 602 plays the role of a control mechanism for activity-related changes in synaptic efficacy. If the group (string) of dendritic pulses is sufficient to exceed the threshold, the axon 603 will generate an action potential; then the subsequent pulse is back-propagated into the dendrite 601A and subsequently generates a weight control together with the somatic cell 604 signal multiplied and added to the NMDA receptor 607A signal. This quasi-local steady-state framework provides a normalization function without destroying Hebbian plasticity, which can effectively keep the net synaptic activation constant by adjusting the postsynaptic strength in a graded manner.

[0137] Figure 7A and Figure 7B The two hardware implementations of are not necessarily used in a multi-core implementation of the present invention, but any spiking neural network 110 may be implemented in any hardware in this manner.

[0138] Each of the combined ensemble systems operates according to biologically plausible mechanisms, for example, a mixture of experts nonlinear gating mechanism based on spike-timing dependent plasticity (STDP), and the combination of STDP and activity-dependent changes in neuronal excitability induces Bayesian information processing (termed spike expectation maximization (SEM) network).

[0139] The proposed ensemble architecture can utilize a SEM network such as a single ensemble unit (classifier). The learning rule used in the SEM is the weight-dependent Hebbian triplet TSTDP rule. Assume that the classifier has a set of output neurons (one for each class), each of which triggers an event (spike) according to its firing probability distribution. The classifier follows a stochastic winner-takes-all (sWTA) mechanism, where only a single neuron 1 can fire for any presented input data.

[0140] Each synapse w if its output (postsynaptic neuron) fires ij Gather its input y i(presynaptic neuron) activation statistics. These statistics can be collected at runtime from samples of the augmented input distribution. Based on this data, each weight can be interpreted as the logarithmic product of two local virtual counters in each synapse, i.e., one representing the number of events and one representing the local learning rate η ij .

[0141] Therefore, we can derive the stochastic online learning rule triggered by the spike event:

[0142]

[0143] This is in synaptic w ij Approximately neuron z i The logarithm of the running average of the pulse time output.

[0144] The (random) variables used to set the random weight updates in the spiking neural network 110 are independent and identically distributed. Due to the randomness introduced in the transitions, the classifiers learn various representations of the target class. Subsequently, the classifier responses are combined into an aggregated, improved classifier. Furthermore, by adding uncertainty to the binding values of the synaptic weights, the level of activation of the classifier's decisions can be controlled.

[0145] Neuron 1 communicates in the spiking neural network 110 primarily through rapid all-or-nothing events (i.e., peaks in its membrane potential). The relative spike firing times within a population of neurons are assumed to be the information code, while synchronization between neuronal populations is assumed to be the signal that encodes and decodes the information. Therefore, the neuroelectric properties of excitatory and inhibitory neuronal networks can be expressed as follows:

[0146]

[0147] Here, Γ i (t) is the ith synaptic drive at time t, which essentially represents the synaptic strength and is defined in terms of the synaptic weight and gain function, λ i is the gain, which regulates the exponential decay of the synaptic voltage and models the spike-time-dependent scaling of the input conductance, function f i (…) represents the firing rate of the i-th neuron, w ji is a constant that specifies the coupling between the jth neuron and the ith neuron, and v r,i (t) represents the input voltage of the i-th neuron, such as a nerve impulse from a sensory receptor. The i-th neuron is the postsynaptic neuron, and the j-th neuron is the connection weight w ji The presynaptic neuron of the synaptic element can drive the synaptic element of neuron i to iConsidered as the total transfer function of all synaptic elements driving neuron i, it can be, for example, a function of the exponentially decaying values, weights and gains of the synaptic elements driving neuron i and so on.

[0148] However, neurons are noisy in both the generation of spikes and the transmission of synaptic signals. The noise comes from the quantitative release of neurotransmitters, the random opening of ion channels, and the coupling of background neural activity.

[0149] Subsequently, noise induces neuronal variation, increases the sensitivity of neurons to environmental stimuli, affects the synchronization between neurons, and promotes probabilistic inference.

[0150] We derive the uncertainty model as a Markov process, where the stochastic integral is interpreted as a stochastic differential equation system; therefore, we extend the above formula (1) with time delay and random input uncertainty:

[0151]

[0152] The first two terms on the right side of formula (2) are the deterministic drift part and the random diffusion part of the stochastic differential equation, in which we define as well as

[0153]

[0154] Here, ω(t)=[ω1(t),ω2(t),…,ω n (t)] T describes the noise in the input voltage and is represented by a Brownian motion, i.e., an n-dimensional standard Wiener process, and σ(Γ)=diag([σ1(Γ1),σ2(Γ2),…,σ n (Γ n )] T ) represents the state-dependent noise matrix of the Gaussian white noise process dω(t). The time-varying function δ ji (t) represents the continuous time-varying delay of the signal from the jth neuron to the ith neuron at time t, where δ ji (t)≥0,t≥0.

[0155] The following assumptions are made: Each entry of the matrices ψ and w of the mean dynamics is perturbed synchronously, such that (where v r,i (t)=0).

[0156] The assumption that synaptic input resembles triangular current pulses and can subsequently be modeled as Gaussian white noise has no significant effect on fast AMPA (decaying by about 2 ms) and GABAA currents (decaying by about 1 ms). ) is effective; however, for slower currents such as NMDA or GABAB currents (decay about ), this assumption may not hold. Therefore, they are modeled as colored noise, including non-zero synaptic time constants within the steady-state firing rate, requiring complex 3-D Fokker-Planck expressions.

[0157] While such approaches are feasible, a more efficient approach involves replacing the variance with a rescaled variance, i.e., noting that the synaptic time constant τ s The main effect is the magnitude of the variance. Therefore, from the ratio of the voltage variance of colored noise to that of white noise, the reduction factor of the synaptic time correlation constant can be derived in where τ m is the membrane time constant, and is the standard deviation of the synaptic current. Therefore, the Gaussian white noise theory is still valid, only σ red Substitute variance

[0158] The goal is to find the variance-covariance matrix of Γ(t). Formula 2 is a set of stochastic differential equations. From this, the variance-covariance matrix of Γ(t) is derived, which is essentially a system of linear ordinary differential equations with time-varying coefficients. To solve, a back-Euler discretization is performed, resulting in the continuous-time algebraic Lyapunov equation shown in Equation 5 below. These problems can be solved iteratively, and the solution is given in Equation 6.

[0159] The goal is to find the synaptic drive Γ for all neurons i i The expression for the variance of (t) is given by i How far the random values of (t) spread out from their mean. The variance of the synaptic drive is the expected squared deviation of the synaptic drive from its mean. By finding such an expression, spiking neural networks can be bounded. That is, the spread of synaptic drive values caused by noise in the spiking neural network can be constrained by adjusting the parameters that make up the variance expression so that the variance is small, and in particular, the variance is minimized in a particular hardware implementation.

[0160] The diagonal elements K of the variance-covariance matrix K(t) of Γ(t) i,i (t) are driven by synapses Γ i The variance of (t) is given by Γ(t). Therefore, solving the variance-covariance matrix K(t) of Γ(t) will provide the synaptic drive Γ of all neurons i. i (t) is the expression for the variance of

[0161] Solving (2) requires first finding σ(Γ) and then taking its matrix square root. We use the static statistics of open channels in the Markov channel model to define the noise process in the conductance model. The general method for constructing σ(Γ) from the deterministic drift and M ion channels (or the number of synaptic elements in a spiking neural network) using the Goldwyn method can be expressed as:

[0162]

[0163] Here, N is the number of states, I N×1 is an N×1 column vector with all entries equal to 1, and I N×N is the N×N identity matrix. In σ(Γ * )=0 equilibrium point Γ * At , the noise part of equation (2) is zero. Using the above expression (4), we can find the equilibrium point Γ of the system * At the equilibrium point Γ * In this case, the spiking neural network will remain stable, i.e., the noise does not affect the behavior of the spiking neural network. Next, by finding the synaptic drive Γ of all neurons i i The expression for the variance of (t) is used to determine the boundary of the network.

[0164] application Stochastic Differentiation Theorem, and then applying the reverse Euler, the variance-covariance matrix K(t) of Γ(t) (initial value is K(0) = E[ΓΓ T ])) can be expressed as a continuous-time algebraic Lyapunov equation:

[0165]

[0166] Calculate the specific time t by solving the system in (5) r K(t) at . Small dense Lyapunov equations can be computed efficiently using the Bartels-Stewart method or the Hammarling method. Alternatively, large dense Lyapunov equations can be computed using techniques based on symbolic functions. In general, the matrices of deterministic drift in neural networks are not full rank; therefore, we rewrite (5) as a sparse linear matrix-vector system in standard form and solve it using the adjusted alternating direction method:

[0167]

[0168] Here, for iteration j=1, 2, ..., K j has a rank of j×n, and n is [σ(Γ)] r The number of vectors in .

[0169] In order to stabilize the network in (2) to the equilibrium point Γ * , for example σ(Γ * )=0, where the random perturbation is reduced, we transform Θ(t)=Γ(t)-Γ * The equilibrium point Γ * Move to the origin,

[0170]

[0171] where g(Θ(t))=f(Γ(t)+Γ * )-f(Γ(t)), and the controller u(t) is set to

[0172]

[0173] where |Θ(t)| γ =(|Θ1(t)| γ ,|Θ2(t)| γ ,…,|Θ n (t)| γ ) T ,sign(Θ(t))=diag(sign(Θ1(t)),sign(Θ2(t)),…,sign(Θ n (t))), is the gain coefficient, and γ satisfies 0 < γ < 1. For γ = 0, u(t) is discontinuous; when 0 < γ < 1, the controller is a continuous function of Θ; for γ = 1, u(t) is set to be asymptotically stable.

[0174] Without loss of generality, Figure 8 and Figure 9 The network activity is shown, and thus the average network activity histograms are shown for the unbound and bound networks, respectively.

[0175] In both figures, the input signal to the spiking neural network 110 is the same. However, by making the synaptic drive Γ of all neurons i in the spiking neural network 110 i (t) falls into the equilibrium point Γ i * By selecting the synaptic driver Γ that appears in the i The parameters in the variance expression of (t) are used to set the equilibrium point Γ i * Each synapse drives Γ iThe variance of is always below a certain value, which depends on the maximum tolerable amount of noise in the network 110. This value can be predefined and depends on the specific application, the input signal, the accuracy requirements of the classification performed by the spiking neural network 110, etc.

[0176] In practice, the network 110 can be bound, for example, by simulating the network in hardware or software and then constraining the network as described above and evaluating the effects. The binding of the network 110 can be performed during the learning process of setting weights. Noise can be artificially added or simulated to test the stability of the network when subjected to noise.

[0177] The above can be implemented in any spiking neural network 110, in a multi-core solution in a specific core 210 of the core array 200, or in a general hardware implementation of a spiking neural network 110.

[0178] The present invention can be implemented as a reconfigurable multi-layer computing network as a collection of multi-receptor multi-dendritic synaptic structures, where each collection implements a unique input-output transfer function, such as filtering, amplification, multiplication, and addition.

[0179] In an embodiment, a method is devised to set reliability and uncertainty bindings on a neural synaptic structure or a collection of such structures for control and adaptability of classifier responses and activation functions.

[0180] In embodiments, an increase in the size of neurosynaptic structures is achieved, allowing for more states and transitions, providing greater flexibility in the implementation of plasticity and metaplastic interactions as well as various neuronal properties (e.g., latency or synaptic transfer function).

[0181] In an embodiment, multiple learning rules may be implemented, where each neurosynaptic structure in a set or a group of sets implements a unique learning rule.

[0182] In an embodiment, a unique input-output transfer function may be generated by adaptively controlling the charge or amount of representative chemical species (eg, calcium, potassium, sodium).

[0183] In embodiments, fine-grained temporal accuracy can be achieved to drive precise learning behavior and improve the learning capabilities of neural synaptic structures.

[0184] In embodiments, various time control mechanisms may be implemented to allow for steady-state regulation in the resulting network.

[0185] In an embodiment, multiple signals may be implemented to model local and global post-synaptic influences.

[0186] In an embodiment, a set of collections may be organized into a reconfigurable neural synapse array.

[0187] In an embodiment, the reconfigurable neurosynaptic fabric may be organized into computational / signal processing cores, where each core may be organized as a single heterogeneous or homogeneous type implementing a specific learning rule, weight storage, etc., depending on the optimal performance-power-area tradeoff.

[0188] The vast differences in energy efficiency and cognitive performance between biological neural systems and conventional computing are profoundly exemplified in tasks related to real-time interaction with the physical environment, particularly in the presence of uncontrolled or noisy sensory inputs. However, due to their learning capabilities (e.g., parallelism of operations, associative memory, multi-factor optimization, and scalability), neuromorphic event-based neuronal networks are an inherent choice for compact and low-power cognitive systems that learn and adapt to statistical variations in complex sensory signals. This new hardware-resilient approach for neuromorphic networks allows the design of energy-efficient solutions for applications such as detecting patterns in biomedical signals (e.g., spike classification, disease seizure detection), classifying images (e.g., handwritten digits), voice commands, and can be widely applied to a wide range of devices, including smart sensors or wearables in cyber-physical systems and the Internet of Things.

[0189] One or more embodiments may be implemented as a computer program product for use with a computer system. The program of the program product may define the functionality of the embodiments (including the methods described herein) and may be contained on various computer-readable storage media. The computer-readable storage medium may be a non-transitory storage medium. Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media on which information can be permanently stored (e.g., a read-only storage device within a computer, such as a CD-ROM disk readable by a CD-ROM drive, a ROM chip, or any type of solid-state non-volatile semiconductor memory; (ii) writable storage media on which variable information can be stored, such as a hard drive or any type of solid-state random access semiconductor memory, flash memory.

[0190] Two or more of the above-described embodiments may be combined in any suitable manner.

Claims

1. A spiking neural network comprising a spiking neuron and a synaptic element connected to the spiking neuron, in, The synaptic element comprises a first receptor and a second receptor adapted to receive a synaptic input signal, wherein the first receptor and the second receptor generate a first receptor signal and a second receptor signal respectively based on the synaptic input signal, wherein the synaptic element applies a weight to the first receptor signal to generate a synaptic output signal, The synaptic element can be configured to adjust a weight applied by the synaptic element based at least on the second receptor signal, and The spiking neuron is adapted to receive a synaptic output signal from the synaptic element and to generate a spatiotemporal pulse train output signal at least in response to the received synaptic output signal.

2. The spiking neural network according to claim 1, wherein The neuron emits a control signal, wherein the control signal, together with the second receptor signal, modulates a weight applied by the synaptic element; Preferably, wherein the control signal is a back-propagating signal and / or wherein the control signal comprises one or more pulses generated by action potentials in the neuron.

3. The spiking neural network according to claim 2, wherein: The neuron includes dendrites, axons and soma, wherein the control signal originates from the dendrites and / or axons and / or soma of the neuron.

4. A spiking neural network according to any one of the preceding claims, wherein The decay time of the first receptor is faster than the decay time of the second receptor.

5. A spiking neural network according to any one of the preceding claims, wherein The first receptor generates a source current or a sink current for the spiking neuron, and / or Wherein, the first receptor comprises a low-pass filter.

6. A spiking neural network according to any one of the preceding claims, wherein The second receptor forms a voltage-gated receptor, and / or The second receptor includes a low-pass filter, a band-pass filter, a high-pass filter and / or an amplifier.

7. A spiking neural network according to any one of the preceding claims, wherein The first receptor is an AMPA receptor, and / or Wherein, the first receptor is a GABA receptor.

8. A spiking neural network according to any one of the preceding claims, wherein The second receptor is the NMDA receptor.

9. A method for regulating weights of synaptic elements in a spiking neural network, the spiking neural network comprising spiking neurons connected to the synaptic elements, in, The synaptic element comprises a first receptor and a second receptor adapted to receive a synaptic input signal, The first receptor and the second receptor receive the synaptic input signal and generate a first receptor signal and a second receptor signal respectively based on the synaptic input signal. wherein the synaptic element applies a weight to the first receptor signal to generate a synaptic output signal, wherein the weight of the synaptic element is regulated based at least on the second receptor signal, and The spiking neuron receives the synaptic output signal from the synaptic element and generates a spatiotemporal pulse train output signal in response to at least the received synaptic output signal.

10. The method according to claim 9, wherein: The neuron emits a control signal, wherein the control signal, together with the second receptor signal, modulates the weight applied by the synaptic element, Preferably, wherein the control signal is a back-propagating signal and / or the control signal comprises one or more pulses generated by action potentials in the neuron.

11. The method according to claim 10, wherein: The neuron includes dendrites, axons and soma, wherein the control signal originates from the dendrites and / or axons and / or soma of the neuron.

12. The method according to any one of claims 9 to 11, wherein: The decay time of the first receptor is faster than the decay time of the second receptor.

13. The method according to any one of claims 9 to 12, wherein: The first receptor generates a source current or a sink current for the spiking neuron, and / or Wherein, the first receptor comprises a low-pass filter.

14. The method according to any one of claims 9 to 13, wherein: The second receptor forms a voltage-gated receptor, and / or The second receptor includes a low-pass filter, a band-pass filter, a high-pass filter and / or an amplifier.

15. The method according to any one of claims 9 to 14, wherein: The first receptor is an AMPA receptor, and / or Wherein, the first receptor is a GABA receptor.

16. The method according to any one of claims 9 to 15, wherein: The second receptor is the NMDA receptor.

17. An integrated circuit comprising a spiking neural network according to claims 1-8.

Images