Method of operating a storage system and storage system

Abstract

This application provides a method for operating a storage system, including: receiving a logical address of data; selecting a storage block mapped in a storage array of the memory according to the logical address; and selecting an actual storage cell mapped within the selected storage block according to the logical address. The logical address is configured to include a block address for selecting the storage block and a cell address for selecting the actual storage cell, with each storage block corresponding to one block address and each storage cell corresponding to one cell address. The method and system shown in this application can not only reduce the impact of bias-induced drift, thus helping to reduce problems caused by bias drift, but also support longer power-on data retention times, and simplify read / write circuitry, test and analysis complexity, and system management complexity.

Description

Technical Field

[0001] This application relates generally to the field of electronic devices, and more particularly to a method of operating a storage system and the storage system itself. Background Technology

[0002] Memory is the foundation of information technology. As a candidate for the next generation of non-volatile semiconductor memory, phase change memory (PCM) has attracted widespread attention due to its advantages such as high-speed read, high number of erase and write cycles, non-volatility, small device size, low power consumption, and resistance to strong shock and radiation, especially 3D PCM.

[0003] However, with the increase in storage capacity, how to effectively extract the physical location of the storage cells in the PCM has become an important issue. In addition, since read and write operations apply bias voltage to each storage cell, how to apply appropriate bias voltage to the storage cell to ensure good data storage maintenance and reduce the offset caused by the operation bias voltage of the storage cell is also an important issue. Therefore, it is necessary to propose an operation method that can solve these problems. Summary of the Invention

[0004] The purpose of this application is to provide an operation method and a storage system for a storage system, which applies appropriate bias voltage to read and write operations according to the physical location of the storage cell to obtain the best read and write performance, while solving the problem of data drift caused by the read and write bias voltage of the storage cell.

[0005] In a first aspect, this application provides a method for operating a storage system, the method comprising:

[0006] The logical address for receiving data;

[0007] Based on the logical address, select the memory block in the memory array mapped to the memory; and

[0008] Based on the logical address, select the actual storage unit mapped to the selected storage block.

[0009] Optionally, the operation method further includes setting the logical address to include a block address for selecting the storage block and a cell address for selecting the actual storage unit, wherein each storage block corresponds to one block address and each storage unit corresponds to one cell address.

[0010] Optionally, the operation method further includes determining the block addresses of the plurality of storage blocks according to the row and column arrangement order of each storage block in the storage array, wherein the storage block includes a plurality of storage cells that are physically adjacent and arranged in an array in the storage array.

[0011] Optionally, the operation method further includes mapping one of the block addresses to a storage block comprising N rows * M columns of storage units, where N and M are positive integers greater than 2, and N is equal to or not equal to M.

[0012] Optionally, the operation method further includes configuring one of the storage blocks to include 2 x *2 y The unit address is used to map to a storage block with x row address bits and y column address bits in the physical address of the storage array, and to divide the storage array into storage blocks, where x and y are positive integers greater than 1, and x is equal to or not equal to y.

[0013] Optionally, the operation method further includes setting the block address in the high-order bits of the logical address and setting the cell address in the low-order bits of the logical address relative to the high-order bits.

[0014] Optionally, the operation method further includes performing calculations using the block address of the logical block to perform any one of read / write compensation management, wear leveling management, and bad block management.

[0015] Optionally, the operation method further includes applying the same read / write pressure conditions to each storage cell within the storage block, and applying different read / write pressure conditions to different units of the storage blocks, taking at least one storage block as the unit.

[0016] Optionally, the storage unit is a phase-change storage unit.

[0017] Secondly, this application provides a storage system, comprising:

[0018] Memory, including a memory array consisting of multiple memory cells; and

[0019] A controller electrically connected to the memory for controlling the memory, and configured to receive a logical address of data; select a memory block mapped in the memory array based on the logical address; and select a memory cell mapped within the selected memory block based on the logical address.

[0020] Optionally, the logical address includes the block address for selecting the storage block and the cell address for selecting the actual storage unit, with each storage block corresponding to one block address and each storage unit corresponding to one cell address.

[0021] Optionally, the block address of the plurality of storage blocks is determined according to the row and column arrangement order of each storage block in the storage array, wherein the storage block includes a plurality of storage cells that are physically adjacent and arranged in an array in the storage array.

[0022] Optionally, a plurality of storage units within a storage block comprise N rows * M columns of storage units, where N and M are positive integers greater than 2, and N is equal to or not equal to M.

[0023] Optionally, the storage block includes 2 x *2 y An address is used to map to a storage block with x row address bits and y column address bits in the physical address of the storage array, and the storage array is divided into the storage blocks, where x and y are positive integers greater than 1, and x is equal to or not equal to y.

[0024] Optionally, the block address is in the high-order bits of the logical address, and the cell address is in the low-order bits of the logical address relative to the high-order bits.

[0025] Optionally, the controller is configured to perform calculations using the block address of the storage block to perform any one of read / write compensation management, wear leveling management, and bad block management.

[0026] Optionally, the controller is configured to apply the same read / write pressure conditions to each storage cell within the storage block, and to apply different read / write pressure conditions to different units of the storage blocks, taking at least one of the storage blocks as a unit.

[0027] Optionally, the storage unit is a phase-change storage unit.

[0028] By using the storage system operation method and storage system provided in this application, not only can several addresses with similar physical locations be selected to form a logically contiguous data block (or storage block), but it can also ensure that all storage units within this data block have basically the same RC response characteristics, thereby obtaining basically consistent read and write pressure conditions and consistent read and write performance.

[0029] When performing read / write compensation, the same conditions can be applied to such storage blocks. Only the block addresses of the storage blocks need to be managed using an algorithm, which greatly simplifies the PCM read / write circuit and reduces the complexity of testing and analysis. Similarly, when performing system media management and bad block management, only the block addresses of the storage blocks need to be managed using an algorithm, simplifying the system management complexity.

[0030] When accessing addresses sequentially, N*N consecutive memory cells can be distributed across N different WLs and BLs. In other words, the physical addresses actually accessed can be distributed across different WLs / BLs, thus reducing the impact of bias drift to 1 / N. This helps to reduce the bias drift problem and supports longer data retention times. Attached Figure Description

[0031] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0032] Figure 1 This is a functional block diagram of a storage system provided according to some embodiments of this application.

[0033] Figure 2 This is a functional block diagram of the peripheral circuitry of a memory provided according to some embodiments of this application.

[0034] Figure 3a This is a circuit diagram of a memory array according to some embodiments of the present application.

[0035] Figure 3b This is a schematic diagram of the structure of a phase-change memory cell provided according to some embodiments of this application.

[0036] Figure 4(a) is a schematic diagram of the setting and resetting operation of a phase change memory cell according to some embodiments of this application.

[0037] Figure 4(b) is a schematic diagram of the operation of a bidirectional threshold switch provided according to some embodiments of this application.

[0038] Figure 5 This is a schematic diagram showing the distribution of threshold voltage drift in a memory cell according to some embodiments of this application.

[0039] Figure 6 This is a schematic diagram illustrating the operation steps of a storage system according to some embodiments of this application.

[0040] Figure 7 This is a schematic diagram of a two-level addressing basis provided according to some embodiments of this application.

[0041] Figure 8 This is a schematic diagram illustrating a two-level addressing example provided according to some embodiments of this application.

[0042] Figure 9 This is a schematic diagram of the operation method steps of another storage system provided according to some embodiments of this application.

[0043] Figure 10 This is a schematic diagram of the operation method steps of another storage system provided according to some embodiments of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0045] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.

[0046] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0047] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a range smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers, as well as one or more dielectric layers.

[0048] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0049] This paper uses Cartesian coordinates to represent directions. With the substrate as the reference, "Z" represents the first direction, which is perpendicular to the substrate; "X" represents the second direction, which is parallel to the substrate; and "Y" represents the third direction, which is parallel to the substrate and perpendicular to X.

[0050] First, please refer to Figure 1 , Figure 1 A functional schematic block diagram of a storage system provided according to some embodiments of this application.

[0051] like Figure 1 As shown, a storage system 1 according to some embodiments of this application includes a controller 100 and a memory 200; the controller 100 is electrically connected to the memory 200 and is used to control the memory 200. The memory 200 then controls the storage array 10 in the memory through peripheral circuits 20 in the memory 200, and can perform various operations on each storage cell (not shown) in the storage array.

[0052] In some implementations, the storage system 1 may be implemented as a memory module, a high-end SSD, high-width memory (HBM), a universal flash storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a PCMCIA card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0053] like Figure 2 As shown, the memory 200 mainly includes a memory array 10 and peripheral circuitry 20 connected to and controlling the memory array 10. The peripheral circuitry 20 is connected to the memory array 10 and typically includes at least a row decoder 210, a word line voltage generator 211, a word line driver 212, a column decoder 220, a bit line driver 222, a bit line voltage generator 221, a reference current / voltage generator 261, a sensitive amplifier / comparator 260, and a logic control module 230 connected to the aforementioned devices for receiving operation commands and controlling the aforementioned devices.

[0054] The row decoder 210 receives the row address signal from the bus 290 and decodes the row address signal to select the address word line.

[0055] The word line driver 212 is connected to multiple word lines WL<0:m>, the word line voltage generator 211, and the row decoder 210. The word line driver 212 receives the row address selection signal and the word line drive voltage, and outputs the word line drive voltage to the multiple word lines WL according to the row address selection signal. <m>At least one word line WL in the memory is connected to at least one row of memory cells.

[0056] Bit line driver 222, bit line voltage generator 221, and column decoder 220 belong to the column drive circuit, and as shown in the figure Figure 2 The connections are shown. The bit line voltage generator 221 and the column decoder 220 are connected to the logic control module 230 to be controlled by the logic control module 230.

[0057] Column decoder 220 receives the column address signal and decodes it to select the address bit line connected to the target memory cell. Bit line voltage generator 221 generates the voltage required for each selected bit line BL and outputs the set voltage to each corresponding selected bit line BL.

[0058] Bit line driver 222 is connected to multiple bit lines BL, bit line voltage generator 221, and column decoder 220. Bit line driver 222 receives bit line voltage and column address selection signal, and outputs the set bit line voltage to multiple bit lines BL according to the column address selection signal. <n>At least one column of memory cells is connected by at least one bit line BL.

[0059] The peripheral circuit 20 also includes a sensitive amplifier comparator 260, a reference current / voltage generator 261, and a data latch 270. The sensitive amplifier comparator 260 is connected to the reference current / voltage generator 261 and multiple bit lines BL<0:n>, and is also connected to the data latch 270. When reading data, the sensitive amplifier comparator 260 compares the received data with the reference value generated by the reference current / voltage generator 261 to determine the data stored in the selected memory cell. The data is then stored in the data latch 270 and, together with the data read from other bit lines, is output to the data bus 290 via the input / output interface 280.

[0060] Based on the aforementioned structural design of the peripheral circuit 20 of the memory, operations on the memory can include erase operations, read operations, and programming operations, or set and reset operations. Furthermore, during these operations, the controller 100 receives logical address information according to an L2P (Logical Address to Physical Address) mapping table, and then sends out the physical address according to the L2P mapping table. After receiving the physical address, the peripheral circuit 20 selects appropriate word lines WL and bit lines BL through row decoder 210 and column decoder 220 to address the memory cells in the memory array 10. Then, word line driver 212 and bit line driver 222 bias the selected word lines WL and bit lines BL, thereby performing various operations on the selected memory cells. Moreover, in some embodiments, during address selection, logical addresses are arranged in the order of word line WL and bit line BL addresses, for example as follows: Figure 3a As shown, a storage array will first address on a WL, traverse different BLs, and then switch to the next WL for addressing.

[0061] Understandably, although the memory 200 and the controller 100 are collectively referred to as a storage system here, the controller 100 may also be integrated with the memory 200 into a single chip in some embodiments. Therefore, the storage system mentioned here can actually be a memory, and is not limited to the term "system".

[0062] Please continue to refer to Figure 3a , Figure 3a This is a circuit diagram illustrating an example of a memory array 10 according to some embodiments of this application. The memory array 10 includes a plurality of memory cells 11 arranged in a multi-row, multi-column array, and word lines WL and bit lines BL respectively connecting the plurality of memory cells 11 in the multiple rows and columns. Each row of memory cells includes a plurality of memory cells 11 arranged along the row direction X. Each column of memory cells includes a plurality of memory cells 11 arranged along the column direction (i.e., the second direction Y). Figure 3a Only the storage units of three rows WLn-1 to WLn+1 and three columns BLn-1 to BLn+1 are shown, where n represents any positive integer greater than 2. The actual number of rows and columns of storage units depends on the storage capacity. Additionally, Figure 3a The illustrated storage cell is a phase-change storage cell 11, which includes an omonic threshold switch (OTS) 111 and a phase-change storage cell (PCM cell) 112 connected in series between the word line WL and the bit line BL. Both the omonic threshold switch (OTS) 111 and the PCM cell 112 are made of phase-change materials. However, in some technologies, since the PCM cell 112 is used as the threshold setting for data storage, in this embodiment, the two phase-change materials in the storage cell 11 are referred to as the omonic threshold switch (OTS) 111 and the PCM storage cell 112, respectively.

[0063] It should be understood that the memory cells in the memory array can be memory cells of various structures, such as floating gate memory cells, ONO memory cells, resistive RAM (RRAM) memory cells, phase change memory cells (PCM / PCRAM / SOM), etc. This application does not limit them, but this application is particularly applicable to phase change memory cells. Therefore, the following will use the phase change memory cell PCM as an example for illustration, but it should be understood that it is not limited to this.

[0064] Figure 3b A schematic diagram of the structure of a storage unit provided for some embodiments of this application. For example... Figure 3b As shown, some embodiments of this application provide a phase-change memory cell structure including: a top electrode 11a and a bottom electrode 11b respectively connecting the word line WL and the bit line BL, and a phase-change memory cell 112, an intermediate electrode 11c, and a bidirectional threshold switch (OTS) 111 located between the top electrode 11a and the bottom electrode 11b. It should be understood that in some embodiments, the intermediate electrode 11c may not be provided, therefore this application is not limited to the structure disclosed herein.

[0065] The phase change memory cell 112 includes one or more phase change materials, such as germanium-antimony-tellurium (Ge-Sb-Te, GST) materials, one example being Ge2Sb2Te5. Currently, the most commonly used phase change materials by various institutions are chalcogenides (represented by Intel) and synthetic materials containing germanium, antimony, and tellurium (GST), such as Ge2Sb2Te5. Phase change materials can have a large resistivity contrast between different phases (e.g., crystalline and amorphous phases). For example, a phase change material can exhibit relatively low resistivity in a crystalline phase but relatively high resistivity in an amorphous phase, and the resistivity of the phase change material in the amorphous phase can be hundreds to thousands of times higher than that in the crystalline phase. When heated, the phase change material can switch between different phases to enable the writing of information (data) (including setting and resetting). In this embodiment, the electrodes 11a and 11c can heat the phase change memory cell 112 via OTS111 to change the phase state of the heated region 112f in the phase change cell 112, thereby reducing the resistance of the phase change memory cell 112. In some embodiments, a heater (not shown) may also be added between the phase change memory cell 112 and the intermediate electrode 11c.

[0066] The top electrode 11a and the bottom electrode 11b are arranged opposite to each other, and their positions can be interchanged. They are also arranged to overlap with the outer bit line BL and word line WL, thereby forming a 3D phase change memory.

[0067] Figure 4a This document provides a schematic diagram of the bias voltage for reset and set operations of a PCM memory cell in some embodiments of this application, illustrating the working principle and operating bias voltage of the phase-change memory cell 112. The basic storage principle of the phase-change memory cell 112 involves applying voltage or current pulse signals of varying widths and heights to the cell, causing a physical phase change in the phase-change material within the heated region 1121f. This involves a reversible phase transition between a crystalline (low-resistance) and amorphous (high-resistance) state, thereby enabling information writing operations, including writing 1 (set) or 0 (reset). The transition process includes two processes: an amorphization transition from crystalline to amorphous state and a crystallization transition from amorphous to crystalline state. The former is referred to as the amorphization process, and the latter as the crystallization process. Information is then read out by measuring and comparing the resistance difference between the two physical phase states. This non-destructive reading process ensures accurate reading of the information stored in the device cell. The resistivity of phase change materials differs by several orders of magnitude between their crystalline and amorphous states, giving them a high noise margin sufficient to distinguish between the "0" and "1" states.

[0068] Figure 4b The diagram shows the logarithmic current versus voltage curve of the bidirectional threshold switch (OTS) 111, which functions as a fast return selector or access element. Starting from the high resistance (reset) state under low electric field, the current in the bidirectional threshold switch (OTS) 111 increases by a very small value Ic as the voltage increases until the threshold voltage V is reached. TH OTS until.

[0069] After the fast return point 115, as long as it is higher than the holding current I... H OTS The current flowing through the bidirectional threshold switch (OTS) 111 maintains a highly conductive dynamic ON state in the bidirectional threshold switch (OTS) 111 with an on-state current Io. This transient highly conductive state originates electronically and does not involve any phase transition in the bidirectional threshold switch (OTS) 111.

[0070] When the threshold voltage V of the bidirectional threshold switch (OTS) 111 is exceeded TH OTS When the bidirectional threshold switch (OTS) 111 switches from the OFF state to the ON state, current flows through the phase-change memory cell 112 connected in series with the OTS 111. In the ON state, as the current flowing through the OTS 111 increases, the voltage across the OTS 112 remains close to the holding voltage (V). H OTS ).

[0071] The bidirectional threshold switch (OTS) 111 can remain in the ON state until the current through the bidirectional threshold switch (OTS) 111 is lower than the holding current (I). H OTS Until the value exceeds V again. Below this value, the bidirectional threshold switch (OTS) 111 can return to the high-resistance, non-conductive OFF state until the value exceeds V again. TH OTS Or I TH OTS Until then. Whenever guided, the bidirectional threshold switch (OTS) can repeatedly and reversibly switch between the OFF and ON states, but it does not crystallize.

[0072] The threshold voltage Vth in the OTS111 is affected by many factors, such as device structure variations, the amplitude of the applied pulse, pulse width, ramp rate, and relaxation time. In further research, when the OTS device is composed of a phase change material such as Ge-Te-As-Si, the threshold voltage Vth of the OTS111 will be altered by the polarity of the applied voltage; more specifically, the threshold voltage changes by ΔVth as the polarity of the applied voltage changes. Using this ΔVth, the OTS device can be used independently as a binary storage device; therefore, in this example, the OTS111 is referred to as an SOM (selector-only memory) cell or an SSM (self-selecting memory) cell. Therefore, it can be understood that the phase change memory (PCM) described in this application includes various variations of PCM, such as Xpoint type PCM, and selector-only memory (SOM) or self-selecting memory (SSM) composed of the aforementioned OTS, and includes various phase change memories arranged in two-dimensional (2D) and three-dimensional (3D) configurations, as well as PCMs with single-level or multi-level storage.

[0073] Further research in this application revealed that in an independent subarray of a 3D-PCM constructed according to some embodiments of this application, due to the small WL / BL pitch and large resistive-capacitive load, the voltage and current waveforms obtained when applying read / write voltage and current vary depending on the distance of the memory cell from the word line / bit line driver (WL / BL driver) within the subarray. For cells closer to the WL driver, the word line voltage and current are applied faster, resulting in a steeper waveform change, while for cells farther from the WL driver, the waveform change is slower. Similarly, for cells closer to the BL driver, the bit line voltage and current are applied faster, resulting in a steeper waveform change, while for cells farther from the BL driver, the waveform change is slower. In other words, the RC characteristics differ depending on the location region. Since PCM read / write speeds are very fast, a difference of a few nanoseconds (ns) in the waveform can cause differences in read / write performance.

[0074] Furthermore, there are certain differences in the read and write performance of storage cells at different locations. In order to minimize the differences in read and write performance of cells at different locations, PCM read and write often requires the introduction of complex location compensation algorithms.

[0075] Meanwhile, in response to potential differences in storage performance, the system side, namely the controller 100 shown above, may need to perform corresponding media management based on the inconsistencies of different regions. For example, the durability of cells in different regions may be different, and wear leveling algorithms need to be managed differently.

[0076] Whether implementing a position compensation algorithm during read / write operations or a system-side region-based media management algorithm, the first step is to extract the physical location of the cell. For a current 128Gb capacity 3D-PCM, an independent cube-shaped subarray has 16Mbits, totaling 24 address bits. If the addresses are arranged in row and column order, considering a centrally symmetric structure, 22 bits would need to be involved in the calculation to determine the physical location of each cell, which is too large. Therefore, a simplified algorithm that effectively extracts the physical location of the cell is needed.

[0077] Furthermore, in 3D-PCM and SOM memories, OTS is used as the selection switch. In further research of this application, it was found that when a voltage smaller than the threshold voltage (Vth) is applied across the cell of the OTS selection device, although the cell will not be turned on, there will be a small subthreshold conduction current. This will cause a certain drift problem in the threshold voltage of the OTS, resulting in Vth drifting over time in both set and reset states. This is referred to as the bias drift effect.

[0078] Figure 5 The diagram shows the Vth distributions for set and reset states when the threshold voltage (Vth) experiences bias drift in this study. The curve to the left of Vread represents the Vth distribution for set states, and the curve to the right of Vread represents the Vth distribution for reset states. The solid line B0 indicates the absence of bias drift. As the number of operations on the same word line WL or bit line BL increases, the corresponding Vth distributions for set and reset states will drift as shown by the dashed lines B1 and B2. Due to the presence of bias drift, the read window margin (RWM) that accurately distinguishes set and reset states is greatly reduced.

[0079] When performing read and write operations on a cell, for example Figure 3a The memory cell 11t will have a higher bias voltage applied to the corresponding WLn (word line) and BLn (bit line), such as Vhh and Vll; the unselected WLn+1 / n-1 and BLn+1 / n-1 will be kept at zero or low bias voltage, such as Vuw and Vub, to ensure that they are not in a conducting state. For other unselected cells on the same WLn and BLn as the selected cell, although they will not be selected to conduct, there will still be a certain bias voltage across the two ends of the cell. These cells will have a bias voltage drift problem. That is, the data drift caused by the bias voltage operation on the same bit line word line to other memory cells. When the logical address is arranged according to the address order of WL and BL, for an n x m array, the addresses addr_wl[i-1:0], addr_bl[j-1:0], 2 i =n,2 j Addressing is determined by m bits, meaning it's addressed using the i bits of the word line and the j bits of the bit line. If sequential read / write operations occur, all cells in a WL (Wide Level) are traversed first. Assuming each cell is operated on k times, in the worst case, a cell may experience (n-1)*k word line bias drifts and (m-1)*k bit line bias drifts, significantly reducing the power-on data retention time of the memory cell.

[0080] Therefore, according to some embodiments of this application, such as Figure 6 As shown, this application further provides a method for operating a storage system, including:

[0081] Step S1, the logical address for receiving data;

[0082] Step S2: Based on the logical address, select a memory block in the memory array mapped to the memory; and

[0083] Step S3: Select the actual storage unit mapped to the selected storage block based on the logical address.

[0084] Specifically, in some embodiments, such as Figure 7 As shown, the address is first addressed within a storage block (ROW) 10b, and then the address of storage block 10b is addressed. For example, assume that each storage block 10b contains 2... x =M line 2 y =N columns of storage unit 11, the address in storage block 10b has g bits: addr[g-1:0], g = x + y, corresponding to a total of 2g = M * N addresses from storage unit number ADDR0 to ADDR(M*N-1), x can be equal to or not equal to y.

[0085] For example Figure 7 As shown, if a storage array has 2 p = J storage block rows, and 2 q =K storage block columns, the ROW block address will have h bits, i.e., row[h-1:0], h = p + q, p can be equal to or not equal to q, corresponding to the storage block number from ROW0 to ROW(J*K-1), a total of 2. h = J*K block addresses, where p can be equal to or not equal to q. This arrangement can distribute M*N consecutive logical memory units across M different WLs and N different BLs, which helps to reduce the impact of bias drift.

[0086] Thus, for an array that originally has n rows and m columns, 2 i =n,2 j =m, a total of i+j address bits, physical addresses addr_wl[i-1:0], addr_bl[j-1:0], which are mapped to logical addresses row[h-1:0], addr[g-1:0], where i+j = h+g.

[0087] In other words, according to some embodiments of this application, the 2i rows and 2j columns of storage units corresponding to the i+j row and column address bits in the conventional array are remapped to the 2i rows and 2j columns of storage units corresponding to the h-bit storage block address bits. h There are 1 storage block, and 2 corresponding to the 2^g intra-block address bits within each storage block. g There are 2 storage units. That is, the row and column addresses are remapped to the h-bit storage block address row[h-1:0], for a total of 2. h Each block contains a storage unit address (addr[g-1:0]) within the block, and the block address corresponds to 2 bits. g There are 10 storage units, where i+j = h+g.

[0088] Specifically, such as Figure 7 As shown, and refer to Figure 1 , 2 And 3a, after receiving the logical address signal Addl from the host (not shown) or the controller itself, the controller 100 will, according to the first L2P mapping table (not shown) stored in the controller 100, select the h-bit block address row[h-1:0] corresponding to the memory block 10b in the memory array 10b in the memory 200, which is mapped to the original array i+j bit row and column address (addr_wl[i-1:0], addr_bl[j-1:0]). h One of the storage blocks is selected, and the physical location g-bit address addr[g-1:0] of the actual storage unit 11 mapped in the selected storage block 10b is found according to the second L2P mapping table. Then, it is sent to the memory 200, and read and write operations are performed on one address 11 in the storage array 10b in the memory 200.

[0089] With this configuration, the original physical addresses addr_wl[i-1:0] and addr_bl[j-1:0] of the actually accessed storage units 11 can be distributed across different WL / BL blocks, each spanning the width of a storage block 10b. When the entire array is divided into J*K storage blocks 10b, each block containing M*N rows and columns of storage units, the impact of WL bias drift can be reduced to 1 / J compared to the undistributed configuration, and the impact of BL bias drift can be reduced to 1 / K. This allows for longer power-on retention. Here, J can be equal to K, and M can be equal to N.

[0090] The operation method can be described as including setting the logical address Addl to include the block address row[p+q-1:0] (or row[h-1:0]) for selecting each of the storage blocks (or data blocks), and the unit address addr[x+y-1:0] (or addr[g-1:0]) for selecting the actual storage unit 11 within each storage block 10b. Furthermore, the numerical codes m, n, p, q, h, g, M, and N mentioned here represent only indefinite numbers. The use of M or N in different embodiments may be repeated, but their meaning varies depending on the specific embodiment.

[0091] In some embodiments, such as Figure 7 As shown, the operation method further includes determining the block address row[h-1:0] of the storage block 10b according to the row and column arrangement order of each storage block 10b in the storage array 10, that is, arranging the block address row[h-1:0] according to the row and column order, and wherein the storage block 10b includes a plurality of storage cells 11 that are physically adjacent and arranged in an array in the storage array 10.

[0092] Also, in Figure 7 In the example shown, the arrangement of storage blocks 10b is exemplified by a J x K matrix, while the storage cells 11 within the storage blocks are exemplified by an M x N matrix. However, it is understood that the J*K array of the logic blocks and the M*N array of the storage cells described above are merely examples. In some embodiments, the number of rows and columns of each storage block or storage cell may be equal or unequal. Furthermore, in some embodiments, N is used to represent the rows of an array, and M is used to represent the columns of an array; however, this is not a limitation. M and N can be interchanged, or each can represent a different array, depending on the specific embodiment.

[0093] Furthermore, as mentioned earlier, in the example of a matrix of N*N blocks storing M=N, the cell address can be addedr[2n-1:0], 2 n =N is used to represent this, while in the example of an N*M storage unit matrix, it can be represented as addr[x-1:0]+[y-1:0], 2 x =N,2 y =M is ​​used to represent this, therefore, according to some embodiments of this application, the operation method further includes configuring one of the storage blocks to include 2 x *2 y The storage array 10 is divided into several units, and a storage block 10b with x row address bits (i.e., x bits of row address) and y column address bits (i.e., y bits of column address) is selected from the physical address of the storage array. The storage block 10b is then used to divide the storage array 10, where x and y are positive integers greater than 1, and x is equal to or not equal to y. That is, when x equals y, it is the aforementioned N*N example, and when x is not equal to y, it is the aforementioned N*M example.

[0094] In some embodiments, the operation method further includes setting the block address row[p-1:0]+[q-1:0] (taking a J*K matrix as an example) in the high-order bits of the logical address, setting the cell address addr[x-1:0]+[y-1:0] (taking an N*N matrix as an example) in the low-order bits of the logical address Addl relative to the high-order bits, and the least significant bit (LSB) address of each memory cell 11 mapped in the memory block 10b is continuous in the logical address.

[0095] Specifically, for example, in an N*N storage cell matrix and an M*M storage block matrix, if N=64 and M=64, that is, a storage capacity of 16M, because 2 6 =64, then there are 6 high-order bits and 6 low-order bits, so the logical address can include 12 bits. However, in contrast, taking a 128Gb capacity PCM array as an example, if the traditional full address method is used, 24 bits are needed to represent the address associated with the WL / BL driver.

[0096] Figure 8 This shows an example of a practical application of storage block 10b and storage cell 11 when N / M = 64. When N = 64, a storage block 10b contains 64 word lines WL and 64 bit lines BL, which is a total of 4K (4096) storage cells 11. A 16M storage matrix will contain 4K (4096) storage blocks 10b.

[0097] by Figure 8 Taking the capacity as an example, for a PCM with a continuous set of N*16 (banks)*32B data, such as N=4k, which is a 64*64 matrix, then for 4k*16 (banks)*32B = 2MB = 16Mb of continuous data, each WL / BL will be affected by a maximum of 64 bias drifts. However, in the row-column ordered full addressing method, each WL / BL will be affected by 4k bias drifts. Through the operation method described in this application, the bias drift pressure is reduced to 1 / 64 = 1.5625%.

[0098] In addition, each memory cell, including PCM memory, gradually fails after a limited number of program-erase (P / E) cycles, with a typical lifespan of several thousand to tens of thousands of P / E cycles.

[0099] Frequent operations on certain areas (such as the metadata area of ​​a file system) can cause these areas to wear out prematurely, leading to storage device failure. Therefore, wear leveling is commonly used for these storage devices. Wear leveling is a management technique for storage devices (such as SSDs, USB flash drives, eMMC, PCM, etc.) that balances the number of writes and erases to storage cells, thereby extending the lifespan of the storage device.

[0100] Wear leveling uses algorithms to evenly distribute write operations across all storage cells of the entire storage device, preventing certain areas from prematurely failing due to overuse. It primarily includes the following two strategies:

[0101] a. Static Wear Leveling: The purpose is to reallocate less frequently used static data (such as files that are rarely modified). This static data is migrated from low-wear storage cells to high-wear cells, allowing the low-wear cells to also participate in writing and erasing.

[0102] b. Dynamic Wear Leveling: Dynamically manages frequently written data, dynamically allocating it to the idle cell with the lowest wear level each time it is written, to ensure that the data is distributed as evenly as possible.

[0103] Therefore, in operation, when the storage controller receives a write request, it determines whether the current write location needs adjustment based on the wear leveling algorithm. If so, the controller writes the data to other cells with less wear and updates the address mapping table to ensure that the logical address and the actual physical address are correctly mapped, thereby extending the overall lifespan of the storage device, improving the reliability of the memory, and reducing the risk of data loss due to excessive local wear.

[0104] Therefore, further according to some embodiments of this application, since the storage array is divided into M*M (or N*M) storage blocks 10b, the operation method also includes that when performing any of the read / write compensation management, wear leveling management, and bad block management on the storage array 10, the calculation can be performed in units of the block address of the storage block 10b, thereby simplifying the calculation.

[0105] Specifically, Figure 9 This diagram illustrates the operational steps of another storage system provided according to some embodiments of this application. Figure 9 As shown, in Figure 9 The operation method shown includes, in addition to the steps S1, S2 and S3 described above, exemplary steps S11 and S12.

[0106] Step S11: Based on the logical address, determine the memory block mapped to the memory array; and

[0107] Step S12: Perform calculations using the block address of the storage block to perform any one of the following management methods: read / write compensation management, wear leveling management, and bad block management.

[0108] Step S12 is similar to step S2. After receiving the logical address in step S1, the memory block to be read or written is identified. Then, in step S12, calculations are performed using the block address of the identified memory block to perform any one of the following management methods: read / write compensation management, wear leveling management, and bad block management. After the various management calculations are completed, the process returns to steps S2 and S3, where a new memory block and memory cell are selected, and subsequent read / write operations can be performed.

[0109] For example, if read / write compensation management is to be performed, steps S11 and S2 can be combined. That is, after the storage block is identified or selected, read / write compensation management is performed, and when the actual storage unit is operated in step S3, the operation can be performed with the required compensation.

[0110] In some embodiments, since the storage array is divided into M*M (or N*M) storage blocks 10b, the operation method further includes applying the same read / write pressure condition to each storage cell within the storage block when read / write pressure conditions are to be applied to the storage array 10b, and applying different read / write pressure conditions to different units of the storage blocks, with at least one of the storage blocks as the unit.

[0111] Specifically, Figure 10 This diagram illustrates the operational steps of another storage system provided according to some embodiments of this application. Figure 10 As shown, in Figure 10 The operation method shown includes step S4 in addition to the steps S1, S2 and S3 mentioned above.

[0112] Step S4: Apply the same read / write pressure conditions to each storage cell within the storage block, and apply different read / write pressure conditions to different units of the storage block, taking at least one storage block as the unit.

[0113] Understandably, according to some embodiments of this application, since the distance between each memory cell 11 in a memory block 10b and the driver of the memory array is close, that is, the resistance and capacitance of the lines between each memory cell in a memory block and the row driver or column driver are close, the effects of the parasitic resistance or capacitance on the word line and the bit line are basically the same. Therefore, each memory cell will have basically the same resistance-capacitance (RC) characteristics relative to the driver. Therefore, by configuring different bias voltages on a per-memory basis in terms of read and write pressure conditions, different appropriate bias voltage conditions can be configured according to the position of the memory block 10b, and the most appropriate bias voltage conditions can be given to each memory block.

[0114] Furthermore, it is understood that in some embodiments, although not illustrated, the operation of step S4 can be applied in... Figure 9 In the various management operations shown, that is, when performing any of the read / write compensation management, wear leveling management, and bad block management, the method in step S4 can be used to apply different read / write pressure conditions to different logic blocks.

[0115] Furthermore, since all storage cells within the storage block have essentially the same RC response characteristics relative to the driver, they achieve essentially consistent read / write pressure conditions and consistent read / write performance, thus facilitating location management.

[0116] Moreover, since the same bias condition can be applied to a memory block when performing read and write compensation, only the memory block address needs to be managed by algorithm, which can greatly simplify the PCM read and write circuit and reduce the complexity of test and analysis, thus facilitating location management.

[0117] For another example, when managing system media, including wear leveling and bad block management, only the block addresses of storage blocks need to be managed using algorithms. This simplifies system management complexity and is beneficial for location management. For instance, in the previous example of N=64, a 10b storage block contains 64 word lines (WL) and 64 bit lines (BL), totaling 4K cells. An 8M storage array contains 2K storage blocks. In some embodiments, the location management algorithm is centrally symmetric, requiring only 9 bits of the storage block address for algorithm management. In contrast, traditional row-column sequential addressing requires 21 bits of the full address for address algorithm management, greatly simplifying the algorithm and making data analysis clearer and more intuitive.

[0118] Based on the operation methods of the storage system provided in the foregoing embodiments, some embodiments of this application also provide a storage system, including:

[0119] Memory, including a memory array consisting of multiple memory cells; and

[0120] A controller electrically connected to the memory for controlling the memory, and configured to receive a logical address of data; select a memory block mapped in the memory array based on the logical address; and select a memory cell mapped within the memory block based on the logical address.

[0121] like Figure 7 and Figure 8 As shown, in some embodiments, the logical address includes a block address for selecting the storage block and a cell address for selecting the actual storage unit, with each storage block corresponding to one block address and each storage unit corresponding to one cell address.

[0122] In some embodiments, the block addresses of the plurality of storage blocks are determined according to the row and column arrangement order of each storage block in the storage array, wherein the storage block includes a plurality of storage cells that are physically adjacent and arranged in an array in the storage array.

[0123] In some embodiments, a plurality of storage cells within a storage block comprises N rows * M columns of storage cells, where N and M are positive integers greater than 2, and N is equal to or not equal to M.

[0124] In some embodiments, the storage block includes 2 x *2 y An address is used to map to a storage block with x row address bits and y column address bits in the physical address of the storage array, and the storage array is divided into storage blocks, where x and y are positive integers greater than 1, and i is equal to or not equal to j.

[0125] In some embodiments, the block address is in the high-order bits of the logical address, and the cell address is in the low-order bits of the logical address relative to the high-order bits.

[0126] All of the above configurations have been described in the previous embodiments regarding the operation method, and therefore will not be repeated here.

[0127] Furthermore, in some embodiments, such as Figure 9 and Figure 10 As shown, the controller is also configured to perform calculations using the block address of the storage block to perform any one of read / write compensation management, wear leveling management, and bad block management.

[0128] In some embodiments, the controller is configured to apply the same read / write pressure conditions to each of the storage cells within the storage block, and to apply different read / write pressure conditions to different units of the storage blocks, taking at least one of the logic blocks as the unit.

[0129] In some embodiments, each of the memory cells within a memory block has substantially the same resistance-capacitance (RC) characteristics relative to the driver as described above.

[0130] The operations for these configurations have already been explained in the corresponding operation methods described above, so they will not be repeated here.

[0131] The storage system disclosed in this application can also achieve the beneficial effects described above for various operating methods and configurations. That is, it can not only reduce the impact of bias drift and help reduce the bias drift problem, but also support a longer power-on data retention time, and simplify the read / write circuit, test and analysis complexity, and system management complexity, which will not be elaborated here.

[0132] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.< / n> < / m>

Claims

1. A method of operating a storage system, the storage system comprising a memory, the memory comprising a storage array, characterized in that, The operation method includes: The logical address for receiving data, wherein the logical address includes a block address and a cell address; Based on the logical address, a selected storage block mapped to the block address from a plurality of storage blocks within the storage array is selected, as well as a selected storage cell within the selected storage block mapped to the cell address. Each of the plurality of storage blocks includes a plurality of storage cells arranged in a matrix in locally consecutive adjacent row lines and locally consecutive adjacent column lines of the storage array. The row and column order of the plurality of storage cells corresponds to the consecutive ascending address order of the logical address. Read and write pressure is applied to each of the selected memory cells, wherein the same read and write pressure conditions are applied to each of the selected memory cells within the same memory block, and different read and write pressure conditions are applied to the selected memory cells in different memory blocks based on the line distance between each memory block and the memory driver.

2. The operating method as described in claim 1, characterized in that, The memory includes multiple storage arrays, each containing n rows by m columns of storage cells. The storage block contains N rows by M columns of storage cells, where N and M are positive integers greater than 2, and N is equal to or not equal to M, and n is equal to N. 2 m equals M 2 .

3. The operating method as described in claim 1, characterized in that, The operation method further includes setting the block address in the high-order bits of the logical address and setting the unit address in the low-order bits of the logical address relative to the high-order bits.

4. The operating method as described in claim 1, characterized in that, The operation method also includes performing any one of the following management methods on a per-block basis: read / write compensation management, wear leveling management, and bad block management.

5. The operating method as described in claim 1, characterized in that, The storage unit is a phase-change storage unit.

6. A storage system, characterized in that, include: Memory, including a memory array consisting of multiple memory cells; as well as A controller electrically connected to the memory for controlling the memory, and the controller being configured to perform the operating method as described in any one of claims 1 to 5.

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