Relay protection and exit matrix detection system, method and device and storage medium

Abstract

The invention discloses a relay protection and exit matrix detection system, method and device and a storage medium. The relay protection and exit matrix detection system comprises an input module, a processing module, an instruction generation module and an error analysis module. The input module is used for receiving an input signal from the exit matrix and sending the input signal to the processing module; the processing module is used for processing and analyzing the input signal and sending a processing result to the error analysis module; the instruction generation module is used for receiving user input, generating an error analysis instruction according to the user input and sending the error analysis instruction to the error analysis module; and the error analysis module is used for generating an error index according to the processing result and the error analysis instruction and generating a final processing result according to the error index. The method pays attention to errors caused by different input interfaces, and is beneficial to improving the accuracy of a detection result.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of power systems, and in particular to a relay protection and export matrix detection system and detection method. Background Art

[0002] In power systems, the outlet matrix typically refers to the status control and monitoring matrix for control devices such as circuit breakers and switches. These devices are responsible for functions such as current flow in and out of the power system, line switching, and load regulation. Outlet matrix monitoring is primarily used to monitor the status of these devices, ensure their proper operation, and perform protection or control operations when necessary.

[0003] At present, when the existing technology detects relay protection and output matrix detection systems, it does not pay attention to the errors caused by different input interfaces, and there is a problem that the accuracy of the detection results is not high enough. Summary of the Invention

[0004] The present invention provides a relay protection and outlet matrix detection system and a detection method. When detecting the relay protection and outlet matrix detection system, attention is paid to errors caused by different input interfaces, which is conducive to improving the accuracy of the detection results.

[0005] According to one aspect of the present invention, a relay protection and outlet matrix detection system is provided, the relay protection and outlet matrix detection system comprising: an input module, a processing module, an instruction generation module and an error analysis module;

[0006] The input module is connected to the processing module, the input module is used to receive input signals from the output matrix and send them to the processing module, the processing module is used to process and analyze the input signals and send the processing results to the error analysis module;

[0007] The instruction generation module is connected to the error analysis module, and is used to receive user input, generate error analysis instructions according to the user input, and send the instructions to the error analysis module;

[0008] The processing module is connected to the error analysis module, and the error analysis module is used to generate an error index according to the processing result and the error analysis instruction, and generate a final processing according to the error index.

[0009] Optionally, it further includes: a display module;

[0010] The display module is connected to the processing module and the error analysis module, and is used to display the processing result of the processing module and the final processing result of the error analysis module.

[0011] Optionally, the input module includes: a signal acquisition unit, a voltage detection unit, a current detection unit, a high impedance input unit and an internal transmission unit;

[0012] The signal acquisition unit is used to collect the outputs of each relay protection device and the output matrix as input signals. The signal acquisition unit is connected to the voltage detection unit and the current detection unit. The voltage detection unit is used to detect the voltage of the input signal and send it to the error analysis module. The current detection unit is used to detect the current of the input signal and send it to the error analysis module.

[0013] The high-impedance input unit is connected to the signal acquisition unit and the internal transmission unit, the internal transmission unit is connected to the processing module, the high-impedance input unit is used to input the input signal into the internal transmission unit, and the internal transmission unit is used to transmit the input signal to the processing module.

[0014] Optionally, the error analysis module includes: a data receiving unit, an error index calculation unit and a processing result generation unit;

[0015] The data receiving unit is connected to the voltage detection unit and the current detection unit, and is used to receive information related to the voltage and current of the input signal from the input module, and receive information related to the processing result from the processing module;

[0016] The error index calculation unit is used to calculate the error index according to the relevant information of the voltage and current of the input signal received by the data receiving unit;

[0017] The processing result generating unit is configured to generate a final processing result according to the acquired error indicator and the related information of the processing result received by the data receiving unit.

[0018] Optionally, the high-impedance input unit includes: the high-impedance input interface, an indicator light, and a protection circuit;

[0019] The number of the high-impedance input interfaces is 16, and the number of the indicator lights is 16. The indicator lights are arranged on the high-impedance input interfaces and correspond one to one therewith, and the indicator lights are used to display the switch status of the high-impedance input interfaces;

[0020] The protection circuit is arranged between the signal output end of the high-impedance input interface and the input end of the internal transmission unit. The protection circuit includes a diode or a fuse. The protection circuit is used to protect the internal transmission unit from overvoltage or transient current.

[0021] Optionally, the processing module includes: a data processing unit, an algorithm storage unit and a data analysis unit;

[0022] The data processing unit is used to process the input signal transmitted to the processing module through the internal transmission unit, the algorithm storage unit is used to store the algorithms for performing various detections on the outlet matrix, and the data analysis unit is used to schedule the algorithms stored in the algorithm storage unit according to user instructions and analyze various data required by the user based on the data processed by the data processing unit to obtain processing results.

[0023] Optionally, the data processing unit includes: a filter, a signal amplifier and an analog-to-digital converter;

[0024] The filter is used to filter the input signal, the signal amplifier is used to amplify the input signal, and the analog-to-digital converter is used to convert the format of the input signal.

[0025] According to another aspect of the present invention, a relay protection and outlet matrix detection method is provided. The relay protection and outlet matrix detection method is applied to the relay protection and outlet matrix detection system described in the above aspect. The detection method includes:

[0026] The input module responds to the user input detection instruction and receives the corresponding input signal from the relay protection device and its output matrix;

[0027] The input signal is transmitted to the processing module through the input module, and the processing module processes the input signal to obtain a processing result;

[0028] The processing module responds to the interface change instruction input by the user to change the interface through which the input signal is input;

[0029] The processing module processes the input signal after the interface is replaced to obtain a processing result after the interface is replaced, and determines whether a specified number of adjustments is reached to obtain a first determination result;

[0030] If the first judgment result is that the specified number of adjustments has not been reached, returning to continue executing the interface when the user changes the input signal input;

[0031] If the first judgment result is that the specified number of adjustments has been reached, the instruction generation module receives the error analysis instruction input by the user, the error analysis module calculates the error index, and generates a final processing result according to the error index.

[0032] Optionally, the error analysis module calculates an error index, and generates a final processing result according to the error index, including:

[0033] The data receiving unit receives information related to the input signal voltage and the input signal current from the input module, and receives information related to the processing result from the processing module;

[0034] The error index calculation unit calculates the interface error index of each interface according to the processing results before and after the interface is replaced;

[0035] The error index calculation unit obtains a relationship between voltage and current and the interface error index based on past data;

[0036] The error index calculation unit calculates the corrected interface error index of each interface based on the current input signal current and the relevant information of the input signal voltage;

[0037] The processing result generating unit calculates a final processing result according to the corrected interface error index and related information of the processing result.

[0038] According to another aspect of the present invention, an electronic device is provided, comprising:

[0039] one or more processors;

[0040] a memory for storing one or more programs;

[0041] When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any embodiment of the present invention.

[0042] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the method according to any embodiment of the present invention is implemented.

[0043] The technical solution of the embodiment of the present invention obtains the error indicators of different input interfaces and corrects them to obtain the final processing result, which is conducive to analyzing the processing results and errors of each interface, understanding and analyzing the impact of the errors of different input interfaces on the processing results, and obtaining the final processing result by integrating the errors of each interface, which is conducive to improving the accuracy of the final processing result and improving the degree of fit between the processing result and the actual situation. In summary, the present invention solves the problem that the existing technology does not pay attention to the errors caused by different input interfaces when detecting relay protection and export matrix detection systems, and the detection result accuracy is not high enough.

[0044] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 1 is a schematic structural diagram of a relay protection and output matrix detection system provided according to an embodiment of the present invention;

[0047] Figure 2 is a flow chart of a relay protection and exit matrix detection method provided according to an embodiment of the present invention;

[0048] Figure 3 is a flow chart of another relay protection and exit matrix detection method provided according to an embodiment of the present invention;

[0049] Figure 4 is a relationship diagram among a corrected interface error indicator, an interface error indicator, and a second interface error indicator provided according to an embodiment of the present invention;

[0050] Figure 5 is a structural diagram of an electronic device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] Figure 1 This is a schematic diagram of a relay protection and output matrix detection system according to an embodiment of the present invention. Figure 1 , an embodiment of the present invention provides a relay protection and export matrix detection system, the relay protection and export matrix detection system includes: an input module 10, a processing module 20, an instruction generation module 40 and an error analysis module 50;

[0054] The input module 10 is connected to the processing module 20. The input module 10 is used to receive input signals from the output matrix and send them to the processing module 20. The processing module 20 is used to process and analyze the input signals and send the processing results to the error analysis module 50.

[0055] The instruction generation module 40 is connected to the error analysis module 50. The instruction generation module 40 is used to receive user input, generate error analysis instructions according to the user input, and send them to the error analysis module 50;

[0056] The processing module 20 is connected to the error analysis module 50 . The error analysis module 50 is used to generate an error index according to the processing result and the error analysis instruction, and generate a final processing result according to the error index.

[0057] Specifically, the user inputs a detection instruction. After receiving the user detection instruction, the input module 10 receives the corresponding input signal from the relay protection device and its output matrix. The input signal is transmitted to the processing module 20 through the input module 10. The processing module 20 processes the input signal to obtain a processing result. If the user changes the interface when inputting the input signal, the processing module 20 processes the input signal after the interface is changed, obtains the processing result after the interface is changed, and determines whether the specified number of adjustments has been reached. If so, the user inputs an error analysis instruction through the instruction generation module 40. The error analysis module 50 calculates the error index and generates the final processing result based on the error index. If not, the process returns to continue executing the interface operation when the user changes the input signal input.

[0058] By considering the reliability of the input signal to weight the corrected error index and obtain the final processing result, it is beneficial to consider the impact of the input signal on the error calculation and processing results during the propagation process. By considering this impact to obtain the final processing result, it is beneficial to the accuracy of the final processing result and improve the degree of fit between the processing result and the actual situation.

[0059] The technical solution of the embodiment of the present invention obtains the error indicators of different input interfaces and corrects them to obtain the final processing result, which is conducive to analyzing the processing results and errors of each interface, understanding and analyzing the impact of the errors of different input interfaces on the processing results, and obtaining the final processing result by integrating the errors of each interface, which is conducive to improving the accuracy of the final processing result and improving the degree of fit between the processing result and the actual situation. In summary, the present invention solves the problem that the existing technology does not pay attention to the errors caused by different input interfaces when detecting relay protection and export matrix detection systems, and the detection result accuracy is not high enough.

[0060] Continue to refer Figure 1 , optionally, further comprising a display module 30;

[0061] The display module 30 is connected to the processing module 20 and the error analysis module 50 . The display module 30 is used to display the processing result of the processing module 20 and the final processing result of the error analysis module 50 .

[0062] Specifically, the processing module 20 is used to process and analyze the input signal and send the processing result to the display module 30. The error analysis module 50 generates an error index based on the processing result and the error analysis instruction, generates a final processing result based on the error index and sends it to the display module 30. The display module 30 displays the processing result of the processing module 20 and the final processing result of the error analysis module 50.

[0063] Optionally, the input module includes: a signal acquisition unit, a voltage detection unit, a current detection unit, a high impedance input unit and an internal transmission unit;

[0064] The signal acquisition unit is used to collect the outputs of each relay protection device and the output matrix as input signals. The signal acquisition unit is connected to the voltage detection unit and the current detection unit. The voltage detection unit is used to detect the voltage of the input signal and send it to the error analysis module. The current detection unit is used to detect the current of the input signal and send it to the error analysis module.

[0065] The high-impedance input unit is connected to the signal acquisition unit and the internal transmission unit. The internal transmission unit is connected to the processing module. The high-impedance input unit is used to input the input signal into the internal transmission unit. The internal transmission unit is used to transmit the input signal to the processing module.

[0066] Optionally, the error analysis module includes: a data receiving unit, an error index calculation unit and a processing result generation unit;

[0067] The data receiving unit is connected to the voltage detection unit and the current detection unit, and is used to receive information related to the voltage and current of the input signal from the input module, and receive information related to the processing result from the processing module;

[0068] The error index calculation unit is used to calculate the error index according to the voltage and current related information of the input signal received by the data receiving unit;

[0069] The processing result generating unit is used to generate a final processing result according to the acquired error index and the relevant information of the processing result received by the data receiving unit.

[0070] Optionally, the high-impedance input unit includes: a high-impedance input interface, an indicator light, and a protection circuit;

[0071] There are 16 high-impedance input interfaces and 16 indicator lights. The indicator lights are set at the high-impedance input interfaces and correspond one to one with them. The indicator lights are used to display the switch status of the high-impedance input interfaces.

[0072] The protection circuit is arranged between the signal output end of the high-impedance input interface and the input end of the internal transmission unit. The protection circuit includes a diode or a fuse. The protection circuit is used to protect the internal transmission unit from overvoltage or transient current.

[0073] Optionally, the processing module includes: a data processing unit, an algorithm storage unit and a data analysis unit;

[0074] The data processing unit is used to process the input signal transmitted to the processing module through the internal transmission unit. The algorithm storage unit is used to store the algorithms for performing various detections on the export matrix. The data analysis unit is used to schedule the algorithms stored in the algorithm storage unit according to user instructions and analyze various data required by the user based on the data processed by the data processing unit to obtain the processing results.

[0075] Optionally, the data processing unit includes: a filter, a signal amplifier and an analog-to-digital converter;

[0076] The filter is used to filter the input signal, the signal amplifier is used to amplify the input signal, and the analog-to-digital converter is used to convert the format of the input signal.

[0077] The embodiment of the present invention further provides a relay protection and outlet matrix detection method, which is applied to the relay protection and outlet matrix detection system in any embodiment of the present invention. Figure 2 This is a flow chart of a relay protection and output matrix detection method provided according to an embodiment of the present invention, with reference to Figure 2 , the relay protection and export matrix detection method includes the following steps:

[0078] S110 , the input module responds to a user input detection instruction and receives a corresponding input signal from the relay protection device and its output matrix.

[0079] S120 , the input signal is transmitted to the processing module through the input module, and the processing module processes the input signal to obtain a processing result.

[0080] S130: The processing module responds to the interface change instruction input by the user and changes the interface through which the input signal is input.

[0081] S140: The processing module processes the input signal after the interface is replaced to obtain a processing result after the interface is replaced, and determines whether a specified number of adjustments is reached to obtain a first determination result.

[0082] Specifically, the designated number of adjustments is set by those skilled in the art and the maximum value does not exceed the number of interfaces included in the detection system.

[0083] S150: If the first judgment result is that the specified number of adjustments has not been reached, return to the interface for continuing to execute the user to change the input signal input.

[0084] S160: If the first judgment result is that the specified number of adjustments has been reached, the instruction generation module receives the error analysis instruction input by the user, the error analysis module calculates the error index, and generates a final processing result according to the error index.

[0085] Specifically, calculating the error index and obtaining the final processing result is helpful to reduce the detection error. Compared with the preliminary processing result and the secondary processing result, the final processing result can more accurately reflect the actual situation of the detected relay protection equipment and the outlet matrix.

[0086] The final processing result is generally the output action time of the relay protection device and the output matrix. The output action time is the time required from the triggering of the fault simulation signal to the output signal of the relay protection device and the output matrix. The fault simulation signal can be generated by the corresponding fault simulation signal generator and the triggering moment is recorded.

[0087] The relay protection and exit matrix detection method provided in the embodiment of the present invention is used to control the relay protection and exit matrix detection system provided in any embodiment of the present invention. Therefore, the relay protection and exit matrix detection method provided in the embodiment of the present invention also has the beneficial effects described in the above embodiments, which will not be repeated here.

[0088] On the basis of the above embodiments, the embodiment of the present invention further refines step S160, which is described in detail below, but is not intended to limit the present invention.

[0089] Figure 3is a flowchart of another relay protection and output matrix detection method provided according to an embodiment of the present invention, with reference to Figure 3 , step S160 includes:

[0090] S161 , a data receiving unit receives information related to an input signal voltage and an input signal current from an input module, and receives information related to a processing result from a processing module.

[0091] S162. The error index calculation unit calculates the interface error index of each interface according to the processing results before and after the interface is replaced.

[0092] Specifically, the interface error index can be calculated according to the following formula:

[0093] JMIS=T-TT+DE-de

[0094] Among them, JMIS is the first interface error index, which is used to characterize the error degree of each interface in calculating the export action time. The larger the index value, the greater the error degree. T is the average export action time detected by each interface, TT is the export action time detected by the interface, DE is the average delay value detected by each interface, de is the delay value detected by the interface, and the delay value is the time taken for the input signal to be transmitted from the interface to the processing module.

[0095] S163. The error index calculation unit obtains a relationship between the voltage and current and the interface error index based on past data.

[0096] Specifically, the relationship can be obtained by fitting past data using a linear model. The past data is the past input signal voltage and the past input signal current of the interface and the past interface error index calculated by the above formula. The obtained relationship is recorded as jmis=F1(U,I), where F1() is the corresponding functional relationship, jmis is the second interface error index obtained through the functional relationship, U is the input signal voltage, and I is the input signal current.

[0097] S164 , the error index calculation unit calculates the corrected interface error index of each interface based on the current input signal current and the related information of the input signal voltage.

[0098] Specifically, the corrected interface error index can be calculated according to the following formula:

[0099] XJMIS=0.5*k1*JMIS′+0.5*k2*F1(U now ,I now )

[0100]

[0101] Among them, XJMIS is the interface error index after correction of the interface, JMIS′ is the interface error index of the interface, k1 is the current data weight, k2 is the past data weight, U now is the current input signal voltage of the interface, I now The current input signal current of the interface.

[0102] e is a natural constant, N is the total number of interfaces used in the detection process, JMIS n is the first interface error index corresponding to the nth interface used, JMIS 均 is the average value of the first interface error index of each interface; M is the number of groups of past data used to obtain the second interface error index, jmis m JMIS is the second interface error index obtained by the functional relationship in the mth group of past data. m jmis is the first interface error indicator corresponding to the interface in the mth group of past data. 均 is the mean of all second interface error indicators obtained for this interface in M groups of past data.

[0103] Figure 4 is a relationship diagram between a corrected interface error indicator, an interface error indicator, and a second interface error indicator provided according to an embodiment of the present invention, such as Figure 4 As shown, Figure 4 When k1 is 0.6 and k2 is 0.4, the corrected interface error index and interface error index (through F1 (U now ,I now )The relationship diagram between the second interface error indicators calculated.

[0104] S165. The processing result generating unit calculates the final processing result according to the corrected interface error index and the related information of the processing result.

[0105] Specifically, the final processing result can be calculated according to the following formula:

[0106]

[0107] Among them, FIN is the final processing result, T is the average export action time detected by each interface, N is the total number of interfaces used in the detection process, XJMIS n is the interface error index after correction of the nth interface, K n is the signal confidence index of the nth interface.

[0108] The following is the procedure used to calculate the final processing results:

[0109] def calculate_FIN(T, N, XJMIS, K):

[0110] #Calculate Σ(XJMIS_n*K_n)

[0111] weighted_sum=sum(xjmis*k for xjmis,k in zip(XJMIS,K))

[0112] #Calculate FIN

[0113] FIN=T-(1 / N)*weighted_sum

[0114] return FIN

[0115] # Sample input data

[0116] T=100#Average value of action time (example)

[0117] N = number of 3# interfaces (example)

[0118] XJMIS=[0.1, 0.05, 0.02]#Corrected error index for each interface (example)

[0119] K = [0.9, 0.8, 0.85] # Signal confidence index for each interface (example)

[0120] #Calculate FIN

[0121] FIN=calculate_FIN(T,N,XJMIS,K)

[0122] print("Final processing result FIN:", FIN)

[0123] The signal confidence index of the interface can be calculated according to the following formula:

[0124]

[0125] Among them, K n SNR is the signal confidence index of the nth interface, which is used to characterize the closeness of the signal transmitted by the interface to the ideal signal (a signal without any distortion, noise or interference, which meets expectations and perfectly presents the required characteristics). The closer the index value is to 1, the greater the closeness; n is the signal-to-noise ratio of the signal at the Nth interface, snr n is the ideal signal-to-noise ratio of the detection system, which is set by those skilled in the art between 5 dB and 20 dB according to the quality of the detection system, e is a natural constant, and t n is the number of fluctuations of the signal of the nth interface in one detection cycle, tmax is the maximum number of fluctuations in the signals of each interface recorded in the past within a detection cycle; time is the duration of a detection cycle, t 1x is the starting time of the xth signal fluctuation, t 2x is the end time of the xth signal fluctuation, FD x (t) is the signal voltage value at time t when the signal fluctuates for the xth time, and FD is the normal voltage value when the signal does not fluctuate.

[0126] It is worth noting that the above method is mainly for DC input signals. For AC input signals, replacing U in the formula jmis=F1(U,I) with the voltage effective value of the AC input signal and replacing I with the current effective value of the AC input signal can obtain the corresponding corrected interface error index, but K n The calculation method of is not universal for AC input signals. Therefore, when the input signal is an AC input signal, the confidence of the signal is not considered. Let K n It is always equal to 1, so that the final processing result can be obtained through calculation.

[0127] This embodiment should be understood to include all the features of any of the aforementioned embodiments and to be further improved thereon. In the aforementioned embodiments, the method for obtaining the final processing result is mainly applicable to DC input signals. For AC input signals, U in the formula jmis=F1(U,I) is replaced with the effective value of the voltage of the AC input signal and I is replaced with the effective value of the current of the AC input signal. The final processing result can be obtained in the manner of the aforementioned embodiment. However, such processing does not specifically consider the AC input signal and still has certain errors. Therefore, a method for obtaining the final processing result when the input signal is an AC signal is proposed to reduce the error, comprising the following steps:

[0128] STEP 1: Calculate the interface error index according to the method of the above embodiment.

[0129] STEP 2: The error index calculation unit obtains the relationship between the voltage effective value, current effective value, frequency of the AC input signal and the interface error index based on past data.

[0130] Specifically, the relationship can be obtained by fitting past data using a linear model. The past data are the voltage effective value, current effective value, frequency of the past AC input signal of the interface and the past interface error index calculated by the above formula. The obtained relationship is recorded as gmis=F2(u, i, f), where F2() is the corresponding functional relationship, gmis is the third interface error index obtained through the functional relationship, u is the voltage effective value of the AC input signal, i is the current effective value of the AC input signal, and f is the frequency of the AC input signal.

[0131] STEP 3: The error index calculation unit calculates the corrected interface error index of each interface when the input signal is an AC input signal based on the current AC input signal.

[0132] When the input signal is an AC input signal, the corrected interface error index can be calculated according to the following formula:

[0133] xjmis=0.5*k3*JMIS+0.5*k4*F2(u now ,u now ,f now )

[0134]

[0135] Among them, xjmis is the interface error index after correction when the input signal is AC input signal, k3 is the current data weight of AC input, k4 is the past data weight of AC input, u now The voltage RMS value of the current AC input signal of the interface, i now is the effective current value of the current AC input signal of the interface, f now The frequency of the current AC input signal of the interface.

[0136] e is a natural constant, N is the total number of interfaces used in the detection process, JMIS n is the first interface error index corresponding to the nth interface used, JMIS 均 is the average value of the first interface error index of each interface; P is the number of groups of past data used to obtain the third interface error index, gmis p JMIS is the third interface error index obtained by the functional relationship in the pth group of past data. p is the first interface error index corresponding to the interface in the pth group of past data, gmis 均 is the mean of all third interface error indicators obtained for this interface in the past data of group P.

[0137] STEP 4: The processing result generating unit calculates the final processing result according to the corrected interface error index when the input signal is an AC input signal.

[0138] When the input signal is an AC input signal, the final processing result fin can be calculated according to the following formula:

[0139]

[0140] Among them, T is the average export action time detected by each interface, N is the total number of interfaces used in the detection process, xjmis nWhen the input signal is an AC input signal, the interface error index after correction of the nth interface, Q n It is the signal confidence index of the nth interface when the input signal is an AC input signal.

[0141] The interface confidence index can be calculated according to the following formula:

[0142]

[0143] Among them, Q n SNR is the signal confidence index of the nth interface when the input signal is an AC input signal. It is used to characterize the degree of closeness between the signal transmitted by the interface and the ideal signal (a signal without any distortion, noise or interference, in line with expectations, and perfectly presenting the required characteristics) when the input signal is an AC input signal. The closer the index value is to 1, the greater the closeness; n is the signal-to-noise ratio of the signal at the Nth interface, snr n is the ideal signal-to-noise ratio of the detection system, which is set by those skilled in the art between 5 dB and 20 dB according to the quality of the detection system, e is a natural constant, and ZC n is the number of noise occurrences of the signal of the nth interface in a detection cycle, ZC max is the maximum number of noise occurrences in one detection cycle of the signals of each interface recorded in the past; Y is the number of phase sampling points, is the phase of the y-th phase sampling point, is the phase of the y-1th phase sampling point, is the average value of the phase difference between each sampling point and its adjacent sampling point, X is the number of peak values of the AC input signal, A x is the absolute value of the xth peak value of the AC input signal, and A is the average absolute value of each peak value of the AC input signal.

[0144] The beneficial effects of this embodiment are: by considering the frequency of the AC input signal to calculate the third interface error index, it is beneficial to improve the accuracy of error correction when the input signal is an AC signal, by using Q n To obtain the final processing result, the influence of the AC signal on the processing result is taken into account, thereby improving the accuracy of the final processing result.

[0145] Figure 5A schematic diagram of the structure of an electronic device 1 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0146] like Figure 5 As shown, electronic device 1 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to at least one processor 11. The memory stores a computer program that can be executed by the at least one processor, and processor 11 can perform various appropriate actions and processes according to the computer program stored in read-only memory (ROM) 12 or the computer program loaded from storage unit 18 into random access memory (RAM) 13. Various programs and data required for the operation of electronic device 1 can also be stored in RAM 13. Processor 11, ROM 12, and RAM 13 are connected to each other via bus 14. Input / output (I / O) interface 15 is also connected to bus 14.

[0147] Multiple components in electronic device 1 are connected to I / O interface 15, including an input unit 16, such as a keyboard, mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, optical disk, etc.; and a communication unit 19, such as a network card, modem, wireless communication transceiver, etc. Communication unit 19 allows electronic device 1 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0148] The processor 11 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the relay protection and outlet matrix detection methods.

[0149] In some embodiments, the relay protection and outlet matrix detection method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 1 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the relay protection and outlet matrix detection method described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the relay protection and outlet matrix detection method in any other appropriate manner (for example, by means of firmware).

[0150] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0151] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0152] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0153] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0154] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0155] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0156] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0157] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A relay protection and outlet matrix detection system, characterized in that: include: Input module, processing module, instruction generation module and error analysis module; The input module is connected to the processing module, the input module is used to receive input signals from the output matrix and send them to the processing module, the processing module is used to process and analyze the input signals and send the processing results to the error analysis module; The instruction generation module is connected to the error analysis module, and is used to receive user input, generate error analysis instructions according to the user input, and send the instructions to the error analysis module; The processing module is connected to the error analysis module, and the error analysis module is used to generate an error index according to the processing result and the error analysis instruction, and generate a final processing result according to the error index.

2. The system according to claim 1, wherein: Also includes: Display module; The display module is connected to the processing module and the error analysis module, and is used to display the processing result of the processing module and the final processing result of the error analysis module.

3. The system according to claim 1, wherein: The input module includes: a signal acquisition unit, a voltage detection unit, a current detection unit, a high impedance input unit and an internal transmission unit; The signal acquisition unit is used to collect the outputs of each relay protection device and the output matrix as input signals. The signal acquisition unit is connected to the voltage detection unit and the current detection unit. The voltage detection unit is used to detect the voltage of the input signal and send it to the error analysis module. The current detection unit is used to detect the current of the input signal and send it to the error analysis module. The high-impedance input unit is connected to the signal acquisition unit and the internal transmission unit, the internal transmission unit is connected to the processing module, the high-impedance input unit is used to input the input signal into the internal transmission unit, and the internal transmission unit is used to transmit the input signal to the processing module.

4. The system according to claim 3, characterized in that The error analysis module includes: a data receiving unit, an error index calculation unit and a processing result generation unit; The data receiving unit is connected to the voltage detection unit and the current detection unit, and is used to receive information related to the voltage and current of the input signal from the input module, and receive information related to the processing result from the processing module; The error index calculation unit is used to calculate the error index according to the relevant information of the voltage and current of the input signal received by the data receiving unit; The processing result generating unit is configured to generate a final processing result according to the acquired error indicator and the related information of the processing result received by the data receiving unit.

5. The system according to claim 3, wherein: The high-impedance input unit includes: a high-impedance input interface, an indicator light, and a protection circuit; The number of the high-impedance input interfaces is 16, and the number of the indicator lights is 16. The indicator lights are arranged on the high-impedance input interfaces and correspond one to one therewith, and the indicator lights are used to display the switch status of the high-impedance input interfaces; The protection circuit is arranged between the signal output end of the high-impedance input interface and the input end of the internal transmission unit. The protection circuit includes a diode or a fuse. The protection circuit is used to protect the internal transmission unit from overvoltage or transient current.

6. The system according to claim 3, wherein: The processing module includes: a data processing unit, an algorithm storage unit and a data analysis unit; The data processing unit is used to process the input signal transmitted to the processing module through the internal transmission unit, the algorithm storage unit is used to store the algorithms for performing various detections on the outlet matrix, and the data analysis unit is used to schedule the algorithms stored in the algorithm storage unit according to user instructions and analyze various data required by the user based on the data processed by the data processing unit to obtain processing results.

7. The system according to claim 6, characterized in that The data processing unit includes: a filter, a signal amplifier and an analog-to-digital converter; The filter is used to filter the input signal, the signal amplifier is used to amplify the input signal, and the analog-to-digital converter is used to convert the format of the input signal.

8. A relay protection and output matrix detection method, characterized in that: Applicable to the relay protection and outlet matrix detection system according to any one of claims 1 to 7, the detection method comprising: The input module responds to the user input detection instruction and receives the corresponding input signal from the relay protection device and its output matrix; The input signal is transmitted to the processing module through the input module, and the processing module processes the input signal to obtain a processing result; The processing module responds to the interface change instruction input by the user to change the interface through which the input signal is input; The processing module processes the input signal after the interface is replaced to obtain a processing result after the interface is replaced, and determines whether a specified number of adjustments is reached to obtain a first determination result; If the first judgment result is that the specified number of adjustments has not been reached, returning to continue executing the interface when the user changes the input signal input; If the first judgment result is that the specified number of adjustments has been reached, the instruction generation module receives the error analysis instruction input by the user, the error analysis module calculates the error index, and generates a final processing result according to the error index.

9. The method according to claim 8, characterized in that The error analysis module calculates the error index and generates a final processing result according to the error index, including: The data receiving unit receives information related to the input signal voltage and the input signal current from the input module, and receives information related to the processing result from the processing module; The error index calculation unit calculates the interface error index of each interface according to the processing results before and after the interface is replaced; The error index calculation unit obtains a relationship between voltage and current and the interface error index based on past data; The error index calculation unit calculates the corrected interface error index of each interface based on the current input signal current and the relevant information of the input signal voltage; The processing result generating unit calculates a final processing result according to the corrected interface error index and the related information of the processing result.

10. An electronic device, characterized in that: include: one or more processors; a memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 8 to 9.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 8 to 9 is implemented.

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