Pin driving circuit and testing device

Abstract

The invention discloses a pin driving circuit and a testing device. The pin driving circuit comprises a signal input and output module, a first end of the signal input and output module is used for being coupled with a processing chip, and a second end of the signal input and output module is coupled with a tested chip; wherein the signal input and output module provides at least two signal paths, and each signal path is used for assisting the processing chip to test the tested chip; and the parameter measuring module is coupled with the tested chip and is used for testing the direct current parameter of the tested chip. Through the mode, the tested chip can be tested at low cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a pin driving circuit and a testing device. Background Art

[0002] The pin driver circuit designs for semiconductor test systems fall into two general categories: 1) Single-chip ATE (Automatic Test Equipment) solutions: This single chip includes the driver, comparator, and parameter measurement unit. While the driver's drive capability supports most existing chip voltages, the cost per chip is high. 2) Discrete chip solutions: The driver and comparator are implemented using an ATE chip, while the parameter measurement is implemented using a parameter measurement chip and switches.

[0003] Both of the above solutions require a large number of ATE chips. While integrated ATE chips offer superior performance, they introduce other system design challenges: 1) ATE chips are expensive, and using a large number of them means the system cost increases exponentially; 2) ATE chips consume a lot of power, significantly increasing the system's thermal design requirements; and 3) ATE chips are large, requiring a large layout area. Using a large number of ATE chips increases the PCB size, increasing costs and also increasing the system hardware size. Summary of the Invention

[0004] The pin drive circuit and test device provided in this application can test the chip under test at a low cost.

[0005] In a first aspect, the present application provides a pin drive circuit, which includes: a signal input and output module, wherein the first end of the signal input and output module is used to couple to a processing chip, and the second end of the signal input and output module is coupled to a chip under test; wherein the signal input and output module provides at least two signal paths, each signal path is used to assist the processing chip in testing the chip under test; and a parameter measurement module, coupled to the chip under test, for testing the DC parameters of the chip under test.

[0006] Among them, the signal input and output module includes: a first pin, the first pin is used to couple the processing chip; a driving circuit, the first end of the driving circuit is coupled to the first pin; a second pin, the second pin is used to couple the processing chip; a first impedance matching circuit, the first end of the first impedance matching circuit is coupled to the second pin; a path control circuit, the path control circuit is respectively coupled to the second end of the first impedance matching circuit, the second end of the driving circuit and the chip under test, and is used to provide at least two signal paths.

[0007] The driving circuit includes: a driving chip, a first end of the driving chip is coupled to the first pin; a second impedance matching circuit, a first end of the second impedance matching circuit is coupled to the second end of the driving chip, and a second end of the second impedance matching circuit is coupled to the path control circuit.

[0008] Among them, at least two signal paths include a first signal path and a second signal path; wherein, the signal output path in the first signal path is formed based on the first pin, the driving circuit, and the path control circuit; the signal input path in the first signal path is formed based on the path control circuit, the first impedance matching circuit, and the second pin; the signal input path and the signal output path in the second signal path are both formed based on the path control circuit, the first impedance matching circuit, and the second pin.

[0009] The signal amplitude provided by the signal output path of the first signal path is greater than the signal amplitude provided by the signal output path of the second signal path.

[0010] The signal sampling function of the chip under test is realized through the path control circuit, the first impedance matching circuit and the second pin.

[0011] The parameter measurement module includes: a path switch matrix, a first end of the path switch matrix is coupled to the chip under test; and a parameter measurement unit, the parameter measurement unit is coupled to a second end of the path switch matrix.

[0012] In response to outputting a command signal from any one of the at least two signal paths to the chip under test, the chip under test is placed in a state corresponding to the command signal.

[0013] In a second aspect, the present application provides a testing device, which includes a processing chip and a pin driving circuit as provided in the first aspect.

[0014] Among them, the processing chip is an FPGA chip, an MCU chip or a CLPD chip.

[0015] The beneficial effects of the present application are: different from the prior art, the pin drive circuit and test device provided by the present application, the pin drive circuit includes: a signal input and output module, the first end of the signal input and output module is used to couple the processing chip, and the second end of the signal input and output module is coupled to the chip under test; wherein, the signal input and output module provides at least two signal paths, each signal path is used to assist the processing chip in testing the chip under test; a parameter measurement module, coupled to the chip under test, is used to test the DC parameters of the chip under test, without the need to use an ATE chip, thereby avoiding the cost, heat dissipation, size and other problems caused by the ATE chip, and then using at least two signal paths and parameter measurement modules to achieve low-cost testing of the chip under test, such as DC parameters, AC parameters and functional item testing of the chip under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0017] Figure 1 This is a schematic structural diagram of an embodiment of a pin driving circuit provided by the present application;

[0018] Figure 2 is a structural diagram of another embodiment of the pin driving circuit provided by the present application;

[0019] Figure 3 is a structural diagram of an embodiment of a driving circuit provided by the present application;

[0020] Figure 4 This is a schematic structural diagram of an embodiment of a parameter measurement module provided by the present application;

[0021] Figure 5 is a structural diagram of another embodiment of the pin driving circuit provided by the present application;

[0022] Figure 6 It is a structural diagram of an embodiment of the testing device provided by this application. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0024] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0025] The pin drive circuit design of related semiconductor test systems can be roughly divided into two categories:

[0026] 1) Single ATE (Automatic Test Equipment) chip solution: A single chip includes a driver, comparator, and parameter measurement unit. The driver's drive capability can support most existing chip voltages, but the cost per chip is high.

[0027] 2) Use discrete chip construction solution: The driver and comparator use ATE chips, and parameter measurement uses parameter measurement chips and switches.

[0028] Both of the above solutions require a large number of ATE chips. While integrated ATE chips offer superior performance, they introduce other system design challenges: 1) ATE chips are expensive, and using a large number of them means the system cost increases exponentially; 2) ATE chips consume a lot of power, significantly increasing the system's thermal design requirements; and 3) ATE chips are large, requiring a large layout area. Using a large number of ATE chips increases the PCB size, increasing costs and also increasing the system hardware size.

[0029] Based on this, the pin driver circuit proposed in this application includes: a signal input / output module, a first end of which is coupled to a processing chip, and a second end of which is coupled to a chip under test; wherein the signal input / output module provides at least two signal paths, each of which is used to assist the processing chip in testing the chip under test; and a parameter measurement module, coupled to the chip under test, for testing the DC parameters of the chip under test, eliminating the need for an ATE chip. This avoids the cost, heat dissipation, and size issues associated with the ATE chip, thereby enabling low-cost testing of the chip under test, such as testing of its DC parameters, AC parameters, and functional items, using at least two signal paths and the parameter measurement module. For details, please refer to any of the following embodiments.

[0030] See Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a pin driving circuit according to an embodiment of the present invention. The pin driving circuit 100 includes a signal input and output module 10 and a parameter measurement module 20 .

[0031] The first end of the signal input / output module 10 is coupled to the processing chip 200, and the second end of the signal input / output module 10 is coupled to the chip under test 300. The signal input / output module 10 provides at least two signal paths, each of which is used to assist the processing chip 200 in testing the chip under test 300. In some embodiments, the components in the signal input / output module 10 are all discrete components.

[0032] The chip under test 300 can be any semiconductor chip. The processing chip 200 can be a chip built based on an FPGA. Therefore, the pins coupling the signal input / output module 10 to the processing chip 200 can be FPGA IO. In other embodiments, the processing chip 200 can be an MCU (Microcontroller Unit) or a CLPD (Complex Programmable Logic Device), and the pins coupling the signal input / output module 10 to the processing chip 200 can be MCU IO or CLPD IO.

[0033] The parameter measurement module 20 is coupled to the chip under test 300 and is used to test the DC parameters of the chip under test 300 .

[0034] In this embodiment, the signal input and output module 10 can provide at least two signal paths to meet the testing requirements of different chips under test 300 , thereby being able to test more types of chips under test 300 .

[0035] For example, different signal paths may provide different signal voltages to adapt to the test voltage requirements of different chips under test 300 .

[0036] For example, different signal paths may be used to form corresponding signal output paths and signal input paths, thereby performing AC parameter and functional item tests on the chip under test 300 .

[0037] Furthermore, a separate parameter measurement module 20 may be used to test the DC parameters of the chip under test 300 to reduce costs.

[0038] In this embodiment, the pin drive circuit 100 includes: a signal input and output module 10, a first end of the signal input and output module 10 is used to couple to the processing chip 200, and a second end of the signal input and output module 10 is coupled to the chip under test 300; wherein, the signal input and output module 10 provides at least two signal paths, each signal path is used to assist the processing chip 200 in testing the chip under test 300; a parameter measurement module 20, coupled to the chip under test 300, is used to test the DC parameters of the chip under test 300, without using an ATE chip, thereby avoiding the cost, heat dissipation, size and other problems caused by the ATE chip, and then using at least two signal paths and the parameter measurement module 20 to achieve low-cost testing of the chip under test 300, such as DC parameter, AC parameter and functional item testing of the chip under test 300.

[0039] See Figure 2 , Figure 2 FIG. 1 is a schematic diagram of another embodiment of a pin driving circuit provided by the present application. The pin driving circuit 100 includes: a signal input and output module 10 and a parameter measurement module 20 .

[0040] The signal input and output module 10 includes: a first pin 11 , a driving circuit 12 , a second pin 13 , a first impedance matching circuit 14 and a path control circuit 15 .

[0041] The first pin 11 is used to couple to the processing chip 200 .

[0042] A first terminal of the driving circuit 12 is coupled to the first pin 11 .

[0043] The second pin 13 is used to couple to the processing chip 200 .

[0044] The first end of the first impedance matching circuit 14 is coupled to the second pin 13. Impedance matching refers to the proper matching between a signal source or transmission line and a load. When the internal impedance of the signal source in the impedance matching circuit is equal in magnitude and phase to the characteristic impedance of the connected transmission line, or when the characteristic impedance of the transmission line is equal in magnitude and phase to the impedance of the connected load, the input or output of the transmission line is said to be in an impedance matching state, referred to as impedance matching. Otherwise, it is called impedance mismatch, sometimes simply referred to as matching or mismatching.

[0045] The path control circuit 15 is respectively coupled to the second end of the first impedance matching circuit 14 , the second end of the driving circuit 12 , and the chip under test 300 , for providing at least two signal paths.

[0046] The path control circuit 15 may be composed of a plurality of selector switches, thereby providing at least two signal paths through the cooperation of the selector switches. In some embodiments, the path control circuit 15 may be a signal relay, an analog switch chip solution, or a MEMS (micro-electromechanical system) switch.

[0047] See Figure 3 , Figure 3 1 is a schematic diagram of a driving circuit according to an embodiment of the present invention. The driving circuit 12 includes a driving chip 121 and a second impedance matching circuit 122 .

[0048] The first terminal of the driver chip 121 is coupled to the first pin 11. In some embodiments, the driver chip 121 may be a driver chip, a chip integrating a driver and a comparator, or a level conversion chip.

[0049] A first end of the second impedance matching circuit 122 is coupled to the second end of the driving chip 121 , and a second end of the second impedance matching circuit 122 is coupled to the path control circuit 15 .

[0050] Among them, at least two signal paths include a first signal path and a second signal path; wherein, the signal output path in the first signal path is formed based on the first pin 11, the driving circuit 12, and the path control circuit 15; the signal input path in the first signal path is formed based on the path control circuit 15, the first impedance matching circuit 14, and the second pin 13.

[0051] That is, the first signal path is a signal output path, and the output signal is output to the chip under test 300 via the first pin 11, the driving circuit 12, and the path control circuit 15. Then, the input signal fed back from the chip under test 300 is input to the processing chip 200 via the path control circuit 15, the first impedance matching circuit 14, and the second pin 13.

[0052] The signal input path and the signal output path in the second signal path are both formed based on the path control circuit 15 , the first impedance matching circuit 14 , and the second pin 13 .

[0053] That is, the second signal path is a signal output path, and the output signal is output to the chip under test 300 via the second pin 13, the first impedance matching circuit 14, and the path control circuit 15. Then, the input signal fed back from the chip under test 300 is input to the processing chip 200 via the path control circuit 15, the first impedance matching circuit 14, and the second pin 13.

[0054] The signal amplitude provided by the signal output path of the first signal path is greater than the signal amplitude provided by the signal output path of the second signal path.

[0055] Therefore, different signal paths can adapt to different test requirements and different chips 300 under test.

[0056] The signal sampling function of the chip under test 300 is realized through the path control circuit 15 , the first impedance matching circuit 14 , and the second pin 13 .

[0057] See Figure 4 , Figure 4 FIG. 2 is a schematic diagram of a parameter measurement module according to an embodiment of the present invention. The parameter measurement module 20 includes a path switch matrix 22 and a parameter measurement unit 21 .

[0058] A first terminal of the path switch matrix 22 is coupled to the chip under test 300. A parameter measurement unit 21 is coupled to a second terminal of the path switch matrix 22. The parameter measurement unit 21 can be a parameter measurement chip or a measurement unit constructed from discrete components. The path switch matrix 22 can be constructed from analog switches or relays.

[0059] In response to outputting a command signal from any one of the at least two signal paths to the chip under test 300 , the chip under test 300 is placed in a state corresponding to the command signal.

[0060] See Figure 5 , Figure 5 FIG1 is a schematic diagram of another embodiment of a pin driver circuit provided by the present application. The pin driver circuit 100 includes: a first pin 11, a driver chip 121, a second impedance matching circuit 122, a second pin 13, a first impedance matching circuit 14, a path control circuit 15, a path switch matrix 22, and a parameter measurement unit 21.

[0061] like Figure 5 As shown, the pin driving circuit 100 has two signal transmission paths.

[0062] 1) Signal path 1 (the first signal path mentioned above):

[0063] Signal output path: The signal passes through the first pin 11 , the driver chip 121 , the second impedance matching circuit 122 , and is then sent to the chip under test 300 by the path control circuit 15 .

[0064] Signal input path: The output signal of the chip under test 300 reaches the second pin 13 through the path control circuit 15 and the first impedance matching circuit 14 .

[0065] 1) Signal Path 2 (the second signal path mentioned above):

[0066] Signal output path: The signal passes through the second pin 13 and the first impedance matching circuit 14 , and is then sent to the chip under test 300 by the path control circuit 15 .

[0067] Signal input path: The output signal of the chip under test 300 reaches the second pin 13 through the path control circuit 15 and the first impedance matching circuit 14 .

[0068] Circuit function description:

[0069] 1) Output signals with different voltage amplitudes can be output:

[0070] The output signal can select a signal output path according to the working power supply of the chip under test 300.

[0071] The usage scenarios of the two paths are: when the signal voltage amplitude required by the chip under test 300 cannot be met by the second pin 13, the signal output module directly selects signal path one; when the signal voltage amplitude required by the chip under test 300 can be met by the second pin 13, the signal input and output module 10 directly selects signal path two.

[0072] Specifically, the second pin 13 in signal path 2 can support a signal voltage greater than 1 volt (V), thus meeting the signal amplitude required by a conventional chip under test 300. Therefore, only chips under test 300 requiring a lower signal amplitude need to use signal path 1.

[0073] 2) Signal sampling function.

[0074] The signal sampling function is realized through the input path in the signal input and output module 10: the output signal of the chip under test 300 reaches the second pin 13 through the path control circuit 15 and the first impedance matching circuit 14, and the signal sampling function is realized through the processing chip 200.

[0075] 3) It can measure the DC parameters of the pins of the chip under test 300, such as chip pin continuity test (Continuity Test), pin leakage current test (Leakage Test), etc. Implementation description: Disconnect the path control circuit 15 of the pin of the chip under test 300, configure the path switch matrix 22, and connect the parameter measurement unit 21 to the pin of the chip under test 300.

[0076] 4) DC parameters of the chip under test 300 can be measured, such as the power supply current in sleep and running states. Implementation Description: Disconnect the path switch matrix 22, connect the path control circuit 15, and output a command signal through the signal input / output module 10 to place the chip under test 300 in the target state. At this point, the power supply current of the chip under test 300 can be measured. This circuit solution enables the chip under test 300 to enter the target state, thereby measuring the corresponding DC parameters through the corresponding signal paths.

[0077] 5) Functional item testing of chip under test 300 can be performed, and AC parameter testing can be performed based on this functional item testing. Implementation Description: Disconnect path switch matrix 22, connect path control circuit 15, output commands and data to chip under test 300 via signal input / output module 10, and receive data returned from chip under test 300.

[0078] Output signals of varying voltage amplitudes can be output, and the output voltage path can be adjusted based on the signal amplitude required by the chip under test 300. This solution supports all signal amplitudes and voltages and offers the potential for optimizing system costs: if the chip under test 300 can select signal path two, the driver chip 121 and second impedance matching circuit 122 required for signal path one can be omitted during printed circuit board assembly (PCBA) production.

[0079] 2) Normalization of the signal sampling path. In the technical solution of the conventional signal input and output module 10, an ATE chip with integrated driver and comparator is generally used. In actual system applications, hundreds of ATE chips are usually used. Due to the inconsistency of chip performance, it is difficult to achieve the nominal performance of a single ATE chip. In the use of signal path 1, the pure driver chip 121 solution is directly selected. The input path adopts the FPGA IO path. Since the FPGA chip is a single chip, the consistency between IOs is better.

[0080] In this application, the chip under test 300 can be a memory chip such as LPDDR2 / 3 / 4 / 4X / 5 / 5X, DDR3 / 4 / 5, NAND FLASH or NOR FLASH.

[0081] See Figure 6 , Figure 6 FIG1 is a schematic diagram of a structure of an embodiment of a test device provided by the present application. The test device 1000 includes a processing chip 200 and a pin driving circuit 100 .

[0082] The processing chip 200 is an FPGA chip, an MCU chip, or a CLPD chip. The pin driving circuit 100 is the pin driving circuit 100 in any of the above embodiments.

[0083] In summary, the pin driving circuit 100 and the testing device 1000 provided in the present application include: a signal input and output module 10, the first end of the signal input and output module 10 is used to couple the processing chip 200, and the second end of the signal input and output module 10 is coupled to the chip under test 300; wherein, the signal input and output module 10 provides at least two signal paths, each signal path is used to assist the processing chip 200 in testing the chip under test 300; a parameter measurement module 20, coupled to the chip under test 300, is used to test the DC parameters of the chip under test 300, without the need to use an ATE chip, thereby avoiding the cost, heat dissipation, size and other problems caused by the ATE chip, and then using at least two signal paths and the parameter measurement module 20 to achieve low-cost testing of the chip under test 300, such as DC parameters, AC parameters and functional item testing of the chip under test 300.

[0084] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or ignoring or not implementing certain features.

[0085] If the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0086] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A pin driving circuit, characterized in that: The pin driving circuit includes: a signal input / output module, wherein a first end of the signal input / output module is coupled to a processing chip, and a second end of the signal input / output module is coupled to a chip under test; wherein the signal input / output module provides at least two signal paths, each signal path being used to assist the processing chip in testing the chip under test; The parameter measurement module is coupled to the chip under test and is used to test the DC parameters of the chip under test.

2. The pin driving circuit according to claim 1, wherein: The signal input and output module includes: a first pin, the first pin being used to couple to the processing chip; a driving circuit, wherein a first terminal of the driving circuit is coupled to the first pin; a second pin, the second pin being used to couple to the processing chip; a first impedance matching circuit, wherein a first end of the first impedance matching circuit is coupled to the second pin; A path control circuit is respectively coupled to the second end of the first impedance matching circuit, the second end of the driving circuit, and the chip under test, and is used to provide the at least two signal paths.

3. The pin driving circuit according to claim 2, wherein: The driving circuit includes: a driving chip, wherein a first end of the driving chip is coupled to the first pin; A second impedance matching circuit, wherein a first end of the second impedance matching circuit is coupled to the second end of the driving chip, and a second end of the second impedance matching circuit is coupled to the path control circuit.

4. The pin driving circuit according to claim 2, wherein: The at least two signal paths include a first signal path and a second signal path; wherein a signal output path in the first signal path is formed based on the first pin, the driving circuit, and the path control circuit; The signal input path in the first signal path is formed based on the path control circuit, the first impedance matching circuit, and the second pin; The signal input path and the signal output path in the second signal path are both formed based on the path control circuit, the first impedance matching circuit, and the second pin.

5. The pin driving circuit according to claim 4, wherein: The signal output path of the first signal path provides a signal with a larger amplitude than the signal output path of the second signal path.

6. The pin driving circuit according to claim 2, wherein: The signal sampling function of the chip under test is realized through the path control circuit, the first impedance matching circuit, and the second pin.

7. The pin driving circuit according to claim 1, wherein: The parameter measurement module includes: a path switch matrix, wherein a first end of the path switch matrix is coupled to the chip under test; A parameter measurement unit is coupled to the second end of the path switch matrix.

8. The pin driving circuit according to claim 1, wherein: In response to outputting a command signal from any one of the at least two signal paths to the chip under test, the chip under test is placed in a state corresponding to the command signal.

9. A testing device, characterized in that: The testing device comprises a processing chip and the pin driving circuit according to any one of claims 1 to 8.

10. The testing device according to claim 9, characterized in that: The processing chip is an FPGA chip, an MCU chip, or a CLPD chip.

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