Optimization method for data type conversion operator, computer device, readable storage medium and computer program product

Abstract

The present application relates to an optimization method, computer device, readable storage medium, and computer program product for a data type conversion operator. The method comprises: allocating memory resources for target data; establishing a read mapping relationship between each logical index in the logical structure of the source data and the memory address of the source data, and establishing a write mapping relationship between each logical index in the logical structure and the memory address of the target data; traversing the logical structure, for any traversed logical index, determining the read address corresponding to the logical index based on the read mapping relationship, and reading data from the memory resource corresponding to the source data based on the read address, converting the read data element from a first data type to a second data type, and then writing the data element after the data type conversion to the memory resource corresponding to the target data according to the write mapping relationship. The use of this method can improve the computing power of the data type conversion operator.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method for optimizing a data type conversion operator, a computer device, a readable storage medium, and a computer program product. Background Art

[0002] In the current field of computer graphics processing and high-performance computing, parallel computing technology based on the mainstream GPU (Graphics Processing Unit) architecture is widely used and has become a key support for improving the efficiency of various computing tasks.

[0003] When performing data type conversion (typecast) operations on this type of GPU architecture, the relevant technologies generally adopt the method of directly mapping the physical memory address to the physical address of the on-chip register. Under this direct mapping mechanism, since each thread needs to independently calculate the memory address corresponding to the corresponding operation, a large amount of address calculation overhead will be generated. This additional overhead will not only continuously consume the chip's computing resources, but also lead to a decrease in overall computing efficiency. Summary of the Invention

[0004] Based on this, it is necessary to provide an optimization method, computer device, readable storage medium and computer program product for a data type conversion operator that can improve the computational efficiency of the data conversion operator in response to the above technical problems.

[0005] In a first aspect, the present application provides a method for optimizing a data type conversion operator, comprising:

[0006] Allocating memory resources for target data, wherein the target data is data obtained by converting the data type of source data, the source data corresponds to a first data type, and the target data corresponds to a second data type;

[0007] Determine a logical structure corresponding to the source data, establish a read mapping relationship between each logical index in the logical structure and a memory address of the source data, and establish a write mapping relationship between each logical index in the logical structure and a memory address of the target data;

[0008] Traverse the logical structure, and for any traversed logical index, determine the read address corresponding to the logical index based on the read mapping relationship, and read data from the memory resource corresponding to the source data based on the read address, convert the read data element from the first data type to the second data type, and write the data element after the data type conversion into the memory resource corresponding to the target data according to the write mapping relationship.

[0009] In one embodiment, determining the logical structure corresponding to the source data, establishing a read mapping relationship between each logical index in the logical structure and the memory address of the source data, and establishing a write mapping relationship between each logical index in the logical structure and the memory address of the target data include:

[0010] Determining a target conversion strategy based on the first data type and the second data type, the target conversion strategy comprising at least one conversion stage, wherein a first conversion stage comprises converting the first data type into a third data type, and a last conversion stage comprises converting a fourth data type into the second data type;

[0011] Determine the logical structure corresponding to the source data, and for any of the conversion stages, determine a first mapping relationship and a second mapping relationship, respectively, wherein the first mapping relationship is a mapping relationship between the logical structure and a memory address corresponding to the first data in the conversion stage, and the second mapping relationship is a mapping relationship between the logical structure and a memory address corresponding to the second data in the conversion stage, the first data is the source data in the conversion stage, and the second data is the target data in the conversion stage.

[0012] In one embodiment, determining the read address corresponding to the logical index based on the read mapping relationship, reading data from the memory resource corresponding to the source data based on the read address, converting the read data element from the first data type to the second data type, and writing the data element after the data type conversion into the memory resource corresponding to the target data according to the write mapping relationship includes:

[0013] The data type conversion corresponding to each conversion stage is performed in sequence. For any conversion stage, the data type conversion process includes:

[0014] A read address corresponding to the logical index is determined based on the first mapping relationship, and data is read from the memory resource corresponding to the first data based on the read address. After the read data element is converted from the data type corresponding to the first data to the data type corresponding to the second data, the data element after the data type conversion is written into the memory resource corresponding to the second data according to the second mapping relationship.

[0015] In one embodiment, the method further comprises:

[0016] For any of the conversion phases, an iterative step length for traversing the logic structure and a length of a burst transmission for reading data from a memory resource in the conversion phase are determined.

[0017] In one embodiment, determining a target conversion strategy based on the first data type and the second data type includes:

[0018] Searching for a mapping relationship based on the first data type and the second data type;

[0019] In the case where a mapping relationship between the first data type and the second data type is found, determining that the target conversion strategy is a direct conversion strategy, the direct conversion strategy includes a conversion stage;

[0020] Alternatively, when no mapping relationship from the first data type to the second data type is found, it is determined that the target conversion strategy is a multi-stage conversion strategy, and the multi-stage conversion strategy includes at least two conversion stages.

[0021] In one embodiment, determining, during the conversion phase, an iteration step length for traversing the logic structure and a burst length for reading data from a memory resource comprises:

[0022] The iteration step and the length of the burst transmission are calculated according to the data type of the first data and the data type of the second data, the physical layout of the first data and the physical layout of the second data, and the maximum length supported by the burst transmission.

[0023] In one embodiment, the iteration step size satisfies the following conditions:

[0024] After the iteration step is converted into a physical byte step, it does not exceed the maximum length of the supported burst transmission, and the starting address is aligned according to the data type;

[0025] The length of the burst transmission is the minimum value of the maximum length of the supported burst transmission and the number of physical bytes of continuous data in the current iteration window.

[0026] In a second aspect, the present application further provides an optimization device for a data type conversion operator, comprising:

[0027] an allocation module, configured to allocate memory resources to target data, wherein the target data is data obtained by converting the data type of the source data, the source data corresponds to a first data type, and the target data corresponds to a second data type;

[0028] an establishment module, configured to determine a logical structure corresponding to the source data, establish a read mapping relationship between each logical index in the logical structure and a memory address of the source data, and establish a write mapping relationship between each logical index in the logical structure and a memory address of the target data;

[0029] A conversion module is used to traverse the logical structure, determine the read address corresponding to any traversed logical index based on the read mapping relationship, and read data from the memory resource corresponding to the source data based on the read address, convert the read data element from the first data type to the second data type, and write the data element after the data type conversion into the memory resource corresponding to the target data according to the write mapping relationship.

[0030] In one embodiment, determining the logical structure corresponding to the source data, establishing a read mapping relationship between each logical index in the logical structure and the memory address of the source data, and establishing a write mapping relationship between each logical index in the logical structure and the memory address of the target data include:

[0031] Determining a target conversion strategy based on the first data type and the second data type, the target conversion strategy comprising at least one conversion stage, wherein a first conversion stage comprises converting the first data type into a third data type, and a last conversion stage comprises converting a fourth data type into the second data type;

[0032] Determine the logical structure corresponding to the source data, and for any of the conversion stages, determine a first mapping relationship and a second mapping relationship, respectively, wherein the first mapping relationship is a mapping relationship between the logical structure and a memory address corresponding to the first data in the conversion stage, and the second mapping relationship is a mapping relationship between the logical structure and a memory address corresponding to the second data in the conversion stage, the first data is the source data in the conversion stage, and the second data is the target data in the conversion stage.

[0033] In one embodiment, determining the read address corresponding to the logical index based on the read mapping relationship, reading data from the memory resource corresponding to the source data based on the read address, converting the read data element from the first data type to the second data type, and writing the data element after the data type conversion into the memory resource corresponding to the target data according to the write mapping relationship includes:

[0034] The data type conversion corresponding to each conversion stage is performed in sequence. For any conversion stage, the data type conversion process includes:

[0035] A read address corresponding to the logical index is determined based on the first mapping relationship, and data is read from the memory resource corresponding to the first data based on the read address. After the read data element is converted from the data type corresponding to the first data to the data type corresponding to the second data, the data element after the data type conversion is written into the memory resource corresponding to the second data according to the second mapping relationship.

[0036] In one embodiment, the method further comprises:

[0037] For any of the conversion phases, an iterative step length for traversing the logic structure and a length of a burst transmission for reading data from a memory resource in the conversion phase are determined.

[0038] In one embodiment, determining a target conversion strategy based on the first data type and the second data type includes:

[0039] Searching for a mapping relationship based on the first data type and the second data type;

[0040] In the case where a mapping relationship between the first data type and the second data type is found, determining that the target conversion strategy is a direct conversion strategy, the direct conversion strategy includes a conversion stage;

[0041] Alternatively, when no mapping relationship from the first data type to the second data type is found, it is determined that the target conversion strategy is a multi-stage conversion strategy, and the multi-stage conversion strategy includes at least two conversion stages.

[0042] In one embodiment, determining, during the conversion phase, an iteration step length for traversing the logic structure and a burst length for reading data from a memory resource comprises:

[0043] The iteration step and the length of the burst transmission are calculated according to the data type of the first data and the data type of the second data, the physical layout of the first data and the physical layout of the second data, and the maximum length supported by the burst transmission.

[0044] In one embodiment, the iteration step size satisfies the following conditions:

[0045] After the iteration step is converted into a physical byte step, it does not exceed the maximum length of the supported burst transmission, and the starting address is aligned according to the data type;

[0046] The length of the burst transmission is the minimum value of the maximum length of the supported burst transmission and the number of physical bytes of continuous data in the current iteration window.

[0047] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements any of the above methods for optimizing data type conversion operators when executing the computer program.

[0048] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the above methods for optimizing data type conversion operators.

[0049] In a fifth aspect, the present application also provides a computer program product, comprising a computer program, which, when executed by a processor, implements any of the above methods for optimizing data type conversion operators.

[0050] The optimization method, computer device, readable storage medium and computer program product of the above-mentioned data type conversion operator can allocate memory resources for target data, wherein the target data is the data after the source data is converted into a data type, the source data corresponds to the first data type, and the target data corresponds to the second data type. Determine the logical structure corresponding to the source data, establish a read mapping relationship between each logical index in the logical structure and the memory address of the source data, and establish a write mapping relationship between each logical index in the logical structure and the memory address of the target data. Traverse the logical structure, for any logical index traversed, determine the read address corresponding to the logical index based on the mapping relationship, and read data from the memory resource corresponding to the source data based on the read address, convert the read data element from the first data type to the second data type, and then write the data element after the data type conversion into the memory resource corresponding to the target data according to the write mapping relationship. Using the optimization method, computer device, readable storage medium and computer program product of the data type conversion operator provided by the embodiment of the present application, by establishing a mapping relationship between the logical index and the memory addresses of the source and target data, each process does not need to perform address calculation during the data type conversion process, and directly queries the read and write memory addresses based on the mapping relationship. This approach significantly reduces the amount of computation, saves chip computing resources, and effectively improves the computational efficiency of data type conversion operators. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 A schematic diagram of a data type conversion process of a traditional data type conversion operator in one embodiment;

[0053] Figure 2 1 is a flow chart of a method for optimizing a data type conversion operator in one embodiment;

[0054] Figure 3is a structural block diagram of an artificial intelligence processor in one embodiment;

[0055] Figure 4 is a schematic diagram of step 204 in one embodiment;

[0056] Figure 5 A schematic diagram of a data type conversion process of a data type conversion operator in one embodiment;

[0057] Figure 6 is a structural block diagram of an optimization device for a data type conversion operator in one embodiment;

[0058] Figure 7 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0060] Related technology: During the data type conversion process, the source data (Source Data, also abbreviated as src) is physically mapped and then a typecast operation is performed in the on-chip register. The target data after data type conversion is then stored in the memory through physical mapping.

[0061] Figure 1 This diagram illustrates how memory physical addresses are directly mapped to on-chip register physical addresses. For example, in the physical layout, numbers 0-15 correspond to memory cells with different physical addresses, storing source data to be converted. For each data element stored in a memory cell, a mapping calculation is performed between the physical address of the memory cell and the on-chip register address to determine the register address to which the data element is written. Figure 1 The mapping relationship between physical address and register address is marked by the same color (where R is the register identifier, T is the thread identifier, R0T0 represents the register R0 of thread T0, and so on). Figure 1 Physical address 1 is marked as 0) corresponds to R0T0, physical address 2 ( Figure 1 The physical address 2 is marked as 1) corresponds to R1T0, and the physical address 3 ( Figure 1 Physical address three is marked as 2) corresponds to R0T1, physical address four ( Figure 1 The physical address 4 is marked as 3) corresponding to R1T1, and so on).

[0062] Based on the above mapping relationship between memory physical addresses and on-chip registers, the source data stored in the memory can be written to the on-chip registers, converted in the on-chip registers, and then written back to the memory. When writing the converted data from the on-chip registers to the memory, the mapping between the on-chip register address storing the converted data and the physical address must also be calculated to determine the physical address to which the data is to be written. Figure 1 In the example of converting data type from f32 to f16, the converted data is stored in R3T0, R3T1, R3T2 and R3T3, where the calculated R3T0 corresponds to physical address 1, R3T1 corresponds to physical address 2, and R3T2 corresponds to physical address 5 ( Figure 1 Physical address five is marked as 8), R3T3 corresponds to physical address six ( Figure 1 Furthermore, based on the mapping relationship between the memory physical address and the on-chip register, the target data stored in the register after data type conversion can be written into the physical memory.

[0063] It can be seen that each time a data type is converted, the thread needs to perform independent mapping address calculation operations from physical address to register and from register to physical address, which consumes a lot of computing resources and slows down the conversion efficiency.

[0064] This embodiment of the application provides an optimization method for a data type conversion operator. By establishing a mapping relationship between logical indexes and the memory addresses of source and target data, each process can directly query the read and write memory addresses based on the mapping relationship without performing address calculations during the data type conversion process. This method significantly reduces the amount of computation, saves chip computing resources, and effectively improves the computational efficiency of the data type conversion operator.

[0065] In an exemplary embodiment, Figure 2As shown, a method for optimizing a data type conversion operator is provided, which is applied to an artificial intelligence processor. In the embodiment of the present application, the artificial intelligence processor is any one of a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural Network Processing Unit), a DPU (Deep Learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose Graphics Processing Unit). In the embodiment of the present application, there is no specific limitation on this, and the following description will take the GPU as an example.

[0066] Reference Figure 3 Figure 1 shows a schematic diagram of the AI ​​processor architecture. The AI ​​processor architecture consists of multiple parallel, independent CUs (Computing Units) and global memory (GLM), which provides shared storage support for all CUs. Each CU is an independent computing submodule, consisting of threads, thread-level registers (TLRs), and group shared memory (GSM). Threads are the finest-grained parallel execution units within a CU, capable of scheduling multiple threads simultaneously and splitting parallel computing tasks (such as matrix operations and convolutions). TLRs, located between threads and GSMs, allocate computing resources to threads or prepare / cache data for computation. GSMs are CU-specific, high-speed local storage used to store frequently accessed data (such as model parameter fragments and intermediate computation results) by the CU, reducing access latency to global memory. Global memory, as globally shared storage, is used to store complete model parameters, input datasets, and intermediate results that need to be shared between CUs.

[0067] Global memory distributes data (such as model weights and input features) to each CU's GSM for local computation. Within each CU, threads, scheduled by TLRs, utilize GSM data to execute AI tasks (such as neural network layer calculations), allowing multiple CUs to work in parallel. CU computation results can be temporarily stored in the GSM or written back to the GLM for other CUs to access, supporting cross-CU collaborative computing.

[0068] Reference Figure 2As shown, the optimization method of the data type conversion operator provided in the embodiment of the present application may include the following steps 202 to 206. Among them:

[0069] Step 202 : Allocate memory resources for target data, wherein the target data is data obtained by converting the data type of the source data, the source data corresponds to a first data type, and the target data corresponds to a second data type.

[0070] In an embodiment of the present application, memory resources can be allocated to target data based on the logical shape and data type of the target data. The target data is the data obtained after a source data type conversion operation. Assuming that the source data corresponds to a first data type, the data type conversion operation is to convert the source data from the first data type to a second data type, and the result of the conversion is the target data.

[0071] For example, the memory resource is global memory. Assuming that the source data and the target data are both matrices with a logical shape of 64×32, and the second data type corresponding to the target data is float32, the required memory size can be calculated as 64×32×4B=8192B, and then global memory of the corresponding size is allocated to the target data.

[0072] Step 204 , determining the logical structure corresponding to the source data, establishing a read mapping relationship between each logical index in the logical structure and the memory address of the source data, and establishing a write mapping relationship between each logical index in the logical structure and the memory address of the target data.

[0073] In the embodiment of the present application, the logical structure of the source data is constructed by the coordinates of each data element within it, and the coordinates of each data element are directly used as its own logical index. In this way, by mapping the physical storage location to a mathematical coordinate space, an abstract expression of data storage and access is achieved. Specifically, for matrix data of any size M×N, the data element at the (i, j) position has its logical index directly defined as the coordinate value (i, j). Taking a 64×32 matrix as an example, the data element at the (32, 16) position in the matrix has a logical index of (32, 16).

[0074] After determining the logical structure corresponding to the source data, the memory address of the source data can be mapped to its corresponding logical structure based on preset mapping rules, resulting in a read mapping relationship between each logical index in the logical structure and the memory address of the source data. Furthermore, the memory address of the target data can be mapped to the logical structure based on preset mapping rules, resulting in a write mapping relationship between each logical index in the logical structure and the memory address of the target data. In this embodiment of the present application, the target data is the result of data type conversion of the source data, that is, the source data and target data structures are exactly the same, and the corresponding logical structures of the two completely match. This consistency design completely decouples the construction of the logical structure from the data type (fp16, bf16, int8, etc.).

[0075] That is, in the embodiment of the present application, after the source data logical structure is established, a two-dimensional mapping rule system is used to respectively construct a bidirectional mapping relationship between the source data memory address and the logical structure, and between the target data memory address and the logical structure. The mapping rule system has a high degree of flexibility and scalability. It should be noted that the present application does not limit the specific mapping rules and allows for a variety of implementation methods, including but not limited to linear mapping, hash mapping, segmented mapping, etc. As long as an effective mapping from physical address to logical structure can be achieved, it can be applied to the embodiment of the present application.

[0076] Step 206, traverse the logical structure, and for any traversed logical index, determine the read address corresponding to the logical index based on the read mapping relationship, and read data from the memory resource corresponding to the source data based on the read address, convert the read data element from the first data type to the second data type, and write the data element after the data type conversion into the memory resource corresponding to the target data according to the write mapping relationship.

[0077] In the embodiment of the present application, during the execution of the instruction corresponding to the data type conversion operator, the logical structure can be traversed to read data. For the logical index of the traversed data element, the corresponding read address and write address are determined from the read mapping relationship and the write mapping relationship, respectively. Then, data is read from the read address, and the read data is converted from the first data type to the second data type, and the data of the second data type is written to the write address. After the traversal of the logical structure is completed, the source data is converted from the first data type to the second data type.

[0078] The optimization method of the above-mentioned data type conversion operator can allocate memory resources for target data, wherein the target data is the data after the source data is converted into a data type, the source data corresponds to the first data type, and the target data corresponds to the second data type. Determine the logical structure corresponding to the source data, establish a read mapping relationship between each logical index in the logical structure and the memory address of the source data, and establish a write mapping relationship between each logical index in the logical structure and the memory address of the target data, and traverse the logical structure. For any logical index traversed, determine the read address corresponding to the logical index based on the mapping relationship, and read data from the memory resource corresponding to the source data based on the read address. After converting the read data element from the first data type to the second data type, write the data element after the data type conversion into the memory resource corresponding to the target data according to the write mapping relationship. Using the optimization method of the data type conversion operator provided by the embodiment of the present application, by establishing a mapping relationship between the logical index and the memory address of the source and target data, each process does not need to perform address calculation during the data type conversion process, and directly queries the read and write memory addresses based on the mapping relationship. This method greatly reduces the amount of calculation, saves chip computing resources, and effectively improves the computing efficiency of the data type conversion operator.

[0079] In an exemplary embodiment, step 204, determining the logical structure corresponding to the source data, establishing a read mapping relationship between each logical index in the logical structure and the memory address of the source data, and establishing a write mapping relationship between each logical index in the logical structure and the memory address of the target data, may include the following steps 402 to 404, referring to Figure 4 As shown, where:

[0080] Step 402: Determine a target conversion strategy based on the first data type and the second data type, wherein the target conversion strategy includes at least one conversion stage, wherein a first conversion stage includes converting the first data type into a third data type, and a last conversion stage includes converting the fourth data type into the second data type.

[0081] Step 404, determine the logical structure corresponding to the source data, and for any conversion stage, determine a first mapping relationship and a second mapping relationship respectively. The first mapping relationship is a mapping relationship between the logical structure and the memory address corresponding to the first data in the conversion stage, and the second mapping relationship is a mapping relationship between the logical structure and the memory address corresponding to the second data in the conversion stage. The first data is the source data in the conversion stage, and the second data is the target data in the conversion stage.

[0082] In embodiments of the present application, conversion strategies may include direct conversion and multi-stage conversion. Direct conversion involves performing a single conversion operation on the source data from a first data type to a second data type without requiring an intermediate data type transition. This means that the entire conversion process includes only one conversion operation phase. For example, if the first data type is float32 and the second data type is float16, the target conversion strategy includes a single conversion phase, namely, converting from float32 to float16.

[0083] Multi-stage conversion can divide the conversion operation of converting source data from the first data type to the second data type into multiple continuous conversion operation stages. For example: the first data type is float32 and the second data type is float8, then the entire conversion operation can include two conversion stages, the first conversion stage is the conversion operation from float32 to float16, and the second conversion stage is the conversion operation from float16 to float8.

[0084] That is, in the embodiment of the present application, the target conversion strategy may include at least one conversion stage, wherein the first conversion stage includes converting the first data type into the third data type, and the last conversion stage includes converting the fourth data type into the second data type. When the target conversion strategy is direct conversion, the target conversion strategy includes one conversion stage, in which case the first conversion stage is also the last conversion stage, wherein the third data type is the second data type, and the fourth data type is the first data type.

[0085] When the target conversion strategy is a multi-stage conversion, the target conversion strategy may include at least two conversion stages. For the sake of clarity, the source data in each conversion stage is referred to as the first data, and the target data in each conversion stage is referred to as the second data, wherein the data type of the second data in the previous conversion stage is the data type of the first data in the next conversion stage, forming a chain conversion path. The data type of the first data in the first conversion stage is the first data type, and the data type of the second data in the last conversion stage is the second data type. It should be noted that in the process where the target conversion strategy includes two conversion stages, the third data type of the second data in the first conversion stage is the same as the fourth data type of the first data in the last stage.

[0086] In an exemplary embodiment, in step 402, determining a target conversion strategy based on the first data type and the second data type may include the following steps:

[0087] Finding a mapping relationship based on the first data type and the second data type;

[0088] When a mapping relationship from the first data type to the second data type is found, the target conversion strategy is determined to be a direct conversion strategy, which includes one conversion stage; or, when a mapping relationship from the first data type to the second data type is not found, the target conversion strategy is determined to be a multi-stage conversion strategy, which includes at least two conversion stages.

[0089] In an embodiment of the present application, it is possible to search from a pre-set mapping relationship whether there is a conversion mapping relationship from a first data type to a second data type, and if the mapping relationship is found, the conversion operation is not split, and the target conversion strategy is determined to be a direct conversion strategy; or, if the mapping relationship is not found, the conversion operation from the first data type to the second data type is split through an intermediate transition data type to obtain a multi-order conversion strategy.

[0090] For example, assuming the first data type is T1 and the second data type is T2, a direct conversion relationship from T1 to T2 is searched in a predefined mapping table. If a direct conversion relationship from T1 to T2 exists, a direct conversion strategy is selected; if not, the intermediate transition data type derivation process is entered. Among them, the intermediate transition data type derivation process includes: trying to find the intermediate transition data type T3, and the intermediate transition data type T3 meets the following conditions: there are conversion relationships of T1→T3 and T3→T2 in the mapping table; if the intermediate transition data type T3 is found, a two-stage multi-stage conversion including T1→T3→T2 is selected; or if the intermediate transition data type T3 is not found, then try to find the intermediate transition data type sequence T3 and T4, and the intermediate transition data types T3 and T4 meet the following conditions: there are conversion relationships of T1→T3, T3→T4, and T4→T2 in the mapping table; if the intermediate transition data types T3 and T4 are found, then a three-stage multi-stage conversion including T1→T3→T4→T2 is selected; the above steps are recursively executed until a feasible intermediate transition data type sequence is found, and a multi-stage conversion strategy is constructed based on the intermediate transition data type.

[0091] After determining the target conversion strategy, for each conversion stage in the target conversion strategy, the first mapping relationship between the logical structure of the source data and the memory address storing the first data, and the second mapping relationship between the logical structure of the source data and the memory address storing the second data can be determined respectively, that is, the mapping relationship between the logical structure and the memory address storing the source data, the mapping relationship between the logical structure and the memory address storing the target data, and the mapping relationship between the logical structure and the memory address storing the data of the intermediate transition data type. Exemplarily, the physical memory of the source data and the target data can be global memory, and the memory address of the data of the intermediate transition data type is shared memory. The establishment of the specific mapping relationship can refer to the relevant description of the aforementioned embodiment, and will not be repeated here in the embodiment of the present application.

[0092] By adopting the optimization method of the data type conversion operator provided in the embodiment of the present application, efficient data type conversion can be achieved by flexibly dividing the conversion stages.

[0093] In an exemplary embodiment, determining a read address corresponding to a logical index based on a read mapping relationship, reading data from a memory resource corresponding to source data based on the read address, converting the read data element from a first data type to a second data type, and writing the data element after data type conversion to a memory resource corresponding to target data according to a write mapping relationship includes:

[0094] The data type conversion corresponding to each conversion stage is executed in sequence. For any conversion stage, the data type conversion process includes: determining the read address corresponding to the logical index based on the first mapping relationship, and reading data from the memory resource corresponding to the first data based on the read address, converting the read data element from the data type corresponding to the first data to the data type corresponding to the second data, and then writing the data element after the data type conversion into the memory resource corresponding to the second data according to the second mapping relationship.

[0095] In an embodiment of the present application, the data type conversion corresponding to each stage can be performed sequentially starting from the source data. During the execution of any conversion stage, the logical structure can be traversed to read data, and the corresponding read address and write address can be determined from the first mapping relationship and the second mapping relationship for the logical index of the traversed data element, and then data is read from the read address, and the data type of the read data is converted from the data type corresponding to the first data to the data type corresponding to the second data, and the second data is written to the write address. After completing the traversal of the logical structure, the data type conversion of the current conversion stage is realized.

[0096] In an exemplary embodiment, during the execution of each conversion phase, step processing can be combined with a burst transmission mechanism to perform data reading, writing, and conversion processing, thereby significantly improving system performance by optimizing the data reading and writing mode. Exemplarily, the above method may further include:

[0097] For any conversion phase, the iteration step length for traversing the logic structure and the length of the burst transmission for reading data from the memory resource in the conversion phase are determined.

[0098] In embodiments of the present application, data access strategies can be dynamically adjusted based on hardware characteristics. For example, for any conversion phase, the optimal iteration step size can be determined based on the current hardware environment and data characteristics. For example, for a memory system that supports burst transfers, the step size can be set to an integer multiple of the maximum burst transfer length. During data traversal, batch data processing using a fixed step size can reduce access frequency.

[0099] Exemplarily, data is traversed based on an iteration step, and for the logical index (i, j) of the traversed data element, a first mapping relationship can be queried to determine the memory address corresponding to the logical index. Furthermore, using the memory address as the starting address, a corresponding number of data elements are continuously read from the physical memory according to the maximum burst transfer length supported by the current hardware. Exemplarily, taking the maximum burst transfer length as 64 bytes and the first data as float32 type, 16 float32 data elements can be read from the starting address.

[0100] During the current conversion phase, the second mapping relationship can be queried based on the logical index of the read data element. After determining the target memory address corresponding to the read data element, the data type of the read data element can be converted and then written to the target memory address. In this way, continuous data reading and writing can be achieved, reducing access to physical resources and improving data reading and writing efficiency.

[0101] In an exemplary embodiment, the above method may further include:

[0102] The iteration step size and the burst transmission length are calculated according to the data type of the first data and the data type of the second data, the physical layout of the first data and the physical layout of the second data, and the maximum length supported by the burst transmission.

[0103] In an embodiment of the present application, the maximum length of a burst transfer supported by the hardware, the data type of the first data, and the physical layout of the first data can be determined. The number of data elements with consecutive physical addresses, starting from the currently traversed data element, can then be determined based on the physical layout of the first data. The number of physical bytes that can be read continuously can then be determined based on the data type of the first data. The minimum value between the maximum length of the burst transfer and the number of physical bytes can then be determined as the length of the burst transfer. After determining the length of the burst transfer, the iteration step can be determined based on the length of the burst transfer and the data type of the first data, ensuring that the iteration step, after being converted into a physical byte step, does not exceed the maximum length supported for the burst transfer and that the starting address is aligned according to the data type.

[0104] For example, assume that the first data is a 1024×1024 float16 matrix, and the maximum length of burst transmission supported by the GPU (Graphics Processing Unit) hardware is 256 bytes. Each data element occupies 2 bytes, and the first data is stored in memory in a row-first manner.

[0105] Since the first data is stored row-first and allocated contiguously in matrix memory, the number of elements with consecutive physical addresses, starting from the currently traversed element, is the number of elements remaining in that row. For example, if the current traversal reaches the element in row i and column j, the number of physically consecutive elements is 1024 - j. Each float16 element occupies 2 bytes, so the number of physical bytes that can be read continuously is (1024 - j) × 2.

[0106] Compare the maximum hardware burst transfer length of 256 bytes with the number of bytes that can be read continuously, and use the smaller value. For example, if the number of remaining elements in the current row is 128, 256 bytes can be read continuously, which is equal to the maximum hardware burst transfer length, so the burst transfer length is set to 256 bytes. If the number of remaining elements is 64 (that is, 128 bytes can be read continuously), the burst transfer length is set to 128 bytes.

[0107] Based on the burst length and data type, the iteration step is burst length / element size. For example, when the burst length is 256 bytes, the iteration step is 256 / 2 = 128 elements, ensuring that the data transferred each time is continuous in the physical address and does not exceed the hardware limit. Iteration is performed in units of 128 elements, each time 256 bytes of data are read from memory, the data type is converted, and then the data is written directly to the corresponding target memory address through the second mapping relationship.

[0108] In an embodiment of the present application, during the write phase, the iteration step size of the second data and the maximum length of the burst transmission can be determined based on the data type and physical layout, or a burst transmission of a larger length can be directly split into multiple burst transmissions of smaller lengths based on the physical layout and data type of the second data.

[0109] For example, assume the first data is a 256×256 matrix of float32 data type, and the second data is of float16 data type. During the read phase, 64 float32 elements (256 bytes) are read in each burst, while during the write phase, 64 float16 elements can also be written. After completing the data type conversion in the on-chip registers, the data is written to the target memory in batches using the optimized step size and burst length, significantly reducing the overhead associated with data type conversion.

[0110] In the data type conversion operator optimization method provided by the embodiment of the present application, in the data type conversion operation, the source data and the target data usually have different physical memory layouts. Figure 5As shown in the pink blocks, the source and target data have significant differences in their physical memory distribution, hardware resource usage, and thread mapping. To address this issue, this embodiment introduces a logical layout abstraction, establishing a physical-to-logical mapping relationship to achieve efficient and universal type conversion operations.

[0111] The implementation strategy of the data type conversion operator optimization method provided in the embodiments of the present application is as follows: Because the logical shape of the source and target data remains consistent during the data type conversion operation (typecast), regardless of whether the conversion is from high-precision to low-precision or from low-precision to high-precision, different physical layouts can be mapped to a unified logical structure. By defining multiple traits to accurately express the mapping relationship between physical addresses and logical coordinates, a physical memory layout of any dimension can be converted into a one-dimensional or multi-dimensional structure in the logical space. When performing data type conversion, only the logical structure needs to be traversed to cover the entire physical data space, thereby converting complex physical address calculations into simple logical coordinate operations.

[0112] At the implementation level, the mapping between memory and logical structures is explicitly defined through the layout information within the feature description. This allows data type conversion operations to be combined with a step-by-step processing mechanism, using trait blocks as the basic processing unit and batch processing at burst granularity. This approach only requires calculating the start address of the current burst block, eliminating the need to calculate the memory address for each thread, significantly reducing address calculation overhead. Furthermore, the burst-based memory access mode fully utilizes hardware caching mechanisms to improve data transmission efficiency.

[0113] The system automatically selects the optimal conversion strategy for different data type conversion requirements: when a direct conversion path exists (e.g., float32 → float16), a single-stage direct conversion is used; when direct conversion is not possible (e.g., float32 → float8), an intermediate transition data type (e.g., float16) is automatically introduced for a multi-stage conversion. During each conversion stage, the system dynamically adjusts memory access patterns based on physical memory continuity to maximize hardware bandwidth utilization and achieve high-performance operators.

[0114] The optimization method for data type conversion operators provided in this application embodiment shields physical layout differences through logical abstraction, transforming complex memory rearrangement problems into unified logical space operations. Based on a trait and burst-based design, the data type conversion operator is generalized to support arbitrary data type combinations and memory layouts. Automatic conversion strategy selection and dynamic memory access optimization mechanisms significantly improve computational efficiency while ensuring conversion correctness. This physical-to-logical mapping concept not only reduces programming complexity but also fully leverages the parallel computing capabilities of modern artificial intelligence chip architectures to achieve high-performance type conversion operators.

[0115] It should be noted that the optimization method for the data type conversion operator provided in the embodiments of the present application is applied at least in the fields of speech processing, image processing, text processing, video processing, and other fields, and is used in scenarios such as deep learning reasoning processes, scientific computing, and graphics rendering. In the speech processing scenario, the source data and target data are audio data of different data types. In the image processing process, the source data and target data are image data of different data types. In the text processing process, the source data and target data are text data of different data types. In the video data process, the metadata and target data are video data of different data types.

[0116] In one example, during the inference phase of a deep learning model (such as a CNN), it's often necessary to convert high-precision floating-point image data (such as float32) to lower-precision data types (such as float16 / int8) to reduce video memory usage and accelerate computation. For an H×W×3 RGB image, when quantizing it from float32 to int8, the following steps can be used to optimize the data type conversion process:

[0117] Allocate contiguous memory space for the target data (int8 image) with a size of H × W × 3 × 1 bytes (int8 occupies 1 byte), and define a three-dimensional logical index space (h, w, c), corresponding to the height, width, and channels of the image, respectively.

[0118] When the hardware does not support direct float32→int8 conversion, a two-stage conversion scheme is adopted: float32→float16→int8. Float16 intermediate results are stored in shared memory, leveraging its low latency to reduce global memory accesses. Mappings are established from the physical addresses of the input data, intermediate results, and target data to logical indices. During each conversion stage, the logical structure is traversed. For each logical index traversed, the read and write addresses corresponding to the currently operated pixel are determined through the mapping relationship. Multiple pixels are then read in batches using burst transfers. For example, 16 float32 pixels (64 bytes) are read in batches, followed by a type conversion operation (float32→float16→int8). The converted int8 data (16 bytes) is then written in batches to the corresponding write addresses.

[0119] The optimization method of the data type conversion operator provided in the embodiment of the present application can effectively improve bandwidth utilization and data conversion efficiency to meet the needs of real-time image classification (such as target detection).

[0120] In another example, in speech signal processing (such as Fourier transform and feature extraction), it is often necessary to convert the time domain signal (float32 sampling points) to a fixed-point type (int16) to adapt to embedded hardware, thereby reducing the latency of single-channel speech signal conversion and meeting the requirements of real-time speech interaction (such as speech recognition front-end preprocessing). Alternatively, in video processing scenarios, in the GPU graphics rendering pipeline, vertex data (such as float32 coordinates) needs to be converted to a normalized integer (such as uint16) to write to the frame buffer to support real-time rendering. Alternatively, in natural language processing models in text processing scenarios, it is often necessary to quantize word embedding vectors (float32) (such as bf16) to accelerate inference, or to convert attention weights (float32) to a smaller format (such as float16) to support real-time inference of models with hundreds of billions of parameters, allowing more layers of weights to be loaded simultaneously and improving model parallelism.

[0121] It can be seen from the above scenarios that the optimization method of the data type conversion operator provided in the embodiment of the present application can significantly improve the data conversion efficiency in different fields and reduce computing resource consumption by flexibly constructing logical structures and mapping relationships and adjusting data conversion strategies in combination with hardware characteristics. It has wide applicability and technical advantages.

[0122] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0123] Based on the same inventive concept, an embodiment of the present application further provides a data type conversion operator optimization device for implementing the aforementioned data type conversion operator optimization method. The solution to the problem provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of the embodiments of the optimization device for one or more data type conversion operators provided below can be found in the limitations of the optimization method for data type conversion operators described above and will not be repeated here.

[0124] In an exemplary embodiment, Figure 6 As shown, a data type conversion operator optimization device 600 is provided, comprising: an allocation module 602, a creation module 604 and a conversion module 606, wherein:

[0125] An allocation module 602 is configured to allocate memory resources to target data, wherein the target data is data obtained by converting the data type of the source data, the source data corresponds to a first data type, and the target data corresponds to a second data type;

[0126] Establishing module 604, configured to determine a logical structure corresponding to the source data, establish a read mapping relationship between each logical index in the logical structure and a memory address of the source data, and establish a write mapping relationship between each logical index in the logical structure and a memory address of the target data;

[0127] The conversion module 606 is used to traverse the logical structure, determine the read address corresponding to any traversed logical index based on the read mapping relationship, and read data from the memory resource corresponding to the source data based on the read address. After converting the read data element from the first data type to the second data type, the data element after the data type conversion is written into the memory resource corresponding to the target data according to the write mapping relationship.

[0128] The optimization device of the above-mentioned data type conversion operator can allocate memory resources for target data, wherein the target data is the data after the source data is converted into a data type, the source data corresponds to the first data type, and the target data corresponds to the second data type. Determine the logical structure corresponding to the source data, establish a read mapping relationship between each logical index in the logical structure and the memory address of the source data, and establish a write mapping relationship between each logical index in the logical structure and the memory address of the target data, and traverse the logical structure. For any logical index traversed, determine the read address corresponding to the logical index based on the mapping relationship, and read data from the memory resource corresponding to the source data based on the read address. After converting the read data element from the first data type to the second data type, write the data element after the data type conversion into the memory resource corresponding to the target data according to the write mapping relationship. Using the optimization device of the data type conversion operator provided by the embodiment of the present application, by establishing a mapping relationship between the logical index and the memory address of the source and target data, each process does not need to perform address calculation during the data type conversion process, and directly queries the read and write memory addresses based on the mapping relationship. This method greatly reduces the amount of calculation, saves chip computing resources, and effectively improves the computing efficiency of the data type conversion operator.

[0129] In one embodiment, determining the logical structure corresponding to the source data, establishing a read mapping relationship between each logical index in the logical structure and the memory address of the source data, and establishing a write mapping relationship between each logical index in the logical structure and the memory address of the target data include:

[0130] Determining a target conversion strategy based on the first data type and the second data type, the target conversion strategy comprising at least one conversion stage, wherein a first conversion stage comprises converting the first data type into a third data type, and a last conversion stage comprises converting a fourth data type into the second data type;

[0131] Determine the logical structure corresponding to the source data, and for any of the conversion stages, determine a first mapping relationship and a second mapping relationship, respectively, wherein the first mapping relationship is a mapping relationship between the logical structure and a memory address corresponding to the first data in the conversion stage, and the second mapping relationship is a mapping relationship between the logical structure and a memory address corresponding to the second data in the conversion stage, the first data is the source data in the conversion stage, and the second data is the target data in the conversion stage.

[0132] In one embodiment, determining the read address corresponding to the logical index based on the read mapping relationship, reading data from the memory resource corresponding to the source data based on the read address, converting the read data element from the first data type to the second data type, and writing the data element after the data type conversion into the memory resource corresponding to the target data according to the write mapping relationship includes:

[0133] The data type conversion corresponding to each conversion stage is performed in sequence. For any conversion stage, the data type conversion process includes:

[0134] A read address corresponding to the logical index is determined based on the first mapping relationship, and data is read from the memory resource corresponding to the first data based on the read address. After the read data element is converted from the data type corresponding to the first data to the data type corresponding to the second data, the data element after the data type conversion is written into the memory resource corresponding to the second data according to the second mapping relationship.

[0135] In one embodiment, the method further comprises:

[0136] For any of the conversion phases, an iterative step length for traversing the logic structure and a length of a burst transmission for reading data from a memory resource in the conversion phase are determined.

[0137] In one embodiment, determining a target conversion strategy based on the first data type and the second data type includes:

[0138] Searching for a mapping relationship based on the first data type and the second data type;

[0139] In the case where a mapping relationship between the first data type and the second data type is found, determining that the target conversion strategy is a direct conversion strategy, the direct conversion strategy includes a conversion stage;

[0140] Alternatively, when no mapping relationship from the first data type to the second data type is found, it is determined that the target conversion strategy is a multi-stage conversion strategy, and the multi-stage conversion strategy includes at least two conversion stages.

[0141] In one embodiment, determining, during the conversion phase, an iteration step length for traversing the logic structure and a burst length for reading data from a memory resource comprises:

[0142] The iteration step and the length of the burst transmission are calculated according to the data type of the first data and the data type of the second data, the physical layout of the first data and the physical layout of the second data, and the maximum length supported by the burst transmission.

[0143] In one embodiment, the iteration step size satisfies the following conditions:

[0144] After the iteration step is converted into a physical byte step, it does not exceed the maximum length of the supported burst transmission, and the starting address is aligned according to the data type;

[0145] The length of the burst transmission is the minimum value of the maximum length of the supported burst transmission and the number of physical bytes of continuous data in the current iteration window.

[0146] Each module in the aforementioned data type conversion operator optimization device may be implemented in whole or in part through software, hardware, or a combination thereof. Each module may be embedded in or independent of a processor in a computer device in the form of hardware, or may be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0147] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 7 As shown. The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals via wired or wireless means, and the wireless means can be implemented via Wi-Fi, a mobile cellular network, near-field communication (NFC), or other technologies. When executed by the processor, the computer program implements a method for optimizing a data type conversion operator. The display unit of the computer device is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device casing, or an external keyboard, touchpad or mouse.

[0148] Those skilled in the art will understand that Figure 7The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0149] In one embodiment, a computer device is further provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0150] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0151] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0152] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0153] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0154] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0155] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for optimizing a data type conversion operator, characterized in that: The method comprises: Allocating memory resources for target data, wherein the target data is data obtained by converting the data type of source data, the source data corresponds to a first data type, and the target data corresponds to a second data type; determining a logical structure corresponding to the source data, mapping the memory address of the source data to the logical structure based on a preset mapping rule to obtain a read mapping relationship between each logical index in the logical structure and the memory address of the source data, and mapping the memory address of the target data to the logical structure based on a preset mapping rule to obtain a write mapping relationship between each logical index in the logical structure and the memory address of the target data, wherein the logical structure of the source data is constructed by the coordinates of each data element within the source data; Traverse the logical structure, and for any traversed logical index, determine the read address corresponding to the logical index based on the read mapping relationship, and read data from the memory resource corresponding to the source data based on the read address, convert the read data element from the first data type to the second data type, and write the data element after the data type conversion into the memory resource corresponding to the target data according to the write mapping relationship.

2. The method according to claim 1, characterized in that The determining of the logical structure corresponding to the source data, mapping the memory address of the source data to the logical structure based on a preset mapping rule, and obtaining a read mapping relationship between each logical index in the logical structure and the memory address of the source data, and mapping the memory address of the target data to the logical structure based on a preset mapping rule, and obtaining a write mapping relationship between each logical index in the logical structure and the memory address of the target data, includes: Determining a target conversion strategy based on the first data type and the second data type, the target conversion strategy comprising at least one conversion stage, wherein a first conversion stage comprises converting the first data type into a third data type, and a last conversion stage comprises converting a fourth data type into the second data type; Determine the logical structure corresponding to the source data, and for any of the conversion stages, determine a first mapping relationship and a second mapping relationship, respectively, wherein the first mapping relationship is a mapping relationship between the logical structure and a memory address corresponding to the first data in the conversion stage, and the second mapping relationship is a mapping relationship between the logical structure and a memory address corresponding to the second data in the conversion stage, the first data is the source data in the conversion stage, and the second data is the target data in the conversion stage.

3. The method according to claim 2, characterized in that The determining, based on the read mapping relationship, a read address corresponding to the logical index, and reading data from the memory resource corresponding to the source data based on the read address, converting the read data element from the first data type to the second data type, and then writing the data element after the data type conversion into the memory resource corresponding to the target data according to the write mapping relationship, includes: The data type conversion corresponding to each conversion stage is performed in sequence. For any conversion stage, the data type conversion process includes: A read address corresponding to the logical index is determined based on the first mapping relationship, and data is read from the memory resource corresponding to the first data based on the read address. After the read data element is converted from the data type corresponding to the first data to the data type corresponding to the second data, the data element after the data type conversion is written into the memory resource corresponding to the second data according to the second mapping relationship.

4. The method according to claim 3, characterized in that The method further comprises: For any of the conversion phases, an iterative step length for traversing the logic structure and a length of a burst transmission for reading data from a memory resource in the conversion phase are determined.

5. The method according to any one of claims 2 to 4, characterized in that The determining a target conversion strategy based on the first data type and the second data type includes: Searching for a mapping relationship based on the first data type and the second data type; In the case where a mapping relationship between the first data type and the second data type is found, determining that the target conversion strategy is a direct conversion strategy, the direct conversion strategy includes a conversion stage; Alternatively, when no mapping relationship from the first data type to the second data type is found, it is determined that the target conversion strategy is a multi-stage conversion strategy, and the multi-stage conversion strategy includes at least two conversion stages.

6. The method according to claim 4, characterized in that The determining, during the conversion phase, an iteration step length for traversing the logic structure and a burst transmission length for reading data from a memory resource comprises: The iteration step and the length of the burst transmission are calculated according to the data type of the first data and the data type of the second data, the physical layout of the first data and the physical layout of the second data, and the maximum length supported by the burst transmission.

7. The method according to claim 6, characterized in that The iterative step size satisfies the following conditions: After the iteration step is converted into a physical byte step, it does not exceed the maximum length of the supported burst transmission, and the starting address is aligned according to the data type; The length of the burst transmission is the minimum value of the maximum length of the supported burst transmission and the number of physical bytes of continuous data in the current iteration window.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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