Chip verification configuration file generation method and device, medium and electronic equipment

Abstract

The invention provides a chip verification configuration file generation method and device, a medium and electronic equipment, and the method comprises the steps: generating corresponding target universal verification configuration according to a verification angle in a file generation request when a test case configuration table comprises a target test case in a file generation request; and generating a chip verification configuration file corresponding to the target general verification configuration according to the test object, the domain configuration mode and the register configuration description file in the test case configuration table. According to the embodiment of the invention, a universal register configuration description format and a matched automation scheme are provided, the configuration requirement for automatically generating different verification modes can be met, the efficiency and correctness of chip verification configuration are greatly improved, and the period of multiple verification modes including Cmodel verification, simultation verification, emulation verification, SDK verification and the like is shortened.

Description

Technical Field

[0001] The present invention relates to the field of chip verification, and in particular to a chip verification configuration file generation method, device, medium and electronic equipment. Background Art

[0002] Chip tapeouts are long and costly, so before tapeout, chip designers verify the chip design process from multiple perspectives. Common verification methods include C-model verification, simulation verification, emulation verification, and SDK verification. All of these verifications require configuration of the chip or design module under test.

[0003] These verification configurations are typically manually filled out by verification personnel based on the chip specifications, or generated using custom scripts. Configuration formats often differ for different chips and verification perspectives, necessitating regeneration. When configuring large-scale chips, manual configuration is time-consuming, labor-intensive, and prone to errors, extending the entire verification cycle. Summary of the Invention

[0004] The object of the present invention is to provide a chip verification configuration file generation method, device, medium and electronic device to improve the above-mentioned problem.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides a method for generating a chip verification configuration file, the method comprising:

[0007] When the test case configuration table includes the target test case in the file generation request, generating a corresponding target general verification configuration according to the verification angle in the file generation request;

[0008] A chip verification configuration file corresponding to the target universal verification configuration is generated according to the test object, domain configuration mode, and register configuration description file in the test case configuration table.

[0009] Optionally, generating a chip verification configuration file corresponding to the target universal verification configuration according to the test object, domain configuration mode, and register configuration description file in the test case configuration table includes:

[0010] Determine whether the i-th test object in the test case configuration table is set with a domain configuration mode associated with the target test case, where the initial value of i is 1;

[0011] If yes, determine chip_ID and ins_ID according to the i-th test object;

[0012] According to the associated domain configuration mode, matching is performed in the register configuration description file to obtain N matching information, wherein the matching information includes a register name, a domain name, and a domain value;

[0013] Generate N verification configuration records based on the target universal verification configuration, chip_ID, ins_ID, and N matching information;

[0014] After generating N verification configuration records, or when no domain configuration mode associated with the target test case is set, let i=i+1 and determine whether i≤I holds, where I is the total number of test objects in the test case configuration table;

[0015] Repeatedly determine whether the i-th test object is set with a domain configuration mode associated with the target test case until i is greater than I, and write the verification configuration record corresponding to the target general verification configuration into the corresponding file template to obtain a chip verification configuration file.

[0016] Optionally, the method further comprises: adding the jth test object to the first column and the j+1th row in the table, 1≤j≤I;

[0017] Add the mth test case to the first row and the M+1th column of the table, where 1≤m≤M, and M is the total number of test cases.

[0018] Determine whether the jth test object is associated with the mth test case based on the association information input by the user;

[0019] If so, the associated domain configuration mode is added to the j+1th row and the M+1th column in the table, thereby constructing the test case configuration table.

[0020] Optionally, the target general verification configuration is any one or more of a general Cmodel verification configuration, a general simulation verification configuration, and a general emulation verification configuration.

[0021] Optionally, the method further comprises: determining whether the test case configuration table includes the target test case in the file generation request;

[0022] When the test case configuration table does not include the target test case in the file generation request, an error is reported.

[0023] Optionally, the format of the register configuration description file is a json file.

[0024] In a second aspect, an embodiment of the present invention provides a device for generating a chip verification configuration file, the device comprising:

[0025] A first processing unit is configured to generate a corresponding target general verification configuration according to a verification angle in the file generation request when the test case configuration table includes a target test case in the file generation request;

[0026] The second processing unit is configured to generate a chip verification configuration file corresponding to the target universal verification configuration according to the test object, domain configuration mode, and register configuration description file in the test case configuration table.

[0027] Optionally, generating a chip verification configuration file corresponding to the target universal verification configuration according to the test object, domain configuration mode, and register configuration description file in the test case configuration table includes:

[0028] Determine whether the i-th test object in the test case configuration table is set with a domain configuration mode associated with the target test case, where the initial value of i is 1;

[0029] If yes, determine chip_ID and ins_ID according to the i-th test object;

[0030] According to the associated domain configuration mode, matching is performed in the register configuration description file to obtain N matching information, wherein the matching information includes a register name, a domain name, and a domain value;

[0031] Generate N verification configuration records based on the target universal verification configuration, chip_ID, ins_ID, and N matching information;

[0032] After generating N verification configuration records, or when no domain configuration mode associated with the target test case is set, let i=i+1 and determine whether i≤I holds, where I is the total number of test objects in the test case configuration table;

[0033] Repeatedly determine whether the i-th test object is set with a domain configuration mode associated with the target test case until i is greater than I, and write the verification configuration record corresponding to the target general verification configuration into the corresponding file template to obtain a chip verification configuration file.

[0034] In a third aspect, an embodiment of the present invention provides a storage medium having a computer program stored thereon, which implements the above method when executed by a processor.

[0035] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising: a processor and a memory, wherein the memory is used to store one or more programs; when the one or more programs are executed by the processor, the above method is implemented.

[0036] Compared with the prior art, the embodiments of the present invention provide a chip verification configuration file generation method, device, medium and electronic device. When the test case configuration table includes the target test case in the file generation request, the corresponding target general verification configuration is generated according to the verification angle in the file generation request; and the chip verification configuration file corresponding to the target general verification configuration is generated according to the test object, domain configuration mode and register configuration description file in the test case configuration table. In the embodiments of the present invention, a universal register configuration description format and its supporting automation solution are proposed, which can meet the configuration requirements of automatically generating different verification modes, greatly improve the efficiency and correctness of chip verification configuration, and reduce the cycle of various verification modes including Cmodel verification, simulation verification, emulation verification, SDK verification, etc. When dealing with complex verification scenarios, the correctness of the generated configuration can also be guaranteed. Moreover, this set of solutions shields the differences between chips and can support multiple chips.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A schematic structural diagram of an electronic device provided by an embodiment of the present invention.

[0040] Figure 2 This is a flowchart of a method for generating a chip verification configuration file provided by an embodiment of the present invention.

[0041] Figure 3 This is a second flow chart of the method for generating a chip verification configuration file provided by an embodiment of the present invention.

[0042] Figure 4 This is a third flow chart of the method for generating a chip verification configuration file provided by an embodiment of the present invention.

[0043] Figure 5 A schematic diagram of the units of the device for generating a chip verification configuration file provided by an embodiment of the present invention.

[0044] In the figure: 10 - processor; 11 - memory; 12 - bus; 13 - communication interface; 501 - first processing unit; 502 - second processing unit. DETAILED DESCRIPTION

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0047] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and should not be understood as indicating or implying relative importance.

[0048] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0049] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limiting the present invention.

[0050] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0051] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0052] The embodiment of the present invention provides an electronic device, which can be a mobile phone, a computer, or a server device. Figure 1 , a schematic diagram of the structure of an electronic device. The electronic device includes a processor 10, a memory 11, and a bus 12. The processor 10 and the memory 11 are connected via the bus 12. The processor 10 is used to execute executable modules stored in the memory 11, such as computer programs.

[0053] The processor 10 can be an integrated circuit chip with signal processing capabilities. During the implementation process, each step of the chip verification configuration file generation method can be completed by the hardware integrated logic circuit in the processor 10 or the instructions in the form of software. The above-mentioned processor 10 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0054] The memory 11 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory.

[0055] The bus 12 may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. Figure 1 Only one bidirectional arrow is used in the figure, but it does not mean that there is only one bus 12 or one type of bus 12.

[0056] Memory 11 is used to store programs, such as a program corresponding to the chip verification profile generation device. The chip verification profile generation device includes at least one software function module that can be stored in the memory 11 in the form of software or firmware, or embedded in the operating system (OS) of the electronic device. After receiving the execution instruction, the processor 10 executes the program to implement the chip verification profile generation method.

[0057] Possibly, the electronic device provided by the embodiment of the present invention further includes a communication interface 13. The communication interface 13 is connected to the processor 10 via a bus.

[0058] It should be understood that Figure 1 The structure shown is only a schematic diagram of a portion of the electronic device. The electronic device may also include Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0059] The chip verification configuration file generation method provided by the embodiment of the present invention can be applied to, but not limited to, Figure 1 For detailed procedures, please refer to the electronic equipment shown in Figure 2 ,The chip verification configuration file generation method includes: S23 and S24, which are specifically described as follows.

[0060] S23 , when the test case configuration table includes the target test case in the file generation request, generating a corresponding target general verification configuration according to the verification angle in the file generation request.

[0061] Optionally, the target general verification configuration is any one or more of a general Cmodel verification configuration, a general simulation verification configuration, a general emulation verification configuration, and an SDK verification configuration.

[0062] The embodiment of the present invention provides corresponding universal verification configurations for different verification modes as a reference for configuration formats. The configurations generated by different verification modes must meet the grammatical requirements of their respective programming languages, and a variety of configuration generation formats can be customized to meet different verification requirements.

[0063] Please refer to Table 1, Table 2, and Table 3. Table 1 shows the format of the general Cmodel verification configuration, Table 2 shows the format of the general simulation verification configuration, and Table 3 shows the format of the general emulation verification configuration.

[0064] Table 1

[0065] write reg_name.ins_ID field_name field_value chip.chip_ID

[0066] Table 2

[0067] chip_chip_ID_reg_name_field_name.ins_ID field_value

[0068] Table 3

[0069]

[0070] Where reg_name indicates the register name, field_name indicates the field name, field_value indicates the field value, ins_ID indicates the instance number, and chip_ID indicates the chip number.

[0071] S24 , generating a chip verification configuration file corresponding to the target general verification configuration according to the test object, domain configuration mode, and register configuration description file in the test case configuration table.

[0072] Optionally, S24 generates a chip verification configuration file corresponding to the target general verification configuration according to the test object, domain configuration mode and register configuration description file in the test case configuration table, including: S241, S242, S243, S244, S245 and S246, which are specifically described as follows.

[0073] S241 , determining whether the i-th test object in the test case configuration table is configured with a domain configuration mode associated with the target test case, wherein the initial value of i is 1. If yes, execute S242 ; if no, execute S245 .

[0074] Please refer to Table 4, which is an example of a test case configuration table in an embodiment of the present invention.

[0075] Table 4

[0076] Test Case 1 Test Case 2 Test Case 3 Test Subject 1 cfgmode_1 cfgmode_2 cfgmode_1 Test Subject 2 cfgmode_2 cfgmode_2 Test Subject 3 cfgmode_2 cfgmode_3 Test Subject 4 cfgmode_2 cfgmode_4

[0077] Table 4 uses four test objects and three test cases as examples, but this is not intended to be limiting. The test objects correspond to different ports. cfgmode_k represents the kth domain configuration mode, where 1≤k≤K. It should be noted that the number of domain configuration modes K is not limited to four.

[0078] For example, the target test case is test case 1. The first test object is associated with test case 1, and an associated domain configuration mode (cfgmode_1) is set between the two. The second, third, and fourth test objects are not associated with test case 1.

[0079] S242 , determining chip_ID and ins_ID according to the i-th test object.

[0080] S243 , performing matching in the register configuration description file according to the associated domain configuration mode to obtain N pieces of matching information, where the matching information includes a register name, a domain name, and a domain value.

[0081] The register configuration description file of the embodiment of the present invention uses a universal register configuration description format. The register configuration description format includes: module name (module_name), register name (reg_name), domain name (field_name), domain configuration mode (cfgmode), and corresponding field values (field_value) for different configuration modes. The register configuration description file can be formatted as a JSON file, which is easy to read and write.

[0082] When only one module, one register, and one domain mode needs to be configured, the contents of register configuration description file 1 can be as follows:

[0083] / / module_name

[0084] CFG_F("module_name","reg_name","field_name",

[0085] {"cfgmode_1":"field_value_1","cfgmode_2":"field_value_2",…"cfgmode_n":"field_value_n"});

[0086] When a mode containing multiple modules, multiple registers, and multiple domains needs to be configured, it can be classified according to the module name. The content of register configuration description file 2 can be as follows:

[0087]

[0088]

[0089] The mapping relationship between the domain configuration mode and the corresponding module, register, domain, and corresponding domain value (field_value) is shown in Table 5 below.

[0090] Table 5

[0091]

[0092] According to the register configuration description file, a mapping relationship between the domain configuration mode and the corresponding module, register, domain, and corresponding domain value (field_value) as shown in Table 5 can be obtained.

[0093] The mapping relationship between the specific configuration mode and the field_value corresponding to the corresponding module, register, and domain. Refer to register configuration description file 2. For example, when the domain configuration mode is cfgmode_2, the corresponding module_name_1, reg_name_1, and field_name_1 correspond to the corresponding field value (field_value) to be configured as field_value_1_2, and the module_name_x, reg_name_a, and field_name_b correspond to the corresponding field value (field_value) to be configured as field_value_xab_2.

[0094] S244 , generating N verification configuration records according to the target universal verification configuration, chip_ID, ins_ID, and N pieces of matching information.

[0095] It should be understood that the unique signal in the chip can be specified through chip_ID, ins_ID, register name, domain name and domain value, so that N verification configuration records can be generated according to the target general verification configuration, chip_ID, ins_ID and N matching information to configure the specified signal.

[0096] After N verification configuration records are generated, or when no domain configuration mode associated with the target test case is set, S245 is executed.

[0097] S245: Let i = i + 1 and determine whether i ≤ I, where I is the total number of test objects in the test case configuration table. If not, execute S246; if so, repeat S241 to determine whether the i-th test object in the test case configuration table is configured with a domain configuration mode associated with the target test case.

[0098] S246 , writing the verification configuration record corresponding to the target universal verification configuration into the corresponding file template to obtain a chip verification configuration file.

[0099] Please refer to Figure 3 In an optional implementation, the chip verification configuration file generation method further includes: S11, S12, S13 and S14, which are specifically described as follows.

[0100] S11, add the jth test object to the first column and the j+1th row in the table.

[0101] Among them, 1≤j≤I.

[0102] S12, add the mth test case to the first row and the M+1th column in the table.

[0103] Where 1≤m≤M, M is the total number of test cases.

[0104] S13: Determine whether the jth test object is associated with the mth test case based on the association information input by the user. If so, execute S14; if not, skip.

[0105] S14, adding the associated domain configuration mode to the j+1th row and the M+1th column in the table, thereby constructing a test case configuration table (as shown in Table 4).

[0106] Please refer to Figure 4 In an optional implementation, the chip verification configuration file generation method further includes: S21 and S22, which are described in detail as follows.

[0107] S21, determine whether the test case configuration table includes the target test case in the file generation request. If so, execute S23; if not, execute S22.

[0108] S22: When the test case configuration table does not include the target test case in the file generation request, an error is reported.

[0109] The present invention proposes a universal register configuration description format and its accompanying automation solution, which can meet the requirements for automatically generating configurations for different verification modes. This significantly improves the efficiency and accuracy of chip verification configurations, and reduces the cycle time for various verification modes, including Cmodel verification, simulation verification, emulation verification, and SDK verification. The correctness of the generated configuration can also be guaranteed when handling complex verification scenarios. Furthermore, this solution shields chip differences and supports a wide range of chips.

[0110] See also Figure 5 , Figure 5 An embodiment of the present invention provides a device for generating a chip verification configuration file. Optionally, the device for generating a chip verification configuration file is applied to the electronic device described above.

[0111] The chip verification configuration file generating device includes: a first processing unit 501 and a second processing unit 502 .

[0112] The first processing unit 501 is configured to generate a corresponding target general verification configuration according to the verification angle in the file generation request when the test case configuration table includes the target test case in the file generation request;

[0113] The second processing unit 502 is configured to generate a chip verification configuration file corresponding to a target universal verification configuration according to the test object, domain configuration mode, and register configuration description file in the test case configuration table.

[0114] Optionally, a chip verification configuration file corresponding to the target general verification configuration is generated according to the test object, domain configuration mode, and register configuration description file in the test case configuration table, including:

[0115] Determine whether the i-th test object in the test case configuration table is set with a domain configuration mode associated with the target test case, where the initial value of i is 1;

[0116] If yes, determine chip_ID and ins_ID based on the i-th test object;

[0117] According to the associated domain configuration mode, matching is performed in the register configuration description file to obtain N matching information, the matching information including the register name, domain name and domain value;

[0118] Generate N verification configuration records based on the target universal verification configuration, chip_ID, ins_ID, and N matching information;

[0119] After N verification configuration records are generated, or when no domain configuration mode associated with the target test case is set, let i = i + 1 and determine whether i ≤ I holds, where I is the total number of test objects in the test case configuration table;

[0120] Repeatedly determine whether the i-th test object is set with a domain configuration mode associated with the target test case until i is greater than I, and write the verification configuration record corresponding to the target general verification configuration into the corresponding file template to obtain a chip verification configuration file.

[0121] Optionally, the second processing unit 502 may execute S24 in the above method embodiment, and the first processing unit 501 may execute other steps in the above method embodiment.

[0122] It should be noted that the chip verification configuration file generation device provided in this embodiment can execute the method flow shown in the above method flow embodiment to achieve the corresponding technical effects. For the sake of brevity, any part not mentioned in this embodiment can be referred to the corresponding content in the above embodiment.

[0123] An embodiment of the present invention further provides a storage medium storing computer instructions and programs that, when read and executed, execute the chip verification configuration file generation method of the above embodiment. The storage medium may include memory, flash memory, registers, or a combination thereof.

[0124] The following provides an electronic device, which can be a mobile phone, a computer, or a server device. Figure 1 As shown, the above-mentioned chip verification profile generation method can be implemented; specifically, the electronic device includes: a processor 10, a memory 11, and a bus 12. The processor 10 can be a CPU. The memory 11 is used to store one or more programs. When the one or more programs are executed by the processor 10, the chip verification profile generation method of the above-mentioned embodiment is executed.

[0125] In summary, the embodiments of the present invention provide a method, device, medium, and electronic device for generating a chip verification configuration file. When the test case configuration table includes a target test case in a file generation request, a corresponding target general verification configuration is generated according to the verification angle in the file generation request; and a chip verification configuration file corresponding to the target general verification configuration is generated according to the test object, domain configuration mode, and register configuration description file in the test case configuration table. In the embodiments of the present invention, a universal register configuration description format and its supporting automation solution are proposed, which can meet the configuration requirements of automatically generating different verification modes, greatly improve the efficiency and correctness of chip verification configuration, and reduce the cycle of various verification modes including Cmodel verification, simulation verification, emulation verification, SDK verification, etc.

[0126] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0127] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A chip verification configuration file generation method, characterized in that: The method comprises: When the test case configuration table includes the target test case in the file generation request, generating a corresponding target general verification configuration according to the verification angle in the file generation request; A chip verification configuration file corresponding to the target universal verification configuration is generated according to the test object, domain configuration mode, and register configuration description file in the test case configuration table.

2. The chip verification configuration file generation method according to claim 1, characterized in that: Generating a chip verification configuration file corresponding to the target universal verification configuration according to the test object, domain configuration mode, and register configuration description file in the test case configuration table includes: Determine whether the i-th test object in the test case configuration table is set with a domain configuration mode associated with the target test case, where the initial value of i is 1; If yes, determine chip_ID and ins_ID according to the i-th test object; According to the associated domain configuration mode, matching is performed in the register configuration description file to obtain N matching information, wherein the matching information includes a register name, a domain name, and a domain value; Generate N verification configuration records based on the target universal verification configuration, chip_ID, ins_ID, and N matching information; After generating N verification configuration records, or when no domain configuration mode associated with the target test case is set, let i=i+1 and determine whether i≤I holds, where I is the total number of test objects in the test case configuration table; Repeatedly determine whether the i-th test object is set with a domain configuration mode associated with the target test case until i is greater than I, and write the verification configuration record corresponding to the target general verification configuration into the corresponding file template to obtain a chip verification configuration file.

3. The chip verification configuration file generation method according to claim 2, characterized in that: The method further comprises: Add the jth test object to the first column and the j+1th row of the table, where 1≤j≤I; Add the mth test case to the first row and the M+1th column of the table, where 1≤m≤M, and M is the total number of test cases. Determine whether the jth test object is associated with the mth test case based on the association information input by the user; If so, the associated domain configuration mode is added to the j+1th row and the M+1th column in the table, thereby constructing the test case configuration table.

4. The chip verification configuration file generation method according to claim 1, characterized in that: The target universal verification configuration is any one or more of a universal Cmodel verification configuration, a universal simulation verification configuration, and a universal emulation verification configuration.

5. The chip verification configuration file generation method according to claim 1, characterized in that: The method further comprises: Determine whether the test case configuration table includes the target test case in the file generation request; When the test case configuration table does not include the target test case in the file generation request, an error is reported.

6. The chip verification configuration file generation method according to claim 1, characterized in that: The format of the register configuration description file is a json file.

7. A chip verification configuration file generating device, characterized in that: The device comprises: A first processing unit is configured to generate a corresponding target general verification configuration according to a verification angle in the file generation request when the test case configuration table includes a target test case in the file generation request; The second processing unit is configured to generate a chip verification configuration file corresponding to the target universal verification configuration according to the test object, domain configuration mode, and register configuration description file in the test case configuration table.

8. The chip verification configuration file generating device according to claim 7, wherein: Generating a chip verification configuration file corresponding to the target universal verification configuration according to the test object, domain configuration mode, and register configuration description file in the test case configuration table includes: Determine whether the i-th test object in the test case configuration table is set with a domain configuration mode associated with the target test case, where the initial value of i is 1; If yes, determine chip_ID and ins_ID according to the i-th test object; According to the associated domain configuration mode, matching is performed in the register configuration description file to obtain N matching information, wherein the matching information includes a register name, a domain name, and a domain value; Generate N verification configuration records based on the target universal verification configuration, chip_ID, ins_ID, and N matching information; After generating N verification configuration records, or when no domain configuration mode associated with the target test case is set, let i=i+1 and determine whether i≤I holds, where I is the total number of test objects in the test case configuration table; Repeatedly determine whether the i-th test object is set with a domain configuration mode associated with the target test case until i is greater than I, and write the verification configuration record corresponding to the target general verification configuration into the corresponding file template to obtain a chip verification configuration file.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. An electronic device, characterized in that: include: a processor and a memory, the memory being configured to store one or more programs; When the one or more programs are executed by the processor, the method according to any one of claims 1 to 6 is implemented.

Images