Method, system and equipment for fixing BIOS (Basic Input / Output System) data and medium

Abstract

The invention discloses a method, a system and equipment for fixing BIOS (Basic Input / Output System) data and a medium. The method comprises the following steps of: entering a BIOS debugging state; simulating an SPI (Serial Peripheral Interface) controller and binding a function; monitoring and responding to the PCH signal; dividing independent storage areas; obtaining a BIOS firmware component, and writing BIOS data; sPI channel communication between the BMC and the PCH is processed; exiting the BIOS debugging state; bIOS debugging and fixing: BIOS development, wherein a hardware module is in a working mode 1; bIOS firmware is uploaded, and after the BMC receives the BIOS firmware completely, the BIOS firmware is written into the storage When the system is started, the PCH obtains data from the ROM simulated by the BMC through the SPI bus and debugs the BIOS; writing the BIOS into the PROM, and switching to a working mode 2; the BMC writes the mature BIOS firmware into a BIOS ROM through an SPI communication protocol; when the BIOS is fixed, switching to a working mode 3; and the server is started, and the PCH acquires information from the BIOS ROM. By controlling BIOS access and modification permission in different stages, the requirements of research and development personnel for randomly modifying the BIOS to facilitate development and debugging are met, and the appeal that customers pursue stable operation of the BIOS and do not hope the BIOS to be modified is met at the same time.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer hardware and firmware, and relates to a method, system, device and medium for fixing BIOS data. Background Art

[0002] The BIOS (Basic Input / Output System) is the first software program loaded during computer startup and is stored in the motherboard's ROM chip. It serves as a critical bridge between system software and computer hardware. Its primary responsibility is to initialize various components on the motherboard, including the CPU, memory, PCIe devices, hard drives, and other devices. It is an essential component for ensuring stable computer operation.

[0003] ROM is widely used as non-volatile memory in server computers and other devices. It can permanently store data and will not lose data even in the event of a power outage. Currently, the common ROM types include the following:

[0004] PROM (Programmable Read Only Memory): The internal circuit mechanism of PROM determines that data can only be written once. Once the data is written, the internal data is permanently fixed and can only be read subsequently. It cannot be erased or rewritten.

[0005] EPROM (Erasable Programmable Read Only Memory): EPROM not only allows data to be written but also erased. It features a small window that can be erased by shining strong ultraviolet light through it. The window must be covered when not in use to prevent accidental exposure to sunlight or other sources of damage.

[0006] EEPROM (Electrically Erasable Programmable Read Only Memory): EEPROM's significant advantage lies in its ability to erase data using electrical signals, making it much more convenient than EPROM, which requires strong ultraviolet light to erase. In the current computer industry, EEPROM is widely used in BIOS ROMs for both personal computers and servers. This greatly facilitates the modification of ROM contents by users and R&D personnel when debugging or upgrading the BIOS.

[0007] Although EEPROM provides great convenience for R&D personnel in the application of BIOS ROM, allowing for free modification and upgrades during the BIOS development process, significantly reducing R&D costs, in some special application scenarios with extremely high stability requirements, the modifiable nature of EEPROM has become a major factor in causing unstable server operation. In the application of computer servers in confidential units, servers are usually placed in a closed computer room for management, connected only to the unit's internal LAN, and completely isolated from the Internet. In this case, once a problem occurs with the server, the return process often requires multiple levels of approval, and the communication cost and time cost with after-sales maintenance personnel are extremely high.

[0008] Due to the numerous options and complex functions in the BIOS, even seemingly minor changes can cause certain functions to deviate from their original state. For those unfamiliar with BIOS, there's a high risk of inadvertently modifying the contents of the BIOS ROM while operating the machine. For example, they might mistakenly modify a BIOS item they believe has no impact, or run unknown software on the system, leading to improper operation of the BIOS ROM. These changes can alter server functionality and hinder normal business operations. Furthermore, due to the confidentiality implications, after-sales maintenance personnel must expend additional time and effort to resolve such issues, further complicating the difficulty of resolving the problem.

[0009] In factory production environments, servers primarily support the efficient operation of production lines, making stability a primary consideration. For factories, time is of the essence, and the continued stable operation of servers is directly linked to the smooth functioning of production lines. However, due to the constant operation of production lines, servers are frequently used, with different personnel rotating between them. In such situations, the aforementioned inadvertent modification of BIOS ROM content is highly likely to occur. Once such an issue occurs, even a minor malfunction requires communication with after-sales service personnel to resolve, which not only consumes considerable time and effort but can also severely impact production schedules.

[0010] In summary, although EEPROM has many advantages as a storage medium for BIOS ROM, in special application scenarios where stable server operation is sought, the instability factors brought about by its modifiable nature cannot be ignored. A new technical solution is urgently needed to solve this problem in order to meet the strict requirements of specific customers for server stability. Summary of the Invention

[0011] The purpose of the present invention is to solve the problem in the prior art of the conflict between BIOS modifiability and stability requirements in specific scenarios, and to provide a method, system, device and medium for fixing BIOS data.

[0012] In order to achieve the above object, the present invention adopts the following technical solutions:

[0013] A method for fixing BIOS data, comprising:

[0014] Enter BIOS debugging state:

[0015] Simulate the SPI controller, call the BMC system interface, apply for processor, memory, and IO interface resources, simulate the SPI controller and bind functions, and provide SPI signals in the form of function interfaces;

[0016] Monitor and respond to PCH signals, establish a process to monitor the IO pin signal fluctuations connecting the BMC and PCH, parse the signal according to the SPI communication protocol for use by other components, or encode information according to the SPI communication protocol and send it to the PCH according to the command of other components;

[0017] Divide independent storage areas, open independent storage areas under the BMC system, query available storage space, select space and record the address segment, and hide the space segment through the system interface;

[0018] Obtain the BIOS firmware and receive the BIOS firmware uploaded through the BMC management network port. After checking that it is complete, write the BIOS data. If there is no BIOS data in the storage area, write it directly. If there is BIOS data, erase the old data first and then write the new data.

[0019] Processes SPI channel communication between BMC and PCH. After booting, it obtains PCH requirements through the monitoring and response module, operates the storage area according to the address segment, and returns information to PCH.

[0020] Exit the BIOS debugging state, close the above-mentioned components, and release the corresponding system resources;

[0021] BIOS debugging and fixing process:

[0022] During the BIOS development phase, the hardware module is in working mode 1. That is, after receiving a control signal, the main control chip controls the switch to connect the SPI channel between the PCH and the BMC and disconnect the SPI channel of the BIOS ROM. The BIOS firmware is uploaded through the BMC management network port. The BMC receives the complete data and writes it to the storage device. When the system is powered on, the PCH obtains data from the BMC-emulated ROM via the SPI bus and uses this data to debug the BIOS.

[0023] During the BIOS writing phase, after the development phase is completed, the BMC sends a control signal to the hardware module, switching to operating mode 2. Upon receiving the control signal, the main control chip controls the switch to connect the channel between the BMC and the BIOS ROM and disconnect the SPI channel of the PCH. That is, the BMC writes the mature BIOS firmware to the BIOS ROM using the SPI communication protocol. The BIOS ROM adopts a PROM design.

[0024] During the BIOS fixation phase, after writing is complete, the BMC sends a control signal again to switch to operating mode 3. That is, after receiving the control signal, the main control chip controls the switch to connect the channel between the PCH and the BIOS ROM and disconnect the BMC's SPI channel. When the server is powered on, the PCH obtains information from the BIOS ROM. Due to the characteristics of the PROM, the BIOS firmware cannot be modified.

[0025] The monitoring and response to PCH signals, establishing a process to monitor the IO pin signal fluctuations connecting the BMC and PCH, parsing the signals according to the SPI communication protocol for use by other components, or encoding information according to the SPI communication protocol and sending it to the PCH according to commands from other components; dividing independent storage areas, opening independent storage areas under the BMC system, querying available storage space, selecting space and recording address segments, and hiding the segment space through the system interface; specifically:

[0026] Signal monitoring: Four processes are pre-established in the BMC system to detect signal changes on specific IO pins connected to the PCH, and corresponding system resources are allocated to them. When the system is powered on and the PCH obtains BIOS data from the SPI bus, the four pin detection processes monitor the signal changes on the corresponding IO pins in real time.

[0027] Request analysis: When the detection process detects a signal change, it is determined that the PCH has sent a request and the detected signal is analyzed according to the SPI communication protocol;

[0028] Storage area operation: Based on the parsed request content, the BMC system interface is called to operate the storage area pre-allocated for storing BIOS firmware. If the request is to read BIOS data, the corresponding BIOS data is read from the storage area according to the data address information in the request. If the request is to write BIOS data, the BIOS data to be written is written to the corresponding location in the storage area according to the data address information in the request.

[0029] Data return: The content to be returned to the PCH is encoded according to the SPI communication protocol to form a data format that complies with the SPI communication specification. The encoded data is returned to the PCH in the form of an SPI signal through the IO pins monitored by the four detection processes using the SPI signal interface simulated by the BMC. This enables normal communication between the BMC simulated SPI controller and the PCH, ensuring that the PCH can correctly obtain or write BIOS data.

[0030] The BIOS firmware is obtained by receiving the BIOS firmware uploaded through the BMC management network port. After the detection is complete, if there is no BIOS data in the storage area, it is directly written. If there is BIOS data, the old data is erased first and then the new data is written. Specifically:

[0031] Complete reception judgment: The BIOS firmware is uploaded to the BMC through the BMC management network port. The BMC monitors the BIOS firmware reception status through the management network port in real time. When the BMC has completely received the BIOS firmware, it starts the subsequent operation of writing the BIOS firmware information to the storage device.

[0032] Storage area status mark: When the BMC receives the BIOS firmware completely and successfully stores it in the storage device, it marks the storage area storing the BIOS firmware as available.

[0033] Write processing in different scenarios: During the first upload, when the software module detects that the storage area is uploading the BIOS firmware for the first time, that is, the storage area has not yet stored BIOS data, it directly writes the received complete BIOS firmware data into the storage area; during subsequent uploads, when the software module detects that the storage area already has BIOS data, that is, when the BIOS firmware information is subsequently uploaded, it first erases the old BIOS data in the storage area, and then writes the received complete new BIOS firmware data into the storage area.

[0034] When writing BIOS data, it is also necessary to prevent concurrent access conflicts in the BIOS firmware storage area in the BMC system, specifically by the following steps:

[0035] System status monitoring: Real-time monitoring of the computer system's operating status, including at least the power-on and power-off states. It also monitors whether a user initiates a BIOS firmware update operation through the BMC dedicated network, and whether there is a need for SPI-based communication between the PCH and the BMC.

[0036] BIOS firmware update restriction in the powered-on state: When the computer system is detected to be powered on, BIOS firmware update requests initiated by users through the BMC dedicated network are intercepted and the BMC is prohibited from performing operations related to the BIOS firmware update request.

[0037] PCH and BMC communication restrictions during BIOS firmware updates: When detecting that a user is updating the BIOS firmware through the BMC dedicated network, a communication disable command is sent to the SPI communication module between the PCH and BMC, preventing SPI bus-based communication between the PCH and BMC.

[0038] BIOS firmware update in shutdown state is isolated from PCH access: When the computer system is detected to be in shutdown state and the R&D personnel initiate a BIOS firmware update operation through the BMC dedicated network, the BMC starts the update process and performs read and write operations on the storage area to complete the BIOS firmware update;

[0039] If the system is manually powered on during the update process, the internal logic control mechanism ensures that the PCH cannot access or interfere with the storage area being operated by the BMC;

[0040] After the BMC completes the BIOS firmware update operation, it controls the computer system to restart so that the PCH can normally obtain the BIOS data from the updated storage area to complete the boot process;

[0041] State synchronization and recovery: When the system switches from the power-on state to the power-off state, the system status flag is updated and the user is allowed to initiate a BIOS firmware update operation through the BMC dedicated network. When the BIOS firmware update operation is completed, the status flag is updated, the SPI communication restriction between the PCH and BMC is lifted, and the system resumes normal PCH and BMC communication functions.

[0042] After the BIOS firmware update operation is completed, the status flag is updated to allow the PCH and BMC to perform normal SPI communication when the system is powered on. At the same time, the user is prohibited from initiating the BIOS firmware update operation again when the system is powered on, ensuring that the storage area is accessed by only one process at a time.

[0043] When exiting the BIOS debugging state, shutting down the above-mentioned enabled components, and releasing the corresponding system resources, specifically:

[0044] Resource release when exiting the BIOS debugging state: When debugging is completed and the BMC is instructed to exit the BIOS debugging state through a command, the exit command is received;

[0045] The following resource release procedures are performed in sequence: four processes used to detect SPI signals are closed, thereby releasing the system resources occupied by the four processes; the simulated SPI controller and the implementation interface of related signals are closed, thereby releasing the system resources related to the simulated SPI controller; on the storage device, all contents in the area allocated for storing BIOS firmware are erased and all marking information related to the area is cleared; the storage resources occupied by the storage area are released, thereby restoring the storage area to an unallocated state;

[0046] Resource restart when re-entering the BIOS debugging state: When a command is sent again to instruct the BMC to enter the BIOS debugging state, the entry command is received; the four processes for detecting SPI signals that were closed when exiting the BIOS debugging state are restarted, and corresponding system resources are re-applied for the processes; the SPI controller is re-simulated and the implementation interface of the relevant signals is enabled, and system resources related to the simulated SPI controller are re-applied for; and the area for storing the BIOS firmware on the storage device is re-applied for and allocated, completing the reconfiguration of resources required for the BIOS debugging process to resume the BIOS debugging operation.

[0047] The method further comprises the following steps:

[0048] Determine and prepare for the end of the R&D process: Continuously monitor the R&D process status. When the R&D process is determined to be complete and the computer system is shipped, enter the BIOS firmware solidification preparation phase. Confirm that the uploaded mature BIOS firmware data is complete and valid.

[0049] Working mode switching and activating the simulated SPI controller: A first control signal is sent to the hardware module, indicating a change in the hardware module's working mode. The first control signal opens the SPI channel between the BMC and the BIOS ROM, while simultaneously closing the SPI channel between the PCH and the BMC. After the working mode switch is completed, the simulated SPI controller within the BMC is activated and its parameters are initialized. The mature BIOS firmware data stored in a designated storage area within the BMC system is written to the BIOS ROM via the simulated SPI controller according to the SPI communication protocol.

[0050] Secondary working mode switching: After confirming that the BIOS firmware data has been successfully written into the BIOS ROM, a second control signal is sent to the hardware module. The second control signal is used to instruct the hardware module to change its working mode, that is, to open the SPI channel between the PCH and the BIOS ROM, and at the same time close the SPI channel between the BMC and the BIOS ROM.

[0051] Operation mode guarantee: When the computer system is powered on, the PCH reads the BIOS data from the BIOS ROM designed with the PROM through the SPI channel between the PCH and the BIOS ROM that has been opened.

[0052] After receiving the first control signal, the hardware module triggers the internal fuse blowing mechanism to blow the fuse associated with working mode 1, and simultaneously establishes an SPI channel between the BMC and the BIOS ROM, so that the simulated SPI controller inside the BMC can communicate with the BIOS ROM through the SPI channel, and closes the SPI channel between the PCH and the BMC, so that the PCH can no longer communicate with the BMC through the hardware module. After receiving the second control signal, the hardware module again triggers the internal fuse blowing mechanism to blow the fuse associated with working mode 2, and simultaneously opens the SPI channel between the PCH and the BIOS ROM, and closes the SPI channel between the BMC and the BIOS ROM, ensuring that SPI communication between the PCH and the BIOS ROM is normally established, and the BMC can no longer communicate with the BIOS ROM through the hardware module.

[0053] A system for fixing BIOS data, comprising:

[0054] BIOS debugging state startup and resource management components:

[0055] The simulated SPI controller module is used to simulate an SPI controller and dynamically apply for processor, memory, and IO interface resources by calling the BMC system interface. After completing the resource application, the simulated SPI controller is bound to the relevant functions and the SPI signal interaction function is provided to other system components in the form of a function interface, so that other components can exchange data with the simulated SPI controller through this function interface.

[0056] The PCH signal monitoring and parsing module establishes an independent process to monitor the signal fluctuations of the IO pins connecting the BMC and PCH. This process parses the monitored signals according to the SPI communication protocol and provides the parsed data to other system components. At the same time, according to the commands of other components, the information sent to the PCH is encoded according to the SPI communication protocol and sent to the PCH through the IO pins.

[0057] The independent storage area management module opens an independent storage area under the BMC system, selects the appropriate storage space and records its address segment by querying the system's available storage space information; and uses the BMC system interface to hide the storage area.

[0058] The BIOS firmware acquisition and write module receives the uploaded BIOS firmware through the BMC management network port and performs integrity checks on the BIOS firmware after receiving it. If the integrity check passes and no BIOS data is detected in the independent storage area, the received BIOS firmware is directly written to the storage area. If BIOS data already exists in the storage area, the old data is erased before the newly received BIOS firmware is written.

[0059] The SPI channel communication processing module between the BMC and the PCH obtains the PCH's BIOS data requirements through the PCH signal monitoring and parsing module after the computer system is powered on. Based on the PCH's requirements, it reads the corresponding BIOS data from the storage area according to the address segment recorded by the independent storage area management module and returns the read data to the PCH to support the PCH in performing BIOS debugging operations.

[0060] BIOS debugging state exit and resource release components:

[0061] When the BIOS debugging work is completed and an instruction to exit the BIOS debugging state is issued, all enabled components in the above-mentioned analog SPI controller module, PCH signal monitoring and analysis module, independent storage area management module, and BIOS firmware acquisition and writing module are shut down; at the same time, the processor, memory, and IO interface system resources occupied during the operation are released;

[0062] Hardware switching module and working mode control components:

[0063] Hardware switching module: The hardware switching module includes a main control chip and a switch. The main control chip can receive control signals sent by the BMC and control the connection state of the switch according to the control signals to connect or disconnect the SPI channels between different components.

[0064] Working Mode 1: During the BIOS development phase, the hardware module is in Working Mode 1. After the main control chip receives the corresponding control signal from the BMC, it controls the switch to connect the SPI channel between the PCH and BMC, while disconnecting the SPI channel of the BIOS ROM.

[0065] Working Mode 2: When the BIOS development phase is complete, the BMC sends a control signal to the hardware module to switch it to working mode 2. After receiving the control signal, the main control chip controls the switch to connect the SPI channel between the BMC and the BIOS ROM, while disconnecting the SPI channel of the PCH.

[0066] Working mode 3: After the BIOS firmware is successfully written to the BIOS ROM, the BMC sends a control signal again to switch the hardware module to working mode 3. After receiving the control signal, the main control chip controls the switch to connect the SPI channel between the PCH and the BIOS ROM, and disconnect the BMC's SPI channel.

[0067] A device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method as described in any one of the preceding items when executing the computer program.

[0068] A computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of the preceding items.

[0069] Compared with the prior art, the present invention has the following beneficial effects:

[0070] The method for fixing BIOS data in this invention flexibly controls BIOS access and modification permissions at different stages, simultaneously satisfying both R&D personnel's need for arbitrary BIOS modification to facilitate development and debugging, and customers' desire for stable BIOS operation and a desire for unmodified BIOS. During the R&D phase, this method provides R&D personnel with an unrestricted BIOS modification environment, enabling them to fully develop and verify various functions. During the shipping phase, by writing the mature BIOS into the PROM, the BIOS data used by customers cannot be modified, achieving a high degree of uniformity in requirements and avoiding the need to design different motherboards or perform complex hardware modifications due to conflicting requirements, significantly reducing product design and development costs.

[0071] During the R&D phase, the BMC's internal simulation conversion method provides BIOS developers with an unlimited modification environment. They can experiment with different BIOS configurations and code modifications without worrying about hardware limitations or data security issues. This allows developers to debug and verify more efficiently, promptly identifying and resolving potential issues, thereby shortening the R&D cycle and accelerating time to market. Furthermore, thorough R&D verification significantly improves BIOS stability and compatibility, providing high-quality, mature BIOS firmware for shipment, reducing the risk of problems encountered during customer use and enhancing overall product quality and market competitiveness.

[0072] During the shipment phase, the mature BIOS is written to the PROM. Leveraging the unmodifiable nature of PROM data, this fundamentally guarantees the stability of the BIOS data in the customer's system. Customers no longer have to worry about accidental or malicious BIOS modifications, ensuring that the server system maintains a consistent startup and operating state over the long term. This reduces the risk of system failures and data loss due to BIOS issues, improving customer service continuity and reliability. Furthermore, the unmodifiable BIOS data enhances system security, preventing potential security vulnerabilities introduced by unauthorized BIOS modifications, safeguarding the security and privacy of customer data, and meeting customers' stringent requirements for system stability and security. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0074] Figure 1 Schematic diagram of the hardware structure of the present invention;

[0075] Figure 2 This is a schematic diagram of working mode 1 of the present invention;

[0076] Figure 3 This is a schematic diagram of the working process of working mode 1 of the present invention;

[0077] Figure 4 This is a schematic diagram of working mode 2 of the present invention;

[0078] Figure 5 This is a schematic diagram of working mode 3 of the present invention;

[0079] Figure 6 This is a schematic diagram of the SPI channel signal line connection of the present invention;

[0080] Figure 7 This is the workflow diagram for BMC entering BIOS debugging state;

[0081] Figure 8 This is the workflow diagram for uploading BIOS firmware through the BMC management network port;

[0082] Figure 9 The workflow diagram for PCH to obtain BIOS data after the system is powered on;

[0083] Figure 10 Workflow diagram for preventing storage areas from being operated simultaneously when uploading BIOS firmware;

[0084] Figure 11 A flowchart for preventing the storage area from being operated simultaneously when the PCH obtains BIOS data after the system is powered on;

[0085] Figure 12 This is the workflow diagram when BMC exits BIOS debugging state;

[0086] Figure 13 This is the workflow diagram for writing BIOS firmware into PROM at the end of the R&D process;

[0087] Figure 14 This is a flowchart of the internal fuse blowing mechanism of the hardware module after shipment. DETAILED DESCRIPTION

[0088] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0089] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0090] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0091] A method for fixing BIOS data in the present invention includes the following steps:

[0092] Enter BIOS debugging state:

[0093] Simulate the SPI controller, call the BMC system interface, apply for processor, memory, and IO interface resources, simulate the SPI controller and bind functions, and provide SPI signals in the form of function interfaces.

[0094] Monitor and respond to PCH signals, establish a process to monitor the IO pin signal fluctuations connecting BMC and PCH, parse the signals according to the SPI communication protocol for use by other components, or encode information according to the SPI communication protocol and send it to PCH based on commands from other components.

[0095] Divide independent storage areas, open independent storage areas under the BMC system, query available storage space, select space and record address segments, and hide the space segment through the system interface. Specifically:

[0096] Signal monitoring: Four processes are pre-established in the BMC system to detect signal changes on specific IO pins connected to the PCH, and corresponding system resources are allocated to them. When the system is powered on and the PCH obtains BIOS data from the SPI bus, the four pin detection processes monitor the signal changes on the corresponding IO pins in real time.

[0097] Request analysis: When the detection process detects a signal change, it is determined that the PCH has sent a request and the detected signal is analyzed according to the SPI communication protocol;

[0098] Storage area operation: Based on the parsed request content, the BMC system interface is called to operate the storage area pre-allocated for storing BIOS firmware. If the request is to read BIOS data, the corresponding BIOS data is read from the storage area according to the data address information in the request. If the request is to write BIOS data, the BIOS data to be written is written to the corresponding location in the storage area according to the data address information in the request.

[0099] Data return: The content to be returned to the PCH is encoded according to the SPI communication protocol to form a data format that complies with the SPI communication specification. The encoded data is returned to the PCH in the form of an SPI signal through the IO pins monitored by the four detection processes using the SPI signal interface simulated by the BMC. This enables normal communication between the BMC simulated SPI controller and the PCH, ensuring that the PCH can correctly obtain or write BIOS data.

[0100] Get the BIOS firmware, receive the BIOS firmware uploaded through the BMC management network port, and write the BIOS data after the test is complete. If there is no BIOS data in the storage area, write it directly. If there is, erase the old data first and then write the new data.

[0101] Complete reception judgment: The BIOS firmware is uploaded to the BMC through the BMC management network port. The BMC monitors the BIOS firmware reception status through the management network port in real time. When the BMC has completely received the BIOS firmware, it starts the subsequent operation of writing the BIOS firmware information to the storage device.

[0102] Storage area status mark: When the BMC receives the BIOS firmware completely and successfully stores it in the storage device, it marks the storage area storing the BIOS firmware as available.

[0103] Write processing in different scenarios: During the first upload, when the software module detects that the storage area is uploading the BIOS firmware for the first time, that is, the storage area has not yet stored BIOS data, it directly writes the received complete BIOS firmware data into the storage area; during subsequent uploads, when the software module detects that the storage area already has BIOS data, that is, when the BIOS firmware information is subsequently uploaded, it first erases the old BIOS data in the storage area, and then writes the received complete new BIOS firmware data into the storage area.

[0104] When writing BIOS data, you must also prevent concurrent access conflicts in the BIOS firmware storage area in the BMC system. Specific steps include:

[0105] System status monitoring: Real-time monitoring of the computer system's operating status, including at least the power-on and power-off states. It also monitors whether a user initiates a BIOS firmware update operation through the BMC dedicated network, and whether there is a need for SPI-based communication between the PCH and the BMC.

[0106] BIOS firmware update restriction in the powered-on state: When the computer system is detected to be powered on, BIOS firmware update requests initiated by users through the BMC dedicated network are intercepted and the BMC is prohibited from performing operations related to the BIOS firmware update request.

[0107] PCH and BMC communication restrictions during BIOS firmware updates: When detecting that a user is updating the BIOS firmware through the BMC dedicated network, a communication disable command is sent to the SPI communication module between the PCH and BMC, preventing SPI bus-based communication between the PCH and BMC.

[0108] BIOS firmware update in shutdown state is isolated from PCH access: When the computer system is detected to be in shutdown state and the R&D personnel initiate a BIOS firmware update operation through the BMC dedicated network, the BMC starts the update process and performs read and write operations on the storage area to complete the BIOS firmware update;

[0109] If the system is manually powered on during the update process, the internal logic control mechanism ensures that the PCH cannot access or interfere with the storage area being operated by the BMC;

[0110] After the BMC completes the BIOS firmware update operation, it controls the computer system to restart so that the PCH can normally obtain the BIOS data from the updated storage area to complete the boot process;

[0111] State synchronization and recovery: When the system switches from the power-on state to the power-off state, the system status flag is updated and the user is allowed to initiate a BIOS firmware update operation through the BMC dedicated network. When the BIOS firmware update operation is completed, the status flag is updated, the SPI communication restriction between the PCH and BMC is lifted, and the system resumes normal PCH and BMC communication functions.

[0112] After the BIOS firmware update operation is completed, the status flag is updated to allow the PCH and BMC to perform normal SPI communication when the system is powered on. At the same time, the user is prohibited from initiating the BIOS firmware update operation again when the system is powered on, ensuring that the storage area is accessed by only one process at a time.

[0113] Processes SPI channel communication between BMC and PCH. After booting, it obtains PCH requirements through the monitoring and response module, operates the storage area according to the address segment and returns information to PCH.

[0114] Exit the BIOS debugging state, close the above-mentioned components, and release the corresponding system resources.

[0115] Specifically:

[0116] Resource release when exiting the BIOS debugging state: When debugging is completed and the BMC is instructed to exit the BIOS debugging state through a command, the exit command is received;

[0117] The following resource release procedures are performed in sequence: four processes used to detect SPI signals are closed, thereby releasing the system resources occupied by the four processes; the simulated SPI controller and the implementation interface of related signals are closed, thereby releasing the system resources related to the simulated SPI controller; on the storage device, all contents in the area allocated for storing BIOS firmware are erased and all marking information related to the area is cleared; the storage resources occupied by the storage area are released, thereby restoring the storage area to an unallocated state;

[0118] Resource restart when re-entering the BIOS debugging state: When a command is sent again to instruct the BMC to enter the BIOS debugging state, the entry command is received; the four processes for detecting SPI signals that were closed when exiting the BIOS debugging state are restarted, and corresponding system resources are re-applied for the processes; the SPI controller is re-simulated and the implementation interface of the relevant signals is enabled, and system resources related to the simulated SPI controller are re-applied for; and the area for storing the BIOS firmware on the storage device is re-applied for and allocated, completing the reconfiguration of resources required for the BIOS debugging process to resume the BIOS debugging operation.

[0119] BIOS debugging and fixing process:

[0120] During the BIOS development phase, the hardware module is in working mode 1. That is, after the main control chip receives a control signal, it controls the switch to connect the SPI channel between the PCH and the BMC and disconnect the SPI channel of the BIOS ROM. The BIOS firmware is uploaded through the BMC management network port. After the BMC receives the complete data, it writes it to the storage device. When the system is powered on, the PCH obtains data from the BMC-emulated ROM through the SPI bus and uses this data to debug the BIOS.

[0121] During the BIOS writing to PROM phase, after the development phase is completed, the BMC sends a control signal to the hardware module to switch to operating mode 2. After receiving the control signal, the main control chip controls the switch to connect the channel between the BMC and the BIOS ROM and disconnect the SPI channel of the PCH. That is, the BMC writes the mature BIOS firmware to the BIOS ROM through the SPI communication protocol, where the BIOS ROM adopts the PROM design.

[0122] During the BIOS fixation phase, after writing is complete, the BMC sends a control signal again to switch to operating mode 3. That is, after receiving the control signal, the main control chip controls the switch to connect the channel between the PCH and the BIOS ROM and disconnect the BMC's SPI channel. When the server is powered on, the PCH obtains information from the BIOS ROM. Due to the characteristics of the PROM, the BIOS firmware cannot be modified.

[0123] Determine and prepare for the end of the R&D process: Continuously monitor the R&D process status. When the R&D process is determined to be complete and the computer system is shipped, enter the BIOS firmware solidification preparation phase. Confirm that the uploaded mature BIOS firmware data is complete and valid.

[0124] Working mode switching and activating the simulated SPI controller: A first control signal is sent to the hardware module, indicating a change in the hardware module's working mode. The first control signal opens the SPI channel between the BMC and the BIOS ROM, while simultaneously closing the SPI channel between the PCH and the BMC. After the working mode switch is completed, the simulated SPI controller within the BMC is activated and its parameters are initialized. The mature BIOS firmware data stored in a designated storage area within the BMC system is written to the BIOS ROM via the simulated SPI controller according to the SPI communication protocol.

[0125] Secondary working mode switching: After confirming that the BIOS firmware data has been successfully written into the BIOS ROM, a second control signal is sent to the hardware module. The second control signal is used to instruct the hardware module to change its working mode, that is, to open the SPI channel between the PCH and the BIOS ROM, and at the same time close the SPI channel between the BMC and the BIOS ROM.

[0126] Operation mode guarantee: When the computer system is powered on, the PCH reads the BIOS data from the BIOS ROM designed with the PROM through the SPI channel between the PCH and the BIOS ROM that has been opened.

[0127] After receiving the first control signal, the hardware module triggers the internal fuse blowing mechanism to blow the fuse associated with working mode 1, and simultaneously establishes an SPI channel between the BMC and the BIOS ROM, so that the simulated SPI controller inside the BMC can communicate with the BIOS ROM through the SPI channel, and closes the SPI channel between the PCH and the BMC, so that the PCH can no longer communicate with the BMC through the hardware module. After receiving the second control signal, the hardware module again triggers the internal fuse blowing mechanism to blow the fuse associated with working mode 2, and simultaneously opens the SPI channel between the PCH and the BIOS ROM, and closes the SPI channel between the BMC and the BIOS ROM, ensuring that SPI communication between the PCH and the BIOS ROM is normally established, and the BMC can no longer communicate with the BIOS ROM through the hardware module.

[0128] An embodiment of the present invention is a system for fixing BIOS data, comprising:

[0129] BIOS debugging state startup and resource management components:

[0130] The simulated SPI controller module is used to simulate an SPI controller and dynamically apply for processor, memory, and IO interface resources by calling the BMC system interface. After completing the resource application, the simulated SPI controller is bound to the relevant functions and the SPI signal interaction function is provided to other system components in the form of a function interface, so that other components can exchange data with the simulated SPI controller through this function interface.

[0131] The PCH signal monitoring and parsing module establishes an independent process to monitor the signal fluctuations of the IO pins connecting the BMC and PCH. This process parses the monitored signals according to the SPI communication protocol and provides the parsed data to other system components. At the same time, according to the commands of other components, the information sent to the PCH is encoded according to the SPI communication protocol and sent to the PCH through the IO pins.

[0132] The independent storage area management module opens an independent storage area under the BMC system, selects the appropriate storage space and records its address segment by querying the system's available storage space information; and uses the BMC system interface to hide the storage area.

[0133] The BIOS firmware acquisition and write module receives the uploaded BIOS firmware through the BMC management network port and performs integrity checks on the BIOS firmware after receiving it. If the integrity check passes and no BIOS data is detected in the independent storage area, the received BIOS firmware is directly written to the storage area. If BIOS data already exists in the storage area, the old data is erased before the newly received BIOS firmware is written.

[0134] The SPI channel communication processing module between the BMC and the PCH obtains the PCH's BIOS data requirements through the PCH signal monitoring and parsing module after the computer system is powered on. Based on the PCH's requirements, it reads the corresponding BIOS data from the storage area according to the address segment recorded by the independent storage area management module and returns the read data to the PCH to support the PCH in performing BIOS debugging operations.

[0135] BIOS debugging state exit and resource release components:

[0136] When the BIOS debugging work is completed and an instruction to exit the BIOS debugging state is issued, all enabled components in the above-mentioned analog SPI controller module, PCH signal monitoring and analysis module, independent storage area management module, and BIOS firmware acquisition and writing module are shut down; at the same time, the processor, memory, and IO interface system resources occupied during the operation are released;

[0137] Hardware switching module and working mode control components:

[0138] Hardware switching module: The hardware switching module includes a main control chip and a switch. The main control chip can receive control signals sent by the BMC and control the connection state of the switch according to the control signals to connect or disconnect the SPI channels between different components.

[0139] Working Mode 1: During the BIOS development phase, the hardware module is in Working Mode 1. After the main control chip receives the corresponding control signal from the BMC, it controls the switch to connect the SPI channel between the PCH and BMC, while disconnecting the SPI channel of the BIOS ROM.

[0140] Working Mode 2: When the BIOS development phase is complete, the BMC sends a control signal to the hardware module to switch it to working mode 2. After receiving the control signal, the main control chip controls the switch to connect the SPI channel between the BMC and the BIOS ROM, while disconnecting the SPI channel of the PCH.

[0141] Working mode 3: After the BIOS firmware is successfully written to the BIOS ROM, the BMC sends a control signal again to switch the hardware module to working mode 3. After receiving the control signal, the main control chip controls the switch to connect the SPI channel between the PCH and the BIOS ROM, and disconnect the BMC's SPI channel.

[0142] The present invention is described in further detail below with reference to the accompanying drawings:

[0143] See also Figure 1 , a schematic diagram of the hardware structure of the present invention, simultaneously connects the PCH, BMC, and BIOS ROM, eliminating the need for the PCH to be directly connected to the BIOS ROM. The hardware module is placed on the motherboard and is a functional module consisting of SPI signal lines, switches, a main control chip, fuses, etc.

[0144] It has the following external functions:

[0145] SPI signal channel switching function: Based on the control signal sent by the BMC, the hardware module has three operating modes. The SPI signal channels in different modes are different. The principle is that after the main control chip receives the control signal, it controls the switch to switch the SPI signal channel. Operating Mode 1: The SPI channel between the PCH and BMC is connected. The SPI channel of the BIOS ROM is disconnected. Operating Mode 2: The channel between the BMC and BIOS ROM is connected. The SPI channel of the PCH is disconnected. Operating Mode 3: The channel between the PCH and BIOS ROM is connected. The SPI channel of the BMC is disconnected.

[0146] Fuse Blowing: When the operating mode changes, the main control chip controls the fuse to blow, changing the corresponding hardware circuit signal. This fuse blowing process is irreversible. If the BMC sends a control signal at this time, requesting the hardware module to reverse the operating mode, for example, from operating mode 3 to operating mode 2, from operating mode 2 to operating mode 1, or from operating mode 3 to operating mode 1, the main control chip will detect the corresponding hardware circuit signal. If it differs from the preset value, it indicates that the circuit signal has changed and the fuse has blown. The main control chip will then ignore the control signal from the BMC, preventing the operating mode from reversing.

[0147] The hardware module and PCH are in SPI mode, the hardware module and BIOS ROM are in SPI mode, and the hardware module and BMC are in SPI mode. However, an additional control signal is connected between the hardware module and BMC for BMC to control the working mode of the hardware module. The default working mode of the module opens the SPI channel between PCH and BMC, and the BIOS ROM is in an uncontrolled state: Figure 2As shown (dashed line indicates disconnected state), this working mode is called working mode 1. At this time, developers can use the BMC management network port to send any BIOS file to the BMC through the network, and the BMC chip will simulate the received file as a ROM. When the PCH is turned on, it will find this simulated ROM through the SPI bus and read and write relevant data to complete the boot. Developers can debug the BIOS in this way until the BIOS firmware is fully mature and stable. The flow chart is as follows Figure 3 .

[0148] like Figure 4 As shown in the figure, when the BIOS development stage is completed and it is time to ship to the customer, the BMC sends a control signal to the hardware module to open the SPI channel between the BMC and the BIOS ROM. At this time, the PCH is in an uncontrolled state. This working mode is called working mode 2.

[0149] like Figure 5 As shown, the BMC writes the mature BIOS firmware to the BIOS ROM via the SPI bus. The BIOS ROM used in this patent is a PROM, which is permanently stored once written and cannot be modified. After the BIOS ROM is written, the BMC sends a control signal to the hardware module to open the SPI channel between the PCH and the BIOS ROM. At this time, the BMC's SPI channel is disconnected. This operating mode is called operating mode 3.

[0150] The software module will create four new processes under the BMC system to monitor the four pins connected to the PCH. When the relevant process detects that the pin receives a signal from the PCH, it will parse the signal according to the SPI communication protocol, and then use the SPI signal interface simulated by the BMC to operate the four pins according to the SPI communication protocol to communicate with the PCH. The software module will also re-allocate an area on the BMC's own storage device (such as the storage card that stores the BMC log, BMC memory, etc.) to store the BIOS firmware uploaded by R&D personnel through the BMC dedicated network. When entering the BIOS debugging state, the area will be divided. When exiting the BIOS debugging state, the area will be released. When entering the BIOS debugging state again, the area will be divided according to the available space queried at this time. When exiting the BIOS debugging state, the area will be released, and so on. The process is as follows Figure 6 As shown in the figure, the dotted box represents the 4 signal lines of the SPI channel. The software module workflow is as follows Figure 7 shown.

[0151] like Figure 8As shown in the figure, R&D personnel upload the BIOS firmware to the BMC through the BMC management network port. Only after the BMC has received the complete BIOS firmware through the management network port will the software module begin writing the BIOS firmware information to the storage device. After the BMC has received the complete BIOS firmware through the management network port and successfully stored it, the software module will mark the area as available for subsequent software processes to operate on the area. If a problem occurs during the transmission, such as a network disconnection or user cancellation, resulting in the failure to receive the complete BIOS firmware, the software module will not operate the storage device and will prompt the user to upload again. There are two actual application scenarios. The first is the first time the BIOS firmware is uploaded. There is no BIOS data in the storage area yet, and the BIOS data needs to be written. The second is a subsequent upload of BIOS firmware information. If there is already BIOS data in the storage area, the old BIOS data needs to be erased before the new BIOS data is written.

[0152] like Figure 9 As shown in the figure, after the system boots up, the PCH retrieves BIOS data from the SPI bus. At this point, the four detection pin processes established by the software module detect signal changes. These processes parse the PCH request according to the SPI communication protocol and, based on the request, call system interfaces to access the allocated storage area, performing read and write operations. The data to be returned to the PCH is then processed using the SPI communication protocol and then returned to the PCH using the SPI signal interface simulated by the BMC, enabling normal communication between the BMC-emulated SPI controller and the PCH.

[0153] In the present invention, in order to prevent the storage area from being operated at the same time, for example, during the boot process, the PCH needs to read and write, and the R&D personnel upload the new BIOS firmware at this time, and the BMC needs to read and write this situation. For another example, when the server is in the shutdown state, the R&D personnel upload the BIOS firmware, and the BMC is reading and writing the storage area, the server is turned on by an unknowing person, causing the PCH to also read and write the storage area. These situations will cause conflicts and cause unpredictable problems. Therefore, the software module must also design some restrictions. When the system is turned on, the user is not allowed to update the BIOS firmware through the BMC dedicated network. When the user updates the BIOS firmware, communication between the PCH and the BMC is not allowed. This ensures that the storage area can only be accessed by one process at the same time. As follows Figure 10-11 As shown, the dotted box is the newly added design for this purpose.

[0154] Under this design, the BIOS firmware cannot be updated through the BMC dedicated network when the server is powered on. When the R&D personnel update the BIOS firmware through the BMC in the powered-off state, even if the server is powered on manually, the PCH cannot affect the BMC operation of the storage area. After the BMC operation is completed and the server is restarted, the PCH can normally obtain the BIOS data from the BMC to complete the boot process. Figure 12 As shown in the figure, when the developer completes debugging and issues a command to the BMC to exit the BIOS debugging state, the software module will sequentially shut down the four processes that detect SPI signals, close the simulated SPI controller, and disable the interfaces for implementing related signals. This releases the corresponding system resources, then erases the contents and markers in the area designated for storing the BIOS firmware on the storage device, releasing the storage resources. This completes the resource release process. When the developer issues another command to have the BMC enter the BIOS debugging state, the relevant processes are restarted and the corresponding resources are re-applied to complete the BIOS debugging process.

[0155] like Figure 13 As shown in the figure, when the R&D process is completed and the product is about to be shipped to the customer, the mature BIOS firmware needs to be written into the PROM. The BMC first sends a control signal to the hardware module designed in this patent, causing the hardware module to change its operating mode to open the SPI channel between the BMC and the BIOS ROM (operating mode 2). The simulated SPI controller inside the BMC is turned on, and the mature BIOS firmware uploaded by the R&D personnel is written into the BIOS ROM through the SPI communication protocol.

[0156] After completing this step, a control signal is sent to the hardware module again, changing its operating mode to open the SPI channel between the PCH and the BIOS ROM (operating mode 3). From then on, each server startup will use the data in the BIOS ROM. However, the BIOS ROM uses a PROM design, and the data is fixed and can only be read but not modified, meeting customer stability requirements.

[0157] For security reasons, the machine in the hands of the customer should not still have the developer's debugging method, that is, the shipped machine can no longer debug the BIOS through the BMC debugging mode by switching the working mode of the hardware module. Therefore, the switching working mode inside the hardware module is designed to be irreversible by this patent. The hardware module uses a fuse blowing mechanism to respond to the control signal of the BMC, that is, when switching from working mode 1 to working mode 2, and when switching from working mode 2 to working mode 3, the corresponding fuse inside the hardware module will blow, and it will no longer be possible to switch to the previous working mode. The flow chart is as follows Figure 14As shown in the figure, the dotted box is a newly added design. This way, the hardware module in the machine in the customer's hand is in operating mode 3 and cannot be switched to other modes. The server can only read BIOS data from the PROM and cannot modify it, greatly improving the stability and security of the server.

[0158] One embodiment of the present invention provides a terminal device. The terminal device of this embodiment includes: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of each of the aforementioned method embodiments are implemented. Alternatively, when the processor executes the computer program, the functions of each module / unit in each of the aforementioned device embodiments are implemented.

[0159] The computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to accomplish the present invention.

[0160] The device / terminal equipment may be a computing device such as a desktop computer, a notebook computer, a palmtop computer, a cloud server, etc. The device / terminal equipment may include, but is not limited to, a processor and a memory.

[0161] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0162] The memory may be used to store the computer programs and / or modules, and the processor implements various functions of the apparatus / terminal device by running or executing the computer programs and / or modules stored in the memory and calling the data stored in the memory.

[0163] If the module / unit integrated into the device / terminal equipment is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention can implement all or part of the process steps in the above-mentioned method embodiments by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal, and software distribution medium. It should be noted that the content of the computer-readable medium can be appropriately increased or decreased based on the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media does not include electric carrier signals and telecommunication signals.

[0164] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for fixing BIOS data, characterized in that: include: Enter BIOS debugging state: Simulate the SPI controller, call the BMC system interface, apply for processor, memory, and IO interface resources, simulate the SPI controller and bind functions, and provide SPI signals in the form of function interfaces; Monitor and respond to PCH signals, establish a process to monitor the IO pin signal fluctuations connecting the BMC and PCH, parse the signal according to the SPI communication protocol for use by other components, or encode information according to the SPI communication protocol and send it to the PCH according to the command of other components; Divide independent storage areas, open independent storage areas under the BMC system, query available storage space, select space and record the address segment, and hide the space segment through the system interface; Obtain the BIOS firmware and receive the BIOS firmware uploaded through the BMC management network port. After checking that it is complete, write the BIOS data. If there is no BIOS data in the storage area, write it directly. If there is BIOS data, erase the old data first and then write the new data. Processes SPI channel communication between BMC and PCH. After booting, it obtains PCH requirements through the monitoring and response module, operates the storage area according to the address segment, and returns information to PCH. Exit the BIOS debugging state, close the above-mentioned components, and release the corresponding system resources; BIOS debugging and fixing process: During the BIOS development phase, the hardware module is in working mode 1. That is, after the main control chip receives the control signal, it controls the switch to connect the SPI channel between the PCH and BMC and disconnect the SPI channel of the BIOS ROM. The BIOS firmware is uploaded through the BMC management network port. The BMC receives the complete data and writes it to the storage device. When the system is powered on, the PCH obtains data from the BMC-emulated ROM through the SPI bus and uses this data to debug the BIOS. During the BIOS writing phase, after the development phase is completed, the BMC sends a control signal to the hardware module, switching to operating mode 2. Upon receiving the control signal, the main control chip controls the switch to connect the channel between the BMC and the BIOS ROM and disconnect the SPI channel of the PCH. That is, the BMC writes the mature BIOS firmware to the BIOS ROM using the SPI communication protocol. The BIOS ROM adopts a PROM design. During the BIOS fixation phase, after writing is complete, the BMC sends a control signal again to switch to operating mode 3. That is, after receiving the control signal, the main control chip controls the switch to connect the channel between the PCH and the BIOS ROM and disconnect the BMC's SPI channel. When the server is powered on, the PCH obtains information from the BIOS ROM. Due to the characteristics of the PROM, the BIOS firmware cannot be modified.

2. The method for fixing BIOS data according to claim 1, wherein: The monitoring and response to PCH signals, establishing a process to monitor the IO pin signal fluctuations connecting the BMC and PCH, parsing the signals according to the SPI communication protocol for use by other components, or encoding information according to the SPI communication protocol and sending it to the PCH according to commands from other components; dividing independent storage areas, opening independent storage areas under the BMC system, querying available storage space, selecting space and recording address segments, and hiding the segment space through the system interface; specifically: Signal monitoring: Four processes are pre-established in the BMC system to detect signal changes on specific IO pins connected to the PCH, and corresponding system resources are allocated to them. When the system is powered on and the PCH obtains BIOS data from the SPI bus, the four pin detection processes monitor the signal changes on the corresponding IO pins in real time. Request analysis: When the detection process detects a signal change, it is determined that the PCH has sent a request and the detected signal is analyzed according to the SPI communication protocol; Storage area operation: Based on the parsed request content, call the BMC system interface to operate the storage area pre-allocated for storing BIOS firmware; If it is a request to read BIOS data, the corresponding BIOS data is read from the storage area according to the data address information in the request; if it is a request to write BIOS data, the BIOS data to be written is written to the corresponding position of the storage area according to the data address information in the request; Data return: The content to be returned to the PCH is encoded according to the SPI communication protocol to form a data format that complies with the SPI communication specification. The encoded data is returned to the PCH in the form of an SPI signal through the IO pins monitored by the four detection processes using the SPI signal interface simulated by the BMC. This enables normal communication between the BMC simulated SPI controller and the PCH, ensuring that the PCH can correctly obtain or write BIOS data.

3. The method for fixing BIOS data according to claim 1, wherein: The BIOS firmware is obtained by receiving the BIOS firmware uploaded through the BMC management network port. After the detection is complete, if there is no BIOS data in the storage area, it is directly written. If there is BIOS data, the old data is erased first and then the new data is written. Specifically: Complete reception judgment: The BIOS firmware is uploaded to the BMC through the BMC management network port. The BMC monitors the BIOS firmware reception status through the management network port in real time. When the BMC has completely received the BIOS firmware, it starts the subsequent operation of writing the BIOS firmware information to the storage device. Storage area status mark: When the BMC receives the BIOS firmware completely and successfully stores it in the storage device, it marks the storage area storing the BIOS firmware as available. Write processing in different scenarios: During the first upload, when the software module detects that the storage area is uploading the BIOS firmware for the first time, that is, the storage area has not yet stored BIOS data, it directly writes the received complete BIOS firmware data into the storage area; during subsequent uploads, when the software module detects that the storage area already has BIOS data, that is, when the BIOS firmware information is subsequently uploaded, it first erases the old BIOS data in the storage area, and then writes the received complete new BIOS firmware data into the storage area.

4. The method for fixing BIOS data according to claim 1, wherein: When writing BIOS data, it is also necessary to prevent concurrent access conflicts in the BIOS firmware storage area in the BMC system, specifically by the following steps: System status monitoring: Real-time monitoring of the computer system's operating status, including at least the power-on and power-off states. It also monitors whether a user initiates a BIOS firmware update operation through the BMC dedicated network, and whether there is a need for SPI-based communication between the PCH and the BMC. BIOS firmware update restriction in the powered-on state: When the computer system is detected to be powered on, BIOS firmware update requests initiated by users through the BMC dedicated network are intercepted and the BMC is prohibited from performing operations related to the BIOS firmware update request. PCH and BMC communication restrictions during BIOS firmware updates: When detecting that a user is updating the BIOS firmware through the BMC dedicated network, a communication disable command is sent to the SPI communication module between the PCH and BMC, preventing SPI bus-based communication between the PCH and BMC. BIOS firmware update in shutdown state is isolated from PCH access: When the computer system is detected to be in shutdown state and the R&D personnel initiate a BIOS firmware update operation through the BMC dedicated network, the BMC starts the update process and performs read and write operations on the storage area to complete the BIOS firmware update; If the system is manually powered on during the update process, the internal logic control mechanism ensures that the PCH cannot access or interfere with the storage area being operated by the BMC; After the BMC completes the BIOS firmware update operation, it controls the computer system to restart so that the PCH can normally obtain the BIOS data from the updated storage area to complete the boot process; State synchronization and recovery: When the system switches from the power-on state to the power-off state, the system status flag is updated and the user is allowed to initiate a BIOS firmware update operation through the BMC dedicated network. When the BIOS firmware update operation is completed, the status flag is updated, the SPI communication restriction between the PCH and BMC is lifted, and the system resumes normal PCH and BMC communication functions. After the BIOS firmware update operation is completed, the status flag is updated to allow the PCH and BMC to perform normal SPI communication when the system is powered on. At the same time, the user is prohibited from initiating the BIOS firmware update operation again when the system is powered on, ensuring that the storage area is accessed by only one process at a time.

5. The method for fixing BIOS data according to claim 1, wherein: When exiting the BIOS debugging state, shutting down the above-mentioned enabled components, and releasing the corresponding system resources, specifically: Resource release when exiting the BIOS debugging state: When debugging is completed and the BMC is instructed to exit the BIOS debugging state through a command, the exit command is received; The following resource release procedures are performed in sequence: four processes used to detect SPI signals are closed, thereby releasing the system resources occupied by the four processes; the simulated SPI controller and the implementation interface of related signals are closed, thereby releasing the system resources related to the simulated SPI controller; on the storage device, all contents in the area allocated for storing BIOS firmware are erased and all marking information related to the area is cleared; the storage resources occupied by the storage area are released, thereby restoring the storage area to an unallocated state; Resource restart when re-entering the BIOS debugging state: When a command is sent again to instruct the BMC to enter the BIOS debugging state, the entry command is received; Restart the four SPI signal detection processes that were closed when exiting the BIOS debugging state, and reapply for corresponding system resources for the processes; re-simulate the SPI controller and enable the implementation interface of the relevant signals, and reapply for system resources related to the simulated SPI controller; reapply and divide the area for storing the BIOS firmware on the storage device, complete the reconfiguration of resources required for the BIOS debugging process, and continue to execute the BIOS debugging operation.

6. The method for fixing BIOS data according to claim 1, wherein: The method further comprises the following steps: Determine and prepare for the end of the R&D process: Continuously monitor the R&D process status. When the R&D process is determined to be complete and the computer system is shipped, enter the BIOS firmware solidification preparation phase. Confirm that the uploaded mature BIOS firmware data is complete and valid. Working mode switching and activating the simulated SPI controller: A first control signal is sent to the hardware module, indicating a change in the hardware module's working mode. The first control signal opens the SPI channel between the BMC and the BIOS ROM, while simultaneously closing the SPI channel between the PCH and the BMC. After the working mode switch is completed, the simulated SPI controller within the BMC is activated and its parameters are initialized. The mature BIOS firmware data stored in a designated storage area within the BMC system is written to the BIOS ROM via the simulated SPI controller according to the SPI communication protocol. Secondary working mode switching: After confirming that the BIOS firmware data has been successfully written into the BIOS ROM, a second control signal is sent to the hardware module. The second control signal is used to instruct the hardware module to change its working mode, that is, to open the SPI channel between the PCH and the BIOS ROM, and at the same time close the SPI channel between the BMC and the BIOS ROM. Operation mode guarantee: When the computer system is powered on, the PCH reads the BIOS data from the BIOS ROM designed with the PROM through the SPI channel between the PCH and the BIOS ROM that has been opened.

7. The method for fixing BIOS data according to claim 6, wherein: After receiving the first control signal, the hardware module triggers the internal fuse blowing mechanism to blow the fuse associated with working mode 1, and simultaneously establishes an SPI channel between the BMC and the BIOS ROM, so that the simulated SPI controller inside the BMC can communicate with the BIOS ROM through the SPI channel, and closes the SPI channel between the PCH and the BMC, so that the PCH can no longer communicate with the BMC through the hardware module. After receiving the second control signal, the hardware module again triggers the internal fuse blowing mechanism to blow the fuse associated with working mode 2, and simultaneously opens the SPI channel between the PCH and the BIOS ROM, and closes the SPI channel between the BMC and the BIOS ROM, ensuring that SPI communication between the PCH and the BIOS ROM is normally established, and the BMC can no longer communicate with the BIOS ROM through the hardware module.

8. A system for fixing BIOS data, characterized in that: include: BIOS debugging state startup and resource management components: The simulated SPI controller module is used to simulate an SPI controller and dynamically apply for processor, memory, and IO interface resources by calling the BMC system interface. After completing the resource application, the simulated SPI controller is bound to the relevant functions and the SPI signal interaction function is provided to other system components in the form of a function interface, so that other components can exchange data with the simulated SPI controller through this function interface. The PCH signal monitoring and parsing module establishes an independent process to monitor the signal fluctuations of the IO pins connecting the BMC and PCH. This process parses the monitored signals according to the SPI communication protocol and provides the parsed data to other system components. At the same time, according to the commands of other components, the information sent to the PCH is encoded according to the SPI communication protocol and sent to the PCH through the IO pins. The independent storage area management module opens an independent storage area under the BMC system, selects the appropriate storage space and records its address segment by querying the system's available storage space information; and uses the BMC system interface to hide the storage area. The BIOS firmware acquisition and write module receives the uploaded BIOS firmware through the BMC management network port and performs integrity checks on the BIOS firmware after receiving it. If the integrity check passes and no BIOS data is detected in the independent storage area, the received BIOS firmware is directly written to the storage area. If BIOS data already exists in the storage area, the old data will be erased first, and then the newly received BIOS firmware will be written; The SPI channel communication processing module between the BMC and the PCH obtains the PCH's BIOS data requirements through the PCH signal monitoring and parsing module after the computer system is powered on. Based on the PCH's requirements, it reads the corresponding BIOS data from the storage area according to the address segment recorded by the independent storage area management module and returns the read data to the PCH to support the PCH in performing BIOS debugging operations. BIOS debugging state exit and resource release components: When the BIOS debugging work is completed and an instruction to exit the BIOS debugging state is issued, all enabled components in the above-mentioned analog SPI controller module, PCH signal monitoring and analysis module, independent storage area management module, and BIOS firmware acquisition and writing module are shut down; at the same time, the processor, memory, and IO interface system resources occupied during the operation are released; Hardware switching module and working mode control components: Hardware switching module: The hardware switching module includes a main control chip and a switch. The main control chip can receive control signals sent by the BMC and control the connection state of the switch according to the control signals to connect or disconnect the SPI channels between different components. Working Mode 1: During the BIOS development phase, the hardware module is in Working Mode 1. After the main control chip receives the corresponding control signal from the BMC, it controls the switch to connect the SPI channel between the PCH and BMC, while disconnecting the SPI channel of the BIOS ROM. Working Mode 2: When the BIOS development phase is complete, the BMC sends a control signal to the hardware module to switch it to working mode 2. After receiving the control signal, the main control chip controls the switch to connect the SPI channel between the BMC and the BIOS ROM, while disconnecting the SPI channel of the PCH. Working mode 3: After the BIOS firmware is successfully written to the BIOS ROM, the BMC sends a control signal again to switch the hardware module to working mode 3; After receiving the control signal, the main control chip controls the switch to connect the SPI channel between the PCH and the BIOS ROM, and disconnect the SPI channel of the BMC.

9. A device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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