Efficient interconnection data transmission technology and interface of XPU chip based on VOC (V2V RDMA BAND Over Chip)

Abstract

The embodiment of the invention provides an efficient interconnection data transmission technology and interface of an XPU chip based on a VOC (V2V RDMA BAND Over Chip), the chip structure can comprise a VOC module, the VOC module can comprise a first interface and a second interface, and the chips are connected through the first interface and the second interface; data can be transmitted to a VOC module of a target chip through a first interface according to a first protocol, or data can be transmitted to the VOC module of the target chip through a second interface according to a VRB protocol; data are transmitted through the first protocol or the VRB protocol, efficient and high-speed data transmission between chips can be achieved, the overall data processing capacity and operation efficiency are improved, and the application requirements of large data volume and high real-time performance are met.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a VOC-based XPU chip structure, system, VRB network interconnection data transmission method, device and medium. Background Art

[0002] With the development of science and technology, in scenarios such as large-scale data centers and high-performance computing clusters, a technology that can achieve efficient and high-speed data transmission between chips is needed. In the existing technology, chips generally transmit data through the PCIe (Peripheral Component Interconnect Express) bus. When faced with large amounts of data transmission, congestion will occur, affecting the data transmission rate. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a VOC-based XPU chip structure, system, VRB network interconnection data transmission method, device and medium that overcome the above problems or at least partially solve the above problems.

[0004] In order to solve the above problems, an embodiment of the present invention discloses a VOC-based XPU chip structure, wherein the chip structure includes a VOC module, and the VOC module includes a first interface and a second interface; the chips are connected via the first interface and the second interface;

[0005] The VOC module is configured to transmit data to the VOC module of the target chip through the first interface in accordance with the first protocol, or to transmit the data to the VOC module of the target chip through the second interface in accordance with the VRB protocol.

[0006] Optionally, the VOC module is used to determine whether the current chip and the target chip are in the same cluster; when the current chip and the target chip are in the same cluster, the data is transmitted to the VOC module of the target chip through the first interface in accordance with the first protocol, or the data is transmitted to the VOC module of the target chip through the second interface in accordance with the VRB protocol; when the current chip and the target chip are not in the same cluster, the data is transmitted to the VOC module of the target chip through the second interface in accordance with the VRB protocol.

[0007] Optionally, the second interface is connected to a second data processor chip via a first data processor chip, and the second data processor chip is connected to the second interface of the target chip;

[0008] The VOC module is configured to, when the current chip and the target chip are not in the same cluster, transmit the data to the first data processor chip through the second interface of the current chip; transmit the data to the second data processor chip through the first data processor chip in accordance with the VRB protocol; and transmit the data to the second interface of the target chip through the second data processor chip.

[0009] Optionally, the data includes a MAC address of a target chip;

[0010] The VOC module is used to determine whether the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip; if the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip, it is determined that the current chip and the target chip are in the same cluster.

[0011] The present invention also discloses a VOC-based XPU chip system, wherein the chip system includes multiple chips, each chip includes a VOC module, and the multiple chips are connected through the VOC module, and the VOC module includes a first interface and a second interface;

[0012] The chip is configured to transmit data to the VOC module of the target chip through the first interface in accordance with the first protocol, or to transmit the data to the VOC module of the target chip through the second interface in accordance with the VRB protocol.

[0013] Optionally, the chip is used to determine whether the current chip and the target chip are in the same cluster; when the current chip and the target chip are in the same cluster, the data is transmitted to the VOC module of the target chip through the first interface in accordance with the first protocol, or, through the second interface, the data is transmitted to the VOC module of the target chip in accordance with the VRB protocol; when the current chip and the target chip are not in the same cluster, the data is transmitted to the VOC module of the target chip through the second interface in accordance with the VRB protocol.

[0014] Optionally, the second interface of the chip is connected to a second data processor chip via a first data processor chip, and the second data processor chip is connected to the second interface of the target chip;

[0015] The chip is configured to, when the current chip and the target chip are not in the same cluster, transmit the data to the first data processor chip through the second interface of the current chip; transmit the data to the second data processor chip according to the VRB protocol through the first data processor chip; and transmit the data to the second interface of the target chip through the second data processor chip.

[0016] Optionally, the data includes a MAC address of a target chip;

[0017] The chip is used to determine whether the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip; if the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip, it is determined that the current chip and the target chip are in the same cluster.

[0018] The present invention also discloses a method for interconnecting and transmitting data in a VRB network. The VRB network includes multiple chips, each chip includes a VOC module, and the VOC module includes a first interface and a second interface. The chips are connected via the first interface and the second interface.

[0019] The method comprises:

[0020] The data is transmitted to the target chip through the first interface in accordance with the first protocol, or the data is transmitted to the target chip through the second interface in accordance with the VRB protocol.

[0021] Optionally, transmitting the data to the target chip through the first interface in accordance with the first protocol, or transmitting the data to the target chip through the second interface in accordance with the VRB protocol, includes:

[0022] Determine whether the current chip and the target chip are in the same cluster;

[0023] When the current chip and the target chip are in the same cluster, transmitting the data to the target chip through the first interface in accordance with the first protocol, or transmitting the data to the target chip through the second interface in accordance with the VRB protocol;

[0024] In a case where the current chip and the target chip are not in the same cluster, the data is transmitted to the target chip through the second interface according to the VRB protocol.

[0025] Optionally, the second interface of the current chip is connected to a second data processor chip through a first data processor chip, and the second data processor chip is connected to the second interface of the target chip;

[0026] When the current chip and the target chip are not in the same cluster, transmitting the data to the target chip through the second interface according to the VRB protocol includes:

[0027] When the current chip and the target chip are not in the same cluster, transmitting the data to the first data processor chip through the second interface of the current chip;

[0028] transmitting the data to the second data processor chip through the first data processor chip according to the VRB protocol;

[0029] The data is transmitted to the second interface of the target chip through the second data processor chip.

[0030] Optionally, the data includes a MAC address of a target chip; and determining whether the current chip and the target chip are in the same cluster includes:

[0031] Determine whether the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip;

[0032] If the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip, it is determined that the current chip and the target chip are in the same cluster.

[0033] The present invention also discloses an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the above-mentioned VRB network interconnection data transmission method are implemented.

[0034] The present invention also discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned VRB network interconnection data transmission method are implemented.

[0035] The embodiments of the present invention include the following advantages:

[0036] The present invention discloses a VOC-based XPU chip structure, system, VRB network interconnection data transmission method, device and medium. The present invention can equip each chip with two independent interfaces to support different transmission protocols respectively. When data needs to be transmitted, the data can be transmitted to the target chip through the first interface and in accordance with the first protocol, or through the second interface and in accordance with the VRB protocol. It can realize the selection of a suitable interface and transmission protocol for transmission according to the data type or real-time requirements, avoid data link congestion, and improve the data transmission rate. The present invention transmits data through the first protocol or the VRB protocol, can realize efficient and high-speed data transmission between chips, improve the overall data processing capability and operating efficiency, and can meet the application requirements of large data volume and high real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a structural block diagram of a VOC-based XPU chip structure provided by an embodiment of the present invention;

[0038] Figure 2 This is a structural block diagram of another VOC-based XPU chip structure provided by an embodiment of the present invention;

[0039] Figure 3 This is a structural block diagram of a VOC-based XPU chip system provided by an embodiment of the present invention;

[0040] Figure 4 This is a flowchart of a method for data transmission over a VRB network interconnection provided by an embodiment of the present invention;

[0041] Figure 5 This is a structural block diagram of an inter-chip architecture provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] One of the core concepts of the embodiments of the present invention is that the present invention can equip each chip with two independent interfaces to support different transmission protocols. When data needs to be transmitted, the data can be transmitted to the target chip through the first interface and in accordance with the first protocol, or through the second interface and in accordance with the VRB protocol. The optimal protocol can be selected for transmission based on the data type or real-time requirements, thereby avoiding congestion in the data link and improving the data transmission rate. The present invention transmits data through the first protocol or the VRB protocol, which can achieve efficient and high-speed data transmission between chips, improve the overall data processing capability and operating efficiency, and meet the application requirements of large data volume and high real-time performance.

[0044] Reference Figure 1 , shows a structural block diagram of a VOC-based XPU chip structure 10 provided in an embodiment of the present invention. The chip structure may include a VOC module 101. The VOC module 101 may include a first interface 1011 and a second interface 1012. Chips may be connected through the first interface 1011 and the second interface 1012.

[0045] The VOC module 101 is configured to transmit data to the VOC module of the target chip via the first interface in accordance with the first protocol, or transmit data to the VOC module of the target chip via the second interface in accordance with the VRB protocol.

[0046] In the embodiment of the present invention, the VOC module 101 refers to the abbreviation of V2V RDMA BAND Over Chip, where V2V refers to the Visual Internet of Things protocol, which is a network protocol for video communication; RDMA stands for Remote Direct Memory Access, which allows a computer to directly access the memory of other computers without the intervention of the operating system; BAND stands for bandwidth, and as a whole refers to an on-chip remote direct memory access bandwidth interface module based on the Visual Internet of Things protocol.

[0047] XPU chip: represents various types of processor chips, such as GPU (graphics processing unit), TPU (tensor processing unit), etc.

[0048] The first protocol refers to the transmission data between chips, which may include PCIE protocol, I2C protocol, SPI protocol, UART, and UVLink protocol. The specific one used is not limited here. In the present invention, the UVlink protocol is selected as the protocol used for the first interface between chips for explanation.

[0049] The UVlink protocol is a high-speed interconnect technology bus protocol optimized for high-performance computing and heterogeneous chip design. It can achieve high-bandwidth, low-latency communication among multiple processing units within or between chips, such as CPUs, GPUs, AI accelerators, memory controllers, etc.

[0050] In the VRB (V2V RDMA BAND, Remote Direct Memory Access Bandwidth based on the Visual Internet Protocol) protocol, V2V refers to the Visual Internet Protocol, a network protocol used for video communication; RDMA stands for Remote Direct Memory Access, which allows computers to directly access the memory of other computers without operating system intervention; BAND stands for bandwidth, and overall refers to the on-chip remote direct memory access bandwidth technology based on the Visual Internet Protocol.

[0051] VRB is an RDMA technology based on the "V2V" visual networking protocol architecture and can run on a standard Ethernet infrastructure. VRB can be composed of the VRB application layer, RDMA API layer, RDMA Software Stack layer, "V2V" visual networking protocol layer, Ethernet link layer and physical layer. The "V2V" visual networking protocol is an autonomous and controllable security protocol that uses a management-first, communication-later approach to ensure communication security while providing high-speed and reliable network communication.

[0052] When the chip is a GPU chip, VRB technology can provide lower latency when communicating between GPU chips. It is based on the RDMA mechanism and bypasses the data processing link of the operating system kernel. When data is frequently exchanged between GPU chips, the data can be directly and quickly transmitted between GPU memories, reducing the delay caused by kernel intervention, enabling data to be shared between chips more promptly, thereby improving computing efficiency. VRB can effectively utilize network bandwidth and transmit data through Ethernet. It uses optimized protocols to reduce protocol overhead, so that more bandwidth can be used for actual data transmission. For large amounts of data interaction between GPU chips, high bandwidth utilization can ensure that data flows quickly between chips, avoiding data transmission bottlenecks caused by insufficient bandwidth.

[0053] The first interface 1011 is a physical interface on the chip specifically designed for data transmission according to the first protocol, and the second interface 1012 is another physical interface specifically designed for data transmission according to the VRB protocol.

[0054] In one example, when chip 1 needs to transmit data to chip 2, the VOC module 101 can select the first interface 1011 and the corresponding protocol to transmit the data to the target chip according to the type of data or the type of chip, or select the second interface 1012 and the corresponding protocol to transmit the data to the VOC module of the target chip.

[0055] The present invention discloses a VOC-based XPU chip structure. By equipping each chip with two independent interfaces, each supporting different transmission protocols, when data needs to be transmitted, the data can be transmitted to the target chip through the first interface and in accordance with the first protocol, or through the second interface and in accordance with the VRB protocol. This enables selection of the optimal protocol for transmission based on the data type or real-time requirements, avoids data link congestion, and improves the data transmission rate. The present invention transmits data through the first protocol or the VRB protocol, thereby achieving efficient and high-speed data transmission between chips, improving overall data processing capabilities and operating efficiency, and meeting the application requirements of large data volumes and high real-time performance.

[0056] In one embodiment of the present invention, the VOC module is used to determine whether the current chip and the target chip are in the same cluster; when the current chip and the target chip are in the same cluster, the data is transmitted to the VOC module of the target chip through the first interface in accordance with the first protocol, or, the data is transmitted to the VOC module of the target chip through the second interface in accordance with the VRB protocol; when the current chip and the target chip are not in the same cluster, the data is transmitted to the VOC module of the target chip through the second interface in accordance with the VRB protocol.

[0057] In the embodiment of the present invention, before the current chip performs data transmission, the VOC module of the current chip needs to determine whether the current chip and the target chip are in the same cluster. The determination method may vary depending on different system architectures and designs, and may include the following methods:

[0058] Chip ID identification: Each chip has a unique ID. By comparing the IDs of the current chip and the target chip and combining them with pre-defined cluster ID rules, we can determine whether they belong to the same cluster. For example, if the first few digits of the chip ID represent the cluster number, we can determine whether these digits are the same.

[0059] Network topology information: Use the network topology structure to determine whether the current chip and the target chip are in the same cluster.

[0060] Configuration information query: Query the system's configuration file or database, which records the cluster information of each chip. By comparing this information, you can determine whether two chips are in the same cluster.

[0061] In one example, when data needs to be transmitted, the data to be transmitted will be encapsulated. First, the data is divided into data frames of appropriate size according to certain rules. Each data frame contains a data payload and necessary protocol header information. The protocol header may contain the source chip address, target chip address, data frame sequence number, CRC check code, etc., which are used to ensure the correct transmission and reception of data. When the current chip receives the data, it can determine whether the current chip and the target chip are in the same cluster based on the information in the data frame package.

[0062] When it is determined that the current chip and the target chip are in the same cluster, there are two transmission methods to choose from: the first method: data can be transmitted to the VOC module of the target chip through the first interface in accordance with the first protocol; the second method: data can be transmitted to the VOC module of the target chip through the second interface in accordance with the VRB protocol; two protocols can be selected for transmission within the same cluster, probably to adapt to different data transmission requirements. For example, for data with higher real-time requirements, the first protocol can be selected; and for data with higher data accuracy requirements, the VRB protocol can be selected.

[0063] When it is determined that the current chip and the target chip are not in the same cluster, the data can be transmitted to the VOC module of the target chip through the second interface according to the VRB protocol. This is because the VRB protocol has better adaptability and reliability in cross-cluster data transmission. VRB allows chips to communicate remotely between different server nodes. In distributed computing environments, such as cluster computing or cloud computing scenarios, GPUs on different servers may need to work together. VRB can cross server boundaries and realize direct communication between GPU chips, so that data can be efficiently transmitted between remote GPUs. By determining whether the chips are in the same cluster to select the transmission method, the system can adapt to different cluster architectures. Whether it is a simple single-cluster system or a complex multi-cluster system, the transmission strategy can be flexibly adjusted according to actual conditions to improve the scalability of the system.

[0064] In one embodiment of the present invention, the second interface is connected to a second data processor chip via a first data processor chip, and the second data processor chip is connected to the second interface of the target chip;

[0065] The VOC module is configured to, when the current chip and the target chip are not in the same cluster, transmit the data to the first data processor chip through the second interface of the current chip; transmit the data to the second data processor chip through the first data processor chip in accordance with the VRB protocol; and transmit the data to the second interface of the target chip through the second data processor chip.

[0066] In the embodiment of the present invention, Figure 2, shows another XPU chip structure block diagram based on VOC provided by an embodiment of the present invention, the chip structure XPU1 refers to the current chip, which can include a NOC1 (Network on Chip) module and a VOC1 module. The NOC1 module can be responsible for path selection and forwarding of data packets, and is usually distributed in different positions of the chip. It can be used as a physical channel to connect to the router, which can be unidirectional or bidirectional and support high-bandwidth transmission. It can connect functional modules (such as CPU, GPU, memory controller, etc.) to the NOC1 module to complete protocol conversion (such as AXI to NOC data packet encapsulation). The VOC module can include a first interface U2U1 interface and a second interface C2V2 interface; the NOC1 module can be connected to the U2U1 interface in the VOC1 module through the UVLink bus, and the NOC1 module can be connected to the C2V1 interface in the VOC1 module through the PCIe bus. The current chip XPU1 and the target chip XPU2 are both configured with corresponding DPUs (Data Processing Unit) network card, the C2V1 interface of the current chip XPU1 is connected to the corresponding DPU1 network card through a PCIe network cable, the DPU1 network card is connected to DPU2 based on the VRB protocol communication, and DPU2 is connected to the C2V2 interface through a PCIe network cable.

[0067] When the VOC module 101 receives data transmitted through the NOC module, it can determine whether the data is in the same cluster as the current chip, and use different interfaces to transmit the data according to the determination result.

[0068] When it is determined that the current chip and the target chip are not in the same cluster, the C2V1 interface can use the VRB protocol to encapsulate and format the data, organize the data into a format suitable for transmission under the visual networking protocol, and then transmit the encapsulated data to the DPU1 network card. The DPU1 network card can use the RDMA channel in the on-chip VRB protocol to directly transmit it to the DPU2 network card of the target XPU2 chip, and then transmit it to the C2V2 interface of the target chip via the DPU2 network card of the target chip. During the transmission process, RDMA technology can be used, and the data can interact directly in the memory space between chips without the frequent intervention of the operating system.

[0069] In one embodiment of the present invention, the data includes a MAC address of a target chip;

[0070] The VOC module is used to determine whether the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip; if the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip, it is determined that the current chip and the target chip are in the same cluster.

[0071] In an embodiment of the present invention, the transmitted data includes the MAC address of the target chip. The MAC address, i.e., the media access control address, is a unique identifier of a network device (such as a chip) at the data link layer. It is globally unique. This address consists of a 48-bit binary number, usually expressed in hexadecimal, such as 00:11:22:33:44:55. In the system, the MAC address is an important basis for identifying and distinguishing different chips.

[0072] To determine whether chips are in the same cluster, you need to pre-establish a mapping between each chip's MAC address and its cluster ID. This mapping can be stored and managed in several ways:

[0073] Database storage: Store the MAC address and the corresponding cluster ID in a database table. For example, create a table containing the mac_address and cluster_id fields in a relational database. Each record represents the information of a chip.

[0074] Memory table maintenance: When the system is running, the mapping relationship is stored in the memory table for quick query.

[0075] Configuration file record: Use a configuration file (such as JSON, XML, etc.) to record this mapping relationship. The specific method used is not limited here.

[0076] When it is necessary to determine whether the current chip and the target chip are in the same cluster, the system performs the following operations: First, based on the MAC address of the current chip, the corresponding cluster identifier is searched in the stored mapping relationship. Then, based on the MAC address of the target chip, its corresponding cluster identifier is also searched in the mapping relationship. Finally, the two cluster identifiers are compared to see if they are the same.

[0077] If the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip, then it can be determined that the current chip and the target chip are in the same cluster. In this case, the system can choose to transmit data to the target chip through the first interface according to the first protocol or through the second interface according to the VRB protocol according to the data transmission requirements.

[0078] If the two cluster identifiers are different, it indicates that the current chip and the target chip are not in the same cluster. In this case, the system will choose to transmit data to the target chip through the second interface according to the VRB protocol. This is because the VRB protocol may be more suitable for cross-cluster data transmission and can better deal with network delays, signal interference and other issues.

[0079] The present invention can use the cluster identification information corresponding to the MAC address to determine whether the current chip and the target chip belong to the same cluster, thereby selecting an appropriate method for subsequent data transmission, which can better adapt to different network environments and data transmission requirements and improve the efficiency and reliability of data transmission.

[0080] In one embodiment of the present invention, the VOC module is used to determine the priority order of the multiple data when the data includes multiple data; according to the priority order, the data is transmitted to the VOC module of the target chip through the first interface in accordance with the first protocol, or the data is transmitted to the VOC module of the target chip through the second interface in accordance with the VRB protocol.

[0081] In an embodiment of the present invention, in a scenario where multiple data need to be transmitted from the current chip to the target chip, it is necessary to first clarify the priority order of these data, and then, based on the priority order, choose to complete the data transmission through the first interface using the first protocol, or through the second interface using the VRB protocol.

[0082] In order to properly arrange the order of data transmission, each data needs to be assigned a priority. There are many ways to determine the priority. The following are some common ones:

[0083] Different data has different importance in the business. For example, in a real-time monitoring system, alarm data usually has a higher priority than ordinary status data because alarm data may be related to the security and stable operation of the system and needs to be processed in a timely manner.

[0084] For financial transaction systems, transaction instruction data has a higher priority than query request data because the execution of transaction instructions directly affects the flow of funds and the completion of transactions.

[0085] Data with high timeliness requirements should have a higher priority. For example, video streaming data and audio streaming data have extremely high real-time requirements. If the transmission delay is too large, it will affect the user experience. Therefore, the priority of this type of data is usually higher than some batch data with lower timeliness requirements, such as log data.

[0086] When determining the priority, a priority value can be used to represent the priority of each data. The larger the value, the higher the priority. For example, the priority of alarm data can be set to 10, and the priority of normal status data can be set to 2.

[0087] After determining the priority order of the data, the data can be transmitted in this order. During the transmission process, the appropriate transmission method needs to be selected based on whether the current chip and the target chip are in the same cluster.

[0088] In one example, the data to be transmitted are data 1 and data 2, data 1 has a higher priority than data 2, and both data 1 and data 2 are transmitted to the VOC module of the target chip. Moreover, the target chip and the current chip are not in the same cluster. At this time, data 1 can be transmitted through the second interface first, and after data 1 is sent, data 2 can be transmitted to the VOC module of the target chip through the second interface.

[0089] The present invention can improve the operating efficiency of the entire system by giving priority to important data and reducing the transmission delay of key data. It can assign priorities according to the business needs and timeliness requirements of the data, ensure that key business data is processed in a timely manner, and guarantee the normal operation and service quality of the business.

[0090] In one embodiment of the present invention, the VOC module is used to add a check code to the data; the data with the check code added is transmitted to the VOC module of the target chip through the first interface in accordance with the first protocol, or the data with the check code added is transmitted to the VOC module of the target chip through the second interface in accordance with the VRB protocol.

[0091] In the embodiments of the present invention, the check code is a piece of additional information appended to the original data. It is calculated based on the original data using a specific algorithm. At the receiving end, the check code is recalculated for the received data using the same algorithm and compared with the received check code. If the two are consistent, it indicates that no errors occurred during the data transmission process; if they are inconsistent, it indicates that an error may have occurred in the data. Common check code algorithms include:

[0092] Cyclic Redundancy Check (CRC): This is a widely used checksum algorithm that obtains a fixed-length remainder as a checksum by performing a polynomial division on the data. CRC has strong error detection capabilities and can detect multiple types of errors, such as single-bit errors, double-bit errors, and odd-bit errors. Different application scenarios may use different CRC polynomials, such as CRC-16 and CRC-32.

[0093] Parity check: This is a simple parity check method that determines the value of the check bit by counting the number of 1s in the data. If odd parity is used, the total number of 1s in the data and check bits should be an odd number; if even parity is used, the total number of 1s in the data and check bits should be an even number. Parity check can only detect errors in an odd number of bits, and its error detection capability is relatively weak.

[0094] Checksum: Each byte of the data is added together and the two's complement of the result is used as the checksum. At the receiving end, the same summing operation is performed on the received data and compared with the received checksum. Checksum calculation is relatively simple, but the error detection capability is limited.

[0095] The specific verification code algorithm can be set according to the user's needs and is not limited here.

[0096] Furthermore, after selecting the check code algorithm, the current chip can add a check code to the data using the selected check code algorithm, and then can select the first interface or the second interface to transmit the data with the added check code to the target chip based on factors such as whether the current chip and the target chip are in the same cluster and the characteristics of the data. If they are in the same cluster, it may be possible to select between the first interface (first protocol) and the second interface (VRB protocol) based on the real-time and accuracy requirements of the data; if they are not in the same cluster, the second interface (VRB protocol) is usually selected for transmission; the present invention can detect errors that may occur during data transmission at the receiving end by adding check codes, so that error correction measures can be taken in a timely manner, such as requesting retransmission, to ensure the accuracy and integrity of the data.

[0097] In one embodiment of the present invention, the VOC module is further configured to determine data traffic; determine whether congestion occurs between chips based on the data traffic; and reduce the data transmission rate if congestion occurs between chips.

[0098] In the embodiments of the present invention, data traffic refers to the amount of data passing through the inter-chip transmission channel within a specific time period. Determining whether there is inter-chip congestion can be based on a pre-set congestion threshold. The congestion threshold is an empirical value or a value determined based on factors such as the chip's processing capability and the bandwidth of the transmission channel. The determination method is as follows:

[0099] The real-time data traffic is compared with the pre-set congestion threshold. If the data traffic exceeds the threshold, it can be considered that congestion has occurred between chips; otherwise, there is no congestion. For example, if the set congestion threshold is 10,000 bytes per second, when the real-time monitored data traffic reaches 12,000 bytes per second, congestion is determined to have occurred.

[0100] In addition to directly comparing data traffic and thresholds, you can also analyze the changing trends of data traffic. If data traffic continues to grow rapidly over a short period of time, even if the current data traffic has not yet exceeded the threshold, it may indicate that congestion is about to occur. In this case, you can take measures in advance to avoid congestion.

[0101] When inter-chip congestion is detected, the data transmission rate needs to be reduced to alleviate the congestion. There are several methods for reducing the transmission rate: Fixed-step reduction: The transmission rate is reduced in fixed steps, for example, by 10% at a time. This gradually reduces data traffic until the congestion is alleviated. Adaptive adjustment: The transmission rate is adaptively adjusted based on the severity of congestion. If congestion is severe, the transmission rate is significantly reduced; if congestion is mild, the transmission rate is slightly reduced. The extent of the reduction is determined by calculating the difference between the data traffic and the congestion threshold.

[0102] The present invention avoids data loss, retransmission and other problems caused by congestion by timely detecting and handling congestion, ensuring that data can be transmitted stably between chips. When congestion is determined to occur, the sending rate can be reduced to allow the chip more time to process the received data, avoiding chip overload due to inability to handle the data, and improving the processing efficiency of the chip.

[0103] The present invention discloses a VOC-based XPU chip structure. By equipping each chip with two independent interfaces, each supporting different transmission protocols, when data needs to be transmitted, the data can be transmitted to the target chip through the first interface and in accordance with the first protocol, or through the second interface and in accordance with the VRB protocol. This enables selection of the optimal protocol for transmission based on the data type or real-time requirements, avoids data link congestion, and improves the data transmission rate. The present invention transmits data through the first protocol or the VRB protocol, thereby achieving efficient and high-speed data transmission between chips, improving overall data processing capabilities and operating efficiency, and meeting the application requirements of large data volumes and high real-time performance.

[0104] Reference Figure 3 , shows a structural block diagram of a VOC-based XPU chip system 20 provided in an embodiment of the present invention. The system may include multiple chips, each of which may include a VOC module. The multiple chips may be connected through the VOC module, and the VOC module includes a first interface and a second interface;

[0105] The chip 201 is configured to transmit data to the VOC module of the target chip through the first interface in accordance with the first protocol, or to transmit the data to the VOC module of the target chip through the second interface in accordance with the VRB protocol.

[0106] In the embodiment of the present invention, Figure 3The XPU chip system may include a chip 201 and a chip 202. The chip 201 may include a VOC module 2011. The chip 202 may include a VOC module 2012. The VOC module 2011 may include a first interface 20111 and a second interface 20112. The VOC module 2012 may include a first interface 20121 and a second interface 20122.

[0107] When chip 201 needs to transmit data to chip 202, it can select the first interface 20111 and the corresponding protocol to transmit the data to the target chip according to the type of data or the type of chip, or select the second interface 20112 and the corresponding protocol to transmit the data to the VOC module of the target chip 202.

[0108] The present invention discloses a VOC-based XPU chip system. By equipping each chip with two independent interfaces, each supporting different transmission protocols, when data needs to be transmitted, the data can be transmitted to the target chip through the first interface and in accordance with the first protocol, or through the second interface and in accordance with the VRB protocol. This enables selection of the optimal protocol for transmission based on the data type or real-time requirements, avoids data link congestion, and improves the data transmission rate. The present invention transmits data through the first protocol or the VRB protocol, thereby achieving efficient and high-speed data transmission between chips, improving overall data processing capabilities and operating efficiency, and meeting the application requirements of large data volumes and high real-time performance.

[0109] In one embodiment of the present invention, the chip is used to determine whether the current chip and the target chip are in the same cluster; when the current chip and the target chip are in the same cluster, the data is transmitted to the VOC module of the target chip through the first interface in accordance with the first protocol, or, the data is transmitted to the VOC module of the target chip through the second interface in accordance with the VRB protocol; when the current chip and the target chip are not in the same cluster, the data is transmitted to the VOC module of the target chip through the second interface in accordance with the VRB protocol.

[0110] In one embodiment of the present invention, the second interface of the chip is connected to a second data processor chip via a first data processor chip, and the second data processor chip is connected to the second interface of the target chip;

[0111] The chip is configured to, when the current chip and the target chip are not in the same cluster, transmit the data to the first data processor chip through the second interface of the current chip; transmit the data to the second data processor chip according to the VRB protocol through the first data processor chip; and transmit the data to the second interface of the target chip through the second data processor chip.

[0112] In one embodiment of the present invention, the data includes a MAC address of a target chip;

[0113] The chip is used to determine whether the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip; if the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip, it is determined that the current chip and the target chip are in the same cluster.

[0114] In one embodiment of the present invention, a chip is used to determine the priority order of multiple data when the data includes multiple data; according to the priority order, the data is transmitted to the VOC module of the target chip through a first interface in accordance with a first protocol, or the data is transmitted to the VOC module of the target chip through a second interface in accordance with a VRB protocol.

[0115] In one embodiment of the present invention, a chip is used to add a check code to data; the data to which the check code has been added is transmitted to the VOC module of the target chip through a first interface in accordance with a first protocol, or the data to which the check code has been added is transmitted to the VOC module of the target chip through a second interface in accordance with a VRB protocol.

[0116] In one embodiment of the present invention, the chip is further configured to determine data traffic; determine whether congestion occurs between chips based on the data traffic; and reduce the data transmission rate if congestion occurs between chips.

[0117] The present invention discloses a VOC-based XPU chip system. By equipping each chip with two independent interfaces, each supporting different transmission protocols, when data needs to be transmitted, the data can be transmitted to the target chip through the first interface and in accordance with the first protocol, or through the second interface and in accordance with the VRB protocol. This enables selection of the optimal protocol for transmission based on the data type or real-time requirements, avoids data link congestion, and improves the data transmission rate. The present invention transmits data through the first protocol or the VRB protocol, thereby achieving efficient and high-speed data transmission between chips, improving overall data processing capabilities and operating efficiency, and meeting the application requirements of large data volumes and high real-time performance.

[0118] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0119] Reference Figure 4 , shows a flowchart of a method for interconnecting and transmitting data over a VRB network provided by an embodiment of the present invention. The VRB network may include multiple chips, each chip including a VOC module. The VOC module may include a first interface and a second interface. The chips are connected via the first interface and the second interface. The method may include the following steps:

[0120] Step 101: Transmit data to a target chip via a first interface in accordance with a first protocol, or transmit data to a target chip via a second interface in accordance with a VRB protocol.

[0121] In an embodiment of the present invention, the first protocol refers to the transmission data between chips, which may include PCIE protocol, I2C protocol, SPI protocol, UART, and UVLink protocol. The specific one used is not limited here. In the present invention, the UVlink protocol is selected as the protocol used for the first interface between chips for explanation.

[0122] The UVlink protocol is a high-speed interconnect technology bus protocol optimized for high-performance computing and heterogeneous chip design. It can achieve high-bandwidth, low-latency communication among multiple processing units within or between chips, such as CPUs, GPUs, AI accelerators, memory controllers, etc.

[0123] In the VRB (V2V RDMA BAND, Remote Direct Memory Access Bandwidth based on the Visual Internet Protocol) protocol, V2V refers to the Visual Internet Protocol, a network protocol used for video communication; RDMA stands for Remote Direct Memory Access, which allows computers to directly access the memory of other computers without operating system intervention; BAND stands for bandwidth, and overall refers to the on-chip remote direct memory access bandwidth technology based on the Visual Internet Protocol.

[0124] VRB is an RDMA technology based on the "V2V" visual networking protocol architecture and can run on a standard Ethernet infrastructure. VRB can be composed of the VRB application layer, RDMA API layer, RDMA Software Stack layer, "V2V" visual networking protocol layer, Ethernet link layer and physical layer. The "V2V" visual networking protocol is an autonomous and controllable security protocol that uses a management-first, communication-later approach to ensure communication security while providing high-speed and reliable network communication.

[0125] The VRB network may be composed of multiple chips, and the multiple chips may communicate with each other through the second interface by implementing the VRB protocol.

[0126] When the chip is a GPU chip, VRB technology can provide lower latency when communicating between GPU chips. It is based on the RDMA mechanism and bypasses the data processing link of the operating system kernel. When data is frequently exchanged between GPU chips, the data can be directly and quickly transmitted between GPU memories, reducing the delay caused by kernel intervention, enabling data to be shared between chips more promptly, thereby improving computing efficiency. VRB can effectively utilize network bandwidth and transmit data through Ethernet. It uses optimized protocols to reduce protocol overhead, so that more bandwidth can be used for actual data transmission. For large amounts of data interaction between GPU chips, high bandwidth utilization can ensure that data flows quickly between chips, avoiding data transmission bottlenecks caused by insufficient bandwidth.

[0127] The first interface is a physical interface on the chip specially designed for data transmission according to the first protocol, and the second interface is another physical interface specially designed for data transmission according to the VRB protocol.

[0128] In the embodiment of the present invention, Figure 5 , showing a structural block diagram of an inter-chip architecture provided by an embodiment of the present invention, the multiple chips include chip 1 and chip 2, chip 1 includes a first interface A1 and a second interface A2, chip 2 includes a first interface A3 and a second interface A4; the first interface A1 is connected to the first interface A3, and the second interface A2 is connected to the second interface A4. When chip 1 needs to transmit data to chip 2, the first interface and the corresponding protocol can be selected according to the type of data or the type of chip to transmit the data to the target chip, or the second interface and the corresponding protocol can be selected to transmit the data to the target chip.

[0129] The present invention discloses a VRB network interconnection data transmission method. The present invention can equip each chip with two independent interfaces, each supporting different transmission protocols. When data needs to be transmitted, the data can be transmitted to the target chip through the first interface and in accordance with the first protocol, or through the second interface and in accordance with the VRB protocol. The optimal protocol can be selected for transmission according to the data type or real-time requirements, thereby avoiding data link congestion and improving the data transmission rate. The present invention can transmit data through the first protocol or the VRB protocol, thereby realizing efficient and high-speed data transmission between chips, improving the overall data processing capability and operating efficiency, and meeting the application requirements of large data volume and high real-time performance.

[0130] In one embodiment of the present invention, data is transmitted to a target chip through a first interface in accordance with a first protocol, or, through a second interface, data is transmitted to the target chip in accordance with a VRB protocol, including: determining whether the current chip and the target chip are in the same cluster; if the current chip and the target chip are in the same cluster, data is transmitted to the target chip through the first interface in accordance with the first protocol, or, if the current chip and the target chip are in the same cluster, data is transmitted to the target chip through the second interface in accordance with the VRB protocol; if the current chip and the target chip are not in the same cluster, data is transmitted to the target chip through the second interface in accordance with the VRB protocol.

[0131] In the embodiment of the present invention, before the current chip performs data transmission, the current chip needs to determine whether the current chip and the target chip are in the same cluster. The determination method may vary depending on different system architectures and designs, and may include the following methods:

[0132] Chip ID identification: Each chip has a unique ID. By comparing the IDs of the current chip and the target chip and combining them with pre-defined cluster ID rules, we can determine whether they belong to the same cluster. For example, if the first few digits of the chip ID represent the cluster number, we can determine whether these digits are the same.

[0133] Network topology information: Use the network topology structure to determine whether the current chip and the target chip are in the same cluster.

[0134] Configuration information query: Query the system's configuration file or database, which records the cluster information of each chip. By comparing this information, you can determine whether two chips are in the same cluster.

[0135] In one example, when data needs to be transmitted, the data to be transmitted will be encapsulated. First, the data is divided into data frames of appropriate size according to certain rules. Each data frame contains a data payload and necessary protocol header information. The protocol header may contain the source chip address, target chip address, data frame sequence number, CRC check code, etc., which are used to ensure the correct transmission and reception of data. When the current chip receives the data, it can determine whether the current chip and the target chip are in the same cluster based on the information in the data frame package.

[0136] When it is determined that the current chip and the target chip are in the same cluster, there are two transmission methods to choose from: the first method: data can be transmitted to the target chip through the first interface in accordance with the first protocol; the second method: data can be transmitted to the target chip through the second interface in accordance with the VRB protocol; two protocols can be selected for transmission within the same cluster, probably to adapt to different data transmission requirements. For example, for data with higher real-time requirements, the first protocol can be selected; and for data with higher data accuracy requirements, the VRB protocol can be selected.

[0137] When it is determined that the current chip and the target chip are not in the same cluster, data can be transmitted to the target chip through the second interface according to the VRB protocol. This is because the VRB protocol has better adaptability and reliability in cross-cluster data transmission. VRB allows chips to communicate remotely between different server nodes. In distributed computing environments, such as cluster computing or cloud computing scenarios, GPUs on different servers may need to work together. VRB can cross server boundaries and realize direct communication between GPU chips, so that data can be efficiently transmitted between remote GPUs. By determining whether the chips are in the same cluster to select the transmission method, the system can adapt to different cluster architectures. Whether it is a simple single-cluster system or a complex multi-cluster system, the transmission strategy can be flexibly adjusted according to actual conditions to improve the scalability of the system.

[0138] In one embodiment of the present invention, the second interface of the current chip is connected to the second data processor chip through the first data processor chip, and the second data processor chip is connected to the second interface of the target chip; when the current chip and the target chip are not in the same cluster, data is transmitted to the target chip through the second interface in accordance with the VRB protocol, including: when the current chip and the target chip are not in the same cluster, data is transmitted to the first data processor chip through the second interface of the current chip; data is transmitted to the second data processor chip through the first data processor chip in accordance with the VRB protocol; and data is transmitted to the second interface of the target chip through the second data processor chip.

[0139] In the embodiment of the present invention, Figure 2In the figure, the XPU1 chip on the left is the current chip, and the XPU2 chip on the right is the target chip. The chips may include a NOC (Network on Chip) module and a VOC module. The NOC module is responsible for path selection and forwarding of data packets and is usually distributed in different locations of the chip. It can serve as a physical channel connecting to a router and can be unidirectional or bidirectional, supporting high-bandwidth transmission. It can connect functional modules (such as CPU, GPU, memory controller, etc.) to the NOC and complete protocol conversion (such as encapsulation of AXI to NOC data packets). The VOC module refers to an interconnection interface module. The VOC module may include a first interface U2U interface and a second interface C2V interface; the NOC module may be connected to the U2U interface in the VOC module through the UVLink bus, and the NOC module may be connected to the C2V interface in the VOC module through the PCIe bus. Both the current chip and the target chip are configured with corresponding DPU (Data Processing Unit) network cards, and the C2V interface of the chip is connected to the corresponding DPU network card through the PCIe bus.

[0140] When the VOC module receives data transmitted by the NOC module, it can determine whether the data is in the same cluster as the current chip, and use different interfaces to transmit the data based on the judgment result.

[0141] When it is determined that the current chip and the target chip are not in the same cluster, the C2V interface can use the VRB protocol to encapsulate and format the data, organize the data into a format suitable for transmission under the visual networking protocol, and then transmit the encapsulated data to the DPU network card. The DPU network card can use the RDMA channel in the on-chip VRB protocol to directly transmit it to the DPU network card of the target XPU chip, and then transmit it to the C2V interface of the target chip via the DPU network card of the target chip. During the transmission process, RDMA technology can be used, and the data can interact directly in the memory space between chips without the frequent intervention of the operating system.

[0142] In one embodiment of the present invention, the data includes the MAC address of the target chip; determining whether the current chip and the target chip are in the same cluster includes: determining whether the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip; if the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip, then determining that the current chip and the target chip are in the same cluster.

[0143] In this embodiment of the present invention, the transmitted data includes the MAC address of the target chip. A MAC address, or Media Access Control address, is a globally unique identifier for a network device (such as a chip) at the data link layer. This address consists of a 48-bit binary number, typically expressed in hexadecimal, such as 00:11:22:33:44:55. Within a system, the MAC address is an important basis for identifying and distinguishing different chips.

[0144] To determine whether chips are in the same cluster, you need to pre-establish a mapping between each chip's MAC address and its cluster ID. This mapping can be stored and managed in several ways:

[0145] Database storage: Store the MAC address and the corresponding cluster ID in a database table. For example, create a table containing the mac_address and cluster_id fields in a relational database. Each record represents the information of a chip.

[0146] Memory table maintenance: When the system is running, the mapping relationship is stored in the memory table for quick query.

[0147] Configuration file record: Use a configuration file (such as JSON, XML, etc.) to record this mapping relationship. The specific method used is not limited here.

[0148] When it is necessary to determine whether the current chip and the target chip are in the same cluster, the system performs the following operations: First, based on the MAC address of the current chip, the corresponding cluster identifier is searched in the stored mapping relationship. Then, based on the MAC address of the target chip, its corresponding cluster identifier is also searched in the mapping relationship. Finally, the two cluster identifiers are compared to see if they are the same.

[0149] If the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip, then it can be determined that the current chip and the target chip are in the same cluster. In this case, the system can choose to transmit data to the target chip through the first interface according to the first protocol or through the second interface according to the VRB protocol according to the data transmission requirements.

[0150] If the two cluster identifiers are different, it indicates that the current chip and the target chip are not in the same cluster. In this case, the system will choose to transmit data to the target chip through the second interface according to the VRB protocol. This is because the VRB protocol may be more suitable for cross-cluster data transmission and can better deal with network delays, signal interference and other issues.

[0151] The present invention can use the cluster identification information corresponding to the MAC address to determine whether the current chip and the target chip belong to the same cluster, thereby selecting an appropriate method for subsequent data transmission, which can better adapt to different network environments and data transmission requirements and improve the efficiency and reliability of data transmission.

[0152] In one embodiment of the present invention, when the data includes multiple data, the data is transmitted to the target chip through the first interface in accordance with the first protocol, or the data is transmitted to the target chip through the second interface in accordance with the VRB protocol, including: determining the priority order of the multiple data; according to the priority order, the data is transmitted to the target chip through the first interface in accordance with the first protocol, or the data is transmitted to the target chip through the second interface in accordance with the VRB protocol.

[0153] In an embodiment of the present invention, in a scenario where multiple data need to be transmitted from the current chip to the target chip, it is necessary to first clarify the priority order of these data, and then, based on the priority order, choose to complete the data transmission through the first interface using the first protocol, or through the second interface using the VRB protocol.

[0154] In order to properly arrange the order of data transmission, each data needs to be assigned a priority. There are many ways to determine the priority, the following are some common ones:

[0155] Different data has different importance in the business. For example, in a real-time monitoring system, alarm data usually has a higher priority than ordinary status data because alarm data may be related to the security and stable operation of the system and needs to be processed in a timely manner.

[0156] For financial transaction systems, transaction instruction data has a higher priority than query request data because the execution of transaction instructions directly affects the flow of funds and the completion of transactions.

[0157] Data with high timeliness requirements should have a higher priority. For example, video streaming data and audio streaming data have extremely high real-time requirements. If the transmission delay is too large, it will affect the user experience. Therefore, the priority of this type of data is usually higher than some batch data with lower timeliness requirements, such as log data.

[0158] When determining the priority, a priority value can be used to represent the priority of each data. The larger the value, the higher the priority. For example, the priority of alarm data can be set to 10, and the priority of normal status data can be set to 2.

[0159] After determining the priority order of the data, the data can be transmitted in this order. During the transmission process, the appropriate transmission method needs to be selected based on whether the current chip and the target chip are in the same cluster.

[0160] In one example, the data to be transmitted are data 1 and data 2, data 1 has a higher priority than data 2, both data 1 and data 2 are transmitted to the target chip, and the target chip is not in the same cluster as the current chip. At this time, data 1 can be transmitted through the second interface first, and then data 2 can be transmitted to the target chip through the second interface after data 1 is sent.

[0161] The present invention can improve the operating efficiency of the entire system by giving priority to important data and reducing the transmission delay of key data. It can assign priorities according to the business needs and timeliness requirements of the data, ensure that key business data is processed in a timely manner, and guarantee the normal operation and service quality of the business.

[0162] In one embodiment of the present invention, data is transmitted to a target chip through a first interface in accordance with a first protocol, or, through a second interface, data is transmitted to a target chip in accordance with a VRB protocol, including: adding a check code to the data; transmitting the data with the check code added to the target chip through the first interface in accordance with the first protocol, or, through the second interface, transmitting the data with the check code added to the target chip in accordance with the VRB protocol.

[0163] In the embodiments of the present invention, the check code is a piece of additional information appended to the original data. It is calculated based on the original data using a specific algorithm. At the receiving end, the check code is recalculated for the received data using the same algorithm and compared with the received check code. If the two are consistent, it indicates that no errors occurred during the data transmission process; if they are inconsistent, it indicates that an error may have occurred in the data. Common check code algorithms include:

[0164] Cyclic Redundancy Check (CRC): This is a widely used checksum algorithm that obtains a fixed-length remainder as a checksum by performing a polynomial division on the data. CRC has strong error detection capabilities and can detect multiple types of errors, such as single-bit errors, double-bit errors, and odd-bit errors. Different application scenarios may use different CRC polynomials, such as CRC-16 and CRC-32.

[0165] Parity check: This is a simple parity check method that determines the value of the check bit by counting the number of 1s in the data. If odd parity is used, the total number of 1s in the data and check bits should be an odd number; if even parity is used, the total number of 1s in the data and check bits should be an even number. Parity check can only detect errors in an odd number of bits, and its error detection capability is relatively weak.

[0166] Checksum: Each byte of the data is added together and the two's complement of the result is used as the checksum. At the receiving end, the same summing operation is performed on the received data and compared with the received checksum. Checksum calculation is relatively simple, but the error detection capability is limited.

[0167] The specific verification code algorithm can be set according to the user's needs and is not limited here.

[0168] Furthermore, after selecting the check code algorithm, the current chip can add a check code to the data using the selected check code algorithm, and then select the first interface or the second interface to transmit the data with the added check code to the target chip based on factors such as whether the current chip and the target chip are in the same cluster and the characteristics of the data. If they are in the same cluster, the choice may be made between the first interface (first protocol) and the second interface (VRB protocol) based on the real-time and accuracy requirements of the data; if they are not in the same cluster, the second interface (VRB protocol) is usually selected for transmission.

[0169] The present invention can detect errors that may occur during data transmission at the receiving end by adding a check code, so that error correction measures such as requesting retransmission can be taken in a timely manner to ensure the accuracy and integrity of the data.

[0170] In one embodiment of the present invention, the method further includes: determining data traffic; judging whether congestion occurs between chips based on the data traffic; and reducing the data transmission rate if congestion occurs between chips.

[0171] In the embodiments of the present invention, data traffic refers to the amount of data passing through the inter-chip transmission channel within a specific time period. Determining whether there is inter-chip congestion can be based on a pre-set congestion threshold. The congestion threshold is an empirical value or a value determined based on factors such as the chip's processing capability and the bandwidth of the transmission channel. The determination method is as follows:

[0172] The real-time data traffic is compared with the pre-set congestion threshold. If the data traffic exceeds the threshold, it can be considered that congestion has occurred between chips; otherwise, there is no congestion. For example, if the set congestion threshold is 10,000 bytes per second, when the real-time monitored data traffic reaches 12,000 bytes per second, congestion is determined to have occurred.

[0173] In addition to directly comparing data traffic and thresholds, you can also analyze the changing trends of data traffic. If data traffic continues to grow rapidly over a short period of time, even if the current data traffic has not yet exceeded the threshold, it may indicate that congestion is about to occur. In this case, you can take measures in advance to avoid congestion.

[0174] When inter-chip congestion is detected, the data transmission rate needs to be reduced to alleviate the congestion. There are several methods for reducing the transmission rate: Fixed-step reduction: The transmission rate is reduced in fixed steps, for example, by 10% at a time. This gradually reduces data traffic until the congestion is alleviated. Adaptive adjustment: The transmission rate is adaptively adjusted based on the severity of congestion. If congestion is severe, the transmission rate is significantly reduced; if congestion is mild, the transmission rate is slightly reduced. The extent of the reduction is determined by calculating the difference between the data traffic and the congestion threshold.

[0175] The present invention avoids data loss, retransmission and other problems caused by congestion by timely detecting and handling congestion, ensuring that data can be transmitted stably between chips. When congestion is determined to occur, the sending rate can be reduced to allow the chip more time to process the received data, avoiding chip overload due to inability to handle the data, and improving the processing efficiency of the chip.

[0176] The present invention discloses a VRB network interconnection data transmission method. The present invention can equip each chip with two independent interfaces, each supporting different transmission protocols. When data needs to be transmitted, the data can be transmitted to the target chip through the first interface and in accordance with the first protocol, or through the second interface and in accordance with the VRB protocol. The optimal protocol can be selected for transmission according to the data type or real-time requirements, thereby avoiding data link congestion and improving the data transmission rate. The present invention can transmit data through the first protocol or the VRB protocol, thereby realizing efficient and high-speed data transmission between chips, improving the overall data processing capability and operating efficiency, and meeting the application requirements of large data volume and high real-time performance.

[0177] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0178] An embodiment of the present invention further provides an electronic device, including:

[0179] The present invention includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, each process of the embodiment of the above-mentioned VRB network interconnection data transmission method is implemented, and the same technical effect can be achieved. To avoid repetition, it is not described here.

[0180] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the various processes of the above-mentioned VRB network interconnection data transmission method embodiment are implemented, and the same technical effects can be achieved. To avoid repetition, they are not described here.

[0181] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0182] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, embodiments of the present invention may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0183] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the process in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0184] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0185] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0186] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0187] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0188] The above is a detailed introduction to the VOC-based XPU chip structure, system, VRB network interconnection data transmission method, device and medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A VOC-based XPU chip structure, characterized in that: The chip structure includes a VOC module, and the VOC module includes a first interface and a second interface; the chips are connected via the first interface and the second interface; The VOC module is configured to transmit data to the VOC module of the target chip through the first interface in accordance with the first protocol, or to transmit the data to the VOC module of the target chip through the second interface in accordance with the VRB protocol.

2. The chip structure according to claim 1, characterized in that: The VOC module is configured to determine whether the current chip and the target chip are in the same cluster; if the current chip and the target chip are in the same cluster, transmit the data to the VOC module of the target chip through the first interface in accordance with the first protocol, or transmit the data to the VOC module of the target chip through the second interface in accordance with the VRB protocol; In a case where the current chip and the target chip are not in the same cluster, the data is transmitted to the VOC module of the target chip through the second interface according to the VRB protocol.

3. The chip structure according to claim 2, characterized in that: The second interface is connected to the second data processor chip via the first data processor chip, and the second data processor chip is connected to the second interface of the target chip; The VOC module is configured to transmit the data to the first data processor chip through the second interface of the current chip when the current chip and the target chip are not in the same cluster; transmitting the data to the second data processor chip through the first data processor chip according to the VRB protocol; The data is transmitted to the second interface of the target chip through the second data processor chip.

4. The chip structure according to claim 2, characterized in that: The data includes the MAC address of the target chip; The VOC module is used to determine whether the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip; if the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip, it is determined that the current chip and the target chip are in the same cluster.

5. A VOC-based XPU chip system, characterized in that: The chip system includes multiple chips, each chip includes a VOC module, the multiple chips are connected through the VOC module, and the VOC module includes a first interface and a second interface; The chip is configured to transmit data to the VOC module of the target chip through the first interface in accordance with the first protocol, or to transmit the data to the VOC module of the target chip through the second interface in accordance with the VRB protocol.

6. The chip system according to claim 5, characterized in that: The chip is configured to determine whether the current chip and the target chip are in the same cluster; if the current chip and the target chip are in the same cluster, transmit the data to the VOC module of the target chip through the first interface in accordance with the first protocol, or transmit the data to the VOC module of the target chip through the second interface in accordance with the VRB protocol; In a case where the current chip and the target chip are not in the same cluster, the data is transmitted to the VOC module of the target chip through the second interface according to the VRB protocol.

7. The chip system according to claim 6, characterized in that: The second interface of the chip is connected to the second data processor chip through the first data processor chip, and the second data processor chip is connected to the second interface of the target chip; the chip being configured to transmit the data to the first data processor chip through the second interface of the current chip when the current chip and the target chip are not in the same cluster; transmitting the data to the second data processor chip through the first data processor chip according to the VRB protocol; The data is transmitted to the second interface of the target chip through the second data processor chip.

8. The chip system according to claim 6, characterized in that: The data includes the MAC address of the target chip; The chip is used to determine whether the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip; if the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip, it is determined that the current chip and the target chip are in the same cluster.

9. A VRB network interconnection data transmission method, characterized in that: The VRB network includes multiple chips, each chip includes a VOC module, and the VOC module includes a first interface and a second interface. The chips are connected via the first interface and the second interface. The method comprises: The data is transmitted to the target chip through the first interface in accordance with the first protocol, or the data is transmitted to the target chip through the second interface in accordance with the VRB protocol.

10. The method according to claim 9, characterized in that The transmitting the data to the target chip through the first interface in accordance with the first protocol, or transmitting the data to the target chip through the second interface in accordance with the VRB protocol, includes: Determine whether the current chip and the target chip are in the same cluster; When the current chip and the target chip are in the same cluster, transmitting the data to the target chip through the first interface in accordance with the first protocol, or transmitting the data to the target chip through the second interface in accordance with the VRB protocol; In a case where the current chip and the target chip are not in the same cluster, the data is transmitted to the target chip through the second interface according to the VRB protocol.

11. The method according to claim 10, characterized in that The second interface of the current chip is connected to a second data processor chip through a first data processor chip, and the second data processor chip is connected to the second interface of the target chip; When the current chip and the target chip are not in the same cluster, transmitting the data to the target chip through the second interface according to the VRB protocol includes: When the current chip and the target chip are not in the same cluster, transmitting the data to the first data processor chip through the second interface of the current chip; transmitting the data to the second data processor chip through the first data processor chip according to the VRB protocol; The data is transmitted to the second interface of the target chip through the second data processor chip.

12. The method according to claim 10, characterized in that The data includes the MAC address of the target chip; The determining whether the current chip and the target chip are in the same cluster includes: Determine whether the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip; If the cluster identifier corresponding to the MAC address of the target chip is the same as the cluster identifier corresponding to the MAC address of the current chip, it is determined that the current chip and the target chip are in the same cluster.

13. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the VRB network interconnection data transmission method according to any one of claims 9 to 12 are implemented.

14. A computer-readable storage medium, characterized in that The computer readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the VRB network interconnection data transmission method according to any one of claims 9 to 12 are implemented.

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