Data transmission method, device, equipment and medium

Abstract

The invention discloses a data transmission method and device, equipment and a medium, and relates to the technical field of computers, the method is used for a processor, and the method comprises the following steps: identifying each board card connected to an interconnection interface of a peripheral component, and obtaining a hardware identifier of each board card; the processor is connected with the plurality of board cards through the peripheral component interconnection interface; the board cards are connected through transceiver interfaces; receiving a data processing task, and determining a target hardware identifier in the data processing task; positioning a corresponding target board card according to the determined target hardware identifier; and sending the to-be-processed data to the target board card, so that the target board card analyzes the to-be-processed data, extracts required parameter information, and processes the to-be-processed data according to the parameter information. In this way, universality and expandability are enhanced, different task requirements and system function expansion can be adapted, the accuracy and efficiency of data transmission are improved, and therefore high-speed and stable communication between the processor and the multiple board cards is achieved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a data transmission method, device, equipment and medium. Background Art

[0002] With the rapid development of computer technology, cutting-edge fields such as artificial intelligence, big data analysis, and cloud computing are booming, placing higher demands on the data processing capabilities of computer systems. To meet these demands, computer equipment often adopts a multi-board architecture that works in concert, processing data in parallel across multiple functional boards. However, with the explosive growth of data volumes, the limited transmission rates of traditional communication methods cannot meet the demand for rapid data exchange. When the processor needs to transmit data to multiple boards simultaneously, traditional communication methods can result in high data transmission delays and increased packet loss, seriously impacting the operational efficiency and stability of the computer system.

[0003] Therefore, how to achieve high-speed and stable communication between the processor and multiple boards is a technical problem that people in this field need to solve urgently. Summary of the Invention

[0004] The purpose of the present invention is to provide a data transmission method, device, equipment and medium, which can realize high-speed and stable communication between a processor and multiple boards, enhance versatility and scalability, and improve the accuracy and efficiency of data transmission.

[0005] In order to solve the above technical problems, the present invention provides a data transmission method for a processor, comprising:

[0006] Identifying each board connected to the peripheral component interconnection interface and obtaining a hardware identifier of each board; the processor is connected to the plurality of boards through the peripheral component interconnection interface;

[0007] receiving a data processing task, and determining a target hardware identifier in the data processing task;

[0008] Locating a corresponding target board according to the determined target hardware identifier; connecting the boards via a transceiver interface;

[0009] The data to be processed is sent to the target board, so that the target board parses the data to be processed, extracts required parameter information, and processes the data to be processed according to the parameter information.

[0010] In a first aspect, in the above-mentioned data transmission method provided by the present invention, identifying each board connected to the peripheral component interconnection interface and obtaining the hardware identifier of each board includes:

[0011] According to the setting mode of the signal interface of the high-speed serial computer expansion bus, the physical layer of the processor is facilitated to sequentially identify each board connected to the signal interface of the high-speed serial computer expansion bus; the processor connects its physical layer to the signal interface of the high-speed serial computer expansion bus through the bridge on the high-speed serial computer expansion bus; the signal interface of the high-speed serial computer expansion bus is connected to the plurality of boards;

[0012] Based on the identification results, read and record the hardware identifier of each board.

[0013] On the other hand, in the above-mentioned data transmission method provided by the present invention, locating the corresponding target board according to the determined target hardware identifier includes:

[0014] According to the determined target hardware identifier, the corresponding target board is located in combination with the mapping relationship between each board and its hardware identifier; and each board is connected via the high-speed serial transceiver interface.

[0015] On the other hand, in the data transmission method provided by the present invention, sending the data to be processed to the target board includes:

[0016] Using a high-speed serial computer expansion bus protocol as a transmission method, the data to be processed is encapsulated into a data packet and sent to the located target board.

[0017] On the other hand, in the above-mentioned data transmission method provided by the present invention, the target board parses the data to be processed and extracts the required parameter information, including:

[0018] After receiving the data to be processed, the target board performs frame check on the data to be processed; the frame check does not include frame synchronization and start frame;

[0019] After the verification is successful, the data to be processed is parsed using the corresponding data packet protocol according to the transmission interface from which the data to be processed comes, to obtain a parsing result;

[0020] The required parameter information is extracted from the parsing result.

[0021] On the other hand, in the above-mentioned data transmission method provided by the present invention, after parsing the data to be processed and obtaining the parsing result, it also includes:

[0022] The parsing results are stored in different cache queues according to type and source; when the parsing result is storage setting data, the cache queue stored is a configuration first-in-first-out queue; when the parsing result is storage business data, the cache queue stored is a sending first-in-first-out queue;

[0023] Using the simulation module and the remote code update module to monitor the non-empty signal of the cache queue in a polling or interrupt manner;

[0024] When it is monitored that the signal of the cache queue is not empty, the storage setting data is processed first, and then the storage service data is processed.

[0025] On the other hand, the data transmission method provided by the present invention further includes:

[0026] After the currently set number of frames of data are sent, determine whether the corresponding handshake success signal is received;

[0027] If yes, continue to send the next set number of frames of data;

[0028] If not, after receiving the error notification signal, the data of the currently set number of frames is resent until the corresponding handshake success signal is received.

[0029] In order to solve the above technical problems, the present invention further provides a data transmission device, comprising:

[0030] a board identification module, configured to identify each board connected to the peripheral component interconnection interface and obtain a hardware identifier of each board; the processor being connected to the plurality of boards via the peripheral component interconnection interface;

[0031] an identifier determination module, configured to receive a data processing task and determine a target hardware identifier in the data processing task;

[0032] A board positioning module is used to locate the corresponding target board according to the determined target hardware identifier; each board is connected via a transceiver interface;

[0033] The data transmission module is used to send the data to be processed to the target board so that the target board parses the data to be processed, extracts the required parameter information, and processes the data to be processed according to the parameter information.

[0034] In order to solve the above technical problems, the present invention also provides an electronic device, comprising: a processor and multiple boards; the processor is connected to the multiple boards via a peripheral component interconnection interface; the boards are connected to each other via a transceiver interface;

[0035] The processor is configured to identify each board connected to the peripheral component interconnection interface and obtain a hardware identifier of each board; receive a data processing task and determine a target hardware identifier in the data processing task; locate a corresponding target board according to the determined target hardware identifier; and send data to be processed to the target board;

[0036] The target board is used to parse the data to be processed, extract required parameter information, and process the data to be processed according to the parameter information.

[0037] In order to solve the above technical problem, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above data transmission method are implemented.

[0038] As can be seen from the above technical solution, the present invention provides a data transmission method for a processor, including: identifying each board connected to the peripheral component interconnection interface and obtaining the hardware identifier of each board; the processor is connected to multiple boards through the peripheral component interconnection interface; receiving a data processing task and determining the target hardware identifier in the data processing task; locating the corresponding target board according to the determined target hardware identifier; the boards are connected through a transceiver interface; and sending the data to be processed to the target board so that the target board parses the data to be processed, extracts the required parameter information, and processes the data to be processed according to the parameter information.

[0039] The beneficial effects of the present invention are that, in the above-mentioned data transmission method provided by the present invention, the processor establishes a communication connection with the board through the peripheral component interconnection interface, and the transceiver interface is used between each board for data transmission, thereby enhancing versatility and scalability, and being able to adapt to different task requirements and system function expansion without the need for large-scale redesign of the entire system; and being able to accurately identify and locate the target board through the hardware identifier, and quickly send data to the corresponding board for processing according to task requirements, thereby combining the transmission capabilities of the peripheral component interconnection and the transceiver to improve the accuracy and efficiency of data transmission, avoiding the situation of data mistransmission or erroneous processing, and effectively completing specific tasks; in addition, the target board can parse the data to be processed and extract the required parameter information, and then perform targeted processing based on this information, thereby improving the overall data processing capability and performance of the system, and helping to realize complex functions. The overall approach can achieve high-speed and stable communication between the processor and multiple boards.

[0040] In addition, the present invention also provides a corresponding data transmission device, electronic device and computer-readable storage medium for the data transmission method, which have the same or corresponding technical features as the above-mentioned data transmission method and have the same effects as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] Figure 1 A flowchart of a data transmission method provided by an embodiment of the present invention;

[0043] Figure 2 A block diagram of communication between a processor and multiple board peripherals provided in an embodiment of the present invention;

[0044] Figure 3 A schematic structural diagram of a data transmission device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0046] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods. Figure 1 A flowchart of a data transmission method provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the method includes:

[0047] S101 , identifying each board connected to the peripheral component interconnection interface and obtaining a hardware identifier of each board; a processor connects to the plurality of boards through the peripheral component interconnection interface.

[0048] It should be noted that the present invention requires establishing a physical connection between the processor and the board. Specifically, a peripheral component interconnect interface is used to connect the processor to each board. The processor can be a central processing unit (CPU) or other types of processors, without limitation. The board can be a field-programmable gate array (FPGA) or other types of boards, without limitation. The peripheral component interconnect (PCI) interface can use a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIE) signal interface or other types of interfaces. The PCIE interface is a fast peripheral component interconnect channel that can be used to connect various high-speed peripherals in a computer system. The PCIE bus transmits data via differential signals and supports full-duplex communication, meaning data can be transmitted in both directions simultaneously. Therefore, the use of PCIE in the present invention further enables high-speed data transmission and device connectivity.

[0049] The processor of the present invention can actively detect and identify boards on the peripheral component interconnect interface and obtain a unique identifier corresponding to each board for subsequent management and communication. Each board is assigned a unique hardware identifier during manufacturing, similar to the device's ID card. The processor can obtain these hardware identifiers by communicating with the boards, allowing it to accurately distinguish between different boards during subsequent operations.

[0050] S102: Receive a data processing task, and determine a target hardware identifier in the data processing task.

[0051] In practice, when executing a task, the processor can first determine the target hardware identifier of the target board corresponding to the task based on the task requirements to ensure that subsequent data can be accurately sent to the designated board. The target hardware identifier can be one or more, and is not limited here.

[0052] S103 , locating a corresponding target board according to the determined target hardware identifier; and connecting the boards via a transceiver interface.

[0053] When the target hardware identifier is one, the located target board is one board; when the target hardware identifier is multiple, the located target boards are multiple boards.

[0054] Figure 2 The communication block diagram of the processor and multiple board peripherals provided in the embodiment of the present invention is as follows. Figure 2As shown, a processor (such as a CPU) is connected to various boards (such as an FPGA) via a peripheral component interconnect (such as PCIE) interface. Each board can be connected to another via a transceiver interface. A transceiver interface is a device used to transmit data and signals between boards. Boards are not independent of each other; they need to exchange data and communicate to collaborate and complete the overall system functionality. The transceiver interface provides a channel that allows a board to transmit processed data and receive data and signals from other boards. The transceiver interface can be a high-speed serial transceiver (GTX) interface or other types of transceiver interfaces, without limitation. GTX is a key network protocol used to facilitate data and signaling transmission in mobile communication networks. The GTX interface is a network interface implemented based on the GTX protocol and is used to transmit data and signaling between different nodes in a mobile communication network. In the present invention, the processor can transmit data with each board via PCIE, and data between boards can be transmitted via the CPU and GTX.

[0055] The present invention ensures the reliability and effectiveness of data communication between the processor and multiple boards through efficient data transmission protocols between PCIE interfaces, between fiber data interfaces, and between customized PCIE and fiber interfaces. Specifically, in the present invention, data exchange between the processor and multiple boards can be accomplished based on the PCIE bus protocol and the GTX protocol. Specifically, the PCIE bus protocol can be used for operations such as discovery, enumeration, configuration, startup, and shutdown, while the GTX protocol can be used for data transmission.

[0056] It's important to note that a processor (such as a CPU) and multiple boards (such as FPGA boards) are linked via peripheral component interconnect (PCIE) interfaces. Some PCIE interfaces connect directly to the CPU, while others require a PCIE switch (a device used to extend and manage PCIE bus connections). The processing speed of PCIE peripherals transiting through the switch is reduced. Furthermore, all PCIE peripheral data transmission is subject to bandwidth limitations. Therefore, GTX is needed to facilitate communication between FPGA peripherals. Key signals between FPGAs can now be exchanged directly through GTX without passing through the CPU. This requires a communication protocol between PCIE and GTX to improve the reliability and efficiency of this communication. Furthermore, thanks to the newly proposed communication protocol, FPGAs can effectively receive and process simulation model data from the CPU.

[0057] S104 , sending the data to be processed to the target board, so that the target board parses the data to be processed, extracts required parameter information, and processes the data to be processed according to the parameter information.

[0058] It should be noted that the processor of the present invention can send the data to be processed to the target board via PCIE. When there are multiple target boards, data between the boards can be transmitted via either CPU interconnection or GTX. After receiving the data to be processed, the target board can parse it, extract the required parameter information, and then perform corresponding processing on the data based on the parameter information. Finally, the board can transmit the processed data back to the processor for subsequent processing.

[0059] In the above-mentioned data transmission method provided by the embodiment of the present invention, the processor establishes a communication connection with the board through the peripheral component interconnection interface, and the transceiver interface is used to transmit data between each board, which enhances the versatility and scalability, and can adapt to different task requirements and system function expansion without the need for large-scale redesign of the entire system; and can accurately identify and locate the target board through the hardware identifier, and quickly send data to the corresponding board for processing according to the task requirements. In this way, the transmission capacity of the peripheral component interconnection and the transceiver is combined to improve the accuracy and efficiency of data transmission, avoid the situation of data mistransmission or erroneous processing, and effectively complete specific tasks; in addition, the target board can parse the data to be processed and extract the required parameter information, and then perform targeted processing based on this information, thereby improving the overall data processing capacity and performance of the system and helping to realize complex functions. The overall approach can achieve high-speed and stable communication between the processor and multiple boards.

[0060] Furthermore, in a specific implementation, in the above-mentioned data transmission method provided in an embodiment of the present invention, step S101 identifies each board connected to the peripheral component interconnection interface and obtains the hardware identifier of each board, which may specifically include: according to the setting mode of the signal interface of the high-speed serial computer expansion bus, facilitating its own physical layer to sequentially identify each board connected to the signal interface of the high-speed serial computer expansion bus; the processor connects its own physical layer to the signal interface of the high-speed serial computer expansion bus through a bridge on the high-speed serial computer expansion bus; the signal interface of the high-speed serial computer expansion bus is connected to multiple boards; and according to the identification result, reading and recording the hardware identifier of each board.

[0061] In practice, the processor must first establish a connection, connecting its physical layer to the relevant PCIE interface through the bridge on the PCIE. This bridge acts as an intermediary, allowing the processor to establish a communication channel with the board connected to the PCIE, allowing the processor to exchange data with other boards connected to the PCIE.

[0062] After establishing a physical connection, the processor needs to identify the specific device connected to the PCIE interface. By enabling a specific mode on the PCIE interface, such as the Advanced Error Reporting (AER) mode within PCIE, the processor can proactively detect and identify the boards connected to the PCIE interface and obtain a unique identifier for each board for subsequent management and communication. Each board is assigned a unique hardware identification number during manufacturing, similar to a device's ID card. The processor communicates with the board, reads, and records this hardware identification number, allowing it to accurately distinguish between different boards during subsequent operations.

[0063] Furthermore, in a specific implementation, in the above-mentioned data transmission method provided in an embodiment of the present invention, step S103 locates the corresponding target board according to the determined target hardware identifier, which may specifically include: locating the corresponding target board according to the determined target hardware identifier, combined with the mapping relationship between each board and the hardware identifier of each board; and each board is connected through a GTX interface.

[0064] In practice, after obtaining the hardware identifiers of all boards, the processor can create a mapping table that maps each hardware identifier to a specific board, establishing a mapping relationship between each board and its hardware identifier. This way, when the processor needs to communicate with a specific board, it can query the mapping table to accurately locate the target board. While executing a task, the processor may need to send data to the target board. In this case, the processor will search the mapping table for the target board's hardware identifier based on the task requirements to ensure that the data is accurately sent to the target board.

[0065] Furthermore, in a specific implementation, in the above-mentioned data transmission method provided in an embodiment of the present invention, step S104 sends the data to be processed to the target board card, which may specifically include: using a high-speed serial computer expansion bus protocol as a transmission method, encapsulating the data to be processed into a data packet and sending it to the located target board card.

[0066] In implementation, after determining the location information of the remote field programmable gate array, the processor can use the established PCIE protocol as a transmission method to encapsulate the data into data packets and send them to the located target board.

[0067] Furthermore, in a specific implementation, in the above-mentioned data transmission method provided in an embodiment of the present invention, step S104 in which the target board parses the data to be processed and extracts the required parameter information may specifically include: after the target board receives the data to be processed, performing a frame check on the data to be processed; the frame check does not include frame synchronization and start frame; after the check is successful, according to the transmission interface from which the data to be processed comes, the corresponding data packet protocol is used to parse the data to be processed to obtain a parsing result; and the required parameter information is extracted from the parsing result.

[0068] In practice, when the remote FPGA receives data from the processor, it checks the data for integrity and correctness. This ensures that no errors or data loss occurred during transmission. This verification can be achieved through frame check. After verifying the data is correct, the remote FPGA parses the data and extracts the specific parameter information sent by the processor. This parameter information is the core content of the processor's instructions and is used to guide the FPGA to perform specific tasks. Finally, the FPGA processes the data accordingly based on the extracted parameter information. This may include performing calculations, storing data, controlling external devices, and other operations, depending on the processor's instructions and the FPGA's configuration.

[0069] It should be noted that the master frame format of the GTX protocol includes: frame synchronization, start frame, master address, number of slave devices, master data type, data length, data segment, and cyclic redundancy check (CRC). The slave frame format of the GTX protocol includes: slave address, slave data type, data length, data segment, WKC (not available yet), and CRC.

[0070] Among them, frame synchronization: use 4 bytes of synchronization code (alternating between 1 and 0) to achieve data synchronization. Start frame: use 1 byte (0xFF) to represent the frame header. Master station address: represents the address of the receiving end, 1 byte. Number of slave devices: represents the number of slave stations in optical fiber communication, 1 byte. Master station data type: if 0X01 represents model communication data, 0X02 represents remote code update data, the default is 0XFF. Data length: 1 byte, indicating the number of bytes in the data segment in the transmission frame. Data segment: represents the specific application data of the transmission frame. WKC: This function is not currently available in the released version design. CRC-32 check: In order to ensure the accuracy of the correct transmission of data, a 4btye CRC check is added. The frame check starts from the master station address and does not include frame synchronization and start frame.

[0071] The frame format of the PCIE protocol includes: frame synchronization, start frame, destination device address, source device address, transmission data type, transmission status, data length, data segment, and CRC-32 check.

[0072] Frame synchronization: Data synchronization is achieved using a 4-byte synchronization code (alternating 1s and 0s). Start frame: A 1-byte frame header is used. Destination device address: This represents the address of the receiving end, a 1-byte value. Based on the application, this is divided into unicast and broadcast addresses. If it is all 0xff, it indicates that the frame is a broadcast frame; otherwise, it is a unicast frame. Source device address: This represents the address of the sending end, a 1-byte value. If the source device address is an x86 CPU, the data segment is used to determine whether the frame is a remote code update instruction, a simulation model setting instruction, or data information from the CPU. Transmission data type: If the source device address is a CPU (x86), 0x00 represents the model, 0x01 represents model communication data, 0x02 represents remote code update data, and 0x03 transfers PCIE data to GTX for transmission. If the original device address is an FPGA, 0x00 indicates successful reception of the simulation model configuration data, 0x01 indicates the simulation model has received five consecutive frames of data, 0x02 indicates the simulation model has sent five consecutive frames of data, 0x03 indicates successful remote upgrade module configuration, 0x04 indicates a simulation model configuration error, 0x05 indicates a data reception error, and 0x06 indicates a remote program upgrade configuration failure. The default value is 0xFF. Transmission Status: 2 bytes are used to represent the transmission status. The upper eight bits record the number of error frames sent. If the number exceeds 0xff, a communication failure is reported to the CPU. The eighth bit represents the transmission status. 0xFF indicates a transmission alarm; other values indicate normal transmission. The default value is 0x0000. Data Length: 1 byte, representing the number of bytes in the data segment of the transmission frame. Data Segment: Represents the specific application data of the transmission frame. CRC-32 Checksum: To ensure correct data transmission, a 4-bit CRC checksum is added. The frame checksum starts at the destination device address and does not include the frame synchronization and start frame.

[0073] Both PCIE and GTX use advanced communication protocols and error correction mechanisms to further ensure the stability and reliability of data transmission.

[0074] It's important to emphasize that the communication method of the present invention is a serial, mutually independent communication method. Each peripheral device cannot modify data segments other than its own and can only update its own data segments. This reduces the stringent synchronization requirements of data and ensures data reliability. This data transmission method reduces latency for critical data between the processor and multiple boards, increases data transmission reliability and consistency, eliminates data ambiguity, and unifies data transmission formats.

[0075] Furthermore, in specific implementation, in the above-mentioned data transmission method provided in the embodiment of the present invention, after parsing the data to be processed and obtaining the parsing results, it can also include: storing the parsing results in different cache queues according to type and source; when the parsing result is storage setting data, the stored cache queue is a configuration first-in-first-out queue; when the parsing result is storage business data, the stored cache queue is a transceiver first-in-first-out queue; using the simulation module and the remote code update module to monitor the non-empty signal of the cache queue through polling or interruption; when the signal of the cache queue is monitored to be non-empty, first process the storage setting data, and then process the storage business data.

[0076] In implementation, PCIE and GTX use different packet protocols for application-layer communication. All data, after being parsed by their respective protocols, is placed into corresponding first-in-first-out (FIFO) queues for configuration or receiving data. The emulation module and remote code update module monitor the configuration and read FIFOs for non-empty signals. If a FIFO is not empty, the module processes the signal accordingly. After processing the configuration information, the module then processes the read FIFO.

[0077] In actual applications, if PCIE and optical fiber have data flowing into the same functional module at the same time, the setting data will be processed first. If configuration information comes at the same time, the configuration data from the PCIE end will be the best.

[0078] Furthermore, in a specific implementation, the above-mentioned data transmission method provided in the embodiment of the present invention may also include: after sending the data of the current set number of frames (such as 5 frames), determining whether a corresponding handshake success signal is received; if so, continuing to send the data of the next set number of frames; if not, after receiving the error notification signal, resending the data of the current set number of frames until the corresponding handshake success signal is received.

[0079] In practice, to prevent data loss, the present invention employs a question-and-answer handshake protocol during configuration data transmission. Specifically, when the emulation module or remote code upgrade module receives configuration information from the X86 CPU, it responds with a successful handshake message upon completion. This feedback is provided every five frames of data during data transmission and reception. If an error occurs, the CPU must retransmit the correct five frames. This improves data transmission security and reduces the risk of data leakage and tampering.

[0080] In the above embodiments, the data transmission method is described in detail. The present invention also provides corresponding embodiments of a data transmission device and an electronic device. It should be noted that the present invention describes the embodiments of the device from two perspectives: one is based on the functional module perspective, and the other is based on the hardware perspective.

[0081] Figure 3 This is a schematic diagram of the structure of the data transmission device provided by the embodiment of the present invention. This embodiment is based on the perspective of functional modules, such as Figure 3 As shown, the device includes:

[0082] The board identification module 10 is used to identify each board connected to the peripheral component interconnection interface and obtain the hardware identifier of each board; the processor is connected to multiple boards through the peripheral component interconnection interface;

[0083] The identifier determination module 11 is used to receive a data processing task and determine a target hardware identifier in the data processing task;

[0084] The board positioning module 12 is used to locate the corresponding target board according to the determined target hardware identifier; each board is connected via a transceiver interface;

[0085] The data transmission module 13 is used to send the data to be processed to the target board so that the target board parses the data to be processed, extracts required parameter information, and processes the data to be processed according to the parameter information.

[0086] In the above-mentioned data transmission device provided in the embodiment of the present invention, the interaction of the above-mentioned four modules can realize high-speed and stable communication between the processor and multiple boards, enhance versatility and scalability, adapt to different task requirements and system function expansion; and improve the accuracy and efficiency of data transmission, avoid data mistransmission or erroneous processing, effectively complete specific tasks, and also improve the overall data processing capabilities and performance of the system, which helps to realize complex functions.

[0087] Since the embodiments of the apparatus part correspond to the embodiments of the method part, the embodiments of the apparatus part refer to the description of the embodiments of the method part and are not described here in detail. The embodiments of the apparatus part have the same beneficial effects as the above-mentioned data transmission method.

[0088] Furthermore, in this embodiment, based on a hardware perspective, the electronic device includes: a processor and multiple boards; the processor is connected to the multiple boards through a peripheral component interconnection interface; the boards are connected to each other through a transceiver interface; the processor is used to identify the boards connected to the peripheral component interconnection interface and obtain the hardware identifier of each board; receive a data processing task and determine the target hardware identifier in the data processing task; locate the corresponding target board according to the determined target hardware identifier; send the data to be processed to the target board; the target board is used to parse the data to be processed, extract the required parameter information, and process the data to be processed according to the parameter information.

[0089] The processor in the electronic device provided by the embodiment of the present invention can implement the data transmission method mentioned above, and the effect is the same as above.

[0090] The present invention also provides a corresponding embodiment of a computer-readable storage medium. The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps described in the above method embodiment. The computer-readable storage medium provided by the present invention can implement the above-mentioned data transmission method, achieving the same effect as described above.

[0091] Finally, the present invention also provides a corresponding embodiment of a computer program product. The computer program product includes a computer program / instructions that, when executed by a processor, implement the steps described in the above-mentioned data transmission method embodiment. The computer program product provided by the present invention can implement the above-mentioned data transmission method, achieving the same effects as described above.

[0092] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the aforementioned elements.

[0093] The data transmission method, device, equipment and medium provided by the present invention are introduced in detail above. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A data transmission method, characterized in that: For processors, including: Identifying each board connected to the peripheral component interconnection interface and obtaining a hardware identifier of each board; the processor is connected to the plurality of boards through the peripheral component interconnection interface; receiving a data processing task, and determining a target hardware identifier in the data processing task; Locating a corresponding target board according to the determined target hardware identifier; connecting the boards via a transceiver interface; The data to be processed is sent to the target board, so that the target board parses the data to be processed, extracts required parameter information, and processes the data to be processed according to the parameter information.

2. The data transmission method according to claim 1, wherein: Identify each board connected to the peripheral component interconnect interface and obtain the hardware identifier of each board, including: According to the setting mode of the signal interface of the high-speed serial computer expansion bus, the physical layer of the processor is facilitated to sequentially identify each board connected to the signal interface of the high-speed serial computer expansion bus; the processor connects its physical layer to the signal interface of the high-speed serial computer expansion bus through the bridge on the high-speed serial computer expansion bus; the signal interface of the high-speed serial computer expansion bus is connected to the plurality of boards; Based on the identification results, read and record the hardware identifier of each board.

3. The data transmission method according to claim 1, wherein: Locating a corresponding target board according to the determined target hardware identifier includes: According to the determined target hardware identifier, the corresponding target board is located in combination with the mapping relationship between each board and its hardware identifier; and each board is connected via the high-speed serial transceiver interface.

4. The data transmission method according to claim 1, wherein: Sending the data to be processed to the target board includes: Using a high-speed serial computer expansion bus protocol as a transmission method, the data to be processed is encapsulated into a data packet and sent to the located target board.

5. The data transmission method according to claim 1, wherein: The target board parses the data to be processed and extracts the required parameter information, including: After receiving the data to be processed, the target board performs frame check on the data to be processed; the frame check does not include frame synchronization and start frame; After the verification is successful, the data to be processed is parsed using the corresponding data packet protocol according to the transmission interface from which the data to be processed comes, to obtain a parsing result; The required parameter information is extracted from the parsing result.

6. The data transmission method according to claim 5, characterized in that: After parsing the data to be processed and obtaining the parsing result, the method further includes: The parsing results are stored in different cache queues according to type and source; when the parsing result is storage setting data, the cache queue stored is a configuration first-in-first-out queue; when the parsing result is storage business data, the cache queue stored is a sending first-in-first-out queue; Using the simulation module and the remote code update module to monitor the non-empty signal of the cache queue in a polling or interrupt manner; When it is monitored that the signal of the cache queue is not empty, the storage setting data is processed first, and then the storage service data is processed.

7. The data transmission method according to claim 1, wherein: Also includes: After the currently set number of frames of data are sent, determine whether the corresponding handshake success signal is received; If yes, continue to send the next set number of frames of data; If not, after receiving the error notification signal, the data of the currently set number of frames is resent until the corresponding handshake success signal is received.

8. A data transmission device, characterized in that: include: A board identification module is used to identify each board connected to the peripheral component interconnection interface and obtain the hardware identifier of each board; The processor is connected to a plurality of boards via the peripheral component interconnection interface; an identifier determination module, configured to receive a data processing task and determine a target hardware identifier in the data processing task; A board positioning module is used to locate the corresponding target board according to the determined target hardware identifier; each board is connected via a transceiver interface; The data transmission module is used to send the data to be processed to the target board so that the target board parses the data to be processed, extracts the required parameter information, and processes the data to be processed according to the parameter information.

9. An electronic device, characterized in that: include: A processor and multiple boards; the processor is connected to the multiple boards via a peripheral component interconnection interface; Each board is connected through a transceiver interface; The processor is configured to identify each board connected to the peripheral component interconnection interface and obtain a hardware identifier of each board; receive a data processing task and determine a target hardware identifier in the data processing task; locate a corresponding target board according to the determined target hardware identifier; and send data to be processed to the target board; The target board is used to parse the data to be processed, extract required parameter information, and process the data to be processed according to the parameter information.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the data transmission method according to any one of claims 1 to 7.

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