Multimodal large model digital circuit experiment platform, method and medium

Abstract

The application relates to the field of digital circuit experiment teaching, in particular to a multi-modal large model digital circuit experiment platform, method and medium, the method comprising the following steps: inputting an experiment task description, extracting structured semantic information through analysis, and constructing a task representation; searching for a circuit function block from an electronic component knowledge base, constructing a context-enhanced prompt word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the code after grammar checking and function verification; using a Yosys tool to perform logic synthesis on the code to generate a standard JSON netlist, and then converting the netlist into an SVG format circuit diagram through a Netlistsvg tool; and constructing an electronic component knowledge base update mechanism to realize knowledge cyclic evolution and self-adaptive enhancement, thereby significantly improving the intelligent level and the training efficiency of circuit experiment teaching.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital circuit experiment teaching, more specifically, it relates to a multi-modal large model digital circuit experiment platform, method and medium. BACKGROUND

[0002] In the field of digital circuit experiment teaching, the technical bottleneck of traditional experiment platform and method is increasingly prominent. In the existing technical system, the landing of experiment task is highly dependent on manual work. This mode not only requires the user to master multiple skills, but also needs to have rich engineering practical experience. The deeper technical limitation lies in the lack of natural language processing and intelligent generation capabilities. The traditional platform is difficult to automatically analyze the natural language task into structured functional requirements, interface constraints and timing parameters, and it is also difficult to generate context-aware prompt words based on the electronic component knowledge base to guide code generation. When facing circuit design containing multiple clock domains and complex combinational logic, manual operation is prone to problems such as signal naming conflict and timing path violation.

[0003] In addition, the electronic component knowledge base in the existing technical system generally adopts a static storage architecture, lacking a dynamic updating mechanism based on experimental data. On the one hand, when new logic units or advanced process libraries are introduced, the knowledge base is difficult to quickly incorporate the latest component models; on the other hand, excellent circuit designs verified in historical experiments cannot be automatically deposited as new nodes of the knowledge base, resulting in a serious "knowledge island" phenomenon.

[0004] Therefore, based on the above background, the present application proposes a multi-modal large model digital circuit experiment platform, method and medium. SUMMARY

[0005] In view of the deficiencies in the prior art, the purpose of the present application is to provide a multi-modal large model digital circuit experiment platform, method and medium.

[0006] To achieve the above purpose, the present application provides the following technical solutions:

[0007] The multi-modal large model digital circuit experiment platform comprises an experiment task semantic analysis module, a circuit prompt word construction module, a Verilog HDL code generation module, a code verification module, a circuit schematic diagram generation module, and an electronic component knowledge base + RAG enhanced updating module.

[0008] The experiment task semantic analysis module converts the input natural language description of the experiment task requirement into a structured representation of the experiment task.

[0009] The circuit prompt word construction module connects the electronic component knowledge base, retrieves the circuit function block according to the experiment task, and generates candidate circuit prompt words using the circuit prompt word construction function, and calculates the circuit prompt word diversity index.

[0010] Verilog HDL code generation module: guided by circuit cues, a multi-modal large model generates Verilog HDL code;

[0011] Code verification module: interface constraints, syntax checking and functional verification are performed on the generated Verilog HDL code;

[0012] Circuit schematic generation module: used for logic synthesis of the verified code to generate a circuit schematic;

[0013] Electronic component knowledge base + RAG enhanced update module: used to update the electronic component knowledge base.

[0014] Step one, experimental task semantic analysis: convert the input natural language description of functional requirements into a structured representation of experimental tasks Task={F, I, T}; where F represents the function type (such as adder, flip-flop, etc.), I represents the interface constraint (such as input / output bit width, signal naming, etc.), and T represents the key timing requirement (such as rising edge trigger, hold time, etc.);

[0015] Step two, circuit cue construction: retrieve the optimal circuit function block from the electronic component knowledge base, and construct the circuit cue using the circuit cue construction function in combination with the error prompt information defined in step one and the experimental task described in step one.

[0016] Step three, Verilog code generation and verification: using the circuit cue described in step two, through a multi-modal large model generate Verilog HDL code V; and perform interface constraint, syntax checking and functional verification on the Verilog HDL code V generated by MLLMs.

[0017] Step four, circuit schematic generation: using the Yosys tool to perform logic synthesis on the Verilog HDL code V described in step three to generate a JSON format circuit netlist ; in which, represents the circuit netlist function; using the set conflict detection mechanism and backtracking generation strategy to perform logic synthesis detection on the code V; using the Netlistsvg tool to convert the circuit netlist N into an SVG format circuit schematic ; in which, represents the schematic generation function;

[0018] Step five, circuit schematic timing verification: using the MLLMs model to perform timing verification on the circuit schematic G obtained in step four to meet the timing constraint set in the experimental task, each timing constraint represents the signal from node to propagation maximum delay ; if the verification fails, update the circuit prompt word And regenerate the Verilog HDL code, continue iteration until the timing consistency is met;

[0019] Step six, electronic component knowledge base update: select candidate circuit function block from electronic component knowledge base ;According to the experimental task Task and the candidate circuit function block Structural semantic similarity, search weight Calculate the search score of the candidate circuit function block , the calculation formula is as follows:

[0020] ;

[0021] Among them, Indicates the structural semantic similarity of the experimental task Task and the circuit function block , Adjusting coefficient, specific according to experience or through search optimization;

[0022] For the candidate circuit function block , according to the search score Descending order, the circuit function block with the highest search score is recorded as the optimal circuit function block B * , the formula is as follows:

[0023] ;

[0024] Among them, Indicates the value of the corresponding independent variable when the function reaches the maximum value;

[0025] Then output the optimal circuit function block To the circuit prompt word construction module; extract the digital circuit structured information after the verification of the circuit schematic diagram generation module , wherein Indicates the code Function semantic label, write As a new circuit function block into the electronic component knowledge base ; Introduce a penalty score adjustment mechanism to update the optimal circuit function block Index weight ;

[0026] ​The application further provides a computer readable storage medium, which stores a computer program, and the program is executed by a processor to realize the digital circuit experiment method of applying a multi-modal large model, and is specifically used in a digital circuit experiment teaching platform to realize a closed process from task semantic analysis, code generation, logic verification, generation of a circuit schematic diagram to knowledge enhancement.

[0027] Further, in step two, the specific steps of constructing the circuit prompt word are as follows:

[0028] S0, define a circuit prompt word construction function set , the round error prompt information , represents the number of circuit prompt word construction functions in the set;

[0029] S1, retrieve the optimal circuit function block of the round from the electronic component knowledge base ;

[0030] S2, use the structured representation of the experiment task Task in step one, the optimal circuit function block , and the error prompt information , the round construction function to generate a candidate circuit prompt word ;

[0031] S3, calculate the diversity index of the candidate circuit prompt word , the greater the value, the better the diversity of the circuit prompt word, and the calculation formula is as follows:

[0032] ;

[0033] Among them, respectively represent the circuit prompt words generated by the round construction function , represents the similarity between the round circuit prompt words based on n-gram;

[0034] S4, set a diversity index threshold , if , the candidate circuit prompt word is taken as the round circuit prompt word ;

[0035] S5, if , calculate the diversity score of each construction function in the circuit prompt word construction function set, and the calculation formula is as follows:​​

[0036] ;

[0037] wherein, represents a consistency weight factor, represents a cosine similarity;

[0038] S6, ranking each construction function according to the diversity score in descending order, and selecting the highest construction function re-generate , the calculation formula is:

[0039] .

[0040] Further, the interface constraint, syntax checking, and function verification in step three are as follows:

[0041] The constraint conditions are as follows:

[0042] ;

[0043] wherein, represents the interface constraint in the experimental task, represents that the code V satisfies the interface constraint in semantics , , respectively represent the Verilog HDL syntax checking and function verification function;

[0044] If the above constraint does not hold, the backtracking mechanism is executed:

[0045] ;

[0046] In the formula, represents the Verilog HDL code generated by the multi-modal large model in the th iteration, represents the optimal circuit function block obtained by RAG retrieval in the th iteration.

[0047] Further, the conflict detection mechanism and the trace generation strategy set in step four are as follows:

[0048] For the signal in the Verilog HDL code V, if there is a conflict set , no processing is performed;

[0049] Otherwise, the conflict set is used to construct a circuit prompt word to guide the MLLMs to repair the target, and the expression is: ​

[0050] ;

[0051] After several iterations until , ;

[0052] In the formula, represents the generation of Verilog HDL code in the first signal, represents the signal conflict set, represents the code defined in the set of all signals, represents the first iteration circuit prompt word, represents the union operation.

[0053] Further, the timing verification of the circuit schematic in step five, the specific process is as follows:

[0054] Modeling the circuit schematic G and recording as a directed graph , where the node set represents the logic unit (such as NAND gate, D flip-flop, etc.), the edge set represents the signal connection direction;

[0055] Define the attribute vector of each logic unit node as:

[0056] ;

[0057] Where, represents the embedding operation function, which can convert the node attribute into a continuous vector, Type(v) represents the type of logic unit represented by node v, Delay(v) represents the static propagation delay of the logic unit represented by node v, and ClockDomain(v) represents the clock domain to which the node v belongs;

[0058] Build a global graph representation of the circuit schematic:

[0059] ;

[0060] Where, represents the graph neural network;

[0061] Capture the timing path dependency relationship and perform timing verification, the formula is as follows:

[0062] ;

[0063] Where, 1 represents successful verification, and 0 represents failed verification; represents the graph along the node src i to dst iThe shortest path propagation delay, the calculation formula is as follows:

[0064] ;

[0065] Wherein, The node src i to dst i All path set, delta uv Indicate that the signal propagates from node u to v Delay.

[0066] Further, the penalty score adjustment mechanism is introduced in step six, as follows:

[0067] If the optimal circuit function block Generate candidate circuit prompt words The diversity index Greater than or equal to The retrieval weight Remain unchanged;

[0068] Otherwise, update the optimal circuit function block Corresponding retrieval weight , The formula is:

[0069] ;

[0070] Wherein: Indicate the current index weight, The penalty term, Indicate the basic penalty amplitude, Indicate the attenuation coefficient, Indicate the circuit function block B * The cumulative number of verification failures, Indicate the weighting coefficient.

[0071] Compared with the prior art, the present application has the following beneficial effects:

[0072] 1、The present application converts the natural language experiment task into a structured representation, guides the multi-modal large model to generate Verilog HDL code according to the circuit prompt word, realizes the intelligent conversion from natural language to circuit code, reduces the tedious process of manual code writing, reduces the technical threshold of experiment operation, enables students to easily carry out digital circuit experiment, and thus improves the intelligent degree of experimental teaching;

[0073] 2、Through circuit function block retrieval score calculation, optimal circuit function block selection, index weight update and penalty score adjustment, etc., the digital circuit structured information that passes the verification is continuously added to the knowledge base, realizing the cyclic evolution and self-adaptive enhancement of knowledge, and providing more comprehensive and accurate knowledge support for subsequent experimental teaching. BRIEF DESCRIPTION OF DRAWINGS

[0074] Figure 1 A module block diagram of the application of the multi-modal large model digital circuit experiment platform of the present application;

[0075] Figure 2 A flowchart of the application of the multi-modal large model digital circuit experiment method of the present application. DETAILED DESCRIPTION

[0076] Embodiment one, with reference to Figure 1 The application of the multi-modal large model digital circuit experiment platform of the present embodiment comprises:

[0077] An experiment task semantic analysis module: the structured semantic information in the input natural language description of the experiment task requirement is extracted through analysis, and is converted into a structured representation of the experiment task Task;

[0078] A circuit prompt word construction module: connecting an electronic component knowledge base, retrieving circuit function blocks according to Task and generating candidate circuit prompt words using a circuit prompt word construction function, and calculating a circuit prompt word diversity index to judge whether the generated circuit prompt words meet the requirements;

[0079] A Verilog HDL code generation module: using circuit prompt words to guide the multi-modal large model to generate Verilog HDL code;

[0080] A code verification module: interface constraints, syntax checking and function verification are performed on the generated Verilog HDL code;

[0081] A circuit schematic diagram generation module: containing Yosys tools and Netlistsvg tools, used for logic synthesis of the verified code, generation of JSON format circuit netlist and conversion into SVG format circuit schematic diagram;

[0082] An electronic component knowledge base + RAG enhanced update module: used to realize the update of the electronic component knowledge base to support the cyclic evolution and adaptive enhancement of knowledge.

[0083] With reference to Figure 2 The application of the multi-modal large model digital circuit experiment method of the present embodiment specifically comprises the following processes:

[0084] Step one, experiment task semantic analysis.

[0085] The input natural language description of the functional requirement is converted into a structured representation of the experiment task:

[0086] Task={F,I,T};

[0087] Wherein, F represents the function type (such as adder, flip-flop, etc.), I represents the interface constraint (such as input / output bit width, signal naming, etc.), T represents the critical timing requirement (such as rising edge trigger, hold time, etc.);

[0088] Step two, circuit prompt word construction.

[0089] S0, define the circuit prompt word construction function set , the round error prompt information , represents the number of circuit prompt word construction functions in the set;

[0090] S1, retrieve the first round optimal circuit function block from the electronic component knowledge base ;

[0091] S2, use the structured representation of the experimental task Task in step one, the optimal circuit function block and the error prompt information , the first round construction function to generate candidate circuit prompt words ;

[0092] S3, calculate the diversity index of the candidate circuit prompt words , the greater the value, the better the circuit prompt word diversification, the calculation formula is as follows:

[0093] ;

[0094] Wherein, respectively represents the circuit prompt word generated by the first round construction function , represents the similarity between the first round circuit prompt words based on n-gram;

[0095] S4, set the diversity index threshold , in the embodiment , the value is 0.68; if , the candidate circuit prompt word is taken as the first round circuit prompt word ;

[0096] S5, if , calculate the diversity score of each construction function in the circuit prompt word construction function set, the calculation formula is as follows:

[0097] ​​;

[0098] wherein, represents a consistency weight factor, represents a cosine similarity;

[0099] S6, rank each construction function according to the diversity score in descending order, select the highest construction function re-generate , the calculation formula is:

[0100] ;

[0101] Step three, Verilog code generation and verification.

[0102] using the circuit cue described in step two , through the multi-modal large model generate Verilog HDL code V, wherein MLLMs represent the multi-modal large model generating Verilog HDL code function;

[0103] The Verilog HDL code V generated by MLLMs is executed for interface constraint, syntax checking, and function verification. The constraint conditions are as follows:

[0104] ;

[0105] wherein, represents the interface constraint in the experimental task, represents that the code V meets the interface constraint in semantics , , respectively represent the Verilog HDL syntax checking function and the function verification function;

[0106] If the above constraint does not hold, the backtracking mechanism is executed:

[0107] ;

[0108] In the formula, represents the Verilog HDL code generated by the multi-modal large model in the th iteration, represents the optimal circuit function block obtained by RAG retrieval in the th iteration;

[0109] Step four, circuit schematic diagram generation.

[0110] ​The Yosys tool is used for logic synthesis on the Verilog HDL code V described in step three to generate a JSON format circuit netlist N:

[0111] ;

[0112] In the formula, indicates the generation of circuit netlist function;

[0113] When the code V is logically synthesized, the conflict detection mechanism and the backtracking generation strategy are set, which includes the following processes:

[0114] For the signal in the Verilog HDL code V, if there is a conflict set , do not make any treatment;

[0115] Otherwise, use the conflict set to construct the circuit prompt word to guide the MLLMs repair target, the expression is:

[0116] ;

[0117] After several iterations until , ;

[0118] In the formula, indicates the generation of the first signal in the Verilog HDL code, indicates that the signal has a conflict set, indicates that the code defines all signal sets, indicates the circuit prompt word of the first iteration, indicates the set operation; The Netlistsvg tool is used to convert the circuit netlist N into an SVG format circuit schematic diagram G:

[0119]

[0120] ;

[0121] In the formula, indicates the generation of the schematic diagram function;

[0122] Step five, circuit schematic timing verification.

[0123] The MLLMs model is used for timing verification on the circuit schematic diagram G obtained in step four, which meets the timing constraint set in the experimental task, and each timing constraint indicates that the signal propagates from node to maximum delay​​ If the verification fails, update the circuit prompt word Regenerate the Verilog HDL code and continue to iterate until timing consistency is met. The specific verification process is as follows:

[0124] Model the circuit schematic diagram G and record it as a directed graph , where the node set Represents a logic unit (such as a NAND gate, a D flip-flop, etc.), an edge set Indicates the signal connection direction;

[0125] Define the attribute vector of each logic unit node as:

[0126] ;

[0127] in, Represents an embedded operation function that can convert node attributes into continuous vectors. Type(v) represents the type of logic unit represented by node v. Delay(v) represents the static propagation delay of the logic unit represented by node v. ClockDomain(v) represents the clock domain to which node v belongs.

[0128] Construct a global diagram representation of the circuit schematic:

[0129] ;

[0130] in, Representing graph neural networks;

[0131] Capture a global view of the circuit schematic The timing path dependency relationship in the experimental task is verified to meet the timing constraint set in the experimental task. , the specific formula is as follows:

[0132] ;

[0133] Among them, 1 indicates successful verification, and 0 indicates failed verification; Represents the global diagram of the circuit schematic mid-edge node src i to dst i The shortest path propagation delay is calculated as follows:

[0134] ;

[0135] in, Represents the node src i to dst i The set of all paths, δ uv represents the propagation delay of the signal from node u to v;

[0136] Step 6: Update the electronic component knowledge base.

[0137] From the Electronic Components Knowledge Base Select candidate circuit functional blocks According to the experimental task Task of step 1 and the candidate circuit function block Structural semantic similarity, retrieval weight Calculate the candidate circuit functional blocks Search score of , the calculation formula is as follows:

[0138] ;

[0139] in, Represents experimental tasks and circuit function blocks Structural semantic similarity, Represents the adjustment coefficient, which is set based on experience or through search optimization. In this embodiment The value is 1.0, The value is 0.5;

[0140] For the candidate circuit functional blocks , according to the search score Sort in descending order and record the circuit function block with the highest search score as the optimal circuit function block B * , the formula is as follows:

[0141] ;

[0142] in, Indicates the value of the independent variable corresponding to the maximum value of the function;

[0143] Then the optimal circuit functional block Output to the circuit prompt word construction module; extract the digital circuit structure information after verification by the circuit schematic generation module ,in Representation code Functional semantic labels, Write into the electronic component knowledge base as a new circuit function block ; Update the optimal circuit function block Index weight , and introduce a penalty score adjustment mechanism, as follows:

[0144] If the optimal circuit functional block Generate candidate circuit hint words Diversity indicators Greater than or equal to The search weight remain unchanged;

[0145] Otherwise, update the optimal circuit function block Corresponding search weight , the formula is:

[0146] ;

[0147] Wherein: Indicates the current index weight, is a penalty term, Indicates the basic penalty amplitude, Indicates the attenuation coefficient, Indicates the circuit function block B * The cumulative number of verification failures, Indicates the weighting coefficient; in the embodiment, η is 0.02, λ is 0.3, and γ is 1.0.

[0148] The embodiment also provides a computer readable storage medium, which stores a computer program, and the program is executed by a processor to realize the digital circuit experiment method for applying a multi-modal large model, and is specifically used in a digital circuit experiment teaching platform to realize a closed process from task semantic analysis, code generation, logic verification, generation of a circuit schematic diagram to knowledge enhancement.

[0149] Through the detailed introduction of the above embodiments, the digital circuit experiment method for applying a multi-modal large model realizes intelligent conversion from natural language to circuit code by converting an experimental task in natural language into a structured representation and guiding a multi-modal large model to generate Verilog HDL code according to a circuit prompt word, reduces the cumbersome process of manually writing code, reduces the technical threshold of experimental operation, enables students to easily carry out digital circuit experiments, and thus improves the intelligent degree of experimental teaching; through continuous enrichment and update of an electronic component knowledge base, the method realizes cyclic evolution and self-adaptive enhancement of knowledge, and provides more comprehensive and accurate knowledge support for subsequent experimental teaching.

[0150] The above formulas are all dimensionless values, and the preset parameters in the formulas are set by a person skilled in the art according to actual conditions.

[0151] The above-described embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are wholly or partially generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center through a wired or wireless (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. containing one or more available medium collections. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state disk.

[0152] It should be understood that the size of the sequence number of each process described above in various embodiments of the present application does not mean the order of execution, and the execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0153] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0154] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0155] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the division of the above-described device embodiments is only a logical function division, and there can be another division manner for actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, or the among different units, can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0156] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various other media that can store program codes.

[0157] The above describes only the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A multi-modal large model digital circuit experiment platform, characterized in that, Comprise: The experimental task semantic analysis module, the input natural language description of the experimental task demand, through the analysis extracts the structured semantic information, is converted into the structured representation of the experimental task; The circuit prompt word construction module is connected with the electronic component knowledge base, the circuit function block is retrieved according to the experimental task, and the candidate circuit prompt word is generated by using the circuit prompt word construction function, and the specific steps include: S0, define the circuit prompt word construction function set , the first wheel error prompt information , represents the number of circuit prompt word construction functions in the set; S1, retrieving the first wheel optimal circuit function block ; S2, using the structured representation experiment task Task in step one, optimal circuit function block and the error prompt information , the first wheel construction function generate candidate circuit prompt words ; S3, calculate a diversity index of the candidate circuit prompt word ; S4, set the diversity index threshold , if , the candidate circuit prompt word as the first round circuit prompt word ; S5、if The computing circuit prompts the diversity score of each construction function in the construction function set. S6, the diversity score of the highest construction function is selected to regenerate the circuit prompt word; The Verilog HDL code generation module generates Verilog HDL code by using the circuit prompt word to guide the multimodal large model; The code verification module performs interface constraint, syntax checking and function verification on the generated Verilog HDL code;Wherein, the interface constraint, syntax checking, function verification, as follows: determining whether a constraint condition is satisfied wherein, represents an interface constraint in the experimental task, represents that the code V semantically satisfies the interface constraint , , respectively represent a Verilog HDL syntax check, a function verification function; if the above constraint is not established, a backtracking mechanism is executed; The circuit schematic diagram generation module is used for logical synthesis of the verified code, and the circuit netlist is generated and converted into a circuit schematic diagram;Wherein, the logical synthesis, the specific process is as follows: A conflict detection mechanism and a trace generation strategy are set up to detect the conflict set in the Verilog HDL code of step three If the conflict set exists , no processing is performed; otherwise, a circuit prompt word is constructed using the conflict set to guide the MLLMs to repair the target, and the expression is: ； After several iterations until , ; where, represents the generation of Verilog HDL code for the th signal, represents the conflict set of signals, represents the set of all signals defined in the code, represents the th iteration circuit cue, represents the union operation; Electronic component knowledge base+RAG enhanced update module is used to update the electronic component knowledge base.

2. The method of claim 1, wherein the method is implemented by a multi-modal large model digital circuit experiment platform. Comprise the following steps: Step one, experimental task semantic analysis: the input natural language description function demand is converted into structured representation of the experimental task Task; Step two, circuit prompt word construction: the optimal circuit function block is retrieved from the electronic component knowledge base, and the circuit prompt word is constructed by using the circuit prompt word construction function; Step three, Verilog code generation and verification: the circuit prompt word in step two is used to generate Verilog HDL code by using the multimodal large model, and interface constraint, syntax checking and function verification are carried out; Step four, circuit schematic diagram generation: the Yosys tool is used for logical synthesis of the Verilog HDL code in step three, and the circuit netlist is generated;The circuit netlist is converted into a circuit schematic diagram by using Netlistsvg tool; Step five, circuit schematic diagram timing verification: the circuit schematic diagram obtained in step four is verified by using MLLMs model;If the verification fails, the circuit prompt word is updated and the Verilog HDL code is regenerated, and the iteration is continued until the timing consistency is satisfied; Step six, electronic component knowledge base update: the candidate circuit function block is selected from the electronic component knowledge base;The retrieval score of the candidate circuit function block is calculated; The circuit prompt word construction module outputs the circuit function block with the highest retrieval score;The digital circuit structured information verified by the circuit schematic diagram generation module is written into the electronic component knowledge base as a new circuit function block;The optimal circuit function block index weight is updated by using the introduced penalty score adjustment mechanism.

3. The method of claim 2, wherein, The timing verification of the circuit schematic diagram in step five is as follows: Model the circuit schematic described in step 4 and record it as a directed graph ; Define each logic unit node attribute vector as ;use Constructing a global graph h of circuit schematics through graph neural networks (GNNs) G ; Using the formula ,capture the timing path dependency and perform timing verification, where 1 indicates successful verification and 0 indicates failed; Representation diagram mid-edge node src i to dst i Longest path propagation delay.

4. The method of claim 2, wherein, In step six, the penalty score adjustment mechanism is introduced, as follows: If the optimal circuit function block generates a diversity index of the candidate circuit prompt word Greater than or equal to Then the retrieval weight remains unchanged; Otherwise, the penalty term, attenuation coefficient and failure accumulation number are introduced to update the retrieval weight of the optimal circuit function block.

5. A multi-modal large model digital circuit experiment medium, characterized in that, A computer readable storage medium is provided, and a computer program is stored on the computer readable storage medium, and the computer program is executed by a processor to implement the application multimodal large model digital circuit experiment method in any one of claims 2-4, and is specifically used in a digital circuit experiment teaching platform, and a knowledge enhancement closed loop process is realized from task semantic analysis, code generation, logic verification, generation of a schematic diagram to knowledge enhancement.

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