EDA verification method and device, readable medium, program product and electronic equipment

Abstract

The invention relates to an EDA verification method and device, a readable medium, a program product and electronic equipment. The EDA verification method provided by the invention is applied to the EDA verification system. The EDA verification system comprises a first simulation module, a post-processing module and a verification module. The EDA verification method comprises the steps that a first simulation module is controlled to execute a first instruction file to obtain a first log file, the first instruction file at least comprises one first-class instruction, and recording time of first instruction decommissioning information corresponding to the same first-class instruction and recording time of a first instruction execution result in the first log file are different. And controlling the post-processing module to write back a first instruction execution result corresponding to the same first type of instruction to a target position in the first instruction decommissioning information to obtain the to-be-verified log file. And controlling the verification module to obtain a verification result based on the second log file and the to-be-verified log file. According to the method, the first log file is subjected to write-back processing, so that research and development personnel can more accurately judge whether the design meets the requirement or not.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, and in particular to an EDA verification method, device, readable medium, program product, and electronic device. Background Art

[0002] In recent years, the fifth-generation Reduced Instruction Set Computing Version 5 (RISC-V) instruction set architecture (ISA), owing to its openness and scalability, has gradually become a mainstream choice in processor design. With the rapid development of the RISC-V ecosystem, its verification methodologies and technical tools have also been evolving. In the RISC-V ISA, instruction retirement is generally used to describe the process of an instruction completing execution and no longer requiring pipeline resources. When an instruction retires, it signifies that it has completed all required operations and no longer needs to maintain state or wait for other instructions. However, for some complex instructions, even after instruction retirement, the execution results of these instructions are not updated until several execution cycles have passed. This results in inaccurate electronic design automation (EDA) verification results for processors designed based on the RISC-V ISA, making it difficult to accurately determine whether the design meets requirements. Summary of the Invention

[0003] In view of this, an embodiment of the present application provides an EDA verification method, device, readable medium, program product and electronic device. The present application writes back the first instruction execution result corresponding to the same first-class instruction in the first log file to the target position in the first instruction retirement information through the post-processing module in the EDA verification system to obtain a log file to be verified, and obtains a verification result based on the second log file and the log file to be verified through the verification module. That is, the log file generated by the processor designed based on the RISC-V instruction set architecture to be verified in the execution of the instruction is post-processed, and the instruction execution result corresponding to the complex instruction in the log file is backfilled to the target position in the complex instruction retirement information to obtain the log file to be verified. Since the second log file is obtained based on the first instruction file, the second log file can be used as a reference log file, and the EDA verification result obtained by comparing the log file to be verified with the second log file is more accurate.

[0004] In a first aspect, the present application provides an EDA verification method, which is applied to an EDA verification system. The EDA verification system includes a first simulation module, a post-processing module, and a verification module. The method includes: inputting the first instruction file into the first simulation module; Controlling the first simulation module to execute a first instruction file to obtain a first log file, wherein the first instruction file includes at least one first-category instruction, and the first simulation module takes multiple clock cycles to execute the first-category instruction; the first log file includes first instruction retirement information and first instruction execution results of the first-category instructions, and the first instruction retirement information and first instruction execution results corresponding to the same first-category instruction in the first log file are recorded at different times; inputting the first log file into a post-processing module; Controlling the post-processing module to write back the first instruction execution result corresponding to the same first-category instruction to the target location in the first instruction retirement information to obtain a log file to be verified; Inputting a second log file and a log file to be verified into a verification module, wherein the second log file is obtained based on the first instruction file; The control verification module obtains a verification result based on the second log file and the log file to be verified.

[0005] In a possible implementation of the first aspect, in the first log file, a first instruction execution result and first instruction retirement information corresponding to the same first-category instruction have the same index information. Before controlling the post-processing module to write back the first instruction execution result corresponding to the same first-category instruction to a target location in the first instruction retirement information to obtain the log file to be verified, the EDA verification method further includes: The control post-processing module matches the first instruction execution result and the first instruction retirement information corresponding to the same first-category instruction in the first instruction file based on the index information.

[0006] In a possible implementation of the first aspect, the verification module obtains a verification result based on the second log file and the log file to be verified in the following manner: Comparing the instruction related information corresponding to the same instruction in the first instruction file in the second log file and the log file to be verified to obtain a comparison result; A verification result is obtained based on the comparison result.

[0007] In a possible implementation of the first aspect, the EDA verification system further includes a first memory, the first memory being used to store a first log file obtained by the first simulation module, and inputting the first log file into the post-processing module, including: Retrieve a first log file from a first storage device; The obtained first log file is input into the post-processing module.

[0008] In a possible implementation of the first aspect, the EDA verification system further includes a second memory, the second memory being used to store a second log file, and inputting the second log file and the log file to be verified into the verification module, including: Retrieve a second log file from the second storage; The second log file obtained from the second memory and the log file to be verified output by the post-processing module are input into the verification module.

[0009] In a possible implementation of the first aspect, the EDA verification system further includes a second simulation module, the second log file is obtained by the second simulation module by executing the first instruction file, and inputting the second log file and the log file to be verified into the verification module includes: Obtaining a second log file output by the second simulation module; The second log file output by the second simulation module and the log file to be verified output by the post-processing module are input into the verification module.

[0010] In a possible implementation of the first aspect, the EDA verification system further includes a first instruction generation module, and the first instruction file is generated by the instruction generation module.

[0011] In a possible implementation of the first aspect, the first instruction generation module includes a first generation unit and a first compilation unit. The first instruction generation module generates the first instruction file in the following manner: Controlling the first generating unit to generate a random instruction stream, where the random instruction stream is a first language file; Inputting a random instruction stream into a first compilation unit; The first compiling unit is controlled to compile the random instruction stream to obtain a first instruction file, where the first instruction file is a second language file, and the second language file is different from the first language file.

[0012] In a possible implementation of the first aspect, the EDA verification system further includes a second instruction generation module, where the second instruction generation module is configured to generate a directional instruction file.

[0013] In a possible implementation of the first aspect, the second instruction generation module includes a second generation unit and a second compilation unit, and the second instruction generation module generates the directional instruction file in the following manner: controlling the second generating unit to generate a directional instruction stream, wherein the directional instruction stream is a first language file; inputting the directed instruction stream into a second compilation unit; The second compilation unit is controlled to compile the directional instruction stream to obtain a directional instruction file, where the directional instruction file is a second language file, and the second language file is different from the first language file.

[0014] In a possible implementation of the first aspect, the EDA verification system further includes a self-monitoring module, and the method further includes: inputting the directional instruction file into the first simulation module; Controlling the first simulation module to execute the directional instruction file to obtain a directional log file; Input the directed log files into the self-monitoring module; The control self-monitoring module compares the directional log file with the preset log file to obtain the self-monitoring result of the first simulation module.

[0015] In a possible implementation of the first aspect, the first language file is an assembly language file, and the second language file is a machine language file.

[0016] In a possible implementation of the first aspect, the first simulation module is a processor based on the RISC-V architecture.

[0017] In a possible implementation of the first aspect, the first instruction file includes at least one second-category instruction, and the first simulation module takes one clock cycle to execute the second-category instruction.

[0018] It should be noted that the second type of instructions here are short instructions. The "taking one clock cycle" mentioned here does not mean that the instructions only require one clock cycle in a narrow sense, but means that the short instructions take effect and generate the instruction execution results in the same beat. Short instructions are relative to long instructions that take multiple clock cycles from the instruction taking effect to the instruction execution results.

[0019] In a possible implementation of the first aspect, the first log file includes second instruction retirement information and second instruction execution results of the second category of instructions, and the recording time of the second instruction retirement information and second instruction execution results corresponding to the second category of instructions in the first log file is the same.

[0020] In a second aspect, the present application provides an EDA verification device, comprising: A first input unit, configured to input a first instruction file into a first simulation module; a first control unit, configured to control the first simulation module to execute a first instruction file to obtain a first log file, wherein the first instruction file includes at least one first-category instruction, and the first simulation module needs to take multiple clock cycles to execute the first-category instruction; the first log file includes first instruction retirement information and first instruction execution results of the first-category instructions, wherein the first instruction retirement information and the first instruction execution results corresponding to the same first-category instruction in the first log file are recorded at different times; A second input unit, configured to input the first log file into a post-processing module; A second control unit is configured to control the post-processing module to write back the first instruction execution result corresponding to the same first-category instruction to a target location in the first instruction retirement information to obtain a log file to be verified; a third input unit, configured to input a second log file and a log file to be verified into the verification module, wherein the second log file is obtained based on the first instruction file; The third control unit is used to control the verification module to obtain a verification result based on the second log file and the log file to be verified.

[0021] In a third aspect, the present application provides a computer-readable storage medium having instructions stored thereon, which, when executed on an electronic device, causes the electronic device to execute the EDA verification method in the above-mentioned first aspect and any possible implementation of the first aspect.

[0022] In a fourth aspect, the present application provides a computer program product, which includes instructions. When the instructions are executed by one or more processors, they are used to implement the EDA verification method in the first aspect and any possible implementation of the first aspect.

[0023] In a fifth aspect, the present application provides an electronic device, including: It includes a memory and a processor, the memory is used to store a computer program executable by the processor; the processor is used to execute the computer program in the memory to implement the EDA verification method in the first aspect and any possible implementation of the first aspect as described above.

[0024] Compared with the prior art, the beneficial effect of the present application is that: the present application writes back the first instruction execution result corresponding to the same first-class instruction in the first log file to the target position in the first instruction retirement information through the post-processing module in the EDA verification system to obtain a log file to be verified, and obtains a verification result based on the second log file and the log file to be verified through the verification module. That is, the log file generated by the processor designed based on the RISC-V instruction set architecture to be verified in the execution of the instruction is post-processed, and the instruction execution result corresponding to the complex instruction in the log file is backfilled to the target position in the complex instruction retirement information to obtain the log file to be verified. Since the second log file is obtained based on the first instruction file, the second log file can be used as a reference log file, and the EDA verification result obtained by comparing the log file to be verified with the second log file is more accurate. In addition, the EDA verification system provided by the present application modularizes the simulation of instruction execution, the backfilling of instruction execution results, and the verification of simulation module functions, and can decouple the backfilling of instruction execution results and the verification of simulation module functions from the simulation of instruction execution. Since in actual applications, the simulation of instruction execution and the simulation of simulation module functions both require a license, after realizing the above-mentioned decoupling of the verification of simulation module functions and the simulation of instruction execution, the license resources can be fully utilized to realize the acceleration of the simulation of instruction execution, the backfilling of instruction execution results, and the verification of simulation module functions, and can also realize flexible adaptation and migration of various functional modules in the EDA verification system according to the actual application environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 According to some embodiments of the present application, a structural block diagram of an EDA verification system is shown; Figure 2 According to some embodiments of the present application, a flow chart of an EDA verification method is shown; Figure 3 According to some embodiments of the present application, a structural block diagram of another EDA verification system is shown; Figure 4 According to some embodiments of the present application, a structural block diagram of another EDA verification system is shown; Figure 5According to some embodiments of the present application, a structural block diagram of another EDA verification system is shown; Figure 6 According to some embodiments of the present application, a structural block diagram of another EDA verification system is shown; Figure 7 According to some embodiments of the present application, a structural block diagram of another EDA verification system is shown; Figure 8A According to some embodiments of the present application, a structural block diagram of a second simulation module is shown; Figure 8B According to some embodiments of the present application, a structural block diagram of another second simulation module is shown; Figure 9 According to some embodiments of the present application, a structural block diagram of an EDA verification device is shown; Figure 10 According to some embodiments of the present application, a structural block diagram of an electronic device is shown. DETAILED DESCRIPTION

[0027] The illustrative embodiments of the present application include, but are not limited to, an EDA verification method, apparatus, readable medium, program product, and electronic device.

[0028] Unless otherwise defined, the technical or scientific terms used in this specification and claims shall have the ordinary meanings understood by persons having ordinary skills in the technical field to which the invention belongs. Specific embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be noted that in the specific description of these embodiments, for the sake of clarity and clarity, this specification cannot provide a detailed description of all features of the actual embodiments. Without departing from the spirit and scope of the present invention, those skilled in the art may modify and replace the embodiments of the present invention, and the resulting embodiments are also within the scope of protection of the present invention.

[0029] Explanation of terms: RISC-V: RISC-V stands for Reduced Instruction Set Computer V. It is an open-source instruction set architecture.

[0030] Instruction retirement: In the RISC-V architecture, instruction retirement is often used to describe the process of an instruction having completed its execution and no longer requiring pipeline resources. When an instruction retires, it has completed all required operations and no longer needs to maintain state or wait for other instructions. For long instructions, the instruction is retired, but the corresponding instruction execution result must be updated after a certain number of instruction execution cycles. In other words, for long instructions, the instruction execution result cannot be generated at the time of the instruction retirement. GPR: General Purpose Registers. These registers are used to store general-purpose data and addresses and are key components of the processor's ability to execute instructions and perform calculations. The RISC-V architecture specification defines a set of 32 general-purpose registers, typically labeled x0 through x31. The x0 register is typically hardware-designed as a special register that always returns a value of zero, while the other 31 registers can be used to store data, addresses, and intermediate calculation results.

[0031] Figure 1 According to some embodiments of the present application, a structural block diagram of an EDA verification system is shown. Figure 1 The EDA verification system 100 shown includes a first simulation module 10 , a post-processing module 11 and a verification module 12 .

[0032] In some embodiments, the first simulation module 10 is configured to obtain a first log file by executing an input first instruction file. In some embodiments, the first simulation module 10 is the verification object of EDA verification, that is, the device under test (DUT). In RISC-V processor design, the DUT generally refers to a processor core that implements the RISC-V instruction set architecture. In the embodiment of the present application, the first simulation module 10 obtains a first log file by executing the above-mentioned first instruction file, which serves as the basis for instruction-level verification of the first simulation module 10.

[0033] In some embodiments, the above-mentioned first instruction file includes at least one first-category instruction, and the first simulation module 10 needs to take multiple clock cycles to execute the first-category instruction. It should be understood that in order to perform instruction-level verification on the first simulation module 10, the first instruction file, as an instruction test set, usually contains multiple instructions, for example, tens of thousands of instructions. The execution of the first-category instruction needs to take multiple clock cycles, and the execution result of the first-category instruction needs to be updated after the retirement of this instruction after multiple clock cycles. In other words, the first-category instruction is a long instruction, and the execution result of the long instruction cannot be updated within the same clock cycle as the retirement of the instruction.

[0034] In some embodiments, the first category of instructions includes cache instructions, multiplication instructions, division instructions, etc. It should be understood that in order to more comprehensively implement instruction-level verification of the first simulation module 10, the first instruction file also includes some short instructions, such as addition instructions, which means that short instructions can be executed within one clock cycle and the execution result of the instruction will also be updated within one clock cycle.

[0035] The post-processing module 11 is configured to post-process the first log file to obtain a log file to be verified. In some embodiments, the post-processing module 11 writes back the execution result of the first instruction corresponding to the same first-category instruction to the target location in the first instruction retirement information to obtain a log file to be verified. That is to say, the post-processing module 11 writes back the instruction execution result corresponding to the first-category instruction (long instruction) in the first log file to the instruction retirement information of the same long instruction, so that the instruction execution result is included in the instruction retirement information of the same instruction in the log file to be verified and the reference log file. By comparing the instruction retirement information of each instruction in the log file to be verified and the reference log file, the verification result of the EDA verification of the processor designed based on the RISC-V instruction set architecture can be made more accurate, which is beneficial for R&D personnel to more accurately judge whether the design meets the requirements.

[0036] The verification module 12 is configured to obtain a verification result based on a second log file and a log file to be verified. The second log file is also the above-mentioned reference log file, and this reference log file is obtained by executing the above-mentioned first instruction file using an open source simulation model. In some embodiments, the above-mentioned open source simulation model is a Spike model. Since the Spike model is a verification tool based on the RISC-V instruction set architecture, the log file obtained by executing the above-mentioned first instruction file using the Spike model can be used as a reference log file and compared with the above-mentioned log file to be verified, thereby realizing instruction-level verification of the above-mentioned first simulation module 10. It should be understood that the selection of the open source simulation model can be selected according to actual needs, and this application does not limit this.

[0037] Figure 2 According to some embodiments of the present application, a flowchart of an EDA verification method is shown. Figure 2 The EDA verification method shown is applied to Figure 1 The EDA verification system 100 shown in FIG. Figure 1 and Figure 2 , a detailed description of the EDA verification method provided by this application is given. Figure 2 , an EDA verification method provided in this application includes the following steps: S10: Input the first instruction file into the first simulation module 10.

[0038] Among them, the first instruction file can be a random instruction stream or a directed instruction stream. The first instruction file can be generated offline or online. In the case where the first instruction file is generated offline, the computer resources occupied by generating the first instruction file can be released, and the first simulation module 10 can be accelerated to execute each instruction in the first instruction file. The first instruction file is a machine language file, which contains a plurality of binary instructions that can be recognized by the computer. Therefore, by inputting the first instruction file into the first simulation module 10, the first simulation module 10 no longer needs to translate the first instruction file, so that the first simulation module 10 can quickly execute the first instruction file.

[0039] In some embodiments, the first simulation module 10 is a processor based on the RISC-V architecture. The relevant technical features of the first simulation module 10 have been combined with the above. Figure 1 It has been described in detail and will not be repeated here.

[0040] S20: Control the first simulation module 10 to execute the first instruction file to obtain a first log file, wherein the first instruction file includes at least one first-category instruction, and the first simulation module 10 needs to take multiple clock cycles to execute the first-category instruction; the first log file includes first instruction retirement information and first instruction execution results of the first-category instruction, and the recording time of the first instruction retirement information and the first instruction execution result corresponding to the same first-category instruction in the first log file is different.

[0041] The first type of instructions are the long instructions or complex instructions mentioned above. For an introduction to complex instructions, please refer to the above Figure 1 The textual description of the embodiment shown will not be repeated here.

[0042] In some embodiments, the first log file is a structured file, and the first log file includes multiple fields such as instruction address, instruction code, instruction operand, instruction identifier, target register identifier, and target register value. Among them, the instruction address represents the execution address of the instruction and is used to track the execution order of the instruction. The instruction operand represents the specific data involved in the instruction operation. For example, for an addition instruction, the operands are A and B, so executing this addition operation is to add A and B. The target register identifier represents the identifier of the target GPR to which the result of the instruction execution is to be written. For example, the target register identifier is x1, indicating that the result of the instruction execution is to be written to the register x1. The target register value is also the result of the instruction execution. For example, for an addition instruction, the operands are A and B, so the result of the instruction execution is the result of the addition of A and B. It should be noted that which fields are specifically included in the first log file can be determined according to demand, and this application does not limit this.

[0043] The aforementioned first instruction retirement information refers to information related to the retirement of first-category instructions; the first instruction execution result refers to the execution result of the first-category instruction. In some embodiments, the aforementioned first instruction retirement information for the first-category instructions includes multiple fields, such as the instruction address, instruction code, instruction operand, instruction identifier, target register identifier, and target register value of the first instruction. Because the first-category instructions are long instructions, the recording of the instruction execution result of the first-category instructions is later than the recording of the instruction retirement information. Therefore, the target register identifier and target register value in the retirement information of the first-category instructions are empty.

[0044] In some embodiments, the first instruction execution result of the first category of instructions includes multiple fields such as an instruction identifier, a target register identifier, and a target register value. Since both the first instruction retirement information and the first instruction execution result include the instruction identifier, it is convenient for the post-processing module 11 to identify which instructions are first category instructions, that is, long instructions, so that the post-processing module 11 can quickly identify the long instructions based on the instruction identifier in the first log file, and then write the target register identifier and target register value corresponding to the long instructions into the target register identifier and target register value fields in the first instruction retirement information, respectively. This process is also called a write-back process.

[0045] The difference in recording time between the first instruction retirement information and the first instruction execution result for the first category of instructions refers to the difference in the time at which the first instruction retirement information and the first instruction execution result are generated in the first log file. It is easy to understand that, because the execution results of first category instructions, i.e., long instructions, are not updated until several cycles after the instruction retirement, the first instruction execution result is generated in the first log file later than the time at which the first instruction retirement information is generated in the first log file.

[0046] In some embodiments, the first instruction file includes at least one second-category instruction, and the first simulation module 10 takes one clock cycle to execute the second-category instruction. It should be noted that the second-category instruction here is a short instruction, and the "taking one clock cycle" mentioned here does not mean that the instruction only takes one clock cycle in the narrow sense, but rather means that the short instruction takes effect and generates the instruction execution result in the same clock cycle. Short instructions are compared with long instructions that take multiple clock cycles from the instruction taking effect to the instruction result generation.

[0047] In some embodiments, the first log file includes second instruction retirement information and second instruction execution results for second-category instructions, and the second instruction retirement information and second instruction execution results corresponding to the second-category instructions in the first log file are recorded at the same time. The second-category instructions herein refer to the short instructions described above, and the execution results of the short instructions are typically generated in the first log file in the same clock cycle as the instruction retirement information.

[0048] The above-mentioned second instruction retirement information refers to the relevant information of the retirement of the second category of instructions; the second instruction execution result refers to the execution result of the second category of instructions. In some embodiments, the above-mentioned second instruction retirement information of the second category of instructions includes multiple fields such as the instruction address, instruction code, instruction operand, instruction identifier, target register identifier, target register value, etc. of the second instruction. In some embodiments, the second instruction execution result of the second category of instructions includes multiple fields such as instruction identifier, target register identifier, target register value, etc. Since the second category of instructions are short instructions, the recording of the instruction execution results of the second category of instructions and the recording of the instruction retirement information can be completed in the same clock cycle. Therefore, the target register identifier and the target register value in the retirement information of the second category of instructions are not empty. In the embodiment of the present application, there is no need to perform the above-mentioned write-back operation on the retirement information of the second category of instructions.

[0049] S30: Input the first log file into the post-processing module 11, so that the post-processing module 11 can perform the above-mentioned write-back operation on the first log file.

[0050] In some embodiments, inputting the first log file into the post-processing module 11 includes: obtaining the first log file output by the first simulation module 10; and inputting the first log file output by the first simulation module 10 into the post-processing module 11. It should be understood that if the first log file output by the first simulation module 10 is directly input into the post-processing module 11, the post-processing module 11 can quickly backfill the first log file obtained after the first simulation module 10 executes the first instruction file. In some embodiments, the first log file can be stored in a memory and then input into the post-processing module 11 after the first log file is retrieved from the memory.

[0051] S40: Control the post-processing module 11 to write back the first instruction execution result corresponding to the same first-category instruction to the target location in the first instruction retirement information to obtain a log file to be verified.

[0052] In some embodiments, the first instruction retirement information for the first category of instructions includes multiple fields, including the instruction address, instruction code, instruction operands, instruction identifier, target register identifier, and target register value of the first instruction. Based on the foregoing description, the first category of instructions are long instructions, and the execution results of the first category of instructions are recorded later than the instruction retirement information. The target register identifier and target register value in the retirement information for the first category of instructions are empty. Therefore, in some embodiments, the current position described above refers to the position of the target register identifier field and the target register value field in the first instruction retirement information.

[0053] In some embodiments, the first instruction execution result of the first type of instruction includes multiple fields such as instruction identification, target register identification, and target register value. The post-processing module 11 can quickly identify the long instruction according to the instruction identification in the first log file, and then write back the target register identification and target register value corresponding to the long instruction to the target register identification and target register value fields in the above-mentioned first instruction retirement information. Through the above-mentioned write-back operation of the post-processing module 11, the target register identification and target register value in the instruction retirement information of the complex instruction in the log file to be verified are not empty, so that the instruction retirement information of the same instruction in the log file to be verified and the reference log file both contain the instruction execution result, so that by comparing the complete instruction retirement information of each instruction in the log file to be verified and the reference log file, the verification result of the EDA verification of the processor designed based on the RISC-V instruction set architecture can be made more accurate, which is beneficial for R&D personnel to more accurately judge whether the design meets the requirements.

[0054] In some embodiments, in the first log file, the first instruction execution result and the first instruction retirement information corresponding to the same first-category instruction have the same index information. The index information may be the target register identifier described above. By setting the same index information for the first instruction execution result and the first instruction retirement information, the post-processing module 11 can quickly match the instruction retirement information and the instruction execution result corresponding to the same long instruction in the first log file based on the same index information. It should be noted that the above-mentioned index information can be set as needed, and this application does not limit this.

[0055] In some embodiments, before the post-processing module 11 writes back the first instruction execution result corresponding to the same first-category instruction to the target location in the first instruction retirement information to obtain the log file to be verified, the EDA verification method provided in this application further includes: controlling the post-processing module 11 to match the first instruction execution result and the first instruction retirement information corresponding to the same first-category instruction in the first instruction file based on the index information. It is not difficult to understand that only when the first instruction execution result and the first instruction retirement information corresponding to the same first-category instruction are accurately matched, can the post-processing module 11 write back the first instruction execution result of the same first-category instruction to the first instruction retirement information.

[0056] In some embodiments, after the post-processing module 11 obtains the log file to be verified through the above-mentioned write-back process, it can also perform further testing based on this log file to be verified. In some embodiments, the post-processing module 11 can count and detect the number of instructions in the log file to be verified, the number of instruction execution results, and the execution order of the instructions. In some embodiments, the post-processing module 11 can report an error for any of the following situations: assuming that for the same GPR, multiple GPR result updates appear after an instruction retire; for the same GPR, the GPR update precedes the instruction retire; for the same GPR, the last instruction retires, but no GPR result update is received; for the same GPR, the total number of instruction retires is greater than the number of GPR updates; for the same GPR, the total number of GPR updates is greater than the number of retires. This can help R&D personnel quickly discover errors in the design and reduce product design time.

[0057] S50: Inputting the second log file and the log file to be verified into the verification module 12, wherein the second log file is obtained based on the first instruction file.

[0058] The second log file here is the aforementioned reference log file. In some embodiments, the reference log file is obtained by executing the above-mentioned first instruction file using an open source simulation model. Figure 1 The description of the text part in the illustrated embodiment will not be repeated here.

[0059] S60: The control verification module 12 obtains a verification result based on the second log file and the log file to be verified.

[0060] Since the open source simulation model used in the embodiment of the present application is a verification tool based on the RISC-V instruction set architecture, the second log file obtained by executing the above-mentioned first instruction file using the open source simulation model can be used as a reference log file and compared with the above-mentioned log file to be verified to achieve instruction-level verification of the above-mentioned first simulation module 10.

[0061] It should be noted that the above-mentioned log file to be verified is obtained after the post-processing module 11 writes back the above-mentioned first log file. The target register identifier and target register value in the instruction retirement information of the complex instruction in the log file to be verified are not empty, so that the instruction retirement information of the same instruction in the log file to be verified and the reference log file both contain the instruction execution results. Therefore, by comparing the complete instruction retirement information of each instruction in the log file to be verified and the reference log file, the verification results of EDA verification of processors designed based on the RISC-V instruction set architecture can be made more accurate, which is beneficial for R&D personnel to more accurately judge whether the design meets the requirements.

[0062] In some embodiments, the verification module 12 obtains a verification result based on the second log file and the log file to be verified by: comparing the instruction-related information in the second log file and the log file to be verified corresponding to the same instruction in the first instruction file to obtain a comparison result; and obtaining a verification result based on the comparison result. In some embodiments, the instruction-related information may include an instruction address, an instruction code, an instruction operand, an instruction identifier, a target register identifier, and a target register value. The instruction-related information may also include other fields defined by the developer, which are not limited in this application.

[0063] It can be understood that the execution order of the above steps S10 to S60 is only an illustration. In other embodiments, other execution orders may be adopted, and some steps may be split or combined, which is not limited here. Combination of the above Figure 1 The EDA verification system 100 provided in the embodiment shown in the figure is Figure 2 The EDA verification method shown is briefly introduced. The following will continue to introduce various structures of the EDA verification system 100 provided in the embodiment of the present application, and further expand on some steps in the above-mentioned EDA verification method under various EDA verification systems 100.

[0064] It should be noted that the various structures of the EDA verification system 100 to be introduced below are all based on Figure 1 Make some changes based on this.

[0065] Figure 3 According to some embodiments of the present application, a structural block diagram of another EDA verification system 100 is shown. Figure 3 The EDA verification system 100 shown is compared to Figure 1 The difference between the EDA verification system 100 shown is that: Figure 1 The EDA verification system 100 shown is based on Figure 3 The illustrated EDA verification system 100 further includes a first memory 13 and a second memory 14 .

[0066] In some embodiments, the first memory 13 is used to store the first log file obtained by the first simulation module 10. Step S30 in the above-mentioned EDA verification method: inputting the first log file into the post-processing module 11 further includes: obtaining the first log file from the first memory 13; inputting the obtained first log file into the post-processing module 11.

[0067] In some embodiments, the second memory 14 is used to store the second log file. Step S50 in the above-mentioned EDA verification method: inputting the second log file and the log file to be verified into the verification module 12 further includes: obtaining the second log file from the second memory 14; inputting the second log file obtained from the second memory 14 and the log file to be verified output by the post-processing module 11 into the verification module 12.

[0068] Since the first log file is stored in the first memory 13, the post-processing module 11 can implement offline post-processing of the first log file (the aforementioned write-back operation). Since the second log file is stored in the second memory 14, the verification module 12 can implement offline instruction-level verification of the first simulation module 10. By modularly designing the functional modules corresponding to instruction execution, post-processing, and verification of the EDA verification system 100, the functional modules corresponding to instruction execution, post-processing, and verification can be run separately, thereby achieving decoupling of the functional modules corresponding to instruction execution, post-processing, and verification. This can improve the simulation speed of the DUT and also enable rapid location of design errors.

[0069] Figure 4 According to some embodiments of the present application, a structural block diagram of another EDA verification system 100 is shown. Figure 4 The EDA verification system 100 shown is compared to Figure 1 The difference between the EDA verification system 100 shown is that: Figure 1 The EDA verification system 100 shown is based on Figure 4 The EDA verification system 100 shown further includes a second simulation module 20 , and the second log file is obtained by the second simulation module 20 executing the first instruction file.

[0070] In some embodiments, the second log file is the aforementioned reference log file, and the second simulation module 20 is the aforementioned open source simulation model, such as the Spike model. Since the Spike model is a verification tool based on the RISC-V instruction set architecture, the second log file obtained by executing the above-mentioned first instruction file using the Spike model can be used as a reference log file and compared with the above-mentioned log file to be verified to achieve instruction-level verification of the above-mentioned first simulation module 10.

[0071] In some embodiments, step S50 in the above-mentioned EDA verification method: inputting the second log file and the log file to be verified into the verification module 12 further includes: obtaining the second log file output by the second simulation module 20; inputting the second log file output by the second simulation module 20 and the log file to be verified output by the post-processing module 11 into the verification module 12.

[0072] Figure 5 According to some embodiments of the present application, a structural block diagram of another EDA verification system 100 is shown. Figure 5 The EDA verification system 100 shown is compared to Figure 1 The difference between the EDA verification system 100 shown is that: Figure 1 The EDA verification system 100 shown is based on Figure 5 The EDA verification system 100 shown further includes a first instruction generation module 15 . The first instruction file is generated by the instruction generation module, that is, the first instruction file is generated online.

[0073] Figure 5 The illustrated first instruction generation module 15 includes a first generation unit 151 and a first compilation unit 152. The first instruction generation module 15 generates a first instruction file by: controlling the first generation unit 151 to generate a random instruction stream, which is a first language file; inputting the random instruction stream into the first compilation unit 152; and controlling the first compilation unit 152 to compile the random instruction stream to generate a first instruction file, which is a second language file that is different from the first language file. In some embodiments, the first language file is an assembly language file, and the second language file is a machine language file.

[0074] Figure 6 According to some embodiments of the present application, a structural block diagram of another EDA verification system 100 is shown. Figure 6 The EDA verification system 100 shown is compared to Figure 1 The difference between the EDA verification system 100 shown is that: Figure 1 The EDA verification system 100 shown is based on Figure 6 The EDA verification system 100 shown in the figure is additionally provided with a second simulation module 20 and a first instruction generation module 15. The relevant descriptions of the second simulation module 20 and the first instruction generation module 15 are referred to above and will not be repeated here.

[0075] Figure 7 According to some embodiments of the present application, a structural block diagram of another EDA verification system 100 is shown. Figure 7 The EDA verification system 100 shown is compared to Figure 1 The difference between the EDA verification system 100 shown is that: Figure 1 The EDA verification system 100 shown is based on Figure 7 The EDA verification system 100 shown in FIG. 1 further includes a second simulation module 20, a first instruction generation module 15, a second instruction generation module 16, and a self-monitoring module 17. The second instruction generation module 16 is configured to generate a directional instruction file. The self-monitoring module 17 is configured to compare the directional log file with a preset log file to obtain the self-monitoring results of the first simulation module 10, thereby detecting whether the test results meet the test intent.

[0076] Figure 7 The second instruction generation module 16 shown includes a second generation unit 161 and a second compilation unit 162. The second instruction generation module 16 generates a directional instruction file in the following manner: controlling the second generation unit 161 to generate a directional instruction stream, which is a first language file; inputting the directional instruction stream into the second compilation unit 162; and controlling the second compilation unit 162 to compile the directional instruction stream to obtain a directional instruction file, which is a second language file.

[0077] In some embodiments, the above-mentioned EDA verification method also includes: inputting a directional instruction file into the first simulation module 10; controlling the first simulation module 10 to execute the directional instruction file to obtain a directional log file; inputting the directional log file into the self-monitoring module 17; and controlling the self-monitoring module 17 to perform self-monitoring based on the directional log file.

[0078] In some embodiments, the second simulation module 20 includes an open source module, such as Figure 8A In other embodiments, the second simulation module 20 includes an open source module and a paid model, such as Figure 8B It should be understood that if the second simulation module 20 includes an open source module and a paid model, the open source model and the paid model can detect each other's operating status. If one of the models fails, the other model can continue to simulate as a backup model, making the performance of the EDA system provided by this application more stable.

[0079] The present application uses a post-processing module to write back the first instruction execution result corresponding to the same first-category instruction to the target location in the first instruction retirement information to obtain a log file to be verified, and then uses the verification module to verify the log file to be verified and the second log file to obtain a verification result, wherein the first simulation module takes multiple clock cycles to execute the first-category instruction. In other words, the first-category instructions are some long instructions, which can solve the problem that the instruction execution result of the complex instruction is updated slowly, resulting in the instruction execution result of the target location in the instruction retirement information of the complex instruction in the instruction execution log file being empty, and then the verification information obtained by using this instruction execution log file and the reference log file is inaccurate. In addition, the EDA verification system provided by the present application modularizes the simulation of instruction execution, the backfilling of instruction execution results, and the verification of simulation module functions, and can decouple the backfilling of instruction execution results and the verification of simulation module functions from the simulation of instruction execution. Since in actual applications, the simulation of instruction execution and the simulation of simulation module functions both require a license, after the above-mentioned decoupling of the verification of simulation module functions and the simulation of instruction execution is achieved, the license resources can be fully utilized to realize the simulation of instruction execution, the backfilling of instruction execution results, and the acceleration of the verification of simulation module functions. In addition, the flexible adaptation and migration of various functional modules in the EDA verification system can be achieved according to the actual application environment.

[0080] The present application also provides an EDA verification device, see Figure 9 , the EDA verification device provided in this application includes: A first input unit 201 is used to input a first instruction file into the first simulation module 10; A first control unit 202 is configured to control the first simulation module 10 to execute a first instruction file to obtain a first log file, wherein the first instruction file includes at least one first-category instruction, and the first simulation module 10 takes multiple clock cycles to execute the first-category instruction; the first log file includes first instruction retirement information and first instruction execution results of the first-category instructions, wherein the first instruction retirement information and first instruction execution results corresponding to the same first-category instruction in the first log file are recorded at different times; The second input unit 203 is used to input the first log file into the post-processing module 11; The second control unit 204 is configured to control the post-processing module 11 to write back the first instruction execution result corresponding to the same first-category instruction to the target location in the first instruction retirement information to obtain a log file to be verified; The third input unit 205 is used to input the second log file and the log file to be verified into the verification module 12, wherein the second log file is obtained based on the first instruction file; The third control unit 206 is configured to control the verification module 12 to obtain a verification result based on the second log file and the log file to be verified.

[0081] Regarding the apparatus in the above embodiment, the specific manner in which the processor performs operations has been described in detail in the embodiment of the method, and will not be elaborated on here.

[0082] The embodiment of the present application further provides an electronic device 300, such as Figure 10 As shown, the electronic device 300 includes a memory 301 and a processor 302. The memory 301 is used to store computer programs executable by the processor 302; the processor 302 is used to execute the computer program in the memory 301 to implement the EDA verification method provided in any of the above embodiments.

[0083] Figure 10 The electronic device 300 shown further includes a communication interface 303. The processor 302, the memory 301 and the communication interface 303 are connected via a communication bus and communicate with each other.

[0084] The processor 302 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the above-mentioned programs.

[0085] The communication interface 303 is used to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc.

[0086] The memory 301 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory can be independent and connected to the processor via a bus. The memory can also be integrated with the processor.

[0087] An embodiment of the present application further provides a computer-readable storage medium having instructions stored thereon. When the instructions are executed on an electronic device, the electronic device executes the EDA verification method provided by any of the above embodiments.

[0088] An embodiment of the present application further provides a computer program product, which includes instructions. When the instructions are executed by one or more processors, they are used to implement the EDA verification method provided in any of the above embodiments.

[0089] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of this application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0090] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems raised by this application. In addition, in order to highlight the innovative part of this application, the above-mentioned device embodiments of this application do not introduce units / modules that are not closely related to solving the technical problems raised by this application. This does not mean that other units / modules do not exist in the above-mentioned device embodiments.

[0091] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "including a" does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0092] Although the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims

1. An EDA verification method, characterized in that: Applied to an EDA verification system, the EDA verification system includes a first simulation module, a post-processing module, and a verification module, and the method includes: inputting the first instruction file into the first simulation module; controlling the first simulation module to execute a first instruction file to obtain a first log file, wherein the first instruction file includes at least one first-category instruction, and the first simulation module takes multiple clock cycles to execute the first-category instruction; the first log file includes first instruction retirement information and first instruction execution results of the first-category instructions, and the first instruction retirement information and first instruction execution results corresponding to the same first-category instruction in the first log file are recorded at different times; inputting the first log file into a post-processing module; Controlling the post-processing module to write back the first instruction execution result corresponding to the same first-category instruction to a target location in the first instruction retirement information to obtain a log file to be verified; Inputting a second log file and the log file to be verified into a verification module, wherein the second log file is obtained based on the first instruction file; The verification module is controlled to obtain a verification result based on the second log file and the log file to be verified.

2. The EDA verification method according to claim 1, wherein: In the first log file, the first instruction execution result and the first instruction retirement information corresponding to the same first-category instruction have the same index information. Before controlling the post-processing module to write back the first instruction execution result corresponding to the same first-category instruction to a target location in the first instruction retirement information to obtain the log file to be verified, the method further includes: The post-processing module is controlled to match the first instruction execution result and the first instruction retirement information corresponding to the same first-category instruction in the first instruction file based on the index information.

3. The EDA verification method according to claim 1, wherein: The verification module obtains a verification result based on the second log file and the log file to be verified in the following manner: Comparing the instruction-related information corresponding to the same instruction in the first instruction file with the instruction-to-be-verified log file in the second log file to obtain a comparison result; The verification result is obtained based on the comparison result.

4. The EDA verification method according to claim 1, wherein: The EDA verification system further includes a first memory, the first memory being used to store the first log file obtained by the first simulation module, and the step of inputting the first log file into the post-processing module includes: Retrieve the first log file from the first storage; The obtained first log file is input into the post-processing module.

5. The EDA verification method according to claim 1, wherein: The EDA verification system further includes a second memory, the second memory being used to store the second log file, and the step of inputting the second log file and the log file to be verified into the verification module includes: Retrieve the second log file from the second storage; The second log file obtained from the second memory and the log file to be verified output by the post-processing module are input into the verification module.

6. The EDA verification method according to claim 1, wherein: The EDA verification system further includes a second simulation module, the second log file is obtained by the second simulation module executing the first instruction file, and the inputting the second log file and the log file to be verified into the verification module includes: Obtaining the second log file output by the second simulation module; The second log file output by the second simulation module and the log file to be verified output by the post-processing module are input into the verification module.

7. The EDA verification method according to claim 1, wherein: The EDA verification system further includes a first instruction generation module, and the first instruction file is generated by the instruction generation module.

8. The EDA verification method according to claim 7, wherein: The first instruction generation module includes a first generation unit and a first compilation unit. The first instruction generation module generates the first instruction file in the following manner: controlling the first generating unit to generate a random instruction stream, wherein the random instruction stream is a first language file; Inputting the random instruction stream into the first compilation unit; The first compilation unit is controlled to compile the random instruction stream to obtain the first instruction file, where the first instruction file is a second language file, and the second language file is different from the first language file.

9. The EDA verification method according to claim 1, wherein: The EDA verification system further includes a second instruction generation module, which is used to generate a directional instruction file.

10. The EDA verification method according to claim 9, characterized in that: The second instruction generation module includes a second generation unit and a second compilation unit. The second instruction generation module generates the directional instruction file in the following manner: controlling the second generating unit to generate a directional instruction stream, wherein the directional instruction stream is a first language file; inputting the directed instruction stream into the second compilation unit; The second compilation unit is controlled to compile the directional instruction stream to obtain the directional instruction file, where the directional instruction file is a second language file, and the second language file is different from the first language file.

11. The EDA verification method according to claim 10, characterized in that: The EDA verification system further includes a self-monitoring module, and the method further includes: inputting the directional instruction file into the first simulation module; Controlling the first simulation module to execute the directional instruction file to obtain a directional log file; inputting the directional log file into the self-monitoring module; The self-monitoring module is controlled to compare the directional log file with a preset log file to obtain a self-monitoring result of the first simulation module.

12. The EDA verification method according to claim 8 or 10, characterized in that: The first language file is an assembly language file, and the second language file is a machine language file.

13. The EDA verification method according to claim 1, wherein: The first simulation module is a processor based on the RISC-V architecture.

14. The EDA verification method according to claim 1, wherein: The first instruction file includes at least one second-category instruction, and the first simulation module takes one clock cycle to execute the second-category instruction.

15. The EDA verification method according to claim 14, characterized in that: The first log file includes second instruction retirement information and second instruction execution results of the second type of instructions. The recording time of the second instruction retirement information and the second instruction execution results corresponding to the second type of instructions in the first log file is the same.

16. An EDA verification device, characterized in that: include: A first input unit, configured to input a first instruction file into a first simulation module; a first control unit, configured to control the first simulation module to execute a first instruction file to obtain a first log file, wherein the first instruction file includes at least one first-category instruction, and the first simulation module takes multiple clock cycles to execute the first-category instruction; the first log file includes first instruction retirement information and first instruction execution results of the first-category instructions, and the first instruction retirement information and first instruction execution results corresponding to the same first-category instruction in the first log file are recorded at different times; a second input unit, configured to input the first log file into a post-processing module; a second control unit, configured to control the post-processing module to write back the execution result of the first instruction corresponding to the same first-category instruction to a target location in the first instruction retirement information, to obtain a log file to be verified; a third input unit, configured to input a second log file and the log file to be verified into a verification module, wherein the second log file is obtained based on the first instruction file; A third control unit is used to control the verification module to obtain a verification result based on the second log file and the log file to be verified.

17. A computer-readable storage medium, characterized in that The computer-readable storage medium stores instructions, which, when executed on an electronic device, enable the electronic device to execute the EDA verification method according to any one of claims 1 to 15.

18. A computer program product, characterized in that The computer program product comprises instructions, which, when executed by one or more processors, are used to implement the EDA verification method according to any one of claims 1 to 15.

19. An electronic device, characterized in that: include: comprising a memory and a processor, wherein the memory is used to store a computer program executable by the processor; The processor is configured to execute the computer program in the memory to implement the EDA verification method according to any one of claims 1 to 15.

Images